1 /* 2 * wm0010.c -- WM0010 DSP Driver 3 * 4 * Copyright 2012 Wolfson Microelectronics PLC. 5 * 6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 8 * Scott Ling <sl@opensource.wolfsonmicro.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/interrupt.h> 18 #include <linux/irqreturn.h> 19 #include <linux/init.h> 20 #include <linux/spi/spi.h> 21 #include <linux/firmware.h> 22 #include <linux/delay.h> 23 #include <linux/fs.h> 24 #include <linux/miscdevice.h> 25 #include <linux/gpio.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/mutex.h> 28 #include <linux/workqueue.h> 29 30 #include <sound/soc.h> 31 #include <sound/wm0010.h> 32 33 #define DEVICE_ID_WM0010 10 34 35 /* We only support v1 of the .dfw INFO record */ 36 #define INFO_VERSION 1 37 38 enum dfw_cmd { 39 DFW_CMD_FUSE = 0x01, 40 DFW_CMD_CODE_HDR, 41 DFW_CMD_CODE_DATA, 42 DFW_CMD_PLL, 43 DFW_CMD_INFO = 0xff 44 }; 45 46 struct dfw_binrec { 47 u8 command; 48 u32 length:24; 49 u32 address; 50 uint8_t data[0]; 51 } __packed; 52 53 struct dfw_inforec { 54 u8 info_version; 55 u8 tool_major_version; 56 u8 tool_minor_version; 57 u8 dsp_target; 58 }; 59 60 struct dfw_pllrec { 61 u8 command; 62 u32 length:24; 63 u32 address; 64 u32 clkctrl1; 65 u32 clkctrl2; 66 u32 clkctrl3; 67 u32 ldetctrl; 68 u32 uart_div; 69 u32 spi_div; 70 } __packed; 71 72 static struct pll_clock_map { 73 int max_sysclk; 74 int max_pll_spi_speed; 75 u32 pll_clkctrl1; 76 } pll_clock_map[] = { /* Dividers */ 77 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 78 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 79 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 80 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 81 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 82 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 83 }; 84 85 enum wm0010_state { 86 WM0010_POWER_OFF, 87 WM0010_OUT_OF_RESET, 88 WM0010_BOOTROM, 89 WM0010_STAGE2, 90 WM0010_FIRMWARE, 91 }; 92 93 struct wm0010_priv { 94 struct snd_soc_codec *codec; 95 96 struct mutex lock; 97 struct device *dev; 98 99 struct wm0010_pdata pdata; 100 101 int gpio_reset; 102 int gpio_reset_value; 103 104 struct regulator_bulk_data core_supplies[2]; 105 struct regulator *dbvdd; 106 107 int sysclk; 108 109 enum wm0010_state state; 110 bool boot_failed; 111 bool ready; 112 bool pll_running; 113 int max_spi_freq; 114 int board_max_spi_speed; 115 u32 pll_clkctrl1; 116 117 spinlock_t irq_lock; 118 int irq; 119 120 struct completion boot_completion; 121 }; 122 123 struct wm0010_spi_msg { 124 struct spi_message m; 125 struct spi_transfer t; 126 u8 *tx_buf; 127 u8 *rx_buf; 128 size_t len; 129 }; 130 131 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 132 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 133 }; 134 135 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 136 { "SDI2 Capture", NULL, "SDI1 Playback" }, 137 { "SDI1 Capture", NULL, "SDI2 Playback" }, 138 139 { "SDI1 Capture", NULL, "CLKIN" }, 140 { "SDI2 Capture", NULL, "CLKIN" }, 141 { "SDI1 Playback", NULL, "CLKIN" }, 142 { "SDI2 Playback", NULL, "CLKIN" }, 143 }; 144 145 static const char *wm0010_state_to_str(enum wm0010_state state) 146 { 147 static const char * const state_to_str[] = { 148 "Power off", 149 "Out of reset", 150 "Boot ROM", 151 "Stage2", 152 "Firmware" 153 }; 154 155 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 156 return "null"; 157 return state_to_str[state]; 158 } 159 160 /* Called with wm0010->lock held */ 161 static void wm0010_halt(struct snd_soc_codec *codec) 162 { 163 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 164 unsigned long flags; 165 enum wm0010_state state; 166 167 /* Fetch the wm0010 state */ 168 spin_lock_irqsave(&wm0010->irq_lock, flags); 169 state = wm0010->state; 170 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 171 172 switch (state) { 173 case WM0010_POWER_OFF: 174 /* If there's nothing to do, bail out */ 175 return; 176 case WM0010_OUT_OF_RESET: 177 case WM0010_BOOTROM: 178 case WM0010_STAGE2: 179 case WM0010_FIRMWARE: 180 /* Remember to put chip back into reset */ 181 gpio_set_value_cansleep(wm0010->gpio_reset, 182 wm0010->gpio_reset_value); 183 /* Disable the regulators */ 184 regulator_disable(wm0010->dbvdd); 185 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 186 wm0010->core_supplies); 187 break; 188 } 189 190 spin_lock_irqsave(&wm0010->irq_lock, flags); 191 wm0010->state = WM0010_POWER_OFF; 192 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 193 } 194 195 struct wm0010_boot_xfer { 196 struct list_head list; 197 struct snd_soc_codec *codec; 198 struct completion *done; 199 struct spi_message m; 200 struct spi_transfer t; 201 }; 202 203 /* Called with wm0010->lock held */ 204 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 205 { 206 enum wm0010_state state; 207 unsigned long flags; 208 209 spin_lock_irqsave(&wm0010->irq_lock, flags); 210 state = wm0010->state; 211 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 212 213 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 214 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 215 216 wm0010->boot_failed = true; 217 } 218 219 static void wm0010_boot_xfer_complete(void *data) 220 { 221 struct wm0010_boot_xfer *xfer = data; 222 struct snd_soc_codec *codec = xfer->codec; 223 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 224 u32 *out32 = xfer->t.rx_buf; 225 int i; 226 227 if (xfer->m.status != 0) { 228 dev_err(codec->dev, "SPI transfer failed: %d\n", 229 xfer->m.status); 230 wm0010_mark_boot_failure(wm0010); 231 if (xfer->done) 232 complete(xfer->done); 233 return; 234 } 235 236 for (i = 0; i < xfer->t.len / 4; i++) { 237 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]); 238 239 switch (be32_to_cpu(out32[i])) { 240 case 0xe0e0e0e0: 241 dev_err(codec->dev, 242 "%d: ROM error reported in stage 2\n", i); 243 wm0010_mark_boot_failure(wm0010); 244 break; 245 246 case 0x55555555: 247 if (wm0010->state < WM0010_STAGE2) 248 break; 249 dev_err(codec->dev, 250 "%d: ROM bootloader running in stage 2\n", i); 251 wm0010_mark_boot_failure(wm0010); 252 break; 253 254 case 0x0fed0000: 255 dev_dbg(codec->dev, "Stage2 loader running\n"); 256 break; 257 258 case 0x0fed0007: 259 dev_dbg(codec->dev, "CODE_HDR packet received\n"); 260 break; 261 262 case 0x0fed0008: 263 dev_dbg(codec->dev, "CODE_DATA packet received\n"); 264 break; 265 266 case 0x0fed0009: 267 dev_dbg(codec->dev, "Download complete\n"); 268 break; 269 270 case 0x0fed000c: 271 dev_dbg(codec->dev, "Application start\n"); 272 break; 273 274 case 0x0fed000e: 275 dev_dbg(codec->dev, "PLL packet received\n"); 276 wm0010->pll_running = true; 277 break; 278 279 case 0x0fed0025: 280 dev_err(codec->dev, "Device reports image too long\n"); 281 wm0010_mark_boot_failure(wm0010); 282 break; 283 284 case 0x0fed002c: 285 dev_err(codec->dev, "Device reports bad SPI packet\n"); 286 wm0010_mark_boot_failure(wm0010); 287 break; 288 289 case 0x0fed0031: 290 dev_err(codec->dev, "Device reports SPI read overflow\n"); 291 wm0010_mark_boot_failure(wm0010); 292 break; 293 294 case 0x0fed0032: 295 dev_err(codec->dev, "Device reports SPI underclock\n"); 296 wm0010_mark_boot_failure(wm0010); 297 break; 298 299 case 0x0fed0033: 300 dev_err(codec->dev, "Device reports bad header packet\n"); 301 wm0010_mark_boot_failure(wm0010); 302 break; 303 304 case 0x0fed0034: 305 dev_err(codec->dev, "Device reports invalid packet type\n"); 306 wm0010_mark_boot_failure(wm0010); 307 break; 308 309 case 0x0fed0035: 310 dev_err(codec->dev, "Device reports data before header error\n"); 311 wm0010_mark_boot_failure(wm0010); 312 break; 313 314 case 0x0fed0038: 315 dev_err(codec->dev, "Device reports invalid PLL packet\n"); 316 break; 317 318 case 0x0fed003a: 319 dev_err(codec->dev, "Device reports packet alignment error\n"); 320 wm0010_mark_boot_failure(wm0010); 321 break; 322 323 default: 324 dev_err(codec->dev, "Unrecognised return 0x%x\n", 325 be32_to_cpu(out32[i])); 326 wm0010_mark_boot_failure(wm0010); 327 break; 328 } 329 330 if (wm0010->boot_failed) 331 break; 332 } 333 334 if (xfer->done) 335 complete(xfer->done); 336 } 337 338 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 339 { 340 int i; 341 342 for (i = 0; i < len / 8; i++) 343 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i])); 344 } 345 346 static int wm0010_firmware_load(const char *name, struct snd_soc_codec *codec) 347 { 348 struct spi_device *spi = to_spi_device(codec->dev); 349 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 350 struct list_head xfer_list; 351 struct wm0010_boot_xfer *xfer; 352 int ret; 353 struct completion done; 354 const struct firmware *fw; 355 const struct dfw_binrec *rec; 356 const struct dfw_inforec *inforec; 357 u64 *img; 358 u8 *out, dsp; 359 u32 len, offset; 360 361 INIT_LIST_HEAD(&xfer_list); 362 363 ret = request_firmware(&fw, name, codec->dev); 364 if (ret != 0) { 365 dev_err(codec->dev, "Failed to request application(%s): %d\n", 366 name, ret); 367 return ret; 368 } 369 370 rec = (const struct dfw_binrec *)fw->data; 371 inforec = (const struct dfw_inforec *)rec->data; 372 offset = 0; 373 dsp = inforec->dsp_target; 374 wm0010->boot_failed = false; 375 if (WARN_ON(!list_empty(&xfer_list))) 376 return -EINVAL; 377 init_completion(&done); 378 379 /* First record should be INFO */ 380 if (rec->command != DFW_CMD_INFO) { 381 dev_err(codec->dev, "First record not INFO\r\n"); 382 ret = -EINVAL; 383 goto abort; 384 } 385 386 if (inforec->info_version != INFO_VERSION) { 387 dev_err(codec->dev, 388 "Unsupported version (%02d) of INFO record\r\n", 389 inforec->info_version); 390 ret = -EINVAL; 391 goto abort; 392 } 393 394 dev_dbg(codec->dev, "Version v%02d INFO record found\r\n", 395 inforec->info_version); 396 397 /* Check it's a DSP file */ 398 if (dsp != DEVICE_ID_WM0010) { 399 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n"); 400 ret = -EINVAL; 401 goto abort; 402 } 403 404 /* Skip the info record as we don't need to send it */ 405 offset += ((rec->length) + 8); 406 rec = (void *)&rec->data[rec->length]; 407 408 while (offset < fw->size) { 409 dev_dbg(codec->dev, 410 "Packet: command %d, data length = 0x%x\r\n", 411 rec->command, rec->length); 412 len = rec->length + 8; 413 414 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL); 415 if (!xfer) { 416 ret = -ENOMEM; 417 goto abort; 418 } 419 420 xfer->codec = codec; 421 list_add_tail(&xfer->list, &xfer_list); 422 423 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 424 if (!out) { 425 ret = -ENOMEM; 426 goto abort1; 427 } 428 xfer->t.rx_buf = out; 429 430 img = kzalloc(len, GFP_KERNEL | GFP_DMA); 431 if (!img) { 432 ret = -ENOMEM; 433 goto abort1; 434 } 435 xfer->t.tx_buf = img; 436 437 byte_swap_64((u64 *)&rec->command, img, len); 438 439 spi_message_init(&xfer->m); 440 xfer->m.complete = wm0010_boot_xfer_complete; 441 xfer->m.context = xfer; 442 xfer->t.len = len; 443 xfer->t.bits_per_word = 8; 444 445 if (!wm0010->pll_running) { 446 xfer->t.speed_hz = wm0010->sysclk / 6; 447 } else { 448 xfer->t.speed_hz = wm0010->max_spi_freq; 449 450 if (wm0010->board_max_spi_speed && 451 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 452 xfer->t.speed_hz = wm0010->board_max_spi_speed; 453 } 454 455 /* Store max usable spi frequency for later use */ 456 wm0010->max_spi_freq = xfer->t.speed_hz; 457 458 spi_message_add_tail(&xfer->t, &xfer->m); 459 460 offset += ((rec->length) + 8); 461 rec = (void *)&rec->data[rec->length]; 462 463 if (offset >= fw->size) { 464 dev_dbg(codec->dev, "All transfers scheduled\n"); 465 xfer->done = &done; 466 } 467 468 ret = spi_async(spi, &xfer->m); 469 if (ret != 0) { 470 dev_err(codec->dev, "Write failed: %d\n", ret); 471 goto abort1; 472 } 473 474 if (wm0010->boot_failed) { 475 dev_dbg(codec->dev, "Boot fail!\n"); 476 ret = -EINVAL; 477 goto abort1; 478 } 479 } 480 481 wait_for_completion(&done); 482 483 ret = 0; 484 485 abort1: 486 while (!list_empty(&xfer_list)) { 487 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 488 list); 489 kfree(xfer->t.rx_buf); 490 kfree(xfer->t.tx_buf); 491 list_del(&xfer->list); 492 kfree(xfer); 493 } 494 495 abort: 496 release_firmware(fw); 497 return ret; 498 } 499 500 static int wm0010_stage2_load(struct snd_soc_codec *codec) 501 { 502 struct spi_device *spi = to_spi_device(codec->dev); 503 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 504 const struct firmware *fw; 505 struct spi_message m; 506 struct spi_transfer t; 507 u32 *img; 508 u8 *out; 509 int i; 510 int ret = 0; 511 512 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev); 513 if (ret != 0) { 514 dev_err(codec->dev, "Failed to request stage2 loader: %d\n", 515 ret); 516 return ret; 517 } 518 519 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 520 521 /* Copy to local buffer first as vmalloc causes problems for dma */ 522 img = kzalloc(fw->size, GFP_KERNEL | GFP_DMA); 523 if (!img) { 524 ret = -ENOMEM; 525 goto abort2; 526 } 527 528 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA); 529 if (!out) { 530 ret = -ENOMEM; 531 goto abort1; 532 } 533 534 memcpy(img, &fw->data[0], fw->size); 535 536 spi_message_init(&m); 537 memset(&t, 0, sizeof(t)); 538 t.rx_buf = out; 539 t.tx_buf = img; 540 t.len = fw->size; 541 t.bits_per_word = 8; 542 t.speed_hz = wm0010->sysclk / 10; 543 spi_message_add_tail(&t, &m); 544 545 dev_dbg(codec->dev, "Starting initial download at %dHz\n", 546 t.speed_hz); 547 548 ret = spi_sync(spi, &m); 549 if (ret != 0) { 550 dev_err(codec->dev, "Initial download failed: %d\n", ret); 551 goto abort; 552 } 553 554 /* Look for errors from the boot ROM */ 555 for (i = 0; i < fw->size; i++) { 556 if (out[i] != 0x55) { 557 dev_err(codec->dev, "Boot ROM error: %x in %d\n", 558 out[i], i); 559 wm0010_mark_boot_failure(wm0010); 560 ret = -EBUSY; 561 goto abort; 562 } 563 } 564 abort: 565 kfree(out); 566 abort1: 567 kfree(img); 568 abort2: 569 release_firmware(fw); 570 571 return ret; 572 } 573 574 static int wm0010_boot(struct snd_soc_codec *codec) 575 { 576 struct spi_device *spi = to_spi_device(codec->dev); 577 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 578 unsigned long flags; 579 int ret; 580 struct spi_message m; 581 struct spi_transfer t; 582 struct dfw_pllrec pll_rec; 583 u32 *p, len; 584 u64 *img_swap; 585 u8 *out; 586 int i; 587 588 spin_lock_irqsave(&wm0010->irq_lock, flags); 589 if (wm0010->state != WM0010_POWER_OFF) 590 dev_warn(wm0010->dev, "DSP already powered up!\n"); 591 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 592 593 if (wm0010->sysclk > 26000000) { 594 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n"); 595 ret = -ECANCELED; 596 goto err; 597 } 598 599 mutex_lock(&wm0010->lock); 600 wm0010->pll_running = false; 601 602 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 603 604 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 605 wm0010->core_supplies); 606 if (ret != 0) { 607 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 608 ret); 609 mutex_unlock(&wm0010->lock); 610 goto err; 611 } 612 613 ret = regulator_enable(wm0010->dbvdd); 614 if (ret != 0) { 615 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 616 goto err_core; 617 } 618 619 /* Release reset */ 620 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value); 621 spin_lock_irqsave(&wm0010->irq_lock, flags); 622 wm0010->state = WM0010_OUT_OF_RESET; 623 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 624 625 if (!wait_for_completion_timeout(&wm0010->boot_completion, 626 msecs_to_jiffies(20))) 627 dev_err(codec->dev, "Failed to get interrupt from DSP\n"); 628 629 spin_lock_irqsave(&wm0010->irq_lock, flags); 630 wm0010->state = WM0010_BOOTROM; 631 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 632 633 ret = wm0010_stage2_load(codec); 634 if (ret) 635 goto abort; 636 637 if (!wait_for_completion_timeout(&wm0010->boot_completion, 638 msecs_to_jiffies(20))) 639 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n"); 640 641 spin_lock_irqsave(&wm0010->irq_lock, flags); 642 wm0010->state = WM0010_STAGE2; 643 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 644 645 /* Only initialise PLL if max_spi_freq initialised */ 646 if (wm0010->max_spi_freq) { 647 648 /* Initialise a PLL record */ 649 memset(&pll_rec, 0, sizeof(pll_rec)); 650 pll_rec.command = DFW_CMD_PLL; 651 pll_rec.length = (sizeof(pll_rec) - 8); 652 653 /* On wm0010 only the CLKCTRL1 value is used */ 654 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 655 656 ret = -ENOMEM; 657 len = pll_rec.length + 8; 658 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 659 if (!out) { 660 dev_err(codec->dev, 661 "Failed to allocate RX buffer\n"); 662 goto abort; 663 } 664 665 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA); 666 if (!img_swap) 667 goto abort_out; 668 669 /* We need to re-order for 0010 */ 670 byte_swap_64((u64 *)&pll_rec, img_swap, len); 671 672 spi_message_init(&m); 673 memset(&t, 0, sizeof(t)); 674 t.rx_buf = out; 675 t.tx_buf = img_swap; 676 t.len = len; 677 t.bits_per_word = 8; 678 t.speed_hz = wm0010->sysclk / 6; 679 spi_message_add_tail(&t, &m); 680 681 ret = spi_sync(spi, &m); 682 if (ret) { 683 dev_err(codec->dev, "First PLL write failed: %d\n", ret); 684 goto abort_swap; 685 } 686 687 /* Use a second send of the message to get the return status */ 688 ret = spi_sync(spi, &m); 689 if (ret) { 690 dev_err(codec->dev, "Second PLL write failed: %d\n", ret); 691 goto abort_swap; 692 } 693 694 p = (u32 *)out; 695 696 /* Look for PLL active code from the DSP */ 697 for (i = 0; i < len / 4; i++) { 698 if (*p == 0x0e00ed0f) { 699 dev_dbg(codec->dev, "PLL packet received\n"); 700 wm0010->pll_running = true; 701 break; 702 } 703 p++; 704 } 705 706 kfree(img_swap); 707 kfree(out); 708 } else 709 dev_dbg(codec->dev, "Not enabling DSP PLL."); 710 711 ret = wm0010_firmware_load("wm0010.dfw", codec); 712 713 if (ret != 0) 714 goto abort; 715 716 spin_lock_irqsave(&wm0010->irq_lock, flags); 717 wm0010->state = WM0010_FIRMWARE; 718 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 719 720 mutex_unlock(&wm0010->lock); 721 722 return 0; 723 724 abort_swap: 725 kfree(img_swap); 726 abort_out: 727 kfree(out); 728 abort: 729 /* Put the chip back into reset */ 730 wm0010_halt(codec); 731 mutex_unlock(&wm0010->lock); 732 return ret; 733 734 err_core: 735 mutex_unlock(&wm0010->lock); 736 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 737 wm0010->core_supplies); 738 err: 739 return ret; 740 } 741 742 static int wm0010_set_bias_level(struct snd_soc_codec *codec, 743 enum snd_soc_bias_level level) 744 { 745 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 746 747 switch (level) { 748 case SND_SOC_BIAS_ON: 749 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE) 750 wm0010_boot(codec); 751 break; 752 case SND_SOC_BIAS_PREPARE: 753 break; 754 case SND_SOC_BIAS_STANDBY: 755 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE) { 756 mutex_lock(&wm0010->lock); 757 wm0010_halt(codec); 758 mutex_unlock(&wm0010->lock); 759 } 760 break; 761 case SND_SOC_BIAS_OFF: 762 break; 763 } 764 765 return 0; 766 } 767 768 static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source, 769 int clk_id, unsigned int freq, int dir) 770 { 771 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 772 unsigned int i; 773 774 wm0010->sysclk = freq; 775 776 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 777 wm0010->max_spi_freq = 0; 778 } else { 779 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 780 if (freq >= pll_clock_map[i].max_sysclk) { 781 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 782 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 783 break; 784 } 785 } 786 787 return 0; 788 } 789 790 static int wm0010_probe(struct snd_soc_codec *codec); 791 792 static struct snd_soc_codec_driver soc_codec_dev_wm0010 = { 793 .probe = wm0010_probe, 794 .set_bias_level = wm0010_set_bias_level, 795 .set_sysclk = wm0010_set_sysclk, 796 .idle_bias_off = true, 797 798 .dapm_widgets = wm0010_dapm_widgets, 799 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 800 .dapm_routes = wm0010_dapm_routes, 801 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 802 }; 803 804 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 805 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 806 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 807 SNDRV_PCM_FMTBIT_S32_LE) 808 809 static struct snd_soc_dai_driver wm0010_dai[] = { 810 { 811 .name = "wm0010-sdi1", 812 .playback = { 813 .stream_name = "SDI1 Playback", 814 .channels_min = 1, 815 .channels_max = 2, 816 .rates = WM0010_RATES, 817 .formats = WM0010_FORMATS, 818 }, 819 .capture = { 820 .stream_name = "SDI1 Capture", 821 .channels_min = 1, 822 .channels_max = 2, 823 .rates = WM0010_RATES, 824 .formats = WM0010_FORMATS, 825 }, 826 }, 827 { 828 .name = "wm0010-sdi2", 829 .playback = { 830 .stream_name = "SDI2 Playback", 831 .channels_min = 1, 832 .channels_max = 2, 833 .rates = WM0010_RATES, 834 .formats = WM0010_FORMATS, 835 }, 836 .capture = { 837 .stream_name = "SDI2 Capture", 838 .channels_min = 1, 839 .channels_max = 2, 840 .rates = WM0010_RATES, 841 .formats = WM0010_FORMATS, 842 }, 843 }, 844 }; 845 846 static irqreturn_t wm0010_irq(int irq, void *data) 847 { 848 struct wm0010_priv *wm0010 = data; 849 850 switch (wm0010->state) { 851 case WM0010_OUT_OF_RESET: 852 case WM0010_BOOTROM: 853 case WM0010_STAGE2: 854 spin_lock(&wm0010->irq_lock); 855 complete(&wm0010->boot_completion); 856 spin_unlock(&wm0010->irq_lock); 857 return IRQ_HANDLED; 858 default: 859 return IRQ_NONE; 860 } 861 862 return IRQ_NONE; 863 } 864 865 static int wm0010_probe(struct snd_soc_codec *codec) 866 { 867 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 868 869 wm0010->codec = codec; 870 871 return 0; 872 } 873 874 static int wm0010_spi_probe(struct spi_device *spi) 875 { 876 unsigned long gpio_flags; 877 int ret; 878 int trigger; 879 int irq; 880 struct wm0010_priv *wm0010; 881 882 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 883 GFP_KERNEL); 884 if (!wm0010) 885 return -ENOMEM; 886 887 mutex_init(&wm0010->lock); 888 spin_lock_init(&wm0010->irq_lock); 889 890 spi_set_drvdata(spi, wm0010); 891 wm0010->dev = &spi->dev; 892 893 if (dev_get_platdata(&spi->dev)) 894 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 895 sizeof(wm0010->pdata)); 896 897 init_completion(&wm0010->boot_completion); 898 899 wm0010->core_supplies[0].supply = "AVDD"; 900 wm0010->core_supplies[1].supply = "DCVDD"; 901 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 902 wm0010->core_supplies); 903 if (ret != 0) { 904 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 905 ret); 906 return ret; 907 } 908 909 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 910 if (IS_ERR(wm0010->dbvdd)) { 911 ret = PTR_ERR(wm0010->dbvdd); 912 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 913 return ret; 914 } 915 916 if (wm0010->pdata.gpio_reset) { 917 wm0010->gpio_reset = wm0010->pdata.gpio_reset; 918 919 if (wm0010->pdata.reset_active_high) 920 wm0010->gpio_reset_value = 1; 921 else 922 wm0010->gpio_reset_value = 0; 923 924 if (wm0010->gpio_reset_value) 925 gpio_flags = GPIOF_OUT_INIT_HIGH; 926 else 927 gpio_flags = GPIOF_OUT_INIT_LOW; 928 929 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset, 930 gpio_flags, "wm0010 reset"); 931 if (ret < 0) { 932 dev_err(wm0010->dev, 933 "Failed to request GPIO for DSP reset: %d\n", 934 ret); 935 return ret; 936 } 937 } else { 938 dev_err(wm0010->dev, "No reset GPIO configured\n"); 939 return -EINVAL; 940 } 941 942 wm0010->state = WM0010_POWER_OFF; 943 944 irq = spi->irq; 945 if (wm0010->pdata.irq_flags) 946 trigger = wm0010->pdata.irq_flags; 947 else 948 trigger = IRQF_TRIGGER_FALLING; 949 trigger |= IRQF_ONESHOT; 950 951 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger, 952 "wm0010", wm0010); 953 if (ret) { 954 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 955 irq, ret); 956 return ret; 957 } 958 wm0010->irq = irq; 959 960 ret = irq_set_irq_wake(irq, 1); 961 if (ret) { 962 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", 963 irq, ret); 964 return ret; 965 } 966 967 if (spi->max_speed_hz) 968 wm0010->board_max_spi_speed = spi->max_speed_hz; 969 else 970 wm0010->board_max_spi_speed = 0; 971 972 ret = snd_soc_register_codec(&spi->dev, 973 &soc_codec_dev_wm0010, wm0010_dai, 974 ARRAY_SIZE(wm0010_dai)); 975 if (ret < 0) 976 return ret; 977 978 return 0; 979 } 980 981 static int wm0010_spi_remove(struct spi_device *spi) 982 { 983 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 984 985 snd_soc_unregister_codec(&spi->dev); 986 987 gpio_set_value_cansleep(wm0010->gpio_reset, 988 wm0010->gpio_reset_value); 989 990 irq_set_irq_wake(wm0010->irq, 0); 991 992 if (wm0010->irq) 993 free_irq(wm0010->irq, wm0010); 994 995 return 0; 996 } 997 998 static struct spi_driver wm0010_spi_driver = { 999 .driver = { 1000 .name = "wm0010", 1001 .owner = THIS_MODULE, 1002 }, 1003 .probe = wm0010_spi_probe, 1004 .remove = wm0010_spi_remove, 1005 }; 1006 1007 module_spi_driver(wm0010_spi_driver); 1008 1009 MODULE_DESCRIPTION("ASoC WM0010 driver"); 1010 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1011 MODULE_LICENSE("GPL"); 1012