1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm0010.c -- WM0010 DSP Driver 4 * 5 * Copyright 2012 Wolfson Microelectronics PLC. 6 * 7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 9 * Scott Ling <sl@opensource.wolfsonmicro.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqreturn.h> 16 #include <linux/init.h> 17 #include <linux/spi/spi.h> 18 #include <linux/firmware.h> 19 #include <linux/delay.h> 20 #include <linux/fs.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/mutex.h> 24 #include <linux/workqueue.h> 25 26 #include <sound/soc.h> 27 #include <sound/wm0010.h> 28 29 #define DEVICE_ID_WM0010 10 30 31 /* We only support v1 of the .dfw INFO record */ 32 #define INFO_VERSION 1 33 34 enum dfw_cmd { 35 DFW_CMD_FUSE = 0x01, 36 DFW_CMD_CODE_HDR, 37 DFW_CMD_CODE_DATA, 38 DFW_CMD_PLL, 39 DFW_CMD_INFO = 0xff 40 }; 41 42 struct dfw_binrec { 43 u8 command; 44 u32 length:24; 45 u32 address; 46 uint8_t data[]; 47 } __packed; 48 49 struct dfw_inforec { 50 u8 info_version; 51 u8 tool_major_version; 52 u8 tool_minor_version; 53 u8 dsp_target; 54 }; 55 56 struct dfw_pllrec { 57 u8 command; 58 u32 length:24; 59 u32 address; 60 u32 clkctrl1; 61 u32 clkctrl2; 62 u32 clkctrl3; 63 u32 ldetctrl; 64 u32 uart_div; 65 u32 spi_div; 66 } __packed; 67 68 static struct pll_clock_map { 69 int max_sysclk; 70 int max_pll_spi_speed; 71 u32 pll_clkctrl1; 72 } pll_clock_map[] = { /* Dividers */ 73 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 74 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 75 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 76 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 77 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 78 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 79 }; 80 81 enum wm0010_state { 82 WM0010_POWER_OFF, 83 WM0010_OUT_OF_RESET, 84 WM0010_BOOTROM, 85 WM0010_STAGE2, 86 WM0010_FIRMWARE, 87 }; 88 89 struct wm0010_priv { 90 struct snd_soc_component *component; 91 92 struct mutex lock; 93 struct device *dev; 94 95 struct wm0010_pdata pdata; 96 97 struct gpio_desc *reset; 98 99 struct regulator_bulk_data core_supplies[2]; 100 struct regulator *dbvdd; 101 102 int sysclk; 103 104 enum wm0010_state state; 105 bool boot_failed; 106 bool ready; 107 bool pll_running; 108 int max_spi_freq; 109 int board_max_spi_speed; 110 u32 pll_clkctrl1; 111 112 spinlock_t irq_lock; 113 int irq; 114 115 struct completion boot_completion; 116 }; 117 118 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 119 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 120 }; 121 122 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 123 { "SDI2 Capture", NULL, "SDI1 Playback" }, 124 { "SDI1 Capture", NULL, "SDI2 Playback" }, 125 126 { "SDI1 Capture", NULL, "CLKIN" }, 127 { "SDI2 Capture", NULL, "CLKIN" }, 128 { "SDI1 Playback", NULL, "CLKIN" }, 129 { "SDI2 Playback", NULL, "CLKIN" }, 130 }; 131 132 static const char *wm0010_state_to_str(enum wm0010_state state) 133 { 134 static const char * const state_to_str[] = { 135 "Power off", 136 "Out of reset", 137 "Boot ROM", 138 "Stage2", 139 "Firmware" 140 }; 141 142 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 143 return "null"; 144 return state_to_str[state]; 145 } 146 147 /* Called with wm0010->lock held */ 148 static void wm0010_halt(struct snd_soc_component *component) 149 { 150 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 151 unsigned long flags; 152 enum wm0010_state state; 153 154 /* Fetch the wm0010 state */ 155 spin_lock_irqsave(&wm0010->irq_lock, flags); 156 state = wm0010->state; 157 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 158 159 switch (state) { 160 case WM0010_POWER_OFF: 161 /* If there's nothing to do, bail out */ 162 return; 163 case WM0010_OUT_OF_RESET: 164 case WM0010_BOOTROM: 165 case WM0010_STAGE2: 166 case WM0010_FIRMWARE: 167 /* Remember to put chip back into reset */ 168 gpiod_set_value_cansleep(wm0010->reset, 1); 169 /* Disable the regulators */ 170 regulator_disable(wm0010->dbvdd); 171 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 172 wm0010->core_supplies); 173 break; 174 } 175 176 spin_lock_irqsave(&wm0010->irq_lock, flags); 177 wm0010->state = WM0010_POWER_OFF; 178 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 179 } 180 181 struct wm0010_boot_xfer { 182 struct list_head list; 183 struct snd_soc_component *component; 184 struct completion *done; 185 struct spi_message m; 186 struct spi_transfer t; 187 }; 188 189 /* Called with wm0010->lock held */ 190 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 191 { 192 enum wm0010_state state; 193 unsigned long flags; 194 195 spin_lock_irqsave(&wm0010->irq_lock, flags); 196 state = wm0010->state; 197 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 198 199 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 200 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 201 202 wm0010->boot_failed = true; 203 } 204 205 static void wm0010_boot_xfer_complete(void *data) 206 { 207 struct wm0010_boot_xfer *xfer = data; 208 struct snd_soc_component *component = xfer->component; 209 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 210 u32 *out32 = xfer->t.rx_buf; 211 int i; 212 213 if (xfer->m.status != 0) { 214 dev_err(component->dev, "SPI transfer failed: %d\n", 215 xfer->m.status); 216 wm0010_mark_boot_failure(wm0010); 217 if (xfer->done) 218 complete(xfer->done); 219 return; 220 } 221 222 for (i = 0; i < xfer->t.len / 4; i++) { 223 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]); 224 225 switch (be32_to_cpu(out32[i])) { 226 case 0xe0e0e0e0: 227 dev_err(component->dev, 228 "%d: ROM error reported in stage 2\n", i); 229 wm0010_mark_boot_failure(wm0010); 230 break; 231 232 case 0x55555555: 233 if (wm0010->state < WM0010_STAGE2) 234 break; 235 dev_err(component->dev, 236 "%d: ROM bootloader running in stage 2\n", i); 237 wm0010_mark_boot_failure(wm0010); 238 break; 239 240 case 0x0fed0000: 241 dev_dbg(component->dev, "Stage2 loader running\n"); 242 break; 243 244 case 0x0fed0007: 245 dev_dbg(component->dev, "CODE_HDR packet received\n"); 246 break; 247 248 case 0x0fed0008: 249 dev_dbg(component->dev, "CODE_DATA packet received\n"); 250 break; 251 252 case 0x0fed0009: 253 dev_dbg(component->dev, "Download complete\n"); 254 break; 255 256 case 0x0fed000c: 257 dev_dbg(component->dev, "Application start\n"); 258 break; 259 260 case 0x0fed000e: 261 dev_dbg(component->dev, "PLL packet received\n"); 262 wm0010->pll_running = true; 263 break; 264 265 case 0x0fed0025: 266 dev_err(component->dev, "Device reports image too long\n"); 267 wm0010_mark_boot_failure(wm0010); 268 break; 269 270 case 0x0fed002c: 271 dev_err(component->dev, "Device reports bad SPI packet\n"); 272 wm0010_mark_boot_failure(wm0010); 273 break; 274 275 case 0x0fed0031: 276 dev_err(component->dev, "Device reports SPI read overflow\n"); 277 wm0010_mark_boot_failure(wm0010); 278 break; 279 280 case 0x0fed0032: 281 dev_err(component->dev, "Device reports SPI underclock\n"); 282 wm0010_mark_boot_failure(wm0010); 283 break; 284 285 case 0x0fed0033: 286 dev_err(component->dev, "Device reports bad header packet\n"); 287 wm0010_mark_boot_failure(wm0010); 288 break; 289 290 case 0x0fed0034: 291 dev_err(component->dev, "Device reports invalid packet type\n"); 292 wm0010_mark_boot_failure(wm0010); 293 break; 294 295 case 0x0fed0035: 296 dev_err(component->dev, "Device reports data before header error\n"); 297 wm0010_mark_boot_failure(wm0010); 298 break; 299 300 case 0x0fed0038: 301 dev_err(component->dev, "Device reports invalid PLL packet\n"); 302 break; 303 304 case 0x0fed003a: 305 dev_err(component->dev, "Device reports packet alignment error\n"); 306 wm0010_mark_boot_failure(wm0010); 307 break; 308 309 default: 310 dev_err(component->dev, "Unrecognised return 0x%x\n", 311 be32_to_cpu(out32[i])); 312 wm0010_mark_boot_failure(wm0010); 313 break; 314 } 315 316 if (wm0010->boot_failed) 317 break; 318 } 319 320 if (xfer->done) 321 complete(xfer->done); 322 } 323 324 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 325 { 326 int i; 327 328 for (i = 0; i < len / 8; i++) 329 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i])); 330 } 331 332 static int wm0010_firmware_load(const char *name, struct snd_soc_component *component) 333 { 334 struct spi_device *spi = to_spi_device(component->dev); 335 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 336 struct list_head xfer_list; 337 struct wm0010_boot_xfer *xfer; 338 int ret; 339 DECLARE_COMPLETION_ONSTACK(done); 340 const struct firmware *fw; 341 const struct dfw_binrec *rec; 342 const struct dfw_inforec *inforec; 343 u64 *img; 344 u8 *out, dsp; 345 u32 len, offset; 346 347 INIT_LIST_HEAD(&xfer_list); 348 349 ret = request_firmware(&fw, name, component->dev); 350 if (ret != 0) { 351 dev_err(component->dev, "Failed to request application(%s): %d\n", 352 name, ret); 353 return ret; 354 } 355 356 rec = (const struct dfw_binrec *)fw->data; 357 inforec = (const struct dfw_inforec *)rec->data; 358 offset = 0; 359 dsp = inforec->dsp_target; 360 wm0010->boot_failed = false; 361 if (WARN_ON(!list_empty(&xfer_list))) 362 return -EINVAL; 363 364 /* First record should be INFO */ 365 if (rec->command != DFW_CMD_INFO) { 366 dev_err(component->dev, "First record not INFO\r\n"); 367 ret = -EINVAL; 368 goto abort; 369 } 370 371 if (inforec->info_version != INFO_VERSION) { 372 dev_err(component->dev, 373 "Unsupported version (%02d) of INFO record\r\n", 374 inforec->info_version); 375 ret = -EINVAL; 376 goto abort; 377 } 378 379 dev_dbg(component->dev, "Version v%02d INFO record found\r\n", 380 inforec->info_version); 381 382 /* Check it's a DSP file */ 383 if (dsp != DEVICE_ID_WM0010) { 384 dev_err(component->dev, "Not a WM0010 firmware file.\r\n"); 385 ret = -EINVAL; 386 goto abort; 387 } 388 389 /* Skip the info record as we don't need to send it */ 390 offset += ((rec->length) + 8); 391 rec = (void *)&rec->data[rec->length]; 392 393 while (offset < fw->size) { 394 dev_dbg(component->dev, 395 "Packet: command %d, data length = 0x%x\r\n", 396 rec->command, rec->length); 397 len = rec->length + 8; 398 399 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL); 400 if (!xfer) { 401 ret = -ENOMEM; 402 goto abort; 403 } 404 405 xfer->component = component; 406 list_add_tail(&xfer->list, &xfer_list); 407 408 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 409 if (!out) { 410 ret = -ENOMEM; 411 goto abort1; 412 } 413 xfer->t.rx_buf = out; 414 415 img = kzalloc(len, GFP_KERNEL | GFP_DMA); 416 if (!img) { 417 ret = -ENOMEM; 418 goto abort1; 419 } 420 xfer->t.tx_buf = img; 421 422 byte_swap_64((u64 *)&rec->command, img, len); 423 424 spi_message_init(&xfer->m); 425 xfer->m.complete = wm0010_boot_xfer_complete; 426 xfer->m.context = xfer; 427 xfer->t.len = len; 428 xfer->t.bits_per_word = 8; 429 430 if (!wm0010->pll_running) { 431 xfer->t.speed_hz = wm0010->sysclk / 6; 432 } else { 433 xfer->t.speed_hz = wm0010->max_spi_freq; 434 435 if (wm0010->board_max_spi_speed && 436 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 437 xfer->t.speed_hz = wm0010->board_max_spi_speed; 438 } 439 440 /* Store max usable spi frequency for later use */ 441 wm0010->max_spi_freq = xfer->t.speed_hz; 442 443 spi_message_add_tail(&xfer->t, &xfer->m); 444 445 offset += ((rec->length) + 8); 446 rec = (void *)&rec->data[rec->length]; 447 448 if (offset >= fw->size) { 449 dev_dbg(component->dev, "All transfers scheduled\n"); 450 xfer->done = &done; 451 } 452 453 ret = spi_async(spi, &xfer->m); 454 if (ret != 0) { 455 dev_err(component->dev, "Write failed: %d\n", ret); 456 goto abort1; 457 } 458 459 if (wm0010->boot_failed) { 460 dev_dbg(component->dev, "Boot fail!\n"); 461 ret = -EINVAL; 462 goto abort1; 463 } 464 } 465 466 wait_for_completion(&done); 467 468 ret = 0; 469 470 abort1: 471 while (!list_empty(&xfer_list)) { 472 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 473 list); 474 kfree(xfer->t.rx_buf); 475 kfree(xfer->t.tx_buf); 476 list_del(&xfer->list); 477 kfree(xfer); 478 } 479 480 abort: 481 release_firmware(fw); 482 return ret; 483 } 484 485 static int wm0010_stage2_load(struct snd_soc_component *component) 486 { 487 struct spi_device *spi = to_spi_device(component->dev); 488 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 489 const struct firmware *fw; 490 struct spi_message m; 491 struct spi_transfer t; 492 u32 *img; 493 u8 *out; 494 int i; 495 int ret = 0; 496 497 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev); 498 if (ret != 0) { 499 dev_err(component->dev, "Failed to request stage2 loader: %d\n", 500 ret); 501 return ret; 502 } 503 504 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 505 506 /* Copy to local buffer first as vmalloc causes problems for dma */ 507 img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA); 508 if (!img) { 509 ret = -ENOMEM; 510 goto abort2; 511 } 512 513 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA); 514 if (!out) { 515 ret = -ENOMEM; 516 goto abort1; 517 } 518 519 spi_message_init(&m); 520 memset(&t, 0, sizeof(t)); 521 t.rx_buf = out; 522 t.tx_buf = img; 523 t.len = fw->size; 524 t.bits_per_word = 8; 525 t.speed_hz = wm0010->sysclk / 10; 526 spi_message_add_tail(&t, &m); 527 528 dev_dbg(component->dev, "Starting initial download at %dHz\n", 529 t.speed_hz); 530 531 ret = spi_sync(spi, &m); 532 if (ret != 0) { 533 dev_err(component->dev, "Initial download failed: %d\n", ret); 534 goto abort; 535 } 536 537 /* Look for errors from the boot ROM */ 538 for (i = 0; i < fw->size; i++) { 539 if (out[i] != 0x55) { 540 dev_err(component->dev, "Boot ROM error: %x in %d\n", 541 out[i], i); 542 wm0010_mark_boot_failure(wm0010); 543 ret = -EBUSY; 544 goto abort; 545 } 546 } 547 abort: 548 kfree(out); 549 abort1: 550 kfree(img); 551 abort2: 552 release_firmware(fw); 553 554 return ret; 555 } 556 557 static int wm0010_boot(struct snd_soc_component *component) 558 { 559 struct spi_device *spi = to_spi_device(component->dev); 560 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 561 unsigned long flags; 562 int ret; 563 struct spi_message m; 564 struct spi_transfer t; 565 struct dfw_pllrec pll_rec; 566 u32 *p, len; 567 u64 *img_swap; 568 u8 *out; 569 int i; 570 571 spin_lock_irqsave(&wm0010->irq_lock, flags); 572 if (wm0010->state != WM0010_POWER_OFF) 573 dev_warn(wm0010->dev, "DSP already powered up!\n"); 574 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 575 576 if (wm0010->sysclk > 26000000) { 577 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n"); 578 ret = -ECANCELED; 579 goto err; 580 } 581 582 mutex_lock(&wm0010->lock); 583 wm0010->pll_running = false; 584 585 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 586 587 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 588 wm0010->core_supplies); 589 if (ret != 0) { 590 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 591 ret); 592 mutex_unlock(&wm0010->lock); 593 goto err; 594 } 595 596 ret = regulator_enable(wm0010->dbvdd); 597 if (ret != 0) { 598 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 599 goto err_core; 600 } 601 602 /* Release reset */ 603 gpiod_set_value_cansleep(wm0010->reset, 0); 604 spin_lock_irqsave(&wm0010->irq_lock, flags); 605 wm0010->state = WM0010_OUT_OF_RESET; 606 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 607 608 if (!wait_for_completion_timeout(&wm0010->boot_completion, 609 msecs_to_jiffies(20))) 610 dev_err(component->dev, "Failed to get interrupt from DSP\n"); 611 612 spin_lock_irqsave(&wm0010->irq_lock, flags); 613 wm0010->state = WM0010_BOOTROM; 614 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 615 616 ret = wm0010_stage2_load(component); 617 if (ret) 618 goto abort; 619 620 if (!wait_for_completion_timeout(&wm0010->boot_completion, 621 msecs_to_jiffies(20))) 622 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n"); 623 624 spin_lock_irqsave(&wm0010->irq_lock, flags); 625 wm0010->state = WM0010_STAGE2; 626 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 627 628 /* Only initialise PLL if max_spi_freq initialised */ 629 if (wm0010->max_spi_freq) { 630 631 /* Initialise a PLL record */ 632 memset(&pll_rec, 0, sizeof(pll_rec)); 633 pll_rec.command = DFW_CMD_PLL; 634 pll_rec.length = (sizeof(pll_rec) - 8); 635 636 /* On wm0010 only the CLKCTRL1 value is used */ 637 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 638 639 ret = -ENOMEM; 640 len = pll_rec.length + 8; 641 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 642 if (!out) 643 goto abort; 644 645 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA); 646 if (!img_swap) 647 goto abort_out; 648 649 /* We need to re-order for 0010 */ 650 byte_swap_64((u64 *)&pll_rec, img_swap, len); 651 652 spi_message_init(&m); 653 memset(&t, 0, sizeof(t)); 654 t.rx_buf = out; 655 t.tx_buf = img_swap; 656 t.len = len; 657 t.bits_per_word = 8; 658 t.speed_hz = wm0010->sysclk / 6; 659 spi_message_add_tail(&t, &m); 660 661 ret = spi_sync(spi, &m); 662 if (ret) { 663 dev_err(component->dev, "First PLL write failed: %d\n", ret); 664 goto abort_swap; 665 } 666 667 /* Use a second send of the message to get the return status */ 668 ret = spi_sync(spi, &m); 669 if (ret) { 670 dev_err(component->dev, "Second PLL write failed: %d\n", ret); 671 goto abort_swap; 672 } 673 674 p = (u32 *)out; 675 676 /* Look for PLL active code from the DSP */ 677 for (i = 0; i < len / 4; i++) { 678 if (*p == 0x0e00ed0f) { 679 dev_dbg(component->dev, "PLL packet received\n"); 680 wm0010->pll_running = true; 681 break; 682 } 683 p++; 684 } 685 686 kfree(img_swap); 687 kfree(out); 688 } else 689 dev_dbg(component->dev, "Not enabling DSP PLL."); 690 691 ret = wm0010_firmware_load("wm0010.dfw", component); 692 693 if (ret != 0) 694 goto abort; 695 696 spin_lock_irqsave(&wm0010->irq_lock, flags); 697 wm0010->state = WM0010_FIRMWARE; 698 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 699 700 mutex_unlock(&wm0010->lock); 701 702 return 0; 703 704 abort_swap: 705 kfree(img_swap); 706 abort_out: 707 kfree(out); 708 abort: 709 /* Put the chip back into reset */ 710 wm0010_halt(component); 711 mutex_unlock(&wm0010->lock); 712 return ret; 713 714 err_core: 715 mutex_unlock(&wm0010->lock); 716 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 717 wm0010->core_supplies); 718 err: 719 return ret; 720 } 721 722 static int wm0010_set_bias_level(struct snd_soc_component *component, 723 enum snd_soc_bias_level level) 724 { 725 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 726 727 switch (level) { 728 case SND_SOC_BIAS_ON: 729 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) 730 wm0010_boot(component); 731 break; 732 case SND_SOC_BIAS_PREPARE: 733 break; 734 case SND_SOC_BIAS_STANDBY: 735 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) { 736 mutex_lock(&wm0010->lock); 737 wm0010_halt(component); 738 mutex_unlock(&wm0010->lock); 739 } 740 break; 741 case SND_SOC_BIAS_OFF: 742 break; 743 } 744 745 return 0; 746 } 747 748 static int wm0010_set_sysclk(struct snd_soc_component *component, int source, 749 int clk_id, unsigned int freq, int dir) 750 { 751 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 752 unsigned int i; 753 754 wm0010->sysclk = freq; 755 756 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 757 wm0010->max_spi_freq = 0; 758 } else { 759 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 760 if (freq >= pll_clock_map[i].max_sysclk) { 761 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 762 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 763 break; 764 } 765 } 766 767 return 0; 768 } 769 770 static int wm0010_probe(struct snd_soc_component *component); 771 772 static const struct snd_soc_component_driver soc_component_dev_wm0010 = { 773 .probe = wm0010_probe, 774 .set_bias_level = wm0010_set_bias_level, 775 .set_sysclk = wm0010_set_sysclk, 776 .dapm_widgets = wm0010_dapm_widgets, 777 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 778 .dapm_routes = wm0010_dapm_routes, 779 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 780 .use_pmdown_time = 1, 781 .endianness = 1, 782 }; 783 784 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 785 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 786 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 787 SNDRV_PCM_FMTBIT_S32_LE) 788 789 static struct snd_soc_dai_driver wm0010_dai[] = { 790 { 791 .name = "wm0010-sdi1", 792 .playback = { 793 .stream_name = "SDI1 Playback", 794 .channels_min = 1, 795 .channels_max = 2, 796 .rates = WM0010_RATES, 797 .formats = WM0010_FORMATS, 798 }, 799 .capture = { 800 .stream_name = "SDI1 Capture", 801 .channels_min = 1, 802 .channels_max = 2, 803 .rates = WM0010_RATES, 804 .formats = WM0010_FORMATS, 805 }, 806 }, 807 { 808 .name = "wm0010-sdi2", 809 .playback = { 810 .stream_name = "SDI2 Playback", 811 .channels_min = 1, 812 .channels_max = 2, 813 .rates = WM0010_RATES, 814 .formats = WM0010_FORMATS, 815 }, 816 .capture = { 817 .stream_name = "SDI2 Capture", 818 .channels_min = 1, 819 .channels_max = 2, 820 .rates = WM0010_RATES, 821 .formats = WM0010_FORMATS, 822 }, 823 }, 824 }; 825 826 static irqreturn_t wm0010_irq(int irq, void *data) 827 { 828 struct wm0010_priv *wm0010 = data; 829 830 switch (wm0010->state) { 831 case WM0010_OUT_OF_RESET: 832 case WM0010_BOOTROM: 833 case WM0010_STAGE2: 834 spin_lock(&wm0010->irq_lock); 835 complete(&wm0010->boot_completion); 836 spin_unlock(&wm0010->irq_lock); 837 return IRQ_HANDLED; 838 default: 839 return IRQ_NONE; 840 } 841 842 return IRQ_NONE; 843 } 844 845 static int wm0010_probe(struct snd_soc_component *component) 846 { 847 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 848 849 wm0010->component = component; 850 851 return 0; 852 } 853 854 static int wm0010_spi_probe(struct spi_device *spi) 855 { 856 int ret; 857 int trigger; 858 int irq; 859 struct wm0010_priv *wm0010; 860 861 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 862 GFP_KERNEL); 863 if (!wm0010) 864 return -ENOMEM; 865 866 mutex_init(&wm0010->lock); 867 spin_lock_init(&wm0010->irq_lock); 868 869 spi_set_drvdata(spi, wm0010); 870 wm0010->dev = &spi->dev; 871 872 if (dev_get_platdata(&spi->dev)) 873 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 874 sizeof(wm0010->pdata)); 875 876 init_completion(&wm0010->boot_completion); 877 878 wm0010->core_supplies[0].supply = "AVDD"; 879 wm0010->core_supplies[1].supply = "DCVDD"; 880 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 881 wm0010->core_supplies); 882 if (ret != 0) { 883 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 884 ret); 885 return ret; 886 } 887 888 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 889 if (IS_ERR(wm0010->dbvdd)) { 890 ret = PTR_ERR(wm0010->dbvdd); 891 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 892 return ret; 893 } 894 895 wm0010->reset = devm_gpiod_get(wm0010->dev, "reset", GPIOD_OUT_HIGH); 896 if (IS_ERR(wm0010->reset)) 897 return dev_err_probe(wm0010->dev, PTR_ERR(wm0010->reset), 898 "could not get RESET GPIO\n"); 899 gpiod_set_consumer_name(wm0010->reset, "wm0010 reset"); 900 901 wm0010->state = WM0010_POWER_OFF; 902 903 irq = spi->irq; 904 if (wm0010->pdata.irq_flags) 905 trigger = wm0010->pdata.irq_flags; 906 else 907 trigger = IRQF_TRIGGER_FALLING; 908 trigger |= IRQF_ONESHOT; 909 910 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger, 911 "wm0010", wm0010); 912 if (ret) { 913 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 914 irq, ret); 915 return ret; 916 } 917 wm0010->irq = irq; 918 919 ret = irq_set_irq_wake(irq, 1); 920 if (ret) { 921 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", 922 irq, ret); 923 return ret; 924 } 925 926 if (spi->max_speed_hz) 927 wm0010->board_max_spi_speed = spi->max_speed_hz; 928 else 929 wm0010->board_max_spi_speed = 0; 930 931 ret = devm_snd_soc_register_component(&spi->dev, 932 &soc_component_dev_wm0010, wm0010_dai, 933 ARRAY_SIZE(wm0010_dai)); 934 if (ret < 0) 935 return ret; 936 937 return 0; 938 } 939 940 static void wm0010_spi_remove(struct spi_device *spi) 941 { 942 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 943 944 gpiod_set_value_cansleep(wm0010->reset, 1); 945 946 irq_set_irq_wake(wm0010->irq, 0); 947 948 if (wm0010->irq) 949 free_irq(wm0010->irq, wm0010); 950 } 951 952 static struct spi_driver wm0010_spi_driver = { 953 .driver = { 954 .name = "wm0010", 955 }, 956 .probe = wm0010_spi_probe, 957 .remove = wm0010_spi_remove, 958 }; 959 960 module_spi_driver(wm0010_spi_driver); 961 962 MODULE_DESCRIPTION("ASoC WM0010 driver"); 963 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 964 MODULE_LICENSE("GPL"); 965 966 MODULE_FIRMWARE("wm0010.dfw"); 967 MODULE_FIRMWARE("wm0010_stage2.bin"); 968