1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/platform_device.h> 11 #include <linux/cleanup.h> 12 #include <linux/device.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kernel.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/component.h> 18 #include <sound/tlv.h> 19 #include <linux/of_graph.h> 20 #include <linux/of.h> 21 #include <sound/jack.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <linux/regmap.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/usb/typec_mux.h> 29 #include <linux/usb/typec_altmode.h> 30 31 #include "wcd-clsh-v2.h" 32 #include "wcd-common.h" 33 #include "wcd-mbhc-v2.h" 34 #include "wcd939x.h" 35 36 #define WCD939X_MAX_MICBIAS (4) 37 #define WCD939X_MBHC_MAX_BUTTONS (8) 38 #define TX_ADC_MAX (4) 39 #define WCD_MBHC_HS_V_MAX 1600 40 41 #define CHIPID_WCD9390 0x0 42 #define CHIPID_WCD9395 0x5 43 44 /* Version major: 1.x */ 45 #define CHIPID_WCD939X_VER_MAJOR_1 0x0 46 /* Version minor: x.1 */ 47 #define CHIPID_WCD939X_VER_MINOR_1 0x3 48 49 enum { 50 WCD939X_VERSION_1_0 = 0, 51 WCD939X_VERSION_1_1, 52 WCD939X_VERSION_2_0, 53 }; 54 55 #define WCD939X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 56 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 57 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 58 SNDRV_PCM_RATE_384000) 59 /* Fractional Rates */ 60 #define WCD939X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 61 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 62 #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 63 SNDRV_PCM_FMTBIT_S24_LE |\ 64 SNDRV_PCM_FMTBIT_S24_3LE |\ 65 SNDRV_PCM_FMTBIT_S32_LE) 66 67 /* Convert from vout ctl to micbias voltage in mV */ 68 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + (v) * 50) 69 #define SWR_CLK_RATE_0P6MHZ (600000) 70 #define SWR_CLK_RATE_1P2MHZ (1200000) 71 #define SWR_CLK_RATE_2P4MHZ (2400000) 72 #define SWR_CLK_RATE_4P8MHZ (4800000) 73 #define SWR_CLK_RATE_9P6MHZ (9600000) 74 #define SWR_CLK_RATE_11P2896MHZ (1128960) 75 76 #define ADC_MODE_VAL_HIFI 0x01 77 #define ADC_MODE_VAL_LO_HIF 0x02 78 #define ADC_MODE_VAL_NORMAL 0x03 79 #define ADC_MODE_VAL_LP 0x05 80 #define ADC_MODE_VAL_ULP1 0x09 81 #define ADC_MODE_VAL_ULP2 0x0B 82 83 /* Z value defined in milliohm */ 84 #define WCD939X_ZDET_VAL_32 (32000) 85 #define WCD939X_ZDET_VAL_400 (400000) 86 #define WCD939X_ZDET_VAL_1200 (1200000) 87 #define WCD939X_ZDET_VAL_100K (100000000) 88 89 /* Z floating defined in ohms */ 90 #define WCD939X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 91 #define WCD939X_ZDET_NUM_MEASUREMENTS (900) 92 #define WCD939X_MBHC_GET_C1(c) (((c) & 0xC000) >> 14) 93 #define WCD939X_MBHC_GET_X1(x) ((x) & 0x3FFF) 94 95 /* Z value compared in milliOhm */ 96 #define WCD939X_ANA_MBHC_ZDET_CONST (1018 * 1024) 97 98 enum { 99 /* INTR_CTRL_INT_MASK_0 */ 100 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 101 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 102 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 103 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 104 WCD939X_IRQ_MBHC_SW_DET, 105 WCD939X_IRQ_HPHR_OCP_INT, 106 WCD939X_IRQ_HPHR_CNP_INT, 107 WCD939X_IRQ_HPHL_OCP_INT, 108 109 /* INTR_CTRL_INT_MASK_1 */ 110 WCD939X_IRQ_HPHL_CNP_INT, 111 WCD939X_IRQ_EAR_CNP_INT, 112 WCD939X_IRQ_EAR_SCD_INT, 113 WCD939X_IRQ_HPHL_PDM_WD_INT, 114 WCD939X_IRQ_HPHR_PDM_WD_INT, 115 WCD939X_IRQ_EAR_PDM_WD_INT, 116 117 /* INTR_CTRL_INT_MASK_2 */ 118 WCD939X_IRQ_MBHC_MOISTURE_INT, 119 WCD939X_IRQ_HPHL_SURGE_DET_INT, 120 WCD939X_IRQ_HPHR_SURGE_DET_INT, 121 WCD939X_NUM_IRQS, 122 }; 123 124 enum { 125 MICB_BIAS_DISABLE = 0, 126 MICB_BIAS_ENABLE, 127 MICB_BIAS_PULL_UP, 128 MICB_BIAS_PULL_DOWN, 129 }; 130 131 enum { 132 WCD_ADC1 = 0, 133 WCD_ADC2, 134 WCD_ADC3, 135 WCD_ADC4, 136 HPH_PA_DELAY, 137 }; 138 139 enum { 140 ADC_MODE_INVALID = 0, 141 ADC_MODE_HIFI, 142 ADC_MODE_LO_HIF, 143 ADC_MODE_NORMAL, 144 ADC_MODE_LP, 145 ADC_MODE_ULP1, 146 ADC_MODE_ULP2, 147 }; 148 149 enum { 150 AIF1_PB = 0, 151 AIF1_CAP, 152 NUM_CODEC_DAIS, 153 }; 154 155 static u8 tx_mode_bit[] = { 156 [ADC_MODE_INVALID] = 0x00, 157 [ADC_MODE_HIFI] = 0x01, 158 [ADC_MODE_LO_HIF] = 0x02, 159 [ADC_MODE_NORMAL] = 0x04, 160 [ADC_MODE_LP] = 0x08, 161 [ADC_MODE_ULP1] = 0x10, 162 [ADC_MODE_ULP2] = 0x20, 163 }; 164 165 struct zdet_param { 166 u16 ldo_ctl; 167 u16 noff; 168 u16 nshift; 169 u16 btn5; 170 u16 btn6; 171 u16 btn7; 172 }; 173 174 struct wcd939x_priv { 175 struct sdw_slave *tx_sdw_dev; 176 struct wcd939x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 177 struct device *txdev; 178 struct device *rxdev; 179 struct device_node *rxnode, *txnode; 180 struct regmap *regmap; 181 struct snd_soc_component *component; 182 /* micb setup lock */ 183 struct mutex micb_lock; 184 /* typec handling */ 185 bool typec_analog_mux; 186 #if IS_ENABLED(CONFIG_TYPEC) 187 enum typec_orientation typec_orientation; 188 unsigned long typec_mode; 189 struct typec_switch *typec_switch; 190 #endif /* CONFIG_TYPEC */ 191 /* mbhc module */ 192 struct wcd_mbhc *wcd_mbhc; 193 struct wcd_mbhc_config mbhc_cfg; 194 struct wcd_mbhc_intr intr_ids; 195 struct wcd_clsh_ctrl *clsh_info; 196 struct wcd_common common; 197 struct irq_domain *virq; 198 struct regmap_irq_chip_data *irq_chip; 199 struct snd_soc_jack *jack; 200 unsigned long status_mask; 201 s32 micb_ref[WCD939X_MAX_MICBIAS]; 202 s32 pullup_ref[WCD939X_MAX_MICBIAS]; 203 u32 hph_mode; 204 u32 tx_mode[TX_ADC_MAX]; 205 int variant; 206 struct gpio_desc *reset_gpio; 207 int hphr_pdm_wd_int; 208 int hphl_pdm_wd_int; 209 int ear_pdm_wd_int; 210 bool comp1_enable; 211 bool comp2_enable; 212 bool ldoh; 213 }; 214 215 static const char * const wcd939x_supplies[] = { 216 "vdd-rxtx", "vdd-io", "vdd-buck", "vdd-mic-bias", "vdd-px", 217 }; 218 219 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 220 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 221 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 222 223 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 224 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD939X_ANA_MBHC_MECH, 0x80), 225 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD939X_ANA_MBHC_MECH, 0x40), 226 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD939X_ANA_MBHC_MECH, 0x20), 227 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 228 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD939X_ANA_MBHC_ELECT, 0x08), 229 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 230 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD939X_ANA_MBHC_MECH, 0x04), 231 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x10), 232 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x08), 233 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD939X_ANA_MBHC_MECH, 0x01), 234 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD939X_ANA_MBHC_ELECT, 0x06), 235 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD939X_ANA_MBHC_ELECT, 0x80), 236 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 237 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD939X_MBHC_NEW_CTL_1, 0x03), 238 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD939X_MBHC_NEW_CTL_2, 0x03), 239 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x08), 240 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD939X_ANA_MBHC_RESULT_3, 0x10), 241 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x20), 242 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x80), 243 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x40), 244 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD939X_HPH_OCP_CTL, 0x10), 245 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x07), 246 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD939X_ANA_MBHC_ELECT, 0x70), 247 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0xFF), 248 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD939X_ANA_MICB2, 0xC0), 249 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD939X_HPH_CNP_WG_TIME, 0xFF), 250 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD939X_ANA_HPH, 0x40), 251 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD939X_ANA_HPH, 0x80), 252 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD939X_ANA_HPH, 0xC0), 253 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD939X_ANA_MBHC_RESULT_3, 0x10), 254 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD939X_MBHC_CTL_BCS, 0x02), 255 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x01), 256 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD939X_MBHC_NEW_CTL_2, 0x70), 257 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x20), 258 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD939X_HPH_PA_CTL2, 0x40), 259 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD939X_HPH_PA_CTL2, 0x10), 260 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD939X_HPH_L_TEST, 0x01), 261 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD939X_HPH_R_TEST, 0x01), 262 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x80), 263 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x20), 264 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD939X_MBHC_NEW_CTL_1, 0x08), 265 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD939X_MBHC_NEW_FSM_STATUS, 0x40), 266 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD939X_MBHC_NEW_FSM_STATUS, 0x80), 267 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD939X_MBHC_NEW_ADC_RESULT, 0xFF), 268 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD939X_ANA_MICB2, 0x3F), 269 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD939X_MBHC_NEW_CTL_1, 0x10), 270 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD939X_MBHC_NEW_CTL_1, 0x04), 271 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD939X_ANA_MBHC_ZDET, 0x02), 272 }; 273 274 static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = { 275 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 276 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 277 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 278 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 279 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10), 280 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20), 281 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40), 282 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80), 283 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01), 284 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02), 285 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04), 286 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 287 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 288 REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80), 289 REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 290 REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 291 REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 292 }; 293 294 static const struct regmap_irq_chip wcd939x_regmap_irq_chip = { 295 .name = "wcd939x", 296 .irqs = wcd939x_irqs, 297 .num_irqs = ARRAY_SIZE(wcd939x_irqs), 298 .num_regs = 3, 299 .status_base = WCD939X_DIGITAL_INTR_STATUS_0, 300 .mask_base = WCD939X_DIGITAL_INTR_MASK_0, 301 .ack_base = WCD939X_DIGITAL_INTR_CLEAR_0, 302 .use_ack = 1, 303 .runtime_pm = true, 304 .irq_drv_data = NULL, 305 }; 306 307 static int wcd939x_get_clk_rate(int mode) 308 { 309 int rate; 310 311 switch (mode) { 312 case ADC_MODE_ULP2: 313 rate = SWR_CLK_RATE_0P6MHZ; 314 break; 315 case ADC_MODE_ULP1: 316 rate = SWR_CLK_RATE_1P2MHZ; 317 break; 318 case ADC_MODE_LP: 319 rate = SWR_CLK_RATE_4P8MHZ; 320 break; 321 case ADC_MODE_NORMAL: 322 case ADC_MODE_LO_HIF: 323 case ADC_MODE_HIFI: 324 case ADC_MODE_INVALID: 325 default: 326 rate = SWR_CLK_RATE_9P6MHZ; 327 break; 328 } 329 330 return rate; 331 } 332 333 static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 334 { 335 u8 mask = (bank ? 0xF0 : 0x0F); 336 u8 val = 0; 337 338 switch (rate) { 339 case SWR_CLK_RATE_0P6MHZ: 340 val = 6; 341 break; 342 case SWR_CLK_RATE_1P2MHZ: 343 val = 5; 344 break; 345 case SWR_CLK_RATE_2P4MHZ: 346 val = 3; 347 break; 348 case SWR_CLK_RATE_4P8MHZ: 349 val = 1; 350 break; 351 case SWR_CLK_RATE_9P6MHZ: 352 default: 353 val = 0; 354 break; 355 } 356 357 snd_soc_component_write_field(component, WCD939X_DIGITAL_SWR_TX_CLK_RATE, mask, val); 358 359 return 0; 360 } 361 362 static int wcd939x_io_init(struct snd_soc_component *component) 363 { 364 snd_soc_component_write_field(component, WCD939X_ANA_BIAS, 365 WCD939X_BIAS_ANALOG_BIAS_EN, true); 366 snd_soc_component_write_field(component, WCD939X_ANA_BIAS, 367 WCD939X_BIAS_PRECHRG_EN, true); 368 369 /* 10 msec delay as per HW requirement */ 370 usleep_range(10000, 10010); 371 snd_soc_component_write_field(component, WCD939X_ANA_BIAS, 372 WCD939X_BIAS_PRECHRG_EN, false); 373 374 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L, 375 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x15); 376 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R, 377 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x15); 378 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL, 379 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true); 380 381 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP, 382 WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M, 1); 383 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP, 384 WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE, 4); 385 386 snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP, 387 WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE, 8); 388 389 snd_soc_component_write_field(component, WCD939X_MICB1_TEST_CTL_1, 390 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 391 snd_soc_component_write_field(component, WCD939X_MICB2_TEST_CTL_1, 392 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 393 snd_soc_component_write_field(component, WCD939X_MICB3_TEST_CTL_1, 394 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 395 snd_soc_component_write_field(component, WCD939X_MICB4_TEST_CTL_1, 396 WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7); 397 snd_soc_component_write_field(component, WCD939X_TX_3_4_TEST_BLK_EN2, 398 WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN, false); 399 400 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 401 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false); 402 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 403 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false); 404 405 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL, 406 WCD939X_OCP_CTL_OCP_FSM_EN, true); 407 snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL, 408 WCD939X_OCP_CTL_SCD_OP_EN, true); 409 410 snd_soc_component_write(component, WCD939X_E_CFG0, 411 WCD939X_CFG0_IDLE_STEREO | 412 WCD939X_CFG0_AUTO_DISABLE_ANC); 413 414 return 0; 415 } 416 417 static int wcd939x_sdw_connect_port(const struct wcd_sdw_ch_info *ch_info, 418 struct sdw_port_config *port_config, 419 u8 enable) 420 { 421 u8 ch_mask, port_num; 422 423 port_num = ch_info->port_num; 424 ch_mask = ch_info->ch_mask; 425 426 port_config->num = port_num; 427 428 if (enable) 429 port_config->ch_mask |= ch_mask; 430 else 431 port_config->ch_mask &= ~ch_mask; 432 433 return 0; 434 } 435 436 static int wcd939x_connect_port(struct wcd939x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 437 { 438 return wcd939x_sdw_connect_port(&wcd->ch_info[ch_id], 439 &wcd->port_config[port_num - 1], 440 enable); 441 } 442 443 static int wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 444 struct snd_kcontrol *kcontrol, 445 int event) 446 { 447 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 448 449 switch (event) { 450 case SND_SOC_DAPM_PRE_PMU: 451 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 452 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, true); 453 454 /* Analog path clock controls */ 455 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 456 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, true); 457 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 458 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN, 459 true); 460 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 461 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN, 462 true); 463 464 /* Digital path clock controls */ 465 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 466 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, true); 467 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 468 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, true); 469 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 470 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, true); 471 break; 472 case SND_SOC_DAPM_POST_PMD: 473 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 474 WCD939X_RX_SUPPLIES_VNEG_EN, false); 475 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 476 WCD939X_RX_SUPPLIES_VPOS_EN, false); 477 478 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 479 WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, false); 480 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 481 WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, false); 482 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 483 WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, false); 484 485 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 486 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN, 487 false); 488 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 489 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN, 490 false); 491 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 492 WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, false); 493 494 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 495 WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, false); 496 497 break; 498 } 499 500 return 0; 501 } 502 503 static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 504 struct snd_kcontrol *kcontrol, 505 int event) 506 { 507 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 508 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 509 510 switch (event) { 511 case SND_SOC_DAPM_PRE_PMU: 512 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1, 513 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN, 514 false); 515 516 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 517 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, true); 518 break; 519 case SND_SOC_DAPM_POST_PMU: 520 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L, 521 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x1d); 522 if (wcd939x->comp1_enable) { 523 snd_soc_component_write_field(component, 524 WCD939X_DIGITAL_CDC_COMP_CTL_0, 525 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN, 526 true); 527 /* 5msec compander delay as per HW requirement */ 528 if (!wcd939x->comp2_enable || 529 snd_soc_component_read_field(component, 530 WCD939X_DIGITAL_CDC_COMP_CTL_0, 531 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN)) 532 usleep_range(5000, 5010); 533 534 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 535 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, 536 false); 537 } else { 538 snd_soc_component_write_field(component, 539 WCD939X_DIGITAL_CDC_COMP_CTL_0, 540 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN, 541 false); 542 snd_soc_component_write_field(component, WCD939X_HPH_L_EN, 543 WCD939X_L_EN_GAIN_SOURCE_SEL, true); 544 } 545 break; 546 case SND_SOC_DAPM_POST_PMD: 547 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L, 548 WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 1); 549 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 550 WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, false); 551 break; 552 } 553 554 return 0; 555 } 556 557 static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 558 struct snd_kcontrol *kcontrol, 559 int event) 560 { 561 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 562 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 563 564 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__, 565 w->name, event); 566 567 switch (event) { 568 case SND_SOC_DAPM_PRE_PMU: 569 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1, 570 WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN, 571 false); 572 573 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 574 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, true); 575 break; 576 case SND_SOC_DAPM_POST_PMU: 577 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R, 578 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x1d); 579 if (wcd939x->comp2_enable) { 580 snd_soc_component_write_field(component, 581 WCD939X_DIGITAL_CDC_COMP_CTL_0, 582 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN, 583 true); 584 /* 5msec compander delay as per HW requirement */ 585 if (!wcd939x->comp1_enable || 586 snd_soc_component_read_field(component, 587 WCD939X_DIGITAL_CDC_COMP_CTL_0, 588 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN)) 589 usleep_range(5000, 5010); 590 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 591 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, 592 false); 593 } else { 594 snd_soc_component_write_field(component, 595 WCD939X_DIGITAL_CDC_COMP_CTL_0, 596 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN, 597 false); 598 snd_soc_component_write_field(component, WCD939X_HPH_R_EN, 599 WCD939X_R_EN_GAIN_SOURCE_SEL, true); 600 } 601 break; 602 case SND_SOC_DAPM_POST_PMD: 603 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R, 604 WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 1); 605 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL, 606 WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, false); 607 break; 608 } 609 610 return 0; 611 } 612 613 static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 614 struct snd_kcontrol *kcontrol, 615 int event) 616 { 617 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 618 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 619 620 switch (event) { 621 case SND_SOC_DAPM_PRE_PMU: 622 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_EAR_GAIN_CTL, 623 WCD939X_CDC_EAR_GAIN_CTL_EAR_EN, true); 624 625 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON, 626 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, false); 627 628 /* 5 msec delay as per HW requirement */ 629 usleep_range(5000, 5010); 630 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 631 WCD_CLSH_STATE_EAR, CLS_AB_HIFI); 632 633 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4, 634 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd); 635 break; 636 case SND_SOC_DAPM_POST_PMD: 637 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON, 638 WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, true); 639 break; 640 } 641 642 return 0; 643 } 644 645 static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 646 struct snd_kcontrol *kcontrol, 647 int event) 648 { 649 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 650 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 651 int hph_mode = wcd939x->hph_mode; 652 653 switch (event) { 654 case SND_SOC_DAPM_PRE_PMU: 655 if (wcd939x->ldoh) 656 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 657 WCD939X_MODE_LDOH_EN, true); 658 659 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 660 WCD_CLSH_STATE_HPHR, hph_mode); 661 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI); 662 663 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP) 664 snd_soc_component_write_field(component, 665 WCD939X_HPH_REFBUFF_LP_CTL, 666 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, true); 667 if (hph_mode == CLS_H_LOHIFI) 668 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 669 WCD939X_HPH_PWR_LEVEL, 0); 670 671 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4, 672 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd); 673 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 674 WCD939X_HPH_HPHR_REF_ENABLE, true); 675 676 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH, 677 WCD939X_HPH_HPHL_REF_ENABLE)) 678 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */ 679 680 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 681 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1, 682 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 3); 683 break; 684 case SND_SOC_DAPM_POST_PMU: 685 /* 686 * 7ms sleep is required if compander is enabled as per 687 * HW requirement. If compander is disabled, then 688 * 20ms delay is required. 689 */ 690 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 691 if (!wcd939x->comp2_enable) 692 usleep_range(20000, 20100); 693 else 694 usleep_range(7000, 7100); 695 696 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 697 hph_mode == CLS_H_ULP) 698 snd_soc_component_write_field(component, 699 WCD939X_HPH_REFBUFF_LP_CTL, 700 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, 701 false); 702 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 703 } 704 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 705 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true); 706 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 707 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 708 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 709 WCD939X_RX_SUPPLIES_REGULATOR_MODE, 710 true); 711 712 enable_irq(wcd939x->hphr_pdm_wd_int); 713 break; 714 case SND_SOC_DAPM_PRE_PMD: 715 disable_irq_nosync(wcd939x->hphr_pdm_wd_int); 716 /* 717 * 7ms sleep is required if compander is enabled as per 718 * HW requirement. If compander is disabled, then 719 * 20ms delay is required. 720 */ 721 if (!wcd939x->comp2_enable) 722 usleep_range(20000, 20100); 723 else 724 usleep_range(7000, 7100); 725 726 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 727 WCD939X_HPH_HPHR_ENABLE, false); 728 729 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 730 WCD_EVENT_PRE_HPHR_PA_OFF); 731 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 732 break; 733 case SND_SOC_DAPM_POST_PMD: 734 /* 735 * 7ms sleep is required if compander is enabled as per 736 * HW requirement. If compander is disabled, then 737 * 20ms delay is required. 738 */ 739 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 740 if (!wcd939x->comp2_enable) 741 usleep_range(20000, 20100); 742 else 743 usleep_range(7000, 7100); 744 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 745 } 746 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 747 WCD_EVENT_POST_HPHR_PA_OFF); 748 749 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 750 WCD939X_HPH_HPHR_REF_ENABLE, false); 751 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1, 752 WCD939X_PDM_WD_CTL1_PDM_WD_EN, 0); 753 754 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA, 755 WCD_CLSH_STATE_HPHR, hph_mode); 756 if (wcd939x->ldoh) 757 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 758 WCD939X_MODE_LDOH_EN, false); 759 break; 760 } 761 762 return 0; 763 } 764 765 static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 766 struct snd_kcontrol *kcontrol, 767 int event) 768 { 769 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 770 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 771 int hph_mode = wcd939x->hph_mode; 772 773 dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__, 774 w->name, event); 775 776 switch (event) { 777 case SND_SOC_DAPM_PRE_PMU: 778 if (wcd939x->ldoh) 779 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 780 WCD939X_MODE_LDOH_EN, true); 781 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 782 WCD_CLSH_STATE_HPHL, hph_mode); 783 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI); 784 785 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP) 786 snd_soc_component_write_field(component, 787 WCD939X_HPH_REFBUFF_LP_CTL, 788 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, 789 true); 790 if (hph_mode == CLS_H_LOHIFI) 791 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 792 WCD939X_HPH_PWR_LEVEL, 0); 793 794 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4, 795 WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd); 796 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 797 WCD939X_HPH_HPHL_REF_ENABLE, true); 798 799 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH, 800 WCD939X_HPH_HPHR_REF_ENABLE)) 801 usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */ 802 803 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 804 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 805 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3); 806 break; 807 case SND_SOC_DAPM_POST_PMU: 808 /* 809 * 7ms sleep is required if compander is enabled as per 810 * HW requirement. If compander is disabled, then 811 * 20ms delay is required. 812 */ 813 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 814 if (!wcd939x->comp1_enable) 815 usleep_range(20000, 20100); 816 else 817 usleep_range(7000, 7100); 818 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 819 hph_mode == CLS_H_ULP) 820 snd_soc_component_write_field(component, 821 WCD939X_HPH_REFBUFF_LP_CTL, 822 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, 823 false); 824 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 825 } 826 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1, 827 WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true); 828 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 829 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 830 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 831 WCD939X_RX_SUPPLIES_REGULATOR_MODE, 832 true); 833 enable_irq(wcd939x->hphl_pdm_wd_int); 834 break; 835 case SND_SOC_DAPM_PRE_PMD: 836 disable_irq_nosync(wcd939x->hphl_pdm_wd_int); 837 /* 838 * 7ms sleep is required if compander is enabled as per 839 * HW requirement. If compander is disabled, then 840 * 20ms delay is required. 841 */ 842 if (!wcd939x->comp1_enable) 843 usleep_range(20000, 20100); 844 else 845 usleep_range(7000, 7100); 846 847 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 848 WCD939X_HPH_HPHL_ENABLE, false); 849 850 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 851 set_bit(HPH_PA_DELAY, &wcd939x->status_mask); 852 break; 853 case SND_SOC_DAPM_POST_PMD: 854 /* 855 * 7ms sleep is required if compander is enabled as per 856 * HW requirement. If compander is disabled, then 857 * 20ms delay is required. 858 */ 859 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) { 860 if (!wcd939x->comp1_enable) 861 usleep_range(21000, 21100); 862 else 863 usleep_range(7000, 7100); 864 clear_bit(HPH_PA_DELAY, &wcd939x->status_mask); 865 } 866 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 867 WCD_EVENT_POST_HPHL_PA_OFF); 868 snd_soc_component_write_field(component, WCD939X_ANA_HPH, 869 WCD939X_HPH_HPHL_REF_ENABLE, false); 870 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 871 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0); 872 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA, 873 WCD_CLSH_STATE_HPHL, hph_mode); 874 if (wcd939x->ldoh) 875 snd_soc_component_write_field(component, WCD939X_LDOH_MODE, 876 WCD939X_MODE_LDOH_EN, false); 877 break; 878 } 879 880 return 0; 881 } 882 883 static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 884 struct snd_kcontrol *kcontrol, int event) 885 { 886 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 887 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 888 889 switch (event) { 890 case SND_SOC_DAPM_PRE_PMU: 891 /* Enable watchdog interrupt for HPHL */ 892 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 893 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3); 894 /* For EAR, use CLASS_AB regulator mode */ 895 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES, 896 WCD939X_RX_SUPPLIES_REGULATOR_MODE, true); 897 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL, 898 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, true); 899 break; 900 case SND_SOC_DAPM_POST_PMU: 901 /* 6 msec delay as per HW requirement */ 902 usleep_range(6000, 6010); 903 enable_irq(wcd939x->ear_pdm_wd_int); 904 break; 905 case SND_SOC_DAPM_PRE_PMD: 906 disable_irq_nosync(wcd939x->ear_pdm_wd_int); 907 break; 908 case SND_SOC_DAPM_POST_PMD: 909 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL, 910 WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, 911 false); 912 /* 7 msec delay as per HW requirement */ 913 usleep_range(7000, 7010); 914 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0, 915 WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0); 916 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA, 917 WCD_CLSH_STATE_EAR, CLS_AB_HIFI); 918 break; 919 } 920 921 return 0; 922 } 923 924 /* TX Controls */ 925 926 static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 927 struct snd_kcontrol *kcontrol, 928 int event) 929 { 930 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 931 u16 dmic_clk_reg, dmic_clk_en_reg; 932 u8 dmic_clk_en_mask; 933 u8 dmic_ctl_mask; 934 u8 dmic_clk_mask; 935 936 switch (w->shift) { 937 case 0: 938 case 1: 939 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2; 940 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC1_CTL; 941 dmic_clk_en_mask = WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN; 942 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE; 943 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL; 944 break; 945 case 2: 946 case 3: 947 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2; 948 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC2_CTL; 949 dmic_clk_en_mask = WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN; 950 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE; 951 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL; 952 break; 953 case 4: 954 case 5: 955 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4; 956 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC3_CTL; 957 dmic_clk_en_mask = WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN; 958 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE; 959 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL; 960 break; 961 case 6: 962 case 7: 963 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4; 964 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC4_CTL; 965 dmic_clk_en_mask = WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN; 966 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE; 967 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL; 968 break; 969 default: 970 dev_err(component->dev, "%s: Invalid DMIC Selection\n", __func__); 971 return -EINVAL; 972 } 973 974 switch (event) { 975 case SND_SOC_DAPM_PRE_PMU: 976 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL, 977 dmic_ctl_mask, false); 978 /* 250us sleep as per HW requirement */ 979 usleep_range(250, 260); 980 if (w->shift == 2) 981 snd_soc_component_write_field(component, 982 WCD939X_DIGITAL_CDC_DMIC2_CTL, 983 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN, 984 true); 985 /* Setting DMIC clock rate to 2.4MHz */ 986 snd_soc_component_write_field(component, dmic_clk_reg, 987 dmic_clk_mask, 3); 988 snd_soc_component_write_field(component, dmic_clk_en_reg, 989 dmic_clk_en_mask, true); 990 /* enable clock scaling */ 991 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL, 992 WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true); 993 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL, 994 WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN, true); 995 break; 996 case SND_SOC_DAPM_POST_PMD: 997 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL, 998 dmic_ctl_mask, 1); 999 if (w->shift == 2) 1000 snd_soc_component_write_field(component, 1001 WCD939X_DIGITAL_CDC_DMIC2_CTL, 1002 WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN, 1003 false); 1004 snd_soc_component_write_field(component, dmic_clk_en_reg, 1005 dmic_clk_en_mask, 0); 1006 break; 1007 } 1008 return 0; 1009 } 1010 1011 static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 1012 struct snd_kcontrol *kcontrol, int event) 1013 { 1014 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1015 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1016 int bank; 1017 int rate; 1018 1019 bank = sdw_slave_get_current_bank(wcd939x->sdw_priv[AIF1_CAP]->sdev); 1020 1021 switch (event) { 1022 case SND_SOC_DAPM_PRE_PMU: 1023 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1024 int mode = 0; 1025 1026 if (test_bit(WCD_ADC1, &wcd939x->status_mask)) 1027 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]]; 1028 if (test_bit(WCD_ADC2, &wcd939x->status_mask)) 1029 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]]; 1030 if (test_bit(WCD_ADC3, &wcd939x->status_mask)) 1031 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]]; 1032 if (test_bit(WCD_ADC4, &wcd939x->status_mask)) 1033 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]]; 1034 1035 if (mode) 1036 rate = wcd939x_get_clk_rate(ffs(mode) - 1); 1037 else 1038 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID); 1039 wcd939x_set_swr_clk_rate(component, rate, bank); 1040 wcd939x_set_swr_clk_rate(component, rate, !bank); 1041 } 1042 break; 1043 case SND_SOC_DAPM_POST_PMD: 1044 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1045 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID); 1046 wcd939x_set_swr_clk_rate(component, rate, !bank); 1047 wcd939x_set_swr_clk_rate(component, rate, bank); 1048 } 1049 break; 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int wcd939x_get_adc_mode(int val) 1056 { 1057 int ret = 0; 1058 1059 switch (val) { 1060 case ADC_MODE_INVALID: 1061 ret = ADC_MODE_VAL_NORMAL; 1062 break; 1063 case ADC_MODE_HIFI: 1064 ret = ADC_MODE_VAL_HIFI; 1065 break; 1066 case ADC_MODE_LO_HIF: 1067 ret = ADC_MODE_VAL_LO_HIF; 1068 break; 1069 case ADC_MODE_NORMAL: 1070 ret = ADC_MODE_VAL_NORMAL; 1071 break; 1072 case ADC_MODE_LP: 1073 ret = ADC_MODE_VAL_LP; 1074 break; 1075 case ADC_MODE_ULP1: 1076 ret = ADC_MODE_VAL_ULP1; 1077 break; 1078 case ADC_MODE_ULP2: 1079 ret = ADC_MODE_VAL_ULP2; 1080 break; 1081 default: 1082 ret = -EINVAL; 1083 break; 1084 } 1085 return ret; 1086 } 1087 1088 static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w, 1089 struct snd_kcontrol *kcontrol, int event) 1090 { 1091 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1092 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1093 1094 switch (event) { 1095 case SND_SOC_DAPM_PRE_PMU: 1096 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1097 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, true); 1098 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1099 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN, 1100 true); 1101 set_bit(w->shift, &wcd939x->status_mask); 1102 break; 1103 case SND_SOC_DAPM_POST_PMD: 1104 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1105 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN, 1106 false); 1107 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1108 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, 1109 false); 1110 clear_bit(w->shift, &wcd939x->status_mask); 1111 break; 1112 } 1113 1114 return 0; 1115 } 1116 1117 static void wcd939x_tx_channel_config(struct snd_soc_component *component, 1118 int channel, bool init) 1119 { 1120 int reg, mask; 1121 1122 switch (channel) { 1123 case 0: 1124 reg = WCD939X_ANA_TX_CH2; 1125 mask = WCD939X_TX_CH2_HPF1_INIT; 1126 break; 1127 case 1: 1128 reg = WCD939X_ANA_TX_CH2; 1129 mask = WCD939X_TX_CH2_HPF2_INIT; 1130 break; 1131 case 2: 1132 reg = WCD939X_ANA_TX_CH4; 1133 mask = WCD939X_TX_CH4_HPF3_INIT; 1134 break; 1135 case 3: 1136 reg = WCD939X_ANA_TX_CH4; 1137 mask = WCD939X_TX_CH4_HPF4_INIT; 1138 break; 1139 default: 1140 return; 1141 } 1142 1143 snd_soc_component_write_field(component, reg, mask, init); 1144 } 1145 1146 static int wcd939x_adc_enable_req(struct snd_soc_dapm_widget *w, 1147 struct snd_kcontrol *kcontrol, int event) 1148 { 1149 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1150 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1151 int mode; 1152 1153 switch (event) { 1154 case SND_SOC_DAPM_PRE_PMU: 1155 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL, 1156 WCD939X_CDC_REQ_CTL_FS_RATE_4P8, true); 1157 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL, 1158 WCD939X_CDC_REQ_CTL_NO_NOTCH, false); 1159 1160 wcd939x_tx_channel_config(component, w->shift, true); 1161 mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]); 1162 if (mode < 0) { 1163 dev_info(component->dev, "Invalid ADC mode\n"); 1164 return -EINVAL; 1165 } 1166 1167 switch (w->shift) { 1168 case 0: 1169 snd_soc_component_write_field(component, 1170 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1171 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE, 1172 mode); 1173 snd_soc_component_write_field(component, 1174 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1175 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, 1176 true); 1177 break; 1178 case 1: 1179 snd_soc_component_write_field(component, 1180 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1181 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE, 1182 mode); 1183 snd_soc_component_write_field(component, 1184 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1185 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, 1186 true); 1187 break; 1188 case 2: 1189 snd_soc_component_write_field(component, 1190 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1191 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE, 1192 mode); 1193 snd_soc_component_write_field(component, 1194 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1195 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, 1196 true); 1197 break; 1198 case 3: 1199 snd_soc_component_write_field(component, 1200 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1201 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE, 1202 mode); 1203 snd_soc_component_write_field(component, 1204 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1205 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, 1206 true); 1207 break; 1208 default: 1209 break; 1210 } 1211 1212 wcd939x_tx_channel_config(component, w->shift, false); 1213 break; 1214 case SND_SOC_DAPM_POST_PMD: 1215 switch (w->shift) { 1216 case 0: 1217 snd_soc_component_write_field(component, 1218 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1219 WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE, 1220 false); 1221 snd_soc_component_write_field(component, 1222 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1223 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, 1224 false); 1225 break; 1226 case 1: 1227 snd_soc_component_write_field(component, 1228 WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1229 WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE, 1230 false); 1231 snd_soc_component_write_field(component, 1232 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1233 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, 1234 false); 1235 break; 1236 case 2: 1237 snd_soc_component_write_field(component, 1238 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1239 WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE, 1240 false); 1241 snd_soc_component_write_field(component, 1242 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1243 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, 1244 false); 1245 break; 1246 case 3: 1247 snd_soc_component_write_field(component, 1248 WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1249 WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE, 1250 false); 1251 snd_soc_component_write_field(component, 1252 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1253 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, 1254 false); 1255 break; 1256 default: 1257 break; 1258 } 1259 break; 1260 } 1261 1262 return 0; 1263 } 1264 1265 static int wcd939x_micbias_control(struct snd_soc_component *component, 1266 int micb_num, int req, bool is_dapm) 1267 { 1268 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1269 int micb_index = micb_num - 1; 1270 u16 micb_reg; 1271 1272 switch (micb_num) { 1273 case MIC_BIAS_1: 1274 micb_reg = WCD939X_ANA_MICB1; 1275 break; 1276 case MIC_BIAS_2: 1277 micb_reg = WCD939X_ANA_MICB2; 1278 break; 1279 case MIC_BIAS_3: 1280 micb_reg = WCD939X_ANA_MICB3; 1281 break; 1282 case MIC_BIAS_4: 1283 micb_reg = WCD939X_ANA_MICB4; 1284 break; 1285 default: 1286 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 1287 __func__, micb_num); 1288 return -EINVAL; 1289 } 1290 1291 switch (req) { 1292 case MICB_PULLUP_ENABLE: 1293 wcd939x->pullup_ref[micb_index]++; 1294 if (wcd939x->pullup_ref[micb_index] == 1 && 1295 wcd939x->micb_ref[micb_index] == 0) 1296 snd_soc_component_write_field(component, micb_reg, 1297 WCD939X_MICB_ENABLE, 1298 MICB_BIAS_PULL_UP); 1299 break; 1300 case MICB_PULLUP_DISABLE: 1301 if (wcd939x->pullup_ref[micb_index] > 0) 1302 wcd939x->pullup_ref[micb_index]--; 1303 if (wcd939x->pullup_ref[micb_index] == 0 && 1304 wcd939x->micb_ref[micb_index] == 0) 1305 snd_soc_component_write_field(component, micb_reg, 1306 WCD939X_MICB_ENABLE, 1307 MICB_BIAS_DISABLE); 1308 break; 1309 case MICB_ENABLE: 1310 wcd939x->micb_ref[micb_index]++; 1311 if (wcd939x->micb_ref[micb_index] == 1) { 1312 snd_soc_component_write_field(component, 1313 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1314 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, true); 1315 snd_soc_component_write_field(component, 1316 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1317 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, true); 1318 snd_soc_component_write_field(component, 1319 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1320 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, true); 1321 snd_soc_component_write_field(component, 1322 WCD939X_DIGITAL_CDC_DIG_CLK_CTL, 1323 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, true); 1324 snd_soc_component_write_field(component, 1325 WCD939X_DIGITAL_CDC_ANA_CLK_CTL, 1326 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN, 1327 true); 1328 snd_soc_component_write_field(component, 1329 WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL, 1330 WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN, 1331 true); 1332 snd_soc_component_write_field(component, 1333 WCD939X_MICB1_TEST_CTL_2, 1334 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1335 snd_soc_component_write_field(component, 1336 WCD939X_MICB2_TEST_CTL_2, 1337 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1338 snd_soc_component_write_field(component, 1339 WCD939X_MICB3_TEST_CTL_2, 1340 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1341 snd_soc_component_write_field(component, 1342 WCD939X_MICB4_TEST_CTL_2, 1343 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true); 1344 snd_soc_component_write_field(component, micb_reg, 1345 WCD939X_MICB_ENABLE, 1346 MICB_BIAS_ENABLE); 1347 if (micb_num == MIC_BIAS_2) 1348 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1349 WCD_EVENT_POST_MICBIAS_2_ON); 1350 } 1351 if (micb_num == MIC_BIAS_2 && is_dapm) 1352 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1353 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1354 break; 1355 case MICB_DISABLE: 1356 if (wcd939x->micb_ref[micb_index] > 0) 1357 wcd939x->micb_ref[micb_index]--; 1358 1359 if (wcd939x->micb_ref[micb_index] == 0 && 1360 wcd939x->pullup_ref[micb_index] > 0) 1361 snd_soc_component_write_field(component, micb_reg, 1362 WCD939X_MICB_ENABLE, 1363 MICB_BIAS_PULL_UP); 1364 else if (wcd939x->micb_ref[micb_index] == 0 && 1365 wcd939x->pullup_ref[micb_index] == 0) { 1366 if (micb_num == MIC_BIAS_2) 1367 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1368 WCD_EVENT_PRE_MICBIAS_2_OFF); 1369 1370 snd_soc_component_write_field(component, micb_reg, 1371 WCD939X_MICB_ENABLE, 1372 MICB_BIAS_DISABLE); 1373 if (micb_num == MIC_BIAS_2) 1374 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1375 WCD_EVENT_POST_MICBIAS_2_OFF); 1376 } 1377 if (is_dapm && micb_num == MIC_BIAS_2) 1378 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, 1379 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1380 break; 1381 } 1382 1383 return 0; 1384 } 1385 1386 static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1387 struct snd_kcontrol *kcontrol, 1388 int event) 1389 { 1390 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1391 int micb_num = w->shift; 1392 1393 switch (event) { 1394 case SND_SOC_DAPM_PRE_PMU: 1395 wcd939x_micbias_control(component, micb_num, MICB_ENABLE, true); 1396 break; 1397 case SND_SOC_DAPM_POST_PMU: 1398 /* 1 msec delay as per HW requirement */ 1399 usleep_range(1000, 1100); 1400 break; 1401 case SND_SOC_DAPM_POST_PMD: 1402 wcd939x_micbias_control(component, micb_num, MICB_DISABLE, true); 1403 break; 1404 } 1405 1406 return 0; 1407 } 1408 1409 static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1410 struct snd_kcontrol *kcontrol, 1411 int event) 1412 { 1413 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1414 int micb_num = w->shift; 1415 1416 switch (event) { 1417 case SND_SOC_DAPM_PRE_PMU: 1418 wcd939x_micbias_control(component, micb_num, 1419 MICB_PULLUP_ENABLE, true); 1420 break; 1421 case SND_SOC_DAPM_POST_PMU: 1422 /* 1 msec delay as per HW requirement */ 1423 usleep_range(1000, 1100); 1424 break; 1425 case SND_SOC_DAPM_POST_PMD: 1426 wcd939x_micbias_control(component, micb_num, 1427 MICB_PULLUP_DISABLE, true); 1428 break; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol, 1435 struct snd_ctl_elem_value *ucontrol) 1436 { 1437 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1438 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1439 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1440 int path = e->shift_l; 1441 1442 ucontrol->value.enumerated.item[0] = wcd939x->tx_mode[path]; 1443 1444 return 0; 1445 } 1446 1447 static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol, 1448 struct snd_ctl_elem_value *ucontrol) 1449 { 1450 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1451 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1452 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1453 int path = e->shift_l; 1454 1455 if (wcd939x->tx_mode[path] == ucontrol->value.enumerated.item[0]) 1456 return 0; 1457 1458 wcd939x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 1459 1460 return 1; 1461 } 1462 1463 /* RX Controls */ 1464 1465 static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1466 struct snd_ctl_elem_value *ucontrol) 1467 { 1468 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1469 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1470 1471 ucontrol->value.integer.value[0] = wcd939x->hph_mode; 1472 1473 return 0; 1474 } 1475 1476 static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1477 struct snd_ctl_elem_value *ucontrol) 1478 { 1479 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1480 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1481 u32 mode_val; 1482 1483 mode_val = ucontrol->value.enumerated.item[0]; 1484 1485 if (mode_val == wcd939x->hph_mode) 1486 return 0; 1487 1488 if (wcd939x->variant == CHIPID_WCD9390) { 1489 switch (mode_val) { 1490 case CLS_H_NORMAL: 1491 case CLS_H_LP: 1492 case CLS_AB: 1493 case CLS_H_LOHIFI: 1494 case CLS_H_ULP: 1495 case CLS_AB_LP: 1496 case CLS_AB_LOHIFI: 1497 wcd939x->hph_mode = mode_val; 1498 return 1; 1499 } 1500 } else { 1501 switch (mode_val) { 1502 case CLS_H_NORMAL: 1503 case CLS_H_HIFI: 1504 case CLS_H_LP: 1505 case CLS_AB: 1506 case CLS_H_LOHIFI: 1507 case CLS_H_ULP: 1508 case CLS_AB_HIFI: 1509 case CLS_AB_LP: 1510 case CLS_AB_LOHIFI: 1511 wcd939x->hph_mode = mode_val; 1512 return 1; 1513 } 1514 } 1515 1516 dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__); 1517 return -EINVAL; 1518 } 1519 1520 static int wcd939x_get_compander(struct snd_kcontrol *kcontrol, 1521 struct snd_ctl_elem_value *ucontrol) 1522 { 1523 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value); 1524 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1525 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1526 1527 if (mc->shift) 1528 ucontrol->value.integer.value[0] = wcd939x->comp2_enable ? 1 : 0; 1529 else 1530 ucontrol->value.integer.value[0] = wcd939x->comp1_enable ? 1 : 0; 1531 1532 return 0; 1533 } 1534 1535 static int wcd939x_set_compander(struct snd_kcontrol *kcontrol, 1536 struct snd_ctl_elem_value *ucontrol) 1537 { 1538 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value); 1539 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1540 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1541 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[AIF1_PB]; 1542 bool value = !!ucontrol->value.integer.value[0]; 1543 int portidx = wcd->ch_info[mc->reg].port_num; 1544 1545 if (mc->shift) 1546 wcd939x->comp2_enable = value; 1547 else 1548 wcd939x->comp1_enable = value; 1549 1550 if (value) 1551 wcd939x_connect_port(wcd, portidx, mc->reg, true); 1552 else 1553 wcd939x_connect_port(wcd, portidx, mc->reg, false); 1554 1555 return 1; 1556 } 1557 1558 static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol, 1559 struct snd_ctl_elem_value *ucontrol) 1560 { 1561 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1562 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1563 1564 ucontrol->value.integer.value[0] = wcd939x->ldoh ? 1 : 0; 1565 1566 return 0; 1567 } 1568 1569 static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol, 1570 struct snd_ctl_elem_value *ucontrol) 1571 { 1572 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1573 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1574 1575 if (wcd939x->ldoh == !!ucontrol->value.integer.value[0]) 1576 return 0; 1577 1578 wcd939x->ldoh = !!ucontrol->value.integer.value[0]; 1579 1580 return 1; 1581 } 1582 1583 static const char * const tx_mode_mux_text_wcd9390[] = { 1584 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1585 }; 1586 1587 static const struct soc_enum tx0_mode_mux_enum_wcd9390 = 1588 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1589 tx_mode_mux_text_wcd9390); 1590 1591 static const struct soc_enum tx1_mode_mux_enum_wcd9390 = 1592 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1593 tx_mode_mux_text_wcd9390); 1594 1595 static const struct soc_enum tx2_mode_mux_enum_wcd9390 = 1596 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1597 tx_mode_mux_text_wcd9390); 1598 1599 static const struct soc_enum tx3_mode_mux_enum_wcd9390 = 1600 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9390), 1601 tx_mode_mux_text_wcd9390); 1602 1603 static const char * const tx_mode_mux_text[] = { 1604 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1605 "ADC_ULP1", "ADC_ULP2", 1606 }; 1607 1608 static const struct soc_enum tx0_mode_mux_enum = 1609 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 1610 tx_mode_mux_text); 1611 1612 static const struct soc_enum tx1_mode_mux_enum = 1613 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 1614 tx_mode_mux_text); 1615 1616 static const struct soc_enum tx2_mode_mux_enum = 1617 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 1618 tx_mode_mux_text); 1619 1620 static const struct soc_enum tx3_mode_mux_enum = 1621 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 1622 tx_mode_mux_text); 1623 1624 static const char * const rx_hph_mode_mux_text_wcd9390[] = { 1625 "CLS_H_NORMAL", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 1626 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 1627 "CLS_AB_LOHIFI", 1628 }; 1629 1630 static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 = 1631 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390), 1632 rx_hph_mode_mux_text_wcd9390); 1633 1634 static const char * const rx_hph_mode_mux_text[] = { 1635 "CLS_H_NORMAL", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 1636 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 1637 }; 1638 1639 static const struct soc_enum rx_hph_mode_mux_enum = 1640 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 1641 rx_hph_mode_mux_text); 1642 1643 static const struct snd_kcontrol_new wcd9390_snd_controls[] = { 1644 SOC_SINGLE_TLV("EAR_PA Volume", WCD939X_ANA_EAR_COMPANDER_CTL, 1645 2, 0x10, 0, ear_pa_gain), 1646 1647 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390, 1648 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put), 1649 1650 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum_wcd9390, 1651 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1652 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum_wcd9390, 1653 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1654 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum_wcd9390, 1655 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1656 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum_wcd9390, 1657 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1658 }; 1659 1660 static const struct snd_kcontrol_new wcd9395_snd_controls[] = { 1661 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 1662 wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put), 1663 1664 SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum, 1665 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1666 SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum, 1667 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1668 SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum, 1669 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1670 SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum, 1671 wcd939x_tx_mode_get, wcd939x_tx_mode_put), 1672 }; 1673 1674 static const struct snd_kcontrol_new adc1_switch[] = { 1675 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1676 }; 1677 1678 static const struct snd_kcontrol_new adc2_switch[] = { 1679 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1680 }; 1681 1682 static const struct snd_kcontrol_new adc3_switch[] = { 1683 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1684 }; 1685 1686 static const struct snd_kcontrol_new adc4_switch[] = { 1687 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1688 }; 1689 1690 static const struct snd_kcontrol_new dmic1_switch[] = { 1691 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1692 }; 1693 1694 static const struct snd_kcontrol_new dmic2_switch[] = { 1695 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1696 }; 1697 1698 static const struct snd_kcontrol_new dmic3_switch[] = { 1699 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1700 }; 1701 1702 static const struct snd_kcontrol_new dmic4_switch[] = { 1703 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1704 }; 1705 1706 static const struct snd_kcontrol_new dmic5_switch[] = { 1707 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1708 }; 1709 1710 static const struct snd_kcontrol_new dmic6_switch[] = { 1711 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1712 }; 1713 1714 static const struct snd_kcontrol_new dmic7_switch[] = { 1715 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1716 }; 1717 1718 static const struct snd_kcontrol_new dmic8_switch[] = { 1719 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1720 }; 1721 1722 static const struct snd_kcontrol_new ear_rdac_switch[] = { 1723 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1724 }; 1725 1726 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 1727 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1728 }; 1729 1730 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 1731 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1732 }; 1733 1734 static const char * const adc1_mux_text[] = { 1735 "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5" 1736 }; 1737 1738 static const struct soc_enum adc1_enum = 1739 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 0, 1740 ARRAY_SIZE(adc1_mux_text), adc1_mux_text); 1741 1742 static const struct snd_kcontrol_new tx_adc1_mux = 1743 SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum); 1744 1745 static const char * const adc2_mux_text[] = { 1746 "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5" 1747 }; 1748 1749 static const struct soc_enum adc2_enum = 1750 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 3, 1751 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 1752 1753 static const struct snd_kcontrol_new tx_adc2_mux = 1754 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 1755 1756 static const char * const adc3_mux_text[] = { 1757 "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5" 1758 }; 1759 1760 static const struct soc_enum adc3_enum = 1761 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 0, 1762 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 1763 1764 static const struct snd_kcontrol_new tx_adc3_mux = 1765 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 1766 1767 static const char * const adc4_mux_text[] = { 1768 "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5" 1769 }; 1770 1771 static const struct soc_enum adc4_enum = 1772 SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 3, 1773 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 1774 1775 static const struct snd_kcontrol_new tx_adc4_mux = 1776 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 1777 1778 static const char * const rdac3_mux_text[] = { 1779 "RX3", "RX1" 1780 }; 1781 1782 static const struct soc_enum rdac3_enum = 1783 SOC_ENUM_SINGLE(WCD939X_DIGITAL_CDC_EAR_PATH_CTL, 0, 1784 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 1785 1786 static const struct snd_kcontrol_new rx_rdac3_mux = 1787 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 1788 1789 static int wcd939x_get_swr_port(struct snd_kcontrol *kcontrol, 1790 struct snd_ctl_elem_value *ucontrol) 1791 { 1792 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1793 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1794 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp); 1795 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift]; 1796 unsigned int portidx = wcd->ch_info[mixer->reg].port_num; 1797 1798 ucontrol->value.integer.value[0] = wcd->port_enable[portidx] ? 1 : 0; 1799 1800 return 0; 1801 } 1802 1803 static const char *version_to_str(u32 version) 1804 { 1805 switch (version) { 1806 case WCD939X_VERSION_1_0: 1807 return __stringify(WCD939X_1_0); 1808 case WCD939X_VERSION_1_1: 1809 return __stringify(WCD939X_1_1); 1810 case WCD939X_VERSION_2_0: 1811 return __stringify(WCD939X_2_0); 1812 } 1813 return NULL; 1814 } 1815 1816 static int wcd939x_set_swr_port(struct snd_kcontrol *kcontrol, 1817 struct snd_ctl_elem_value *ucontrol) 1818 { 1819 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1820 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1821 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp); 1822 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift]; 1823 unsigned int portidx = wcd->ch_info[mixer->reg].port_num; 1824 1825 wcd->port_enable[portidx] = !!ucontrol->value.integer.value[0]; 1826 1827 wcd939x_connect_port(wcd, portidx, mixer->reg, wcd->port_enable[portidx]); 1828 1829 return 1; 1830 } 1831 1832 /* MBHC Related */ 1833 1834 static void wcd939x_mbhc_clk_setup(struct snd_soc_component *component, 1835 bool enable) 1836 { 1837 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_1, 1838 WCD939X_CTL_1_RCO_EN, enable); 1839 } 1840 1841 static void wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1842 bool enable) 1843 { 1844 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT, 1845 WCD939X_MBHC_ELECT_BIAS_EN, enable); 1846 } 1847 1848 static void wcd939x_mbhc_program_btn_thr(struct snd_soc_component *component, 1849 int *btn_low, int *btn_high, 1850 int num_btn, bool is_micbias) 1851 { 1852 int i, vth; 1853 1854 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1855 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1856 __func__, num_btn); 1857 return; 1858 } 1859 1860 for (i = 0; i < num_btn; i++) { 1861 vth = (btn_high[i] * 2) / 25; 1862 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_BTN0 + i, 1863 WCD939X_MBHC_BTN0_VTH, vth); 1864 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 1865 __func__, i, btn_high[i], vth); 1866 } 1867 } 1868 1869 static bool wcd939x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1870 { 1871 if (micb_num == MIC_BIAS_2) { 1872 u8 val; 1873 1874 val = FIELD_GET(WCD939X_MICB_ENABLE, 1875 snd_soc_component_read(component, WCD939X_ANA_MICB2)); 1876 if (val == MICB_BIAS_ENABLE) 1877 return true; 1878 } 1879 1880 return false; 1881 } 1882 1883 static void wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1884 int pull_up_cur) 1885 { 1886 /* Default pull up current to 2uA */ 1887 if (pull_up_cur > HS_PULLUP_I_OFF || 1888 pull_up_cur < HS_PULLUP_I_3P0_UA || 1889 pull_up_cur == HS_PULLUP_I_DEFAULT) 1890 pull_up_cur = HS_PULLUP_I_2P0_UA; 1891 1892 dev_dbg(component->dev, "%s: HS pull up current:%d\n", 1893 __func__, pull_up_cur); 1894 1895 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 1896 WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL, pull_up_cur); 1897 } 1898 1899 static int wcd939x_mbhc_request_micbias(struct snd_soc_component *component, 1900 int micb_num, int req) 1901 { 1902 return wcd939x_micbias_control(component, micb_num, req, false); 1903 } 1904 1905 static void wcd939x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1906 bool enable) 1907 { 1908 if (enable) { 1909 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1910 WCD939X_MICB2_RAMP_SHIFT_CTL, 3); 1911 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1912 WCD939X_MICB2_RAMP_RAMP_ENABLE, true); 1913 } else { 1914 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1915 WCD939X_MICB2_RAMP_RAMP_ENABLE, false); 1916 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP, 1917 WCD939X_MICB2_RAMP_SHIFT_CTL, 0); 1918 } 1919 } 1920 1921 static int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1922 int req_volt, int micb_num) 1923 { 1924 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1925 unsigned int micb_reg, cur_vout_ctl, micb_en; 1926 int req_vout_ctl; 1927 1928 switch (micb_num) { 1929 case MIC_BIAS_1: 1930 micb_reg = WCD939X_ANA_MICB1; 1931 break; 1932 case MIC_BIAS_2: 1933 micb_reg = WCD939X_ANA_MICB2; 1934 break; 1935 case MIC_BIAS_3: 1936 micb_reg = WCD939X_ANA_MICB3; 1937 break; 1938 case MIC_BIAS_4: 1939 micb_reg = WCD939X_ANA_MICB4; 1940 break; 1941 default: 1942 return -EINVAL; 1943 } 1944 guard(mutex)(&wcd939x->micb_lock); 1945 1946 /* 1947 * If requested micbias voltage is same as current micbias 1948 * voltage, then just return. Otherwise, adjust voltage as 1949 * per requested value. If micbias is already enabled, then 1950 * to avoid slow micbias ramp-up or down enable pull-up 1951 * momentarily, change the micbias value and then re-enable 1952 * micbias. 1953 */ 1954 micb_en = snd_soc_component_read_field(component, micb_reg, 1955 WCD939X_MICB_ENABLE); 1956 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 1957 WCD939X_MICB_VOUT_CTL); 1958 1959 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt); 1960 if (req_vout_ctl < 0) 1961 return req_vout_ctl; 1962 1963 if (cur_vout_ctl == req_vout_ctl) 1964 return 0; 1965 1966 dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n", 1967 __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl), 1968 req_volt, micb_en); 1969 1970 if (micb_en == MICB_BIAS_ENABLE) 1971 snd_soc_component_write_field(component, micb_reg, 1972 WCD939X_MICB_ENABLE, 1973 MICB_BIAS_PULL_DOWN); 1974 1975 snd_soc_component_write_field(component, micb_reg, 1976 WCD939X_MICB_VOUT_CTL, req_vout_ctl); 1977 1978 if (micb_en == MICB_BIAS_ENABLE) { 1979 snd_soc_component_write_field(component, micb_reg, 1980 WCD939X_MICB_ENABLE, 1981 MICB_BIAS_ENABLE); 1982 /* 1983 * Add 2ms delay as per HW requirement after enabling 1984 * micbias 1985 */ 1986 usleep_range(2000, 2100); 1987 } 1988 1989 return 0; 1990 } 1991 1992 static int wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 1993 int micb_num, bool req_en) 1994 { 1995 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 1996 int micb_mv; 1997 1998 if (micb_num != MIC_BIAS_2) 1999 return -EINVAL; 2000 /* 2001 * If device tree micbias level is already above the minimum 2002 * voltage needed to detect threshold microphone, then do 2003 * not change the micbias, just return. 2004 */ 2005 if (wcd939x->common.micb_mv[1] >= WCD_MBHC_THR_HS_MICB_MV) 2006 return 0; 2007 2008 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd939x->common.micb_mv[1]; 2009 2010 return wcd939x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2011 } 2012 2013 /* Selected by WCD939X_MBHC_GET_C1() */ 2014 static const s16 wcd939x_wcd_mbhc_d1_a[4] = { 2015 0, 30, 30, 6 2016 }; 2017 2018 /* Selected by zdet_param.noff */ 2019 static const int wcd939x_mbhc_mincode_param[] = { 2020 3277, 1639, 820, 410, 205, 103, 52, 26 2021 }; 2022 2023 static const struct zdet_param wcd939x_mbhc_zdet_param = { 2024 .ldo_ctl = 4, 2025 .noff = 0, 2026 .nshift = 6, 2027 .btn5 = 0x18, 2028 .btn6 = 0x60, 2029 .btn7 = 0x78, 2030 }; 2031 2032 static void wcd939x_mbhc_get_result_params(struct snd_soc_component *component, 2033 int32_t *zdet) 2034 { 2035 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param; 2036 s32 x1, d1, denom; 2037 int val; 2038 s16 c1; 2039 int i; 2040 2041 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2042 WCD939X_MBHC_ZDET_ZDET_CHG_EN, true); 2043 for (i = 0; i < WCD939X_ZDET_NUM_MEASUREMENTS; i++) { 2044 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2, 2045 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB); 2046 if (val & BIT(7)) 2047 break; 2048 } 2049 val = val << 8; 2050 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1, 2051 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB); 2052 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2053 WCD939X_MBHC_ZDET_ZDET_CHG_EN, false); 2054 x1 = WCD939X_MBHC_GET_X1(val); 2055 c1 = WCD939X_MBHC_GET_C1(val); 2056 2057 /* If ramp is not complete, give additional 5ms */ 2058 if (c1 < 2 && x1) 2059 mdelay(5); 2060 2061 if (!c1 || !x1) { 2062 dev_dbg(component->dev, 2063 "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2064 __func__, c1, x1); 2065 goto ramp_down; 2066 } 2067 2068 d1 = wcd939x_wcd_mbhc_d1_a[c1]; 2069 denom = (x1 * d1) - (1 << (14 - zdet_param->noff)); 2070 if (denom > 0) 2071 *zdet = (WCD939X_ANA_MBHC_ZDET_CONST * 1000) / denom; 2072 else if (x1 < wcd939x_mbhc_mincode_param[zdet_param->noff]) 2073 *zdet = WCD939X_ZDET_FLOATING_IMPEDANCE; 2074 2075 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n", 2076 __func__, d1, c1, x1, *zdet); 2077 ramp_down: 2078 i = 0; 2079 while (x1) { 2080 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1, 2081 WCD939X_MBHC_RESULT_1_Z_RESULT_LSB) << 8; 2082 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2, 2083 WCD939X_MBHC_RESULT_2_Z_RESULT_MSB); 2084 x1 = WCD939X_MBHC_GET_X1(val); 2085 i++; 2086 if (i == WCD939X_ZDET_NUM_MEASUREMENTS) 2087 break; 2088 } 2089 } 2090 2091 static void wcd939x_mbhc_zdet_ramp(struct snd_soc_component *component, 2092 s32 *zl, int32_t *zr) 2093 { 2094 const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param; 2095 s32 zdet = 0; 2096 2097 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, 2098 WCD939X_ZDET_ANA_CTL_MAXV_CTL, zdet_param->ldo_ctl); 2099 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN5, WCD939X_MBHC_BTN5_VTH, 2100 zdet_param->btn5); 2101 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN6, WCD939X_MBHC_BTN6_VTH, 2102 zdet_param->btn6); 2103 snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN7, WCD939X_MBHC_BTN7_VTH, 2104 zdet_param->btn7); 2105 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, 2106 WCD939X_ZDET_ANA_CTL_RANGE_CTL, zdet_param->noff); 2107 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL, 2108 WCD939X_ZDET_RAMP_CTL_TIME_CTL, zdet_param->nshift); 2109 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL, 2110 WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL, 6); /*acc1_min_63 */ 2111 2112 if (!zl) 2113 goto z_right; 2114 2115 /* Start impedance measurement for HPH_L */ 2116 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2117 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, true); 2118 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2119 __func__, zdet_param->noff); 2120 wcd939x_mbhc_get_result_params(component, &zdet); 2121 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2122 WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, false); 2123 2124 *zl = zdet; 2125 2126 z_right: 2127 if (!zr) 2128 return; 2129 2130 /* Start impedance measurement for HPH_R */ 2131 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2132 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, true); 2133 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2134 __func__, zdet_param->noff); 2135 wcd939x_mbhc_get_result_params(component, &zdet); 2136 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET, 2137 WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, false); 2138 2139 *zr = zdet; 2140 } 2141 2142 static void wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2143 s32 *z_val, int flag_l_r) 2144 { 2145 int q1_cal; 2146 s16 q1; 2147 2148 q1 = snd_soc_component_read(component, WCD939X_DIGITAL_EFUSE_REG_21 + flag_l_r); 2149 if (q1 & BIT(7)) 2150 q1_cal = (10000 - ((q1 & GENMASK(6, 0)) * 10)); 2151 else 2152 q1_cal = (10000 + (q1 * 10)); 2153 2154 if (q1_cal > 0) 2155 *z_val = ((*z_val) * 10000) / q1_cal; 2156 } 2157 2158 static void wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2159 u32 *zl, uint32_t *zr) 2160 { 2161 struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev); 2162 unsigned int reg0, reg1, reg2, reg3, reg4; 2163 int z_mono, z_diff1, z_diff2; 2164 bool is_fsm_disable = false; 2165 s32 z1l, z1r, z1ls; 2166 2167 reg0 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN5); 2168 reg1 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN6); 2169 reg2 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN7); 2170 reg3 = snd_soc_component_read(component, WCD939X_MBHC_CTL_CLK); 2171 reg4 = snd_soc_component_read(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL); 2172 2173 if (snd_soc_component_read_field(component, WCD939X_ANA_MBHC_ELECT, 2174 WCD939X_MBHC_ELECT_FSM_EN)) { 2175 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT, 2176 WCD939X_MBHC_ELECT_FSM_EN, false); 2177 is_fsm_disable = true; 2178 } 2179 2180 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2181 if (wcd939x->mbhc_cfg.hphl_swh) 2182 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2183 WCD939X_MBHC_MECH_L_DET_EN, false); 2184 2185 /* Turn off 100k pull down on HPHL */ 2186 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2187 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, 2188 false); 2189 2190 /* 2191 * Disable surge protection before impedance detection. 2192 * This is done to give correct value for high impedance. 2193 */ 2194 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2195 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false); 2196 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2197 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false); 2198 2199 /* 1ms delay needed after disable surge protection */ 2200 usleep_range(1000, 1010); 2201 2202 /* First get impedance on Left */ 2203 wcd939x_mbhc_zdet_ramp(component, &z1l, NULL); 2204 if (z1l == WCD939X_ZDET_FLOATING_IMPEDANCE || z1l > WCD939X_ZDET_VAL_100K) { 2205 *zl = WCD939X_ZDET_FLOATING_IMPEDANCE; 2206 } else { 2207 *zl = z1l / 1000; 2208 wcd939x_wcd_mbhc_qfuse_cal(component, zl, 0); 2209 } 2210 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2211 __func__, *zl); 2212 2213 /* Start of right impedance ramp and calculation */ 2214 wcd939x_mbhc_zdet_ramp(component, NULL, &z1r); 2215 if (z1r == WCD939X_ZDET_FLOATING_IMPEDANCE || z1r > WCD939X_ZDET_VAL_100K) { 2216 *zr = WCD939X_ZDET_FLOATING_IMPEDANCE; 2217 } else { 2218 *zr = z1r / 1000; 2219 wcd939x_wcd_mbhc_qfuse_cal(component, zr, 1); 2220 } 2221 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2222 __func__, *zr); 2223 2224 /* Mono/stereo detection */ 2225 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE && 2226 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE) { 2227 dev_dbg(component->dev, 2228 "%s: plug type is invalid or extension cable\n", 2229 __func__); 2230 goto zdet_complete; 2231 } 2232 2233 if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE || 2234 *zr == WCD939X_ZDET_FLOATING_IMPEDANCE || 2235 (*zl < WCD_MONO_HS_MIN_THR && *zr > WCD_MONO_HS_MIN_THR) || 2236 (*zl > WCD_MONO_HS_MIN_THR && *zr < WCD_MONO_HS_MIN_THR)) { 2237 dev_dbg(component->dev, 2238 "%s: Mono plug type with one ch floating or shorted to GND\n", 2239 __func__); 2240 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2241 goto zdet_complete; 2242 } 2243 2244 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST, 2245 WCD939X_R_ATEST_HPH_GND_OVR, true); 2246 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2247 WCD939X_PA_CTL2_HPHPA_GND_R, true); 2248 wcd939x_mbhc_zdet_ramp(component, &z1ls, NULL); 2249 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2250 WCD939X_PA_CTL2_HPHPA_GND_R, false); 2251 snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST, 2252 WCD939X_R_ATEST_HPH_GND_OVR, false); 2253 2254 z1ls /= 1000; 2255 wcd939x_wcd_mbhc_qfuse_cal(component, &z1ls, 0); 2256 2257 /* Parallel of left Z and 9 ohm pull down resistor */ 2258 z_mono = (*zl * 9) / (*zl + 9); 2259 z_diff1 = z1ls > z_mono ? z1ls - z_mono : z_mono - z1ls; 2260 z_diff2 = *zl > z1ls ? *zl - z1ls : z1ls - *zl; 2261 if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + z_mono))) { 2262 dev_dbg(component->dev, "%s: stereo plug type detected\n", 2263 __func__); 2264 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 2265 } else { 2266 dev_dbg(component->dev, "%s: MONO plug type detected\n", 2267 __func__); 2268 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2269 } 2270 2271 /* Enable surge protection again after impedance detection */ 2272 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2273 WCD939X_EN_EN_SURGE_PROTECTION_HPHR, true); 2274 snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN, 2275 WCD939X_EN_EN_SURGE_PROTECTION_HPHL, true); 2276 2277 zdet_complete: 2278 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN5, reg0); 2279 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN6, reg1); 2280 snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN7, reg2); 2281 2282 /* Turn on 100k pull down on HPHL */ 2283 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2284 WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, true); 2285 2286 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2287 if (wcd939x->mbhc_cfg.hphl_swh) 2288 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2289 WCD939X_MBHC_MECH_L_DET_EN, true); 2290 2291 snd_soc_component_write(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2292 snd_soc_component_write(component, WCD939X_MBHC_CTL_CLK, reg3); 2293 2294 if (is_fsm_disable) 2295 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT, 2296 WCD939X_MBHC_ELECT_FSM_EN, true); 2297 } 2298 2299 static void wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2300 bool enable) 2301 { 2302 if (enable) { 2303 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2304 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN, 2305 true); 2306 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2307 WCD939X_MBHC_MECH_GND_DET_EN, true); 2308 } else { 2309 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2310 WCD939X_MBHC_MECH_GND_DET_EN, false); 2311 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH, 2312 WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN, 2313 false); 2314 } 2315 } 2316 2317 static void wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2318 bool enable) 2319 { 2320 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2321 WCD939X_PA_CTL2_HPHPA_GND_R, enable); 2322 snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2, 2323 WCD939X_PA_CTL2_HPHPA_GND_L, enable); 2324 } 2325 2326 static void wcd939x_mbhc_moisture_config(struct snd_soc_component *component) 2327 { 2328 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2329 2330 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) { 2331 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2332 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2333 return; 2334 } 2335 2336 /* Do not enable moisture detection if jack type is NC */ 2337 if (!wcd939x->mbhc_cfg.hphl_swh) { 2338 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2339 __func__); 2340 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2341 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2342 return; 2343 } 2344 2345 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2346 WCD939X_CTL_2_M_RTH_CTL, wcd939x->mbhc_cfg.moist_rref); 2347 } 2348 2349 static void wcd939x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 2350 { 2351 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2352 2353 if (enable) 2354 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2355 WCD939X_CTL_2_M_RTH_CTL, 2356 wcd939x->mbhc_cfg.moist_rref); 2357 else 2358 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2359 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2360 } 2361 2362 static bool wcd939x_mbhc_get_moisture_status(struct snd_soc_component *component) 2363 { 2364 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2365 bool ret = false; 2366 2367 if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) { 2368 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2369 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2370 goto done; 2371 } 2372 2373 /* Do not enable moisture detection if jack type is NC */ 2374 if (!wcd939x->mbhc_cfg.hphl_swh) { 2375 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2376 __func__); 2377 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2, 2378 WCD939X_CTL_2_M_RTH_CTL, R_OFF); 2379 goto done; 2380 } 2381 2382 /* 2383 * If moisture_en is already enabled, then skip to plug type 2384 * detection. 2385 */ 2386 if (snd_soc_component_read_field(component, WCD939X_MBHC_NEW_CTL_2, 2387 WCD939X_CTL_2_M_RTH_CTL)) 2388 goto done; 2389 2390 wcd939x_mbhc_moisture_detect_en(component, true); 2391 2392 /* Read moisture comparator status, invert of status bit */ 2393 ret = !snd_soc_component_read_field(component, WCD939X_MBHC_NEW_FSM_STATUS, 2394 WCD939X_FSM_STATUS_HS_M_COMP_STATUS); 2395 done: 2396 return ret; 2397 } 2398 2399 static void wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 2400 bool enable) 2401 { 2402 snd_soc_component_write_field(component, 2403 WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 2404 WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING, 2405 enable); 2406 } 2407 2408 static const struct wcd_mbhc_cb mbhc_cb = { 2409 .clk_setup = wcd939x_mbhc_clk_setup, 2410 .mbhc_bias = wcd939x_mbhc_mbhc_bias_control, 2411 .set_btn_thr = wcd939x_mbhc_program_btn_thr, 2412 .micbias_enable_status = wcd939x_mbhc_micb_en_status, 2413 .hph_pull_up_control_v2 = wcd939x_mbhc_hph_l_pull_up_control, 2414 .mbhc_micbias_control = wcd939x_mbhc_request_micbias, 2415 .mbhc_micb_ramp_control = wcd939x_mbhc_micb_ramp_control, 2416 .mbhc_micb_ctrl_thr_mic = wcd939x_mbhc_micb_ctrl_threshold_mic, 2417 .compute_impedance = wcd939x_wcd_mbhc_calc_impedance, 2418 .mbhc_gnd_det_ctrl = wcd939x_mbhc_gnd_det_ctrl, 2419 .hph_pull_down_ctrl = wcd939x_mbhc_hph_pull_down_ctrl, 2420 .mbhc_moisture_config = wcd939x_mbhc_moisture_config, 2421 .mbhc_get_moisture_status = wcd939x_mbhc_get_moisture_status, 2422 .mbhc_moisture_polling_ctrl = wcd939x_mbhc_moisture_polling_ctrl, 2423 .mbhc_moisture_detect_en = wcd939x_mbhc_moisture_detect_en, 2424 }; 2425 2426 static int wcd939x_get_hph_type(struct snd_kcontrol *kcontrol, 2427 struct snd_ctl_elem_value *ucontrol) 2428 { 2429 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2430 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2431 2432 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd939x->wcd_mbhc); 2433 2434 return 0; 2435 } 2436 2437 static int wcd939x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2438 struct snd_ctl_elem_value *ucontrol) 2439 { 2440 struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value); 2441 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2442 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2443 bool hphr = mc->shift; 2444 u32 zl, zr; 2445 2446 wcd_mbhc_get_impedance(wcd939x->wcd_mbhc, &zl, &zr); 2447 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2448 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2449 2450 return 0; 2451 } 2452 2453 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2454 SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, 2455 wcd939x_get_hph_type, NULL), 2456 }; 2457 2458 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2459 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, 2460 wcd939x_hph_impedance_get, NULL), 2461 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, 2462 wcd939x_hph_impedance_get, NULL), 2463 }; 2464 2465 static int wcd939x_mbhc_init(struct snd_soc_component *component) 2466 { 2467 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2468 struct wcd_mbhc_intr *intr_ids = &wcd939x->intr_ids; 2469 2470 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2471 WCD939X_IRQ_MBHC_SW_DET); 2472 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2473 WCD939X_IRQ_MBHC_BUTTON_PRESS_DET); 2474 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2475 WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET); 2476 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2477 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2478 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd939x->irq_chip, 2479 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET); 2480 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd939x->irq_chip, 2481 WCD939X_IRQ_HPHL_OCP_INT); 2482 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd939x->irq_chip, 2483 WCD939X_IRQ_HPHR_OCP_INT); 2484 2485 wcd939x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2486 if (IS_ERR(wcd939x->wcd_mbhc)) 2487 return PTR_ERR(wcd939x->wcd_mbhc); 2488 2489 snd_soc_add_component_controls(component, impedance_detect_controls, 2490 ARRAY_SIZE(impedance_detect_controls)); 2491 snd_soc_add_component_controls(component, hph_type_detect_controls, 2492 ARRAY_SIZE(hph_type_detect_controls)); 2493 2494 return 0; 2495 } 2496 2497 static void wcd939x_mbhc_deinit(struct snd_soc_component *component) 2498 { 2499 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2500 2501 wcd_mbhc_deinit(wcd939x->wcd_mbhc); 2502 } 2503 2504 /* END MBHC */ 2505 2506 static const struct snd_kcontrol_new wcd939x_snd_controls[] = { 2507 /* RX Path */ 2508 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD939X_COMP_L, 0, 1, 0, 2509 wcd939x_get_compander, wcd939x_set_compander), 2510 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD939X_COMP_R, 1, 1, 0, 2511 wcd939x_get_compander, wcd939x_set_compander), 2512 SOC_SINGLE_EXT("HPHL Switch", WCD939X_HPH_L, 0, 1, 0, 2513 wcd939x_get_swr_port, wcd939x_set_swr_port), 2514 SOC_SINGLE_EXT("HPHR Switch", WCD939X_HPH_R, 0, 1, 0, 2515 wcd939x_get_swr_port, wcd939x_set_swr_port), 2516 SOC_SINGLE_EXT("CLSH Switch", WCD939X_CLSH, 0, 1, 0, 2517 wcd939x_get_swr_port, wcd939x_set_swr_port), 2518 SOC_SINGLE_EXT("LO Switch", WCD939X_LO, 0, 1, 0, 2519 wcd939x_get_swr_port, wcd939x_set_swr_port), 2520 SOC_SINGLE_EXT("DSD_L Switch", WCD939X_DSD_L, 0, 1, 0, 2521 wcd939x_get_swr_port, wcd939x_set_swr_port), 2522 SOC_SINGLE_EXT("DSD_R Switch", WCD939X_DSD_R, 0, 1, 0, 2523 wcd939x_get_swr_port, wcd939x_set_swr_port), 2524 SOC_SINGLE_TLV("HPHL Volume", WCD939X_HPH_L_EN, 0, 20, 1, line_gain), 2525 SOC_SINGLE_TLV("HPHR Volume", WCD939X_HPH_R_EN, 0, 20, 1, line_gain), 2526 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 2527 wcd939x_ldoh_get, wcd939x_ldoh_put), 2528 2529 /* TX Path */ 2530 SOC_SINGLE_EXT("ADC1 Switch", WCD939X_ADC1, 1, 1, 0, 2531 wcd939x_get_swr_port, wcd939x_set_swr_port), 2532 SOC_SINGLE_EXT("ADC2 Switch", WCD939X_ADC2, 1, 1, 0, 2533 wcd939x_get_swr_port, wcd939x_set_swr_port), 2534 SOC_SINGLE_EXT("ADC3 Switch", WCD939X_ADC3, 1, 1, 0, 2535 wcd939x_get_swr_port, wcd939x_set_swr_port), 2536 SOC_SINGLE_EXT("ADC4 Switch", WCD939X_ADC4, 1, 1, 0, 2537 wcd939x_get_swr_port, wcd939x_set_swr_port), 2538 SOC_SINGLE_EXT("DMIC0 Switch", WCD939X_DMIC0, 1, 1, 0, 2539 wcd939x_get_swr_port, wcd939x_set_swr_port), 2540 SOC_SINGLE_EXT("DMIC1 Switch", WCD939X_DMIC1, 1, 1, 0, 2541 wcd939x_get_swr_port, wcd939x_set_swr_port), 2542 SOC_SINGLE_EXT("MBHC Switch", WCD939X_MBHC, 1, 1, 0, 2543 wcd939x_get_swr_port, wcd939x_set_swr_port), 2544 SOC_SINGLE_EXT("DMIC2 Switch", WCD939X_DMIC2, 1, 1, 0, 2545 wcd939x_get_swr_port, wcd939x_set_swr_port), 2546 SOC_SINGLE_EXT("DMIC3 Switch", WCD939X_DMIC3, 1, 1, 0, 2547 wcd939x_get_swr_port, wcd939x_set_swr_port), 2548 SOC_SINGLE_EXT("DMIC4 Switch", WCD939X_DMIC4, 1, 1, 0, 2549 wcd939x_get_swr_port, wcd939x_set_swr_port), 2550 SOC_SINGLE_EXT("DMIC5 Switch", WCD939X_DMIC5, 1, 1, 0, 2551 wcd939x_get_swr_port, wcd939x_set_swr_port), 2552 SOC_SINGLE_EXT("DMIC6 Switch", WCD939X_DMIC6, 1, 1, 0, 2553 wcd939x_get_swr_port, wcd939x_set_swr_port), 2554 SOC_SINGLE_EXT("DMIC7 Switch", WCD939X_DMIC7, 1, 1, 0, 2555 wcd939x_get_swr_port, wcd939x_set_swr_port), 2556 SOC_SINGLE_TLV("ADC1 Volume", WCD939X_ANA_TX_CH1, 0, 20, 0, 2557 analog_gain), 2558 SOC_SINGLE_TLV("ADC2 Volume", WCD939X_ANA_TX_CH2, 0, 20, 0, 2559 analog_gain), 2560 SOC_SINGLE_TLV("ADC3 Volume", WCD939X_ANA_TX_CH3, 0, 20, 0, 2561 analog_gain), 2562 SOC_SINGLE_TLV("ADC4 Volume", WCD939X_ANA_TX_CH4, 0, 20, 0, 2563 analog_gain), 2564 }; 2565 2566 static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = { 2567 /*input widgets*/ 2568 SND_SOC_DAPM_INPUT("AMIC1"), 2569 SND_SOC_DAPM_INPUT("AMIC2"), 2570 SND_SOC_DAPM_INPUT("AMIC3"), 2571 SND_SOC_DAPM_INPUT("AMIC4"), 2572 SND_SOC_DAPM_INPUT("AMIC5"), 2573 2574 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 2575 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 2576 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 2577 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 2578 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 2579 2580 /* TX widgets */ 2581 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2582 wcd939x_codec_enable_adc, 2583 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2584 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2585 wcd939x_codec_enable_adc, 2586 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2587 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2588 wcd939x_codec_enable_adc, 2589 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2590 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 2591 wcd939x_codec_enable_adc, 2592 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2593 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2594 wcd939x_codec_enable_dmic, 2595 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2596 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2597 wcd939x_codec_enable_dmic, 2598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2599 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2600 wcd939x_codec_enable_dmic, 2601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2602 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2603 wcd939x_codec_enable_dmic, 2604 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2605 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2606 wcd939x_codec_enable_dmic, 2607 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2608 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2609 wcd939x_codec_enable_dmic, 2610 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2611 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 2612 wcd939x_codec_enable_dmic, 2613 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2614 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 2615 wcd939x_codec_enable_dmic, 2616 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2617 2618 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, NULL, 0, 2619 wcd939x_adc_enable_req, 2620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2621 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, NULL, 0, 2622 wcd939x_adc_enable_req, 2623 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2624 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, NULL, 0, 2625 wcd939x_adc_enable_req, 2626 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2627 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 2628 wcd939x_adc_enable_req, 2629 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2630 2631 SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0, &tx_adc1_mux), 2632 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2633 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 2634 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 2635 2636 /* tx mixers */ 2637 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, 2638 adc1_switch, ARRAY_SIZE(adc1_switch), wcd939x_tx_swr_ctrl, 2639 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2640 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, 2641 adc2_switch, ARRAY_SIZE(adc2_switch), wcd939x_tx_swr_ctrl, 2642 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2643 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, 2644 adc3_switch, ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl, 2645 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2646 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, 2647 adc4_switch, ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl, 2648 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2649 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, 2650 dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd939x_tx_swr_ctrl, 2651 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2652 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, 2653 dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd939x_tx_swr_ctrl, 2654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2655 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, 2656 dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd939x_tx_swr_ctrl, 2657 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2658 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, 2659 dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd939x_tx_swr_ctrl, 2660 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2661 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, 2662 dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd939x_tx_swr_ctrl, 2663 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2664 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, 2665 dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd939x_tx_swr_ctrl, 2666 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2667 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, 2668 dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd939x_tx_swr_ctrl, 2669 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2670 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, 2671 dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd939x_tx_swr_ctrl, 2672 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2673 2674 /* micbias widgets */ 2675 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2676 wcd939x_codec_enable_micbias, 2677 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2678 SND_SOC_DAPM_POST_PMD), 2679 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2680 wcd939x_codec_enable_micbias, 2681 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2682 SND_SOC_DAPM_POST_PMD), 2683 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2684 wcd939x_codec_enable_micbias, 2685 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2686 SND_SOC_DAPM_POST_PMD), 2687 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2688 wcd939x_codec_enable_micbias, 2689 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2690 SND_SOC_DAPM_POST_PMD), 2691 2692 /* micbias pull up widgets */ 2693 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2694 wcd939x_codec_enable_micbias_pullup, 2695 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2696 SND_SOC_DAPM_POST_PMD), 2697 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2698 wcd939x_codec_enable_micbias_pullup, 2699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2700 SND_SOC_DAPM_POST_PMD), 2701 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2702 wcd939x_codec_enable_micbias_pullup, 2703 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2704 SND_SOC_DAPM_POST_PMD), 2705 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2706 wcd939x_codec_enable_micbias_pullup, 2707 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2708 SND_SOC_DAPM_POST_PMD), 2709 2710 /* output widgets tx */ 2711 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2712 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2713 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2714 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 2715 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2716 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2717 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2718 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2719 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2720 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2721 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 2722 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 2723 2724 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2725 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2726 SND_SOC_DAPM_INPUT("IN3_EAR"), 2727 2728 /* rx widgets */ 2729 SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_ANA_EAR, 7, 0, NULL, 0, 2730 wcd939x_codec_enable_ear_pa, 2731 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2732 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2733 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_ANA_HPH, 7, 0, NULL, 0, 2734 wcd939x_codec_enable_hphl_pa, 2735 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2736 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2737 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_ANA_HPH, 6, 0, NULL, 0, 2738 wcd939x_codec_enable_hphr_pa, 2739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2740 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2741 2742 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2743 wcd939x_codec_hphl_dac_event, 2744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2745 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2746 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2747 wcd939x_codec_hphr_dac_event, 2748 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2749 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2750 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2751 wcd939x_codec_ear_dac_event, 2752 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2753 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2754 2755 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2756 2757 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2758 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 2759 wcd939x_codec_enable_rxclk, 2760 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2761 SND_SOC_DAPM_POST_PMD), 2762 2763 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2764 2765 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2766 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2767 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2768 2769 /* rx mixer widgets */ 2770 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2771 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2772 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2773 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2774 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2775 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2776 2777 /* output widgets rx */ 2778 SND_SOC_DAPM_OUTPUT("EAR"), 2779 SND_SOC_DAPM_OUTPUT("HPHL"), 2780 SND_SOC_DAPM_OUTPUT("HPHR"), 2781 }; 2782 2783 static const struct snd_soc_dapm_route wcd939x_audio_map[] = { 2784 /* TX Path */ 2785 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 2786 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 2787 {"ADC1 REQ", NULL, "ADC1"}, 2788 {"ADC1", NULL, "ADC1 MUX"}, 2789 {"ADC1 MUX", "CH1_AMIC1", "AMIC1"}, 2790 {"ADC1 MUX", "CH1_AMIC2", "AMIC2"}, 2791 {"ADC1 MUX", "CH1_AMIC3", "AMIC3"}, 2792 {"ADC1 MUX", "CH1_AMIC4", "AMIC4"}, 2793 {"ADC1 MUX", "CH1_AMIC5", "AMIC5"}, 2794 2795 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 2796 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 2797 {"ADC2 REQ", NULL, "ADC2"}, 2798 {"ADC2", NULL, "ADC2 MUX"}, 2799 {"ADC2 MUX", "CH2_AMIC1", "AMIC1"}, 2800 {"ADC2 MUX", "CH2_AMIC2", "AMIC2"}, 2801 {"ADC2 MUX", "CH2_AMIC3", "AMIC3"}, 2802 {"ADC2 MUX", "CH2_AMIC4", "AMIC4"}, 2803 {"ADC2 MUX", "CH2_AMIC5", "AMIC5"}, 2804 2805 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 2806 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 2807 {"ADC3 REQ", NULL, "ADC3"}, 2808 {"ADC3", NULL, "ADC3 MUX"}, 2809 {"ADC3 MUX", "CH3_AMIC1", "AMIC1"}, 2810 {"ADC3 MUX", "CH3_AMIC3", "AMIC3"}, 2811 {"ADC3 MUX", "CH3_AMIC4", "AMIC4"}, 2812 {"ADC3 MUX", "CH3_AMIC5", "AMIC5"}, 2813 2814 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 2815 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 2816 {"ADC4 REQ", NULL, "ADC4"}, 2817 {"ADC4", NULL, "ADC4 MUX"}, 2818 {"ADC4 MUX", "CH4_AMIC1", "AMIC1"}, 2819 {"ADC4 MUX", "CH4_AMIC3", "AMIC3"}, 2820 {"ADC4 MUX", "CH4_AMIC4", "AMIC4"}, 2821 {"ADC4 MUX", "CH4_AMIC5", "AMIC5"}, 2822 2823 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 2824 {"DMIC1_MIXER", "Switch", "DMIC1"}, 2825 2826 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 2827 {"DMIC2_MIXER", "Switch", "DMIC2"}, 2828 2829 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 2830 {"DMIC3_MIXER", "Switch", "DMIC3"}, 2831 2832 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 2833 {"DMIC4_MIXER", "Switch", "DMIC4"}, 2834 2835 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 2836 {"DMIC5_MIXER", "Switch", "DMIC5"}, 2837 2838 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 2839 {"DMIC6_MIXER", "Switch", "DMIC6"}, 2840 2841 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 2842 {"DMIC7_MIXER", "Switch", "DMIC7"}, 2843 2844 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 2845 {"DMIC8_MIXER", "Switch", "DMIC8"}, 2846 2847 /* RX Path */ 2848 {"IN1_HPHL", NULL, "VDD_BUCK"}, 2849 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 2850 2851 {"RX1", NULL, "IN1_HPHL"}, 2852 {"RX1", NULL, "RXCLK"}, 2853 {"RDAC1", NULL, "RX1"}, 2854 {"HPHL_RDAC", "Switch", "RDAC1"}, 2855 {"HPHL PGA", NULL, "HPHL_RDAC"}, 2856 {"HPHL", NULL, "HPHL PGA"}, 2857 2858 {"IN2_HPHR", NULL, "VDD_BUCK"}, 2859 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 2860 {"RX2", NULL, "IN2_HPHR"}, 2861 {"RDAC2", NULL, "RX2"}, 2862 {"RX2", NULL, "RXCLK"}, 2863 {"HPHR_RDAC", "Switch", "RDAC2"}, 2864 {"HPHR PGA", NULL, "HPHR_RDAC"}, 2865 {"HPHR", NULL, "HPHR PGA"}, 2866 2867 {"IN3_EAR", NULL, "VDD_BUCK"}, 2868 {"RX3", NULL, "IN3_EAR"}, 2869 {"RX3", NULL, "RXCLK"}, 2870 2871 {"RDAC3_MUX", "RX3", "RX3"}, 2872 {"RDAC3_MUX", "RX1", "RX1"}, 2873 {"RDAC3", NULL, "RDAC3_MUX"}, 2874 {"EAR_RDAC", "Switch", "RDAC3"}, 2875 {"EAR PGA", NULL, "EAR_RDAC"}, 2876 {"EAR", NULL, "EAR PGA"}, 2877 }; 2878 2879 static void wcd939x_set_micbias_data(struct device *dev, struct wcd939x_priv *wcd939x) 2880 { 2881 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB1, 2882 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[0]); 2883 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB2, 2884 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[1]); 2885 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB3, 2886 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[2]); 2887 regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB4, 2888 WCD939X_MICB_VOUT_CTL, wcd939x->common.micb_vout[3]); 2889 } 2890 2891 static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data) 2892 { 2893 /* 2894 * HPHR/HPHL/EAR Watchdog interrupt threaded handler 2895 * 2896 * Watchdog interrupts are expected to be enabled when switching 2897 * on the HPHL/R and EAR RX PGA in order to make sure the interrupts 2898 * are acked by the regmap_irq handler to allow PDM sync. 2899 * We could leave those interrupts masked but we would not have 2900 * any valid way to enable/disable them without violating irq layers. 2901 * 2902 * The HPHR/HPHL/EAR Watchdog interrupts are handled 2903 * by regmap_irq, so requesting a threaded handler is the 2904 * safest way to be able to ack those interrupts without 2905 * colliding with the regmap_irq setup. 2906 */ 2907 2908 return IRQ_HANDLED; 2909 } 2910 2911 /* 2912 * Setup a virtual interrupt domain to hook regmap_irq 2913 * The root domain will have a single interrupt which mapping 2914 * will trigger the regmap_irq handler. 2915 * 2916 * root: 2917 * wcd_irq_chip 2918 * [0] wcd939x_regmap_irq_chip 2919 * [0] MBHC_BUTTON_PRESS_DET 2920 * [1] MBHC_BUTTON_RELEASE_DET 2921 * ... 2922 * [16] HPHR_SURGE_DET_INT 2923 * 2924 * Interrupt trigger: 2925 * soundwire_interrupt_callback() 2926 * \-handle_nested_irq(0) 2927 * \- regmap_irq_thread() 2928 * \- handle_nested_irq(i) 2929 */ 2930 static const struct irq_chip wcd_irq_chip = { 2931 .name = "WCD939x", 2932 }; 2933 2934 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2935 irq_hw_number_t hw) 2936 { 2937 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2938 irq_set_nested_thread(virq, 1); 2939 irq_set_noprobe(virq); 2940 2941 return 0; 2942 } 2943 2944 static const struct irq_domain_ops wcd_domain_ops = { 2945 .map = wcd_irq_chip_map, 2946 }; 2947 2948 static int wcd939x_irq_init(struct wcd939x_priv *wcd, struct device *dev) 2949 { 2950 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 2951 if (!(wcd->virq)) { 2952 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 2953 return -EINVAL; 2954 } 2955 2956 return devm_regmap_add_irq_chip(dev, wcd->regmap, 2957 irq_create_mapping(wcd->virq, 0), 2958 IRQF_ONESHOT, 0, &wcd939x_regmap_irq_chip, 2959 &wcd->irq_chip); 2960 } 2961 2962 static int wcd939x_soc_codec_probe(struct snd_soc_component *component) 2963 { 2964 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 2965 struct device *dev = component->dev; 2966 int ret, i; 2967 2968 ret = sdw_slave_wait_for_init(wcd939x->tx_sdw_dev, 2000); 2969 if (ret) 2970 return ret; 2971 2972 snd_soc_component_init_regmap(component, wcd939x->regmap); 2973 2974 ret = pm_runtime_resume_and_get(dev); 2975 if (ret < 0) 2976 return ret; 2977 2978 wcd939x->variant = snd_soc_component_read_field(component, 2979 WCD939X_DIGITAL_EFUSE_REG_0, 2980 WCD939X_EFUSE_REG_0_WCD939X_ID); 2981 2982 wcd939x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD939X); 2983 if (IS_ERR(wcd939x->clsh_info)) { 2984 pm_runtime_put(dev); 2985 return PTR_ERR(wcd939x->clsh_info); 2986 } 2987 2988 wcd939x_io_init(component); 2989 2990 /* Set all interrupts as edge triggered */ 2991 for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++) 2992 regmap_write(wcd939x->regmap, 2993 (WCD939X_DIGITAL_INTR_LEVEL_0 + i), 0); 2994 2995 pm_runtime_put(dev); 2996 2997 /* Request for watchdog interrupt */ 2998 wcd939x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip, 2999 WCD939X_IRQ_HPHR_PDM_WD_INT); 3000 wcd939x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip, 3001 WCD939X_IRQ_HPHL_PDM_WD_INT); 3002 wcd939x->ear_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip, 3003 WCD939X_IRQ_EAR_PDM_WD_INT); 3004 3005 ret = request_threaded_irq(wcd939x->hphr_pdm_wd_int, NULL, wcd939x_wd_handle_irq, 3006 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3007 "HPHR PDM WD INT", wcd939x); 3008 if (ret) { 3009 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3010 goto err_free_clsh_ctrl; 3011 } 3012 3013 ret = request_threaded_irq(wcd939x->hphl_pdm_wd_int, NULL, wcd939x_wd_handle_irq, 3014 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3015 "HPHL PDM WD INT", wcd939x); 3016 if (ret) { 3017 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3018 goto err_free_hphr_pdm_wd_int; 3019 } 3020 3021 ret = request_threaded_irq(wcd939x->ear_pdm_wd_int, NULL, wcd939x_wd_handle_irq, 3022 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3023 "AUX PDM WD INT", wcd939x); 3024 if (ret) { 3025 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3026 goto err_free_hphl_pdm_wd_int; 3027 } 3028 3029 /* Disable watchdog interrupt for HPH and AUX */ 3030 disable_irq_nosync(wcd939x->hphr_pdm_wd_int); 3031 disable_irq_nosync(wcd939x->hphl_pdm_wd_int); 3032 disable_irq_nosync(wcd939x->ear_pdm_wd_int); 3033 3034 switch (wcd939x->variant) { 3035 case CHIPID_WCD9390: 3036 ret = snd_soc_add_component_controls(component, wcd9390_snd_controls, 3037 ARRAY_SIZE(wcd9390_snd_controls)); 3038 if (ret < 0) { 3039 dev_err(component->dev, 3040 "%s: Failed to add snd ctrls for variant: %d\n", 3041 __func__, wcd939x->variant); 3042 goto err_free_ear_pdm_wd_int; 3043 } 3044 break; 3045 case CHIPID_WCD9395: 3046 ret = snd_soc_add_component_controls(component, wcd9395_snd_controls, 3047 ARRAY_SIZE(wcd9395_snd_controls)); 3048 if (ret < 0) { 3049 dev_err(component->dev, 3050 "%s: Failed to add snd ctrls for variant: %d\n", 3051 __func__, wcd939x->variant); 3052 goto err_free_ear_pdm_wd_int; 3053 } 3054 break; 3055 default: 3056 break; 3057 } 3058 3059 ret = wcd939x_mbhc_init(component); 3060 if (ret) { 3061 dev_err(component->dev, "mbhc initialization failed\n"); 3062 goto err_free_ear_pdm_wd_int; 3063 } 3064 3065 return 0; 3066 3067 err_free_ear_pdm_wd_int: 3068 free_irq(wcd939x->ear_pdm_wd_int, wcd939x); 3069 err_free_hphl_pdm_wd_int: 3070 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x); 3071 err_free_hphr_pdm_wd_int: 3072 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x); 3073 err_free_clsh_ctrl: 3074 wcd_clsh_ctrl_free(wcd939x->clsh_info); 3075 3076 return ret; 3077 } 3078 3079 static void wcd939x_soc_codec_remove(struct snd_soc_component *component) 3080 { 3081 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 3082 3083 wcd939x_mbhc_deinit(component); 3084 3085 free_irq(wcd939x->ear_pdm_wd_int, wcd939x); 3086 free_irq(wcd939x->hphl_pdm_wd_int, wcd939x); 3087 free_irq(wcd939x->hphr_pdm_wd_int, wcd939x); 3088 3089 wcd_clsh_ctrl_free(wcd939x->clsh_info); 3090 } 3091 3092 static int wcd939x_codec_set_jack(struct snd_soc_component *comp, 3093 struct snd_soc_jack *jack, void *data) 3094 { 3095 struct wcd939x_priv *wcd = dev_get_drvdata(comp->dev); 3096 3097 if (jack) 3098 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 3099 3100 wcd_mbhc_stop(wcd->wcd_mbhc); 3101 3102 return 0; 3103 } 3104 3105 static const struct snd_soc_component_driver soc_codec_dev_wcd939x = { 3106 .name = "wcd939x_codec", 3107 .probe = wcd939x_soc_codec_probe, 3108 .remove = wcd939x_soc_codec_remove, 3109 .controls = wcd939x_snd_controls, 3110 .num_controls = ARRAY_SIZE(wcd939x_snd_controls), 3111 .dapm_widgets = wcd939x_dapm_widgets, 3112 .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets), 3113 .dapm_routes = wcd939x_audio_map, 3114 .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map), 3115 .set_jack = wcd939x_codec_set_jack, 3116 .endianness = 1, 3117 }; 3118 3119 #if IS_ENABLED(CONFIG_TYPEC) 3120 /* Get USB-C plug orientation to provide swap event for MBHC */ 3121 static int wcd939x_typec_switch_set(struct typec_switch_dev *sw, 3122 enum typec_orientation orientation) 3123 { 3124 struct wcd939x_priv *wcd939x = typec_switch_get_drvdata(sw); 3125 3126 wcd939x->typec_orientation = orientation; 3127 3128 return 0; 3129 } 3130 3131 static int wcd939x_typec_mux_set(struct typec_mux_dev *mux, 3132 struct typec_mux_state *state) 3133 { 3134 struct wcd939x_priv *wcd939x = typec_mux_get_drvdata(mux); 3135 unsigned int previous_mode = wcd939x->typec_mode; 3136 3137 if (!wcd939x->wcd_mbhc) 3138 return -EINVAL; 3139 3140 if (wcd939x->typec_mode != state->mode) { 3141 wcd939x->typec_mode = state->mode; 3142 3143 if (wcd939x->typec_mode == TYPEC_MODE_AUDIO) 3144 return wcd_mbhc_typec_report_plug(wcd939x->wcd_mbhc); 3145 else if (previous_mode == TYPEC_MODE_AUDIO) 3146 return wcd_mbhc_typec_report_unplug(wcd939x->wcd_mbhc); 3147 } 3148 3149 return 0; 3150 } 3151 #endif /* CONFIG_TYPEC */ 3152 3153 #if IS_ENABLED(CONFIG_TYPEC) 3154 static bool wcd939x_swap_gnd_mic(struct snd_soc_component *component) 3155 { 3156 struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component); 3157 3158 if (!wcd939x->typec_analog_mux || !wcd939x->typec_switch) 3159 return false; 3160 3161 /* Report inversion via Type Switch of USBSS */ 3162 typec_switch_set(wcd939x->typec_switch, 3163 wcd939x->typec_orientation == TYPEC_ORIENTATION_REVERSE ? 3164 TYPEC_ORIENTATION_NORMAL : TYPEC_ORIENTATION_REVERSE); 3165 3166 return true; 3167 } 3168 #endif /* CONFIG_TYPEC */ 3169 3170 static int wcd939x_populate_dt_data(struct wcd939x_priv *wcd939x, struct device *dev) 3171 { 3172 struct wcd_mbhc_config *cfg = &wcd939x->mbhc_cfg; 3173 #if IS_ENABLED(CONFIG_TYPEC) 3174 struct device_node *np; 3175 #endif /* CONFIG_TYPEC */ 3176 int ret; 3177 3178 wcd939x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 3179 if (IS_ERR(wcd939x->reset_gpio)) 3180 return dev_err_probe(dev, PTR_ERR(wcd939x->reset_gpio), 3181 "Failed to get reset gpio\n"); 3182 3183 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd939x_supplies), 3184 wcd939x_supplies); 3185 if (ret) 3186 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 3187 3188 ret = wcd_dt_parse_micbias_info(&wcd939x->common); 3189 if (ret) 3190 return dev_err_probe(dev, ret, "Failed to get micbias\n"); 3191 3192 cfg->mbhc_micbias = MIC_BIAS_2; 3193 cfg->anc_micbias = MIC_BIAS_2; 3194 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 3195 cfg->num_btn = WCD939X_MBHC_MAX_BUTTONS; 3196 cfg->micb_mv = wcd939x->common.micb_mv[1]; 3197 cfg->linein_th = 5000; 3198 cfg->hs_thr = 1700; 3199 cfg->hph_thr = 50; 3200 3201 wcd_dt_parse_mbhc_data(dev, cfg); 3202 3203 #if IS_ENABLED(CONFIG_TYPEC) 3204 /* 3205 * Is node has a port and a valid remote endpoint 3206 * consider HP lines are connected to the USBSS part 3207 */ 3208 np = of_graph_get_remote_node(dev->of_node, 0, 0); 3209 if (np) { 3210 wcd939x->typec_analog_mux = true; 3211 cfg->typec_analog_mux = true; 3212 cfg->swap_gnd_mic = wcd939x_swap_gnd_mic; 3213 } 3214 #endif /* CONFIG_TYPEC */ 3215 3216 return 0; 3217 } 3218 3219 static int wcd939x_reset(struct wcd939x_priv *wcd939x) 3220 { 3221 gpiod_set_value(wcd939x->reset_gpio, 1); 3222 /* 20us sleep required after pulling the reset gpio to LOW */ 3223 usleep_range(20, 30); 3224 gpiod_set_value(wcd939x->reset_gpio, 0); 3225 /* 20us sleep required after pulling the reset gpio to HIGH */ 3226 usleep_range(20, 30); 3227 3228 return 0; 3229 } 3230 3231 static int wcd939x_codec_hw_params(struct snd_pcm_substream *substream, 3232 struct snd_pcm_hw_params *params, 3233 struct snd_soc_dai *dai) 3234 { 3235 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev); 3236 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id]; 3237 3238 return wcd939x_sdw_hw_params(wcd, substream, params, dai); 3239 } 3240 3241 static int wcd939x_codec_free(struct snd_pcm_substream *substream, 3242 struct snd_soc_dai *dai) 3243 { 3244 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev); 3245 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id]; 3246 3247 return wcd939x_sdw_free(wcd, substream, dai); 3248 } 3249 3250 static int wcd939x_codec_set_sdw_stream(struct snd_soc_dai *dai, 3251 void *stream, int direction) 3252 { 3253 struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev); 3254 struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id]; 3255 3256 return wcd939x_sdw_set_sdw_stream(wcd, dai, stream, direction); 3257 } 3258 3259 static const struct snd_soc_dai_ops wcd939x_sdw_dai_ops = { 3260 .hw_params = wcd939x_codec_hw_params, 3261 .hw_free = wcd939x_codec_free, 3262 .set_stream = wcd939x_codec_set_sdw_stream, 3263 }; 3264 3265 static struct snd_soc_dai_driver wcd939x_dais[] = { 3266 [0] = { 3267 .name = "wcd939x-sdw-rx", 3268 .playback = { 3269 .stream_name = "WCD AIF1 Playback", 3270 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK, 3271 .formats = WCD939X_FORMATS, 3272 .rate_max = 384000, 3273 .rate_min = 8000, 3274 .channels_min = 1, 3275 .channels_max = 2, 3276 }, 3277 .ops = &wcd939x_sdw_dai_ops, 3278 }, 3279 [1] = { 3280 .name = "wcd939x-sdw-tx", 3281 .capture = { 3282 .stream_name = "WCD AIF1 Capture", 3283 .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK, 3284 .formats = WCD939X_FORMATS, 3285 .rate_min = 8000, 3286 .rate_max = 384000, 3287 .channels_min = 1, 3288 .channels_max = 4, 3289 }, 3290 .ops = &wcd939x_sdw_dai_ops, 3291 }, 3292 }; 3293 3294 static int wcd939x_bind(struct device *dev) 3295 { 3296 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev); 3297 unsigned int version, id1, status1; 3298 int ret; 3299 3300 #if IS_ENABLED(CONFIG_TYPEC) 3301 /* 3302 * Get USBSS type-c switch to send gnd/mic swap events 3303 * typec_switch is fetched now to avoid a probe deadlock since 3304 * the USBSS depends on the typec_mux register in wcd939x_probe() 3305 */ 3306 if (wcd939x->typec_analog_mux) { 3307 wcd939x->typec_switch = fwnode_typec_switch_get(dev->fwnode); 3308 if (IS_ERR(wcd939x->typec_switch)) 3309 return dev_err_probe(dev, PTR_ERR(wcd939x->typec_switch), 3310 "failed to acquire orientation-switch\n"); 3311 } 3312 #endif /* CONFIG_TYPEC */ 3313 3314 ret = component_bind_all(dev, wcd939x); 3315 if (ret) { 3316 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 3317 __func__, ret); 3318 goto err_put_typec_switch; 3319 } 3320 3321 wcd939x->rxdev = of_sdw_find_device_by_node(wcd939x->rxnode); 3322 if (!wcd939x->rxdev) { 3323 dev_err(dev, "could not find slave with matching of node\n"); 3324 ret = -EINVAL; 3325 goto err_unbind; 3326 } 3327 wcd939x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd939x->rxdev); 3328 wcd939x->sdw_priv[AIF1_PB]->wcd939x = wcd939x; 3329 3330 wcd939x->txdev = of_sdw_find_device_by_node(wcd939x->txnode); 3331 if (!wcd939x->txdev) { 3332 dev_err(dev, "could not find txslave with matching of node\n"); 3333 ret = -EINVAL; 3334 goto err_put_rxdev; 3335 } 3336 wcd939x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd939x->txdev); 3337 wcd939x->sdw_priv[AIF1_CAP]->wcd939x = wcd939x; 3338 wcd939x->tx_sdw_dev = dev_to_sdw_dev(wcd939x->txdev); 3339 3340 /* 3341 * As TX is main CSR reg interface, which should not be suspended first. 3342 * explicitly add the dependency link 3343 */ 3344 if (!device_link_add(wcd939x->rxdev, wcd939x->txdev, DL_FLAG_STATELESS | 3345 DL_FLAG_PM_RUNTIME)) { 3346 dev_err(dev, "could not devlink tx and rx\n"); 3347 ret = -EINVAL; 3348 goto err_put_txdev; 3349 } 3350 3351 if (!device_link_add(dev, wcd939x->txdev, DL_FLAG_STATELESS | 3352 DL_FLAG_PM_RUNTIME)) { 3353 dev_err(dev, "could not devlink wcd and tx\n"); 3354 ret = -EINVAL; 3355 goto err_remove_rxtx_link; 3356 } 3357 3358 if (!device_link_add(dev, wcd939x->rxdev, DL_FLAG_STATELESS | 3359 DL_FLAG_PM_RUNTIME)) { 3360 dev_err(dev, "could not devlink wcd and rx\n"); 3361 ret = -EINVAL; 3362 goto err_remove_tx_link; 3363 } 3364 3365 /* Get regmap from TX SoundWire device */ 3366 wcd939x->regmap = wcd939x->sdw_priv[AIF1_CAP]->regmap; 3367 if (!wcd939x->regmap) { 3368 dev_err(dev, "could not get TX device regmap\n"); 3369 ret = -ENODEV; 3370 goto err_remove_rx_link; 3371 } 3372 3373 ret = wcd939x_irq_init(wcd939x, dev); 3374 if (ret) { 3375 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 3376 goto err_remove_rx_link; 3377 } 3378 3379 wcd939x->sdw_priv[AIF1_PB]->slave_irq = wcd939x->virq; 3380 wcd939x->sdw_priv[AIF1_CAP]->slave_irq = wcd939x->virq; 3381 3382 wcd939x_set_micbias_data(dev, wcd939x); 3383 3384 /* Check WCD9395 version */ 3385 regmap_read(wcd939x->regmap, WCD939X_DIGITAL_CHIP_ID1, &id1); 3386 regmap_read(wcd939x->regmap, WCD939X_EAR_STATUS_REG_1, &status1); 3387 3388 if (id1 == CHIPID_WCD939X_VER_MAJOR_1) 3389 version = ((status1 & CHIPID_WCD939X_VER_MINOR_1) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0); 3390 else 3391 version = WCD939X_VERSION_2_0; 3392 3393 dev_dbg(dev, "wcd939x version: %s\n", version_to_str(version)); 3394 3395 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x, 3396 wcd939x_dais, ARRAY_SIZE(wcd939x_dais)); 3397 if (ret) { 3398 dev_err(dev, "%s: Codec registration failed\n", 3399 __func__); 3400 goto err_remove_rx_link; 3401 } 3402 3403 return 0; 3404 3405 err_remove_rx_link: 3406 device_link_remove(dev, wcd939x->rxdev); 3407 err_remove_tx_link: 3408 device_link_remove(dev, wcd939x->txdev); 3409 err_remove_rxtx_link: 3410 device_link_remove(wcd939x->rxdev, wcd939x->txdev); 3411 err_put_txdev: 3412 put_device(wcd939x->txdev); 3413 err_put_rxdev: 3414 put_device(wcd939x->rxdev); 3415 err_unbind: 3416 component_unbind_all(dev, wcd939x); 3417 err_put_typec_switch: 3418 #if IS_ENABLED(CONFIG_TYPEC) 3419 if (wcd939x->typec_analog_mux) 3420 typec_switch_put(wcd939x->typec_switch); 3421 #endif /* CONFIG_TYPEC */ 3422 3423 return ret; 3424 } 3425 3426 static void wcd939x_unbind(struct device *dev) 3427 { 3428 struct wcd939x_priv *wcd939x = dev_get_drvdata(dev); 3429 3430 snd_soc_unregister_component(dev); 3431 device_link_remove(dev, wcd939x->txdev); 3432 device_link_remove(dev, wcd939x->rxdev); 3433 device_link_remove(wcd939x->rxdev, wcd939x->txdev); 3434 put_device(wcd939x->txdev); 3435 put_device(wcd939x->rxdev); 3436 component_unbind_all(dev, wcd939x); 3437 } 3438 3439 static const struct component_master_ops wcd939x_comp_ops = { 3440 .bind = wcd939x_bind, 3441 .unbind = wcd939x_unbind, 3442 }; 3443 3444 static void __maybe_unused wcd939x_typec_mux_unregister(void *data) 3445 { 3446 struct typec_mux_dev *typec_mux = data; 3447 3448 typec_mux_unregister(typec_mux); 3449 } 3450 3451 static void __maybe_unused wcd939x_typec_switch_unregister(void *data) 3452 { 3453 struct typec_switch_dev *typec_sw = data; 3454 3455 typec_switch_unregister(typec_sw); 3456 } 3457 3458 static int wcd939x_add_typec(struct wcd939x_priv *wcd939x, struct device *dev) 3459 { 3460 #if IS_ENABLED(CONFIG_TYPEC) 3461 int ret; 3462 struct typec_mux_dev *typec_mux; 3463 struct typec_switch_dev *typec_sw; 3464 struct typec_mux_desc mux_desc = { 3465 .drvdata = wcd939x, 3466 .fwnode = dev_fwnode(dev), 3467 .set = wcd939x_typec_mux_set, 3468 }; 3469 struct typec_switch_desc sw_desc = { 3470 .drvdata = wcd939x, 3471 .fwnode = dev_fwnode(dev), 3472 .set = wcd939x_typec_switch_set, 3473 }; 3474 3475 /* 3476 * Is USBSS is used to mux analog lines, 3477 * register a typec mux/switch to get typec events 3478 */ 3479 if (!wcd939x->typec_analog_mux) 3480 return 0; 3481 3482 typec_mux = typec_mux_register(dev, &mux_desc); 3483 if (IS_ERR(typec_mux)) 3484 return dev_err_probe(dev, PTR_ERR(typec_mux), 3485 "failed to register typec mux\n"); 3486 3487 ret = devm_add_action_or_reset(dev, wcd939x_typec_mux_unregister, 3488 typec_mux); 3489 if (ret) 3490 return ret; 3491 3492 typec_sw = typec_switch_register(dev, &sw_desc); 3493 if (IS_ERR(typec_sw)) 3494 return dev_err_probe(dev, PTR_ERR(typec_sw), 3495 "failed to register typec switch\n"); 3496 3497 ret = devm_add_action_or_reset(dev, wcd939x_typec_switch_unregister, 3498 typec_sw); 3499 if (ret) 3500 return ret; 3501 #endif 3502 3503 return 0; 3504 } 3505 3506 static int wcd939x_add_slave_components(struct wcd939x_priv *wcd939x, 3507 struct device *dev, 3508 struct component_match **matchptr) 3509 { 3510 struct device_node *np = dev->of_node; 3511 3512 wcd939x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 3513 if (!wcd939x->rxnode) { 3514 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 3515 return -ENODEV; 3516 } 3517 3518 component_match_add_release(dev, matchptr, component_release_of, 3519 component_compare_of, wcd939x->rxnode); 3520 3521 wcd939x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 3522 if (!wcd939x->txnode) { 3523 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 3524 return -ENODEV; 3525 } 3526 3527 component_match_add_release(dev, matchptr, component_release_of, 3528 component_compare_of, wcd939x->txnode); 3529 return 0; 3530 } 3531 3532 static int wcd939x_probe(struct platform_device *pdev) 3533 { 3534 struct component_match *match = NULL; 3535 struct wcd939x_priv *wcd939x = NULL; 3536 struct device *dev = &pdev->dev; 3537 int ret; 3538 3539 wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv), 3540 GFP_KERNEL); 3541 if (!wcd939x) 3542 return -ENOMEM; 3543 3544 dev_set_drvdata(dev, wcd939x); 3545 mutex_init(&wcd939x->micb_lock); 3546 wcd939x->common.dev = dev; 3547 wcd939x->common.max_bias = 4; 3548 3549 ret = wcd939x_populate_dt_data(wcd939x, dev); 3550 if (ret) { 3551 dev_err(dev, "%s: Fail to obtain platform data\n", __func__); 3552 return -EINVAL; 3553 } 3554 3555 ret = wcd939x_add_typec(wcd939x, dev); 3556 if (ret) 3557 return ret; 3558 3559 ret = wcd939x_add_slave_components(wcd939x, dev, &match); 3560 if (ret) 3561 return ret; 3562 3563 wcd939x_reset(wcd939x); 3564 3565 ret = component_master_add_with_match(dev, &wcd939x_comp_ops, match); 3566 if (ret) 3567 return ret; 3568 3569 pm_runtime_set_autosuspend_delay(dev, 1000); 3570 pm_runtime_use_autosuspend(dev); 3571 pm_runtime_mark_last_busy(dev); 3572 pm_runtime_set_active(dev); 3573 pm_runtime_enable(dev); 3574 pm_runtime_idle(dev); 3575 3576 return 0; 3577 } 3578 3579 static void wcd939x_remove(struct platform_device *pdev) 3580 { 3581 struct device *dev = &pdev->dev; 3582 3583 component_master_del(dev, &wcd939x_comp_ops); 3584 3585 pm_runtime_disable(dev); 3586 pm_runtime_set_suspended(dev); 3587 pm_runtime_dont_use_autosuspend(dev); 3588 } 3589 3590 #if defined(CONFIG_OF) 3591 static const struct of_device_id wcd939x_dt_match[] = { 3592 { .compatible = "qcom,wcd9390-codec" }, 3593 { .compatible = "qcom,wcd9395-codec" }, 3594 {} 3595 }; 3596 MODULE_DEVICE_TABLE(of, wcd939x_dt_match); 3597 #endif 3598 3599 static struct platform_driver wcd939x_codec_driver = { 3600 .probe = wcd939x_probe, 3601 .remove = wcd939x_remove, 3602 .driver = { 3603 .name = "wcd939x_codec", 3604 .of_match_table = of_match_ptr(wcd939x_dt_match), 3605 .suppress_bind_attrs = true, 3606 }, 3607 }; 3608 3609 module_platform_driver(wcd939x_codec_driver); 3610 MODULE_DESCRIPTION("WCD939X Codec driver"); 3611 MODULE_LICENSE("GPL"); 3612