1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/cleanup.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/platform_device.h> 8 #include <linux/device.h> 9 #include <linux/delay.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/component.h> 14 #include <sound/tlv.h> 15 #include <linux/of.h> 16 #include <sound/jack.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <linux/regmap.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <linux/mux/consumer.h> 23 #include <linux/regulator/consumer.h> 24 25 #include "wcd-clsh-v2.h" 26 #include "wcd-common.h" 27 #include "wcd-mbhc-v2.h" 28 #include "wcd938x.h" 29 30 #define CHIPID_WCD9380 0x0 31 #define CHIPID_WCD9385 0x5 32 33 #define WCD938X_MAX_MICBIAS (4) 34 #define WCD938X_MBHC_MAX_BUTTONS (8) 35 #define TX_ADC_MAX (4) 36 37 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 38 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 39 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 40 /* Fractional Rates */ 41 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 42 SNDRV_PCM_RATE_176400) 43 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 44 SNDRV_PCM_FMTBIT_S24_LE) 45 #define SWR_CLK_RATE_0P6MHZ (600000) 46 #define SWR_CLK_RATE_1P2MHZ (1200000) 47 #define SWR_CLK_RATE_2P4MHZ (2400000) 48 #define SWR_CLK_RATE_4P8MHZ (4800000) 49 #define SWR_CLK_RATE_9P6MHZ (9600000) 50 #define SWR_CLK_RATE_11P2896MHZ (1128960) 51 52 #define EAR_RX_PATH_AUX (1) 53 54 #define ADC_MODE_VAL_HIFI 0x01 55 #define ADC_MODE_VAL_LO_HIF 0x02 56 #define ADC_MODE_VAL_NORMAL 0x03 57 #define ADC_MODE_VAL_LP 0x05 58 #define ADC_MODE_VAL_ULP1 0x09 59 #define ADC_MODE_VAL_ULP2 0x0B 60 61 /* Z value defined in milliohm */ 62 #define WCD938X_ZDET_VAL_32 (32000) 63 #define WCD938X_ZDET_VAL_400 (400000) 64 #define WCD938X_ZDET_VAL_1200 (1200000) 65 #define WCD938X_ZDET_VAL_100K (100000000) 66 /* Z floating defined in ohms */ 67 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 68 #define WCD938X_ZDET_NUM_MEASUREMENTS (900) 69 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 70 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 71 /* Z value compared in milliOhm */ 72 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 73 #define WCD938X_MBHC_ZDET_CONST (86 * 16384) 74 #define WCD_MBHC_HS_V_MAX 1600 75 76 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 77 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, snd_soc_get_volsw, \ 78 wcd938x_ear_pa_put_gain, tlv_array) 79 80 enum { 81 /* INTR_CTRL_INT_MASK_0 */ 82 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 83 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 84 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 85 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 86 WCD938X_IRQ_MBHC_SW_DET, 87 WCD938X_IRQ_HPHR_OCP_INT, 88 WCD938X_IRQ_HPHR_CNP_INT, 89 WCD938X_IRQ_HPHL_OCP_INT, 90 91 /* INTR_CTRL_INT_MASK_1 */ 92 WCD938X_IRQ_HPHL_CNP_INT, 93 WCD938X_IRQ_EAR_CNP_INT, 94 WCD938X_IRQ_EAR_SCD_INT, 95 WCD938X_IRQ_AUX_CNP_INT, 96 WCD938X_IRQ_AUX_SCD_INT, 97 WCD938X_IRQ_HPHL_PDM_WD_INT, 98 WCD938X_IRQ_HPHR_PDM_WD_INT, 99 WCD938X_IRQ_AUX_PDM_WD_INT, 100 101 /* INTR_CTRL_INT_MASK_2 */ 102 WCD938X_IRQ_LDORT_SCD_INT, 103 WCD938X_IRQ_MBHC_MOISTURE_INT, 104 WCD938X_IRQ_HPHL_SURGE_DET_INT, 105 WCD938X_IRQ_HPHR_SURGE_DET_INT, 106 WCD938X_NUM_IRQS, 107 }; 108 109 enum { 110 WCD_ADC1 = 0, 111 WCD_ADC2, 112 WCD_ADC3, 113 WCD_ADC4, 114 ALLOW_BUCK_DISABLE, 115 HPH_COMP_DELAY, 116 HPH_PA_DELAY, 117 AMIC2_BCS_ENABLE, 118 WCD_SUPPLIES_LPM_MODE, 119 }; 120 121 enum { 122 ADC_MODE_INVALID = 0, 123 ADC_MODE_HIFI, 124 ADC_MODE_LO_HIF, 125 ADC_MODE_NORMAL, 126 ADC_MODE_LP, 127 ADC_MODE_ULP1, 128 ADC_MODE_ULP2, 129 }; 130 131 enum { 132 AIF1_PB = 0, 133 AIF1_CAP, 134 NUM_CODEC_DAIS, 135 }; 136 137 static u8 tx_mode_bit[] = { 138 [ADC_MODE_INVALID] = 0x00, 139 [ADC_MODE_HIFI] = 0x01, 140 [ADC_MODE_LO_HIF] = 0x02, 141 [ADC_MODE_NORMAL] = 0x04, 142 [ADC_MODE_LP] = 0x08, 143 [ADC_MODE_ULP1] = 0x10, 144 [ADC_MODE_ULP2] = 0x20, 145 }; 146 147 struct wcd938x_priv { 148 struct sdw_slave *tx_sdw_dev; 149 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 150 struct device *txdev; 151 struct device *rxdev; 152 struct device_node *rxnode, *txnode; 153 struct regmap *regmap; 154 struct mutex micb_lock; 155 /* mbhc module */ 156 struct wcd_mbhc *wcd_mbhc; 157 struct wcd_mbhc_config mbhc_cfg; 158 struct wcd_mbhc_intr intr_ids; 159 struct wcd_clsh_ctrl *clsh_info; 160 struct wcd_common common; 161 struct irq_domain *virq; 162 struct regmap_irq_chip_data *irq_chip; 163 struct snd_soc_jack *jack; 164 unsigned long status_mask; 165 s32 micb_ref[WCD938X_MAX_MICBIAS]; 166 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 167 u32 hph_mode; 168 u32 tx_mode[TX_ADC_MAX]; 169 int flyback_cur_det_disable; 170 int ear_rx_path; 171 struct gpio_desc *reset_gpio; 172 struct gpio_desc *us_euro_gpio; 173 struct mux_control *us_euro_mux; 174 unsigned int mux_state; 175 int hphr_pdm_wd_int; 176 int hphl_pdm_wd_int; 177 int aux_pdm_wd_int; 178 bool comp1_enable; 179 bool comp2_enable; 180 bool ldoh; 181 bool mux_setup_done; 182 }; 183 184 static const char * const wcd938x_supplies[] = { 185 "vdd-rxtx", "vdd-io", "vdd-buck", "vdd-mic-bias", 186 }; 187 188 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 189 static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, 0); 190 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 191 192 struct wcd938x_mbhc_zdet_param { 193 u16 ldo_ctl; 194 u16 noff; 195 u16 nshift; 196 u16 btn5; 197 u16 btn6; 198 u16 btn7; 199 }; 200 201 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 202 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 203 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 204 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 205 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 206 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 207 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 208 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 209 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 210 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 211 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 212 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 213 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 214 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 215 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 216 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 217 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 218 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 219 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 220 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 221 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 222 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 223 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 224 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 225 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 226 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 227 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 228 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 229 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 230 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 231 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 232 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 233 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 234 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 235 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 236 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 237 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 238 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 239 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 240 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 241 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 242 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 243 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 244 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 245 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 246 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 247 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 248 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 249 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 250 }; 251 252 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 253 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 254 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 255 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 256 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 257 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 258 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 259 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 260 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 261 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 262 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 263 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 264 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 265 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 266 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 267 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 268 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 269 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 270 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 271 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 272 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 273 }; 274 275 static const struct regmap_irq_chip wcd938x_regmap_irq_chip = { 276 .name = "wcd938x", 277 .irqs = wcd938x_irqs, 278 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 279 .num_regs = 3, 280 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 281 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 282 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 283 .use_ack = 1, 284 .runtime_pm = true, 285 .irq_drv_data = NULL, 286 }; 287 288 static int wcd938x_get_clk_rate(int mode) 289 { 290 int rate; 291 292 switch (mode) { 293 case ADC_MODE_ULP2: 294 rate = SWR_CLK_RATE_0P6MHZ; 295 break; 296 case ADC_MODE_ULP1: 297 rate = SWR_CLK_RATE_1P2MHZ; 298 break; 299 case ADC_MODE_LP: 300 rate = SWR_CLK_RATE_4P8MHZ; 301 break; 302 case ADC_MODE_NORMAL: 303 case ADC_MODE_LO_HIF: 304 case ADC_MODE_HIFI: 305 case ADC_MODE_INVALID: 306 default: 307 rate = SWR_CLK_RATE_9P6MHZ; 308 break; 309 } 310 311 return rate; 312 } 313 314 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 315 { 316 u8 mask = (bank ? 0xF0 : 0x0F); 317 u8 val = 0; 318 319 switch (rate) { 320 case SWR_CLK_RATE_0P6MHZ: 321 val = (bank ? 0x60 : 0x06); 322 break; 323 case SWR_CLK_RATE_1P2MHZ: 324 val = (bank ? 0x50 : 0x05); 325 break; 326 case SWR_CLK_RATE_2P4MHZ: 327 val = (bank ? 0x30 : 0x03); 328 break; 329 case SWR_CLK_RATE_4P8MHZ: 330 val = (bank ? 0x10 : 0x01); 331 break; 332 case SWR_CLK_RATE_9P6MHZ: 333 default: 334 val = 0x00; 335 break; 336 } 337 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 338 mask, val); 339 340 return 0; 341 } 342 343 static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 344 { 345 struct regmap *rm = wcd938x->regmap; 346 347 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 348 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 349 /* 1 msec delay as per HW requirement */ 350 usleep_range(1000, 1010); 351 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 352 /* 1 msec delay as per HW requirement */ 353 usleep_range(1000, 1010); 354 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 355 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 356 0xF0, 0x80); 357 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 358 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 359 /* 10 msec delay as per HW requirement */ 360 usleep_range(10000, 10010); 361 362 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 363 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 364 0xF0, 0x00); 365 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 366 0x1F, 0x15); 367 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 368 0x1F, 0x15); 369 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 370 0xC0, 0x80); 371 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 372 0x02, 0x02); 373 374 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 375 0xFF, 0x14); 376 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 377 0x1F, 0x08); 378 379 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 380 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 381 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 382 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 383 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 384 385 /* Set Noise Filter Resistor value */ 386 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 387 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 388 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 389 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 390 391 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 392 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 393 394 return 0; 395 396 } 397 398 static int wcd938x_sdw_connect_port(const struct wcd_sdw_ch_info *ch_info, 399 struct sdw_port_config *port_config, 400 u8 enable) 401 { 402 u8 ch_mask, port_num; 403 404 port_num = ch_info->port_num; 405 ch_mask = ch_info->ch_mask; 406 407 port_config->num = port_num; 408 409 if (enable) 410 port_config->ch_mask |= ch_mask; 411 else 412 port_config->ch_mask &= ~ch_mask; 413 414 return 0; 415 } 416 417 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 418 { 419 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 420 &wcd->port_config[port_num - 1], 421 enable); 422 } 423 424 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 425 struct snd_kcontrol *kcontrol, 426 int event) 427 { 428 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 429 430 switch (event) { 431 case SND_SOC_DAPM_PRE_PMU: 432 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 433 WCD938X_ANA_RX_CLK_EN_MASK, 1); 434 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 435 WCD938X_RX_BIAS_EN_MASK, 1); 436 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 437 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 438 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 439 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 440 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 441 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 442 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 443 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 444 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 445 WCD938X_AUXPA_CLK_EN_MASK, 1); 446 break; 447 case SND_SOC_DAPM_POST_PMD: 448 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 449 WCD938X_VNEG_EN_MASK, 0); 450 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 451 WCD938X_VPOS_EN_MASK, 0); 452 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 453 WCD938X_RX_BIAS_EN_MASK, 0); 454 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 455 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 456 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 457 WCD938X_ANA_RX_CLK_EN_MASK, 0); 458 break; 459 } 460 return 0; 461 } 462 463 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 464 struct snd_kcontrol *kcontrol, 465 int event) 466 { 467 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 468 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 469 470 switch (event) { 471 case SND_SOC_DAPM_PRE_PMU: 472 snd_soc_component_write_field(component, 473 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 474 WCD938X_RXD0_CLK_EN_MASK, 0x01); 475 snd_soc_component_write_field(component, 476 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 477 WCD938X_HPHL_RX_EN_MASK, 1); 478 snd_soc_component_write_field(component, 479 WCD938X_HPH_RDAC_CLK_CTL1, 480 WCD938X_CHOP_CLK_EN_MASK, 0); 481 break; 482 case SND_SOC_DAPM_POST_PMU: 483 snd_soc_component_write_field(component, 484 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 485 WCD938X_HPH_RES_DIV_MASK, 0x02); 486 if (wcd938x->comp1_enable) { 487 snd_soc_component_write_field(component, 488 WCD938X_DIGITAL_CDC_COMP_CTL_0, 489 WCD938X_HPHL_COMP_EN_MASK, 1); 490 /* 5msec compander delay as per HW requirement */ 491 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 492 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 493 usleep_range(5000, 5010); 494 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 495 WCD938X_AUTOCHOP_TIMER_EN, 0); 496 } else { 497 snd_soc_component_write_field(component, 498 WCD938X_DIGITAL_CDC_COMP_CTL_0, 499 WCD938X_HPHL_COMP_EN_MASK, 0); 500 snd_soc_component_write_field(component, 501 WCD938X_HPH_L_EN, 502 WCD938X_GAIN_SRC_SEL_MASK, 503 WCD938X_GAIN_SRC_SEL_REGISTER); 504 505 } 506 break; 507 case SND_SOC_DAPM_POST_PMD: 508 snd_soc_component_write_field(component, 509 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 510 WCD938X_HPH_RES_DIV_MASK, 0x1); 511 break; 512 } 513 514 return 0; 515 } 516 517 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 518 struct snd_kcontrol *kcontrol, 519 int event) 520 { 521 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 522 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 523 524 switch (event) { 525 case SND_SOC_DAPM_PRE_PMU: 526 snd_soc_component_write_field(component, 527 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 528 WCD938X_RXD1_CLK_EN_MASK, 1); 529 snd_soc_component_write_field(component, 530 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 531 WCD938X_HPHR_RX_EN_MASK, 1); 532 snd_soc_component_write_field(component, 533 WCD938X_HPH_RDAC_CLK_CTL1, 534 WCD938X_CHOP_CLK_EN_MASK, 0); 535 break; 536 case SND_SOC_DAPM_POST_PMU: 537 snd_soc_component_write_field(component, 538 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 539 WCD938X_HPH_RES_DIV_MASK, 0x02); 540 if (wcd938x->comp2_enable) { 541 snd_soc_component_write_field(component, 542 WCD938X_DIGITAL_CDC_COMP_CTL_0, 543 WCD938X_HPHR_COMP_EN_MASK, 1); 544 /* 5msec compander delay as per HW requirement */ 545 if (!wcd938x->comp1_enable || 546 (snd_soc_component_read(component, 547 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 548 usleep_range(5000, 5010); 549 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 550 WCD938X_AUTOCHOP_TIMER_EN, 0); 551 } else { 552 snd_soc_component_write_field(component, 553 WCD938X_DIGITAL_CDC_COMP_CTL_0, 554 WCD938X_HPHR_COMP_EN_MASK, 0); 555 snd_soc_component_write_field(component, 556 WCD938X_HPH_R_EN, 557 WCD938X_GAIN_SRC_SEL_MASK, 558 WCD938X_GAIN_SRC_SEL_REGISTER); 559 } 560 break; 561 case SND_SOC_DAPM_POST_PMD: 562 snd_soc_component_write_field(component, 563 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 564 WCD938X_HPH_RES_DIV_MASK, 0x01); 565 break; 566 } 567 568 return 0; 569 } 570 571 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 572 struct snd_kcontrol *kcontrol, 573 int event) 574 { 575 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 576 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 577 578 switch (event) { 579 case SND_SOC_DAPM_PRE_PMU: 580 wcd938x->ear_rx_path = 581 snd_soc_component_read( 582 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 583 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 584 snd_soc_component_write_field(component, 585 WCD938X_EAR_EAR_DAC_CON, 586 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 587 snd_soc_component_write_field(component, 588 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 589 WCD938X_AUX_EN_MASK, 1); 590 snd_soc_component_write_field(component, 591 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 592 WCD938X_RXD2_CLK_EN_MASK, 1); 593 snd_soc_component_write_field(component, 594 WCD938X_ANA_EAR_COMPANDER_CTL, 595 WCD938X_GAIN_OVRD_REG_MASK, 1); 596 } else { 597 snd_soc_component_write_field(component, 598 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 599 WCD938X_HPHL_RX_EN_MASK, 1); 600 snd_soc_component_write_field(component, 601 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 602 WCD938X_RXD0_CLK_EN_MASK, 1); 603 if (wcd938x->comp1_enable) 604 snd_soc_component_write_field(component, 605 WCD938X_DIGITAL_CDC_COMP_CTL_0, 606 WCD938X_HPHL_COMP_EN_MASK, 1); 607 } 608 /* 5 msec delay as per HW requirement */ 609 usleep_range(5000, 5010); 610 if (wcd938x->flyback_cur_det_disable == 0) 611 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 612 WCD938X_EN_CUR_DET_MASK, 0); 613 wcd938x->flyback_cur_det_disable++; 614 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 615 WCD_CLSH_EVENT_PRE_DAC, 616 WCD_CLSH_STATE_EAR, 617 wcd938x->hph_mode); 618 break; 619 case SND_SOC_DAPM_POST_PMD: 620 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 621 snd_soc_component_write_field(component, 622 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 623 WCD938X_AUX_EN_MASK, 0); 624 snd_soc_component_write_field(component, 625 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 626 WCD938X_RXD2_CLK_EN_MASK, 0); 627 } else { 628 snd_soc_component_write_field(component, 629 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 630 WCD938X_HPHL_RX_EN_MASK, 0); 631 snd_soc_component_write_field(component, 632 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 633 WCD938X_RXD0_CLK_EN_MASK, 0); 634 if (wcd938x->comp1_enable) 635 snd_soc_component_write_field(component, 636 WCD938X_DIGITAL_CDC_COMP_CTL_0, 637 WCD938X_HPHL_COMP_EN_MASK, 0); 638 } 639 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 640 WCD938X_GAIN_OVRD_REG_MASK, 0); 641 snd_soc_component_write_field(component, 642 WCD938X_EAR_EAR_DAC_CON, 643 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 644 break; 645 } 646 return 0; 647 648 } 649 650 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 651 struct snd_kcontrol *kcontrol, 652 int event) 653 { 654 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 655 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 656 657 switch (event) { 658 case SND_SOC_DAPM_PRE_PMU: 659 snd_soc_component_write_field(component, 660 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 661 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 662 snd_soc_component_write_field(component, 663 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 664 WCD938X_RXD2_CLK_EN_MASK, 1); 665 snd_soc_component_write_field(component, 666 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 667 WCD938X_AUX_EN_MASK, 1); 668 if (wcd938x->flyback_cur_det_disable == 0) 669 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 670 WCD938X_EN_CUR_DET_MASK, 0); 671 wcd938x->flyback_cur_det_disable++; 672 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 673 WCD_CLSH_EVENT_PRE_DAC, 674 WCD_CLSH_STATE_AUX, 675 wcd938x->hph_mode); 676 break; 677 case SND_SOC_DAPM_POST_PMD: 678 snd_soc_component_write_field(component, 679 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 680 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 681 break; 682 } 683 return 0; 684 685 } 686 687 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 688 struct snd_kcontrol *kcontrol, int event) 689 { 690 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 691 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 692 int hph_mode = wcd938x->hph_mode; 693 694 switch (event) { 695 case SND_SOC_DAPM_PRE_PMU: 696 if (wcd938x->ldoh) 697 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 698 WCD938X_LDOH_EN_MASK, 1); 699 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 700 WCD_CLSH_STATE_HPHR, hph_mode); 701 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 702 703 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 704 hph_mode == CLS_H_ULP) { 705 snd_soc_component_write_field(component, 706 WCD938X_HPH_REFBUFF_LP_CTL, 707 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 708 } 709 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 710 WCD938X_HPHR_REF_EN_MASK, 1); 711 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 712 /* 100 usec delay as per HW requirement */ 713 usleep_range(100, 110); 714 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 715 snd_soc_component_write_field(component, 716 WCD938X_DIGITAL_PDM_WD_CTL1, 717 WCD938X_PDM_WD_EN_MASK, 0x3); 718 break; 719 case SND_SOC_DAPM_POST_PMU: 720 /* 721 * 7ms sleep is required if compander is enabled as per 722 * HW requirement. If compander is disabled, then 723 * 20ms delay is required. 724 */ 725 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 726 if (!wcd938x->comp2_enable) 727 usleep_range(20000, 20100); 728 else 729 usleep_range(7000, 7100); 730 731 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 732 hph_mode == CLS_H_ULP) 733 snd_soc_component_write_field(component, 734 WCD938X_HPH_REFBUFF_LP_CTL, 735 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 736 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 737 } 738 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 739 WCD938X_AUTOCHOP_TIMER_EN, 1); 740 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 741 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 742 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 743 WCD938X_REGULATOR_MODE_MASK, 744 WCD938X_REGULATOR_MODE_CLASS_AB); 745 enable_irq(wcd938x->hphr_pdm_wd_int); 746 break; 747 case SND_SOC_DAPM_PRE_PMD: 748 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 749 /* 750 * 7ms sleep is required if compander is enabled as per 751 * HW requirement. If compander is disabled, then 752 * 20ms delay is required. 753 */ 754 if (!wcd938x->comp2_enable) 755 usleep_range(20000, 20100); 756 else 757 usleep_range(7000, 7100); 758 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 759 WCD938X_HPHR_EN_MASK, 0); 760 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 761 WCD_EVENT_PRE_HPHR_PA_OFF); 762 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 763 break; 764 case SND_SOC_DAPM_POST_PMD: 765 /* 766 * 7ms sleep is required if compander is enabled as per 767 * HW requirement. If compander is disabled, then 768 * 20ms delay is required. 769 */ 770 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 771 if (!wcd938x->comp2_enable) 772 usleep_range(20000, 20100); 773 else 774 usleep_range(7000, 7100); 775 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 776 } 777 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 778 WCD_EVENT_POST_HPHR_PA_OFF); 779 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 780 WCD938X_HPHR_REF_EN_MASK, 0); 781 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 782 WCD938X_PDM_WD_EN_MASK, 0); 783 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 784 WCD_CLSH_STATE_HPHR, hph_mode); 785 if (wcd938x->ldoh) 786 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 787 WCD938X_LDOH_EN_MASK, 0); 788 break; 789 } 790 791 return 0; 792 } 793 794 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 795 struct snd_kcontrol *kcontrol, int event) 796 { 797 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 798 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 799 int hph_mode = wcd938x->hph_mode; 800 801 switch (event) { 802 case SND_SOC_DAPM_PRE_PMU: 803 if (wcd938x->ldoh) 804 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 805 WCD938X_LDOH_EN_MASK, 1); 806 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 807 WCD_CLSH_STATE_HPHL, hph_mode); 808 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 809 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 810 hph_mode == CLS_H_ULP) { 811 snd_soc_component_write_field(component, 812 WCD938X_HPH_REFBUFF_LP_CTL, 813 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 814 } 815 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 816 WCD938X_HPHL_REF_EN_MASK, 1); 817 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 818 /* 100 usec delay as per HW requirement */ 819 usleep_range(100, 110); 820 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 821 snd_soc_component_write_field(component, 822 WCD938X_DIGITAL_PDM_WD_CTL0, 823 WCD938X_PDM_WD_EN_MASK, 0x3); 824 break; 825 case SND_SOC_DAPM_POST_PMU: 826 /* 827 * 7ms sleep is required if compander is enabled as per 828 * HW requirement. If compander is disabled, then 829 * 20ms delay is required. 830 */ 831 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 832 if (!wcd938x->comp1_enable) 833 usleep_range(20000, 20100); 834 else 835 usleep_range(7000, 7100); 836 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 837 hph_mode == CLS_H_ULP) 838 snd_soc_component_write_field(component, 839 WCD938X_HPH_REFBUFF_LP_CTL, 840 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 841 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 842 } 843 844 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 845 WCD938X_AUTOCHOP_TIMER_EN, 1); 846 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 847 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 848 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 849 WCD938X_REGULATOR_MODE_MASK, 850 WCD938X_REGULATOR_MODE_CLASS_AB); 851 enable_irq(wcd938x->hphl_pdm_wd_int); 852 break; 853 case SND_SOC_DAPM_PRE_PMD: 854 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 855 /* 856 * 7ms sleep is required if compander is enabled as per 857 * HW requirement. If compander is disabled, then 858 * 20ms delay is required. 859 */ 860 if (!wcd938x->comp1_enable) 861 usleep_range(20000, 20100); 862 else 863 usleep_range(7000, 7100); 864 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 865 WCD938X_HPHL_EN_MASK, 0); 866 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 867 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 868 break; 869 case SND_SOC_DAPM_POST_PMD: 870 /* 871 * 7ms sleep is required if compander is enabled as per 872 * HW requirement. If compander is disabled, then 873 * 20ms delay is required. 874 */ 875 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 876 if (!wcd938x->comp1_enable) 877 usleep_range(21000, 21100); 878 else 879 usleep_range(7000, 7100); 880 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 881 } 882 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 883 WCD_EVENT_POST_HPHL_PA_OFF); 884 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 885 WCD938X_HPHL_REF_EN_MASK, 0); 886 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 887 WCD938X_PDM_WD_EN_MASK, 0); 888 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 889 WCD_CLSH_STATE_HPHL, hph_mode); 890 if (wcd938x->ldoh) 891 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 892 WCD938X_LDOH_EN_MASK, 0); 893 break; 894 } 895 896 return 0; 897 } 898 899 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 900 struct snd_kcontrol *kcontrol, int event) 901 { 902 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 903 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 904 int hph_mode = wcd938x->hph_mode; 905 906 switch (event) { 907 case SND_SOC_DAPM_PRE_PMU: 908 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 909 WCD938X_AUX_PDM_WD_EN_MASK, 1); 910 break; 911 case SND_SOC_DAPM_POST_PMU: 912 /* 1 msec delay as per HW requirement */ 913 usleep_range(1000, 1010); 914 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 915 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 916 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 917 WCD938X_REGULATOR_MODE_MASK, 918 WCD938X_REGULATOR_MODE_CLASS_AB); 919 enable_irq(wcd938x->aux_pdm_wd_int); 920 break; 921 case SND_SOC_DAPM_PRE_PMD: 922 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 923 break; 924 case SND_SOC_DAPM_POST_PMD: 925 /* 1 msec delay as per HW requirement */ 926 usleep_range(1000, 1010); 927 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 928 WCD938X_AUX_PDM_WD_EN_MASK, 0); 929 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 930 WCD_CLSH_EVENT_POST_PA, 931 WCD_CLSH_STATE_AUX, 932 hph_mode); 933 934 wcd938x->flyback_cur_det_disable--; 935 if (wcd938x->flyback_cur_det_disable == 0) 936 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 937 WCD938X_EN_CUR_DET_MASK, 1); 938 break; 939 } 940 return 0; 941 } 942 943 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 944 struct snd_kcontrol *kcontrol, int event) 945 { 946 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 947 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 948 int hph_mode = wcd938x->hph_mode; 949 950 switch (event) { 951 case SND_SOC_DAPM_PRE_PMU: 952 /* 953 * Enable watchdog interrupt for HPHL or AUX 954 * depending on mux value 955 */ 956 wcd938x->ear_rx_path = snd_soc_component_read(component, 957 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 958 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 959 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 960 WCD938X_AUX_PDM_WD_EN_MASK, 1); 961 else 962 snd_soc_component_write_field(component, 963 WCD938X_DIGITAL_PDM_WD_CTL0, 964 WCD938X_PDM_WD_EN_MASK, 0x3); 965 if (!wcd938x->comp1_enable) 966 snd_soc_component_write_field(component, 967 WCD938X_ANA_EAR_COMPANDER_CTL, 968 WCD938X_GAIN_OVRD_REG_MASK, 1); 969 970 break; 971 case SND_SOC_DAPM_POST_PMU: 972 /* 6 msec delay as per HW requirement */ 973 usleep_range(6000, 6010); 974 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 975 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 976 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 977 WCD938X_REGULATOR_MODE_MASK, 978 WCD938X_REGULATOR_MODE_CLASS_AB); 979 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 980 enable_irq(wcd938x->aux_pdm_wd_int); 981 else 982 enable_irq(wcd938x->hphl_pdm_wd_int); 983 break; 984 case SND_SOC_DAPM_PRE_PMD: 985 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 986 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 987 else 988 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 989 break; 990 case SND_SOC_DAPM_POST_PMD: 991 if (!wcd938x->comp1_enable) 992 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 993 WCD938X_GAIN_OVRD_REG_MASK, 0); 994 /* 7 msec delay as per HW requirement */ 995 usleep_range(7000, 7010); 996 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 997 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 998 WCD938X_AUX_PDM_WD_EN_MASK, 0); 999 else 1000 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1001 WCD938X_PDM_WD_EN_MASK, 0); 1002 1003 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1004 WCD_CLSH_STATE_EAR, hph_mode); 1005 1006 wcd938x->flyback_cur_det_disable--; 1007 if (wcd938x->flyback_cur_det_disable == 0) 1008 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1009 WCD938X_EN_CUR_DET_MASK, 1); 1010 break; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 1017 struct snd_kcontrol *kcontrol, 1018 int event) 1019 { 1020 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1021 u16 dmic_clk_reg, dmic_clk_en_reg; 1022 u8 dmic_sel_mask, dmic_clk_mask; 1023 1024 switch (w->shift) { 1025 case 0: 1026 case 1: 1027 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1028 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 1029 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 1030 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 1031 break; 1032 case 2: 1033 case 3: 1034 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1035 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 1036 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 1037 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 1038 break; 1039 case 4: 1040 case 5: 1041 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1042 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 1043 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 1044 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 1045 break; 1046 case 6: 1047 case 7: 1048 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1049 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 1050 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 1051 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 1052 break; 1053 default: 1054 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 1055 __func__); 1056 return -EINVAL; 1057 } 1058 1059 switch (event) { 1060 case SND_SOC_DAPM_PRE_PMU: 1061 snd_soc_component_write_field(component, 1062 WCD938X_DIGITAL_CDC_AMIC_CTL, 1063 dmic_sel_mask, 1064 WCD938X_AMIC1_IN_SEL_DMIC); 1065 /* 250us sleep as per HW requirement */ 1066 usleep_range(250, 260); 1067 /* Setting DMIC clock rate to 2.4MHz */ 1068 snd_soc_component_write_field(component, dmic_clk_reg, 1069 dmic_clk_mask, 1070 WCD938X_DMIC4_RATE_2P4MHZ); 1071 snd_soc_component_write_field(component, dmic_clk_en_reg, 1072 WCD938X_DMIC_CLK_EN_MASK, 1); 1073 /* enable clock scaling */ 1074 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 1075 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 1076 break; 1077 case SND_SOC_DAPM_POST_PMD: 1078 snd_soc_component_write_field(component, 1079 WCD938X_DIGITAL_CDC_AMIC_CTL, 1080 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 1081 snd_soc_component_write_field(component, dmic_clk_en_reg, 1082 WCD938X_DMIC_CLK_EN_MASK, 0); 1083 break; 1084 } 1085 return 0; 1086 } 1087 1088 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 1089 struct snd_kcontrol *kcontrol, int event) 1090 { 1091 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1092 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1093 int bank; 1094 int rate; 1095 1096 bank = sdw_slave_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev); 1097 1098 switch (event) { 1099 case SND_SOC_DAPM_PRE_PMU: 1100 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1101 int i = 0, mode = 0; 1102 1103 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 1104 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 1105 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 1106 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 1107 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 1108 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 1109 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 1110 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 1111 1112 if (mode != 0) { 1113 for (i = 0; i < ADC_MODE_ULP2; i++) { 1114 if (mode & (1 << i)) { 1115 i++; 1116 break; 1117 } 1118 } 1119 } 1120 rate = wcd938x_get_clk_rate(i); 1121 wcd938x_set_swr_clk_rate(component, rate, bank); 1122 /* Copy clk settings to active bank */ 1123 wcd938x_set_swr_clk_rate(component, rate, !bank); 1124 } 1125 break; 1126 case SND_SOC_DAPM_POST_PMD: 1127 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1128 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 1129 wcd938x_set_swr_clk_rate(component, rate, !bank); 1130 wcd938x_set_swr_clk_rate(component, rate, bank); 1131 } 1132 break; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int wcd938x_get_adc_mode(int val) 1139 { 1140 int ret = 0; 1141 1142 switch (val) { 1143 case ADC_MODE_INVALID: 1144 ret = ADC_MODE_VAL_NORMAL; 1145 break; 1146 case ADC_MODE_HIFI: 1147 ret = ADC_MODE_VAL_HIFI; 1148 break; 1149 case ADC_MODE_LO_HIF: 1150 ret = ADC_MODE_VAL_LO_HIF; 1151 break; 1152 case ADC_MODE_NORMAL: 1153 ret = ADC_MODE_VAL_NORMAL; 1154 break; 1155 case ADC_MODE_LP: 1156 ret = ADC_MODE_VAL_LP; 1157 break; 1158 case ADC_MODE_ULP1: 1159 ret = ADC_MODE_VAL_ULP1; 1160 break; 1161 case ADC_MODE_ULP2: 1162 ret = ADC_MODE_VAL_ULP2; 1163 break; 1164 default: 1165 ret = -EINVAL; 1166 break; 1167 } 1168 return ret; 1169 } 1170 1171 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 1172 struct snd_kcontrol *kcontrol, int event) 1173 { 1174 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1175 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1176 1177 switch (event) { 1178 case SND_SOC_DAPM_PRE_PMU: 1179 snd_soc_component_write_field(component, 1180 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1181 WCD938X_ANA_TX_CLK_EN_MASK, 1); 1182 snd_soc_component_write_field(component, 1183 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1184 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1185 set_bit(w->shift, &wcd938x->status_mask); 1186 break; 1187 case SND_SOC_DAPM_POST_PMD: 1188 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1189 WCD938X_ANA_TX_CLK_EN_MASK, 0); 1190 clear_bit(w->shift, &wcd938x->status_mask); 1191 break; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static void wcd938x_tx_channel_config(struct snd_soc_component *component, 1198 int channel, int mode) 1199 { 1200 int reg, mask; 1201 1202 switch (channel) { 1203 case 0: 1204 reg = WCD938X_ANA_TX_CH2; 1205 mask = WCD938X_HPF1_INIT_MASK; 1206 break; 1207 case 1: 1208 reg = WCD938X_ANA_TX_CH2; 1209 mask = WCD938X_HPF2_INIT_MASK; 1210 break; 1211 case 2: 1212 reg = WCD938X_ANA_TX_CH4; 1213 mask = WCD938X_HPF3_INIT_MASK; 1214 break; 1215 case 3: 1216 reg = WCD938X_ANA_TX_CH4; 1217 mask = WCD938X_HPF4_INIT_MASK; 1218 break; 1219 default: 1220 return; 1221 } 1222 1223 snd_soc_component_write_field(component, reg, mask, mode); 1224 } 1225 1226 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 1227 struct snd_kcontrol *kcontrol, int event) 1228 { 1229 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1230 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1231 int mode; 1232 1233 switch (event) { 1234 case SND_SOC_DAPM_PRE_PMU: 1235 snd_soc_component_write_field(component, 1236 WCD938X_DIGITAL_CDC_REQ_CTL, 1237 WCD938X_FS_RATE_4P8_MASK, 1); 1238 snd_soc_component_write_field(component, 1239 WCD938X_DIGITAL_CDC_REQ_CTL, 1240 WCD938X_NO_NOTCH_MASK, 0); 1241 wcd938x_tx_channel_config(component, w->shift, 1); 1242 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 1243 if (mode < 0) { 1244 dev_info(component->dev, "Invalid ADC mode\n"); 1245 return -EINVAL; 1246 } 1247 switch (w->shift) { 1248 case 0: 1249 snd_soc_component_write_field(component, 1250 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1251 WCD938X_TXD0_MODE_MASK, mode); 1252 snd_soc_component_write_field(component, 1253 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1254 WCD938X_TXD0_CLK_EN_MASK, 1); 1255 break; 1256 case 1: 1257 snd_soc_component_write_field(component, 1258 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1259 WCD938X_TXD1_MODE_MASK, mode); 1260 snd_soc_component_write_field(component, 1261 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1262 WCD938X_TXD1_CLK_EN_MASK, 1); 1263 break; 1264 case 2: 1265 snd_soc_component_write_field(component, 1266 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1267 WCD938X_TXD2_MODE_MASK, mode); 1268 snd_soc_component_write_field(component, 1269 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1270 WCD938X_TXD2_CLK_EN_MASK, 1); 1271 break; 1272 case 3: 1273 snd_soc_component_write_field(component, 1274 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1275 WCD938X_TXD3_MODE_MASK, mode); 1276 snd_soc_component_write_field(component, 1277 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1278 WCD938X_TXD3_CLK_EN_MASK, 1); 1279 break; 1280 default: 1281 break; 1282 } 1283 1284 wcd938x_tx_channel_config(component, w->shift, 0); 1285 break; 1286 case SND_SOC_DAPM_POST_PMD: 1287 switch (w->shift) { 1288 case 0: 1289 snd_soc_component_write_field(component, 1290 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1291 WCD938X_TXD0_MODE_MASK, 0); 1292 snd_soc_component_write_field(component, 1293 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1294 WCD938X_TXD0_CLK_EN_MASK, 0); 1295 break; 1296 case 1: 1297 snd_soc_component_write_field(component, 1298 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1299 WCD938X_TXD1_MODE_MASK, 0); 1300 snd_soc_component_write_field(component, 1301 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1302 WCD938X_TXD1_CLK_EN_MASK, 0); 1303 break; 1304 case 2: 1305 snd_soc_component_write_field(component, 1306 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1307 WCD938X_TXD2_MODE_MASK, 0); 1308 snd_soc_component_write_field(component, 1309 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1310 WCD938X_TXD2_CLK_EN_MASK, 0); 1311 break; 1312 case 3: 1313 snd_soc_component_write_field(component, 1314 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1315 WCD938X_TXD3_MODE_MASK, 0); 1316 snd_soc_component_write_field(component, 1317 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1318 WCD938X_TXD3_CLK_EN_MASK, 0); 1319 break; 1320 default: 1321 break; 1322 } 1323 snd_soc_component_write_field(component, 1324 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1325 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 1326 break; 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int wcd938x_micbias_control(struct snd_soc_component *component, 1333 int micb_num, int req, bool is_dapm) 1334 { 1335 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1336 int micb_index = micb_num - 1; 1337 u16 micb_reg; 1338 1339 switch (micb_num) { 1340 case MIC_BIAS_1: 1341 micb_reg = WCD938X_ANA_MICB1; 1342 break; 1343 case MIC_BIAS_2: 1344 micb_reg = WCD938X_ANA_MICB2; 1345 break; 1346 case MIC_BIAS_3: 1347 micb_reg = WCD938X_ANA_MICB3; 1348 break; 1349 case MIC_BIAS_4: 1350 micb_reg = WCD938X_ANA_MICB4; 1351 break; 1352 default: 1353 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 1354 __func__, micb_num); 1355 return -EINVAL; 1356 } 1357 1358 switch (req) { 1359 case MICB_PULLUP_ENABLE: 1360 wcd938x->pullup_ref[micb_index]++; 1361 if ((wcd938x->pullup_ref[micb_index] == 1) && 1362 (wcd938x->micb_ref[micb_index] == 0)) 1363 snd_soc_component_write_field(component, micb_reg, 1364 WCD938X_MICB_EN_MASK, 1365 WCD938X_MICB_PULL_UP); 1366 break; 1367 case MICB_PULLUP_DISABLE: 1368 if (wcd938x->pullup_ref[micb_index] > 0) 1369 wcd938x->pullup_ref[micb_index]--; 1370 1371 if ((wcd938x->pullup_ref[micb_index] == 0) && 1372 (wcd938x->micb_ref[micb_index] == 0)) 1373 snd_soc_component_write_field(component, micb_reg, 1374 WCD938X_MICB_EN_MASK, 0); 1375 break; 1376 case MICB_ENABLE: 1377 wcd938x->micb_ref[micb_index]++; 1378 if (wcd938x->micb_ref[micb_index] == 1) { 1379 snd_soc_component_write_field(component, 1380 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1381 WCD938X_TX_CLK_EN_MASK, 0xF); 1382 snd_soc_component_write_field(component, 1383 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1384 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1385 snd_soc_component_write_field(component, 1386 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 1387 WCD938X_TX_SC_CLK_EN_MASK, 1); 1388 1389 snd_soc_component_write_field(component, micb_reg, 1390 WCD938X_MICB_EN_MASK, 1391 WCD938X_MICB_ENABLE); 1392 if (micb_num == MIC_BIAS_2) 1393 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1394 WCD_EVENT_POST_MICBIAS_2_ON); 1395 } 1396 if (micb_num == MIC_BIAS_2 && is_dapm) 1397 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1398 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1399 1400 1401 break; 1402 case MICB_DISABLE: 1403 if (wcd938x->micb_ref[micb_index] > 0) 1404 wcd938x->micb_ref[micb_index]--; 1405 1406 if ((wcd938x->micb_ref[micb_index] == 0) && 1407 (wcd938x->pullup_ref[micb_index] > 0)) 1408 snd_soc_component_write_field(component, micb_reg, 1409 WCD938X_MICB_EN_MASK, 1410 WCD938X_MICB_PULL_UP); 1411 else if ((wcd938x->micb_ref[micb_index] == 0) && 1412 (wcd938x->pullup_ref[micb_index] == 0)) { 1413 if (micb_num == MIC_BIAS_2) 1414 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1415 WCD_EVENT_PRE_MICBIAS_2_OFF); 1416 1417 snd_soc_component_write_field(component, micb_reg, 1418 WCD938X_MICB_EN_MASK, 0); 1419 if (micb_num == MIC_BIAS_2) 1420 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1421 WCD_EVENT_POST_MICBIAS_2_OFF); 1422 } 1423 if (is_dapm && micb_num == MIC_BIAS_2) 1424 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1425 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1426 break; 1427 } 1428 1429 return 0; 1430 } 1431 1432 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1433 struct snd_kcontrol *kcontrol, 1434 int event) 1435 { 1436 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1437 int micb_num = w->shift; 1438 1439 switch (event) { 1440 case SND_SOC_DAPM_PRE_PMU: 1441 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 1442 break; 1443 case SND_SOC_DAPM_POST_PMU: 1444 /* 1 msec delay as per HW requirement */ 1445 usleep_range(1000, 1100); 1446 break; 1447 case SND_SOC_DAPM_POST_PMD: 1448 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 1449 break; 1450 } 1451 1452 return 0; 1453 } 1454 1455 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1456 struct snd_kcontrol *kcontrol, 1457 int event) 1458 { 1459 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1460 int micb_num = w->shift; 1461 1462 switch (event) { 1463 case SND_SOC_DAPM_PRE_PMU: 1464 wcd938x_micbias_control(component, micb_num, 1465 MICB_PULLUP_ENABLE, true); 1466 break; 1467 case SND_SOC_DAPM_POST_PMU: 1468 /* 1 msec delay as per HW requirement */ 1469 usleep_range(1000, 1100); 1470 break; 1471 case SND_SOC_DAPM_POST_PMD: 1472 wcd938x_micbias_control(component, micb_num, 1473 MICB_PULLUP_DISABLE, true); 1474 break; 1475 } 1476 1477 return 0; 1478 } 1479 1480 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 1481 struct snd_ctl_elem_value *ucontrol) 1482 { 1483 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1484 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1485 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1486 int path = e->shift_l; 1487 1488 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path]; 1489 1490 return 0; 1491 } 1492 1493 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 1494 struct snd_ctl_elem_value *ucontrol) 1495 { 1496 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1497 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1498 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1499 int path = e->shift_l; 1500 1501 if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0]) 1502 return 0; 1503 1504 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 1505 1506 return 1; 1507 } 1508 1509 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1510 struct snd_ctl_elem_value *ucontrol) 1511 { 1512 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1513 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1514 1515 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode; 1516 1517 return 0; 1518 } 1519 1520 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1521 struct snd_ctl_elem_value *ucontrol) 1522 { 1523 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1524 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1525 1526 if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0]) 1527 return 0; 1528 1529 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 1530 1531 return 1; 1532 } 1533 1534 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 1535 struct snd_ctl_elem_value *ucontrol) 1536 { 1537 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1538 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1539 1540 if (wcd938x->comp1_enable) { 1541 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 1542 return -EINVAL; 1543 } 1544 1545 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1546 WCD938X_EAR_GAIN_MASK, 1547 ucontrol->value.integer.value[0]); 1548 1549 return 1; 1550 } 1551 1552 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 1553 struct snd_ctl_elem_value *ucontrol) 1554 { 1555 1556 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1557 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1558 struct soc_mixer_control *mc; 1559 bool hphr; 1560 1561 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1562 hphr = mc->shift; 1563 1564 if (hphr) 1565 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 1566 else 1567 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 1568 1569 return 0; 1570 } 1571 1572 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 1573 struct snd_ctl_elem_value *ucontrol) 1574 { 1575 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1576 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1577 struct wcd938x_sdw_priv *wcd; 1578 int value = ucontrol->value.integer.value[0]; 1579 int portidx; 1580 struct soc_mixer_control *mc; 1581 bool hphr; 1582 1583 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1584 hphr = mc->shift; 1585 1586 wcd = wcd938x->sdw_priv[AIF1_PB]; 1587 1588 if (hphr) 1589 wcd938x->comp2_enable = value; 1590 else 1591 wcd938x->comp1_enable = value; 1592 1593 portidx = wcd->ch_info[mc->reg].port_num; 1594 1595 if (value) 1596 wcd938x_connect_port(wcd, portidx, mc->reg, true); 1597 else 1598 wcd938x_connect_port(wcd, portidx, mc->reg, false); 1599 1600 return 1; 1601 } 1602 1603 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 1604 struct snd_ctl_elem_value *ucontrol) 1605 { 1606 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1607 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1608 1609 ucontrol->value.integer.value[0] = wcd938x->ldoh; 1610 1611 return 0; 1612 } 1613 1614 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 1615 struct snd_ctl_elem_value *ucontrol) 1616 { 1617 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1618 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1619 1620 if (wcd938x->ldoh == ucontrol->value.integer.value[0]) 1621 return 0; 1622 1623 wcd938x->ldoh = ucontrol->value.integer.value[0]; 1624 1625 return 1; 1626 } 1627 1628 static const char * const tx_mode_mux_text_wcd9380[] = { 1629 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1630 }; 1631 1632 static const char * const tx_mode_mux_text[] = { 1633 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1634 "ADC_ULP1", "ADC_ULP2", 1635 }; 1636 1637 static const char * const rx_hph_mode_mux_text_wcd9380[] = { 1638 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 1639 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 1640 "CLS_AB_LOHIFI", 1641 }; 1642 1643 static const char * const rx_hph_mode_mux_text[] = { 1644 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 1645 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 1646 }; 1647 1648 static const char * const adc2_mux_text[] = { 1649 "INP2", "INP3" 1650 }; 1651 1652 static const char * const adc3_mux_text[] = { 1653 "INP4", "INP6" 1654 }; 1655 1656 static const char * const adc4_mux_text[] = { 1657 "INP5", "INP7" 1658 }; 1659 1660 static const char * const rdac3_mux_text[] = { 1661 "RX1", "RX3" 1662 }; 1663 1664 static const char * const hdr12_mux_text[] = { 1665 "NO_HDR12", "HDR12" 1666 }; 1667 1668 static const char * const hdr34_mux_text[] = { 1669 "NO_HDR34", "HDR34" 1670 }; 1671 1672 static const struct soc_enum tx0_mode_enum_wcd9380 = 1673 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1674 tx_mode_mux_text_wcd9380); 1675 1676 static const struct soc_enum tx1_mode_enum_wcd9380 = 1677 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1678 tx_mode_mux_text_wcd9380); 1679 1680 static const struct soc_enum tx2_mode_enum_wcd9380 = 1681 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1682 tx_mode_mux_text_wcd9380); 1683 1684 static const struct soc_enum tx3_mode_enum_wcd9380 = 1685 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1686 tx_mode_mux_text_wcd9380); 1687 1688 static const struct soc_enum tx0_mode_enum_wcd9385 = 1689 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 1690 tx_mode_mux_text); 1691 1692 static const struct soc_enum tx1_mode_enum_wcd9385 = 1693 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 1694 tx_mode_mux_text); 1695 1696 static const struct soc_enum tx2_mode_enum_wcd9385 = 1697 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 1698 tx_mode_mux_text); 1699 1700 static const struct soc_enum tx3_mode_enum_wcd9385 = 1701 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 1702 tx_mode_mux_text); 1703 1704 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 1705 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 1706 rx_hph_mode_mux_text_wcd9380); 1707 1708 static const struct soc_enum rx_hph_mode_mux_enum = 1709 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 1710 rx_hph_mode_mux_text); 1711 1712 static const struct soc_enum adc2_enum = 1713 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 1714 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 1715 1716 static const struct soc_enum adc3_enum = 1717 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 1718 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 1719 1720 static const struct soc_enum adc4_enum = 1721 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 1722 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 1723 1724 static const struct soc_enum hdr12_enum = 1725 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 1726 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 1727 1728 static const struct soc_enum hdr34_enum = 1729 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 1730 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 1731 1732 static const struct soc_enum rdac3_enum = 1733 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 1734 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 1735 1736 static const struct snd_kcontrol_new adc1_switch[] = { 1737 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1738 }; 1739 1740 static const struct snd_kcontrol_new adc2_switch[] = { 1741 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1742 }; 1743 1744 static const struct snd_kcontrol_new adc3_switch[] = { 1745 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1746 }; 1747 1748 static const struct snd_kcontrol_new adc4_switch[] = { 1749 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1750 }; 1751 1752 static const struct snd_kcontrol_new dmic1_switch[] = { 1753 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1754 }; 1755 1756 static const struct snd_kcontrol_new dmic2_switch[] = { 1757 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1758 }; 1759 1760 static const struct snd_kcontrol_new dmic3_switch[] = { 1761 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1762 }; 1763 1764 static const struct snd_kcontrol_new dmic4_switch[] = { 1765 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1766 }; 1767 1768 static const struct snd_kcontrol_new dmic5_switch[] = { 1769 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1770 }; 1771 1772 static const struct snd_kcontrol_new dmic6_switch[] = { 1773 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1774 }; 1775 1776 static const struct snd_kcontrol_new dmic7_switch[] = { 1777 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1778 }; 1779 1780 static const struct snd_kcontrol_new dmic8_switch[] = { 1781 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1782 }; 1783 1784 static const struct snd_kcontrol_new ear_rdac_switch[] = { 1785 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1786 }; 1787 1788 static const struct snd_kcontrol_new aux_rdac_switch[] = { 1789 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1790 }; 1791 1792 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 1793 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1794 }; 1795 1796 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 1797 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1798 }; 1799 1800 static const struct snd_kcontrol_new tx_adc2_mux = 1801 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 1802 1803 static const struct snd_kcontrol_new tx_adc3_mux = 1804 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 1805 1806 static const struct snd_kcontrol_new tx_adc4_mux = 1807 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 1808 1809 static const struct snd_kcontrol_new tx_hdr12_mux = 1810 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 1811 1812 static const struct snd_kcontrol_new tx_hdr34_mux = 1813 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 1814 1815 static const struct snd_kcontrol_new rx_rdac3_mux = 1816 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 1817 1818 static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 1819 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 1820 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1821 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 1822 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1823 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 1824 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1825 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 1826 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1827 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 1828 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1829 }; 1830 1831 static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 1832 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 1833 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1834 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 1835 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1836 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 1837 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1838 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 1839 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1840 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 1841 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1842 }; 1843 1844 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 1845 struct snd_ctl_elem_value *ucontrol) 1846 { 1847 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1848 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1849 struct wcd938x_sdw_priv *wcd; 1850 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1851 int dai_id = mixer->shift; 1852 int portidx, ch_idx = mixer->reg; 1853 1854 1855 wcd = wcd938x->sdw_priv[dai_id]; 1856 portidx = wcd->ch_info[ch_idx].port_num; 1857 1858 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1859 1860 return 0; 1861 } 1862 1863 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 1864 struct snd_ctl_elem_value *ucontrol) 1865 { 1866 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 1867 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1868 struct wcd938x_sdw_priv *wcd; 1869 struct soc_mixer_control *mixer = 1870 (struct soc_mixer_control *)kcontrol->private_value; 1871 int ch_idx = mixer->reg; 1872 int portidx; 1873 int dai_id = mixer->shift; 1874 bool enable; 1875 1876 wcd = wcd938x->sdw_priv[dai_id]; 1877 1878 portidx = wcd->ch_info[ch_idx].port_num; 1879 if (ucontrol->value.integer.value[0]) 1880 enable = true; 1881 else 1882 enable = false; 1883 1884 wcd->port_enable[portidx] = enable; 1885 1886 wcd938x_connect_port(wcd, portidx, ch_idx, enable); 1887 1888 return 1; 1889 1890 } 1891 1892 /* MBHC related */ 1893 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 1894 bool enable) 1895 { 1896 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 1897 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 1898 } 1899 1900 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1901 bool enable) 1902 { 1903 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 1904 WCD938X_ANA_MBHC_BIAS_EN, enable); 1905 } 1906 1907 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 1908 int *btn_low, int *btn_high, 1909 int num_btn, bool is_micbias) 1910 { 1911 int i, vth; 1912 1913 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1914 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1915 __func__, num_btn); 1916 return; 1917 } 1918 1919 for (i = 0; i < num_btn; i++) { 1920 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1921 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 1922 WCD938X_MBHC_BTN_VTH_MASK, vth); 1923 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 1924 __func__, i, btn_high[i], vth); 1925 } 1926 } 1927 1928 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1929 { 1930 u8 val; 1931 1932 if (micb_num == MIC_BIAS_2) { 1933 val = snd_soc_component_read_field(component, 1934 WCD938X_ANA_MICB2, 1935 WCD938X_MICB_EN_MASK); 1936 if (val == WCD938X_MICB_ENABLE) 1937 return true; 1938 } 1939 return false; 1940 } 1941 1942 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1943 int pull_up_cur) 1944 { 1945 /* Default pull up current to 2uA */ 1946 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1947 pull_up_cur = HS_PULLUP_I_2P0_UA; 1948 1949 snd_soc_component_write_field(component, 1950 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 1951 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 1952 } 1953 1954 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 1955 int micb_num, int req) 1956 { 1957 return wcd938x_micbias_control(component, micb_num, req, false); 1958 } 1959 1960 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1961 bool enable) 1962 { 1963 if (enable) { 1964 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1965 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1966 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1967 WCD938X_RAMP_EN_MASK, 1); 1968 } else { 1969 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1970 WCD938X_RAMP_EN_MASK, 0); 1971 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1972 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 1973 } 1974 } 1975 1976 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1977 int req_volt, int micb_num) 1978 { 1979 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1980 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en; 1981 1982 switch (micb_num) { 1983 case MIC_BIAS_1: 1984 micb_reg = WCD938X_ANA_MICB1; 1985 break; 1986 case MIC_BIAS_2: 1987 micb_reg = WCD938X_ANA_MICB2; 1988 break; 1989 case MIC_BIAS_3: 1990 micb_reg = WCD938X_ANA_MICB3; 1991 break; 1992 case MIC_BIAS_4: 1993 micb_reg = WCD938X_ANA_MICB4; 1994 break; 1995 default: 1996 return -EINVAL; 1997 } 1998 guard(mutex)(&wcd938x->micb_lock); 1999 /* 2000 * If requested micbias voltage is same as current micbias 2001 * voltage, then just return. Otherwise, adjust voltage as 2002 * per requested value. If micbias is already enabled, then 2003 * to avoid slow micbias ramp-up or down enable pull-up 2004 * momentarily, change the micbias value and then re-enable 2005 * micbias. 2006 */ 2007 micb_en = snd_soc_component_read_field(component, micb_reg, 2008 WCD938X_MICB_EN_MASK); 2009 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2010 WCD938X_MICB_VOUT_MASK); 2011 2012 req_vout_ctl = wcd_get_micb_vout_ctl_val(component->dev, req_volt); 2013 if (req_vout_ctl < 0) 2014 return -EINVAL; 2015 2016 if (cur_vout_ctl == req_vout_ctl) 2017 return 0; 2018 2019 if (micb_en == WCD938X_MICB_ENABLE) 2020 snd_soc_component_write_field(component, micb_reg, 2021 WCD938X_MICB_EN_MASK, 2022 WCD938X_MICB_PULL_UP); 2023 2024 snd_soc_component_write_field(component, micb_reg, 2025 WCD938X_MICB_VOUT_MASK, 2026 req_vout_ctl); 2027 2028 if (micb_en == WCD938X_MICB_ENABLE) { 2029 snd_soc_component_write_field(component, micb_reg, 2030 WCD938X_MICB_EN_MASK, 2031 WCD938X_MICB_ENABLE); 2032 /* 2033 * Add 2ms delay as per HW requirement after enabling 2034 * micbias 2035 */ 2036 usleep_range(2000, 2100); 2037 } 2038 2039 return 0; 2040 } 2041 2042 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2043 int micb_num, bool req_en) 2044 { 2045 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2046 int micb_mv; 2047 2048 if (micb_num != MIC_BIAS_2) 2049 return -EINVAL; 2050 /* 2051 * If device tree micbias level is already above the minimum 2052 * voltage needed to detect threshold microphone, then do 2053 * not change the micbias, just return. 2054 */ 2055 if (wcd938x->common.micb_mv[2] >= WCD_MBHC_THR_HS_MICB_MV) 2056 return 0; 2057 2058 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->common.micb_mv[2]; 2059 2060 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2061 } 2062 2063 static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component, 2064 s16 *d1_a, u16 noff, 2065 int32_t *zdet) 2066 { 2067 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2068 int i; 2069 int val, val1; 2070 s16 c1; 2071 s32 x1, d1; 2072 int32_t denom; 2073 static const int minCode_param[] = { 2074 3277, 1639, 820, 410, 205, 103, 52, 26 2075 }; 2076 2077 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 2078 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 2079 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 2080 if (val & 0x80) 2081 break; 2082 } 2083 val = val << 0x8; 2084 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 2085 val |= val1; 2086 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 2087 x1 = WCD938X_MBHC_GET_X1(val); 2088 c1 = WCD938X_MBHC_GET_C1(val); 2089 /* If ramp is not complete, give additional 5ms */ 2090 if ((c1 < 2) && x1) 2091 usleep_range(5000, 5050); 2092 2093 if (!c1 || !x1) { 2094 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 2095 c1, x1); 2096 goto ramp_down; 2097 } 2098 d1 = d1_a[c1]; 2099 denom = (x1 * d1) - (1 << (14 - noff)); 2100 if (denom > 0) 2101 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 2102 else if (x1 < minCode_param[noff]) 2103 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 2104 2105 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 2106 __func__, d1, c1, x1, *zdet); 2107 ramp_down: 2108 i = 0; 2109 while (x1) { 2110 regmap_read(wcd938x->regmap, 2111 WCD938X_ANA_MBHC_RESULT_1, &val); 2112 regmap_read(wcd938x->regmap, 2113 WCD938X_ANA_MBHC_RESULT_2, &val1); 2114 val = val << 0x08; 2115 val |= val1; 2116 x1 = WCD938X_MBHC_GET_X1(val); 2117 i++; 2118 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 2119 break; 2120 } 2121 } 2122 2123 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 2124 struct wcd938x_mbhc_zdet_param *zdet_param, 2125 int32_t *zl, int32_t *zr, s16 *d1_a) 2126 { 2127 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2128 int32_t zdet = 0; 2129 2130 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2131 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2132 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 2133 WCD938X_VTH_MASK, zdet_param->btn5); 2134 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 2135 WCD938X_VTH_MASK, zdet_param->btn6); 2136 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 2137 WCD938X_VTH_MASK, zdet_param->btn7); 2138 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2139 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2140 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 2141 0x0F, zdet_param->nshift); 2142 2143 if (!zl) 2144 goto z_right; 2145 /* Start impedance measurement for HPH_L */ 2146 regmap_update_bits(wcd938x->regmap, 2147 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 2148 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2149 __func__, zdet_param->noff); 2150 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2151 regmap_update_bits(wcd938x->regmap, 2152 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 2153 2154 *zl = zdet; 2155 2156 z_right: 2157 if (!zr) 2158 return; 2159 /* Start impedance measurement for HPH_R */ 2160 regmap_update_bits(wcd938x->regmap, 2161 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 2162 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2163 __func__, zdet_param->noff); 2164 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2165 regmap_update_bits(wcd938x->regmap, 2166 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 2167 2168 *zr = zdet; 2169 } 2170 2171 static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2172 int32_t *z_val, int flag_l_r) 2173 { 2174 s16 q1; 2175 int q1_cal; 2176 2177 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 2178 q1 = snd_soc_component_read(component, 2179 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 2180 else 2181 q1 = snd_soc_component_read(component, 2182 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 2183 if (q1 & 0x80) 2184 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2185 else 2186 q1_cal = (10000 + (q1 * 25)); 2187 if (q1_cal > 0) 2188 *z_val = ((*z_val) * 10000) / q1_cal; 2189 } 2190 2191 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2192 uint32_t *zl, uint32_t *zr) 2193 { 2194 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2195 s16 reg0, reg1, reg2, reg3, reg4; 2196 int32_t z1L, z1R, z1Ls; 2197 int zMono, z_diff1, z_diff2; 2198 bool is_fsm_disable = false; 2199 struct wcd938x_mbhc_zdet_param zdet_param[] = { 2200 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2201 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2202 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2203 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2204 }; 2205 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 2206 s16 d1_a[][4] = { 2207 {0, 30, 90, 30}, 2208 {0, 30, 30, 5}, 2209 {0, 30, 30, 5}, 2210 {0, 30, 30, 5}, 2211 }; 2212 s16 *d1 = NULL; 2213 2214 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 2215 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 2216 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 2217 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 2218 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 2219 2220 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 2221 is_fsm_disable = true; 2222 regmap_update_bits(wcd938x->regmap, 2223 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 2224 } 2225 2226 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2227 if (wcd938x->mbhc_cfg.hphl_swh) 2228 regmap_update_bits(wcd938x->regmap, 2229 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 2230 2231 /* Turn off 100k pull down on HPHL */ 2232 regmap_update_bits(wcd938x->regmap, 2233 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 2234 2235 /* Disable surge protection before impedance detection. 2236 * This is done to give correct value for high impedance. 2237 */ 2238 regmap_update_bits(wcd938x->regmap, 2239 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 2240 /* 1ms delay needed after disable surge protection */ 2241 usleep_range(1000, 1010); 2242 2243 /* First get impedance on Left */ 2244 d1 = d1_a[1]; 2245 zdet_param_ptr = &zdet_param[1]; 2246 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2247 2248 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2249 goto left_ch_impedance; 2250 2251 /* Second ramp for left ch */ 2252 if (z1L < WCD938X_ZDET_VAL_32) { 2253 zdet_param_ptr = &zdet_param[0]; 2254 d1 = d1_a[0]; 2255 } else if ((z1L > WCD938X_ZDET_VAL_400) && 2256 (z1L <= WCD938X_ZDET_VAL_1200)) { 2257 zdet_param_ptr = &zdet_param[2]; 2258 d1 = d1_a[2]; 2259 } else if (z1L > WCD938X_ZDET_VAL_1200) { 2260 zdet_param_ptr = &zdet_param[3]; 2261 d1 = d1_a[3]; 2262 } 2263 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2264 2265 left_ch_impedance: 2266 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2267 (z1L > WCD938X_ZDET_VAL_100K)) { 2268 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 2269 zdet_param_ptr = &zdet_param[1]; 2270 d1 = d1_a[1]; 2271 } else { 2272 *zl = z1L/1000; 2273 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 2274 } 2275 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2276 __func__, *zl); 2277 2278 /* Start of right impedance ramp and calculation */ 2279 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2280 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2281 if (((z1R > WCD938X_ZDET_VAL_1200) && 2282 (zdet_param_ptr->noff == 0x6)) || 2283 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 2284 goto right_ch_impedance; 2285 /* Second ramp for right ch */ 2286 if (z1R < WCD938X_ZDET_VAL_32) { 2287 zdet_param_ptr = &zdet_param[0]; 2288 d1 = d1_a[0]; 2289 } else if ((z1R > WCD938X_ZDET_VAL_400) && 2290 (z1R <= WCD938X_ZDET_VAL_1200)) { 2291 zdet_param_ptr = &zdet_param[2]; 2292 d1 = d1_a[2]; 2293 } else if (z1R > WCD938X_ZDET_VAL_1200) { 2294 zdet_param_ptr = &zdet_param[3]; 2295 d1 = d1_a[3]; 2296 } 2297 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2298 } 2299 right_ch_impedance: 2300 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2301 (z1R > WCD938X_ZDET_VAL_100K)) { 2302 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 2303 } else { 2304 *zr = z1R/1000; 2305 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 2306 } 2307 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2308 __func__, *zr); 2309 2310 /* Mono/stereo detection */ 2311 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 2312 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 2313 dev_dbg(component->dev, 2314 "%s: plug type is invalid or extension cable\n", 2315 __func__); 2316 goto zdet_complete; 2317 } 2318 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2319 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2320 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2321 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2322 dev_dbg(component->dev, 2323 "%s: Mono plug type with one ch floating or shorted to GND\n", 2324 __func__); 2325 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2326 goto zdet_complete; 2327 } 2328 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2329 WCD938X_HPHPA_GND_OVR_MASK, 1); 2330 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2331 WCD938X_HPHPA_GND_R_MASK, 1); 2332 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 2333 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2334 else 2335 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2336 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2337 WCD938X_HPHPA_GND_R_MASK, 0); 2338 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2339 WCD938X_HPHPA_GND_OVR_MASK, 0); 2340 z1Ls /= 1000; 2341 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2342 /* Parallel of left Z and 9 ohm pull down resistor */ 2343 zMono = ((*zl) * 9) / ((*zl) + 9); 2344 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2345 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2346 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2347 dev_dbg(component->dev, "%s: stereo plug type detected\n", 2348 __func__); 2349 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 2350 } else { 2351 dev_dbg(component->dev, "%s: MONO plug type detected\n", 2352 __func__); 2353 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2354 } 2355 2356 /* Enable surge protection again after impedance detection */ 2357 regmap_update_bits(wcd938x->regmap, 2358 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 2359 zdet_complete: 2360 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 2361 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 2362 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 2363 /* Turn on 100k pull down on HPHL */ 2364 regmap_update_bits(wcd938x->regmap, 2365 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 2366 2367 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2368 if (wcd938x->mbhc_cfg.hphl_swh) 2369 regmap_update_bits(wcd938x->regmap, 2370 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 2371 2372 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2373 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 2374 if (is_fsm_disable) 2375 regmap_update_bits(wcd938x->regmap, 2376 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 2377 } 2378 2379 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2380 bool enable) 2381 { 2382 if (enable) { 2383 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2384 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 2385 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2386 WCD938X_MBHC_GND_DET_EN_MASK, 1); 2387 } else { 2388 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2389 WCD938X_MBHC_GND_DET_EN_MASK, 0); 2390 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2391 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 2392 } 2393 } 2394 2395 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2396 bool enable) 2397 { 2398 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2399 WCD938X_HPHPA_GND_R_MASK, enable); 2400 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2401 WCD938X_HPHPA_GND_L_MASK, enable); 2402 } 2403 2404 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 2405 { 2406 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2407 2408 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2409 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2410 WCD938X_M_RTH_CTL_MASK, R_OFF); 2411 return; 2412 } 2413 2414 /* Do not enable moisture detection if jack type is NC */ 2415 if (!wcd938x->mbhc_cfg.hphl_swh) { 2416 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2417 __func__); 2418 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2419 WCD938X_M_RTH_CTL_MASK, R_OFF); 2420 return; 2421 } 2422 2423 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2424 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2425 } 2426 2427 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 2428 { 2429 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2430 2431 if (enable) 2432 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2433 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2434 else 2435 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2436 WCD938X_M_RTH_CTL_MASK, R_OFF); 2437 } 2438 2439 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 2440 { 2441 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2442 bool ret = false; 2443 2444 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2445 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2446 WCD938X_M_RTH_CTL_MASK, R_OFF); 2447 goto done; 2448 } 2449 2450 /* Do not enable moisture detection if jack type is NC */ 2451 if (!wcd938x->mbhc_cfg.hphl_swh) { 2452 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2453 __func__); 2454 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2455 WCD938X_M_RTH_CTL_MASK, R_OFF); 2456 goto done; 2457 } 2458 2459 /* 2460 * If moisture_en is already enabled, then skip to plug type 2461 * detection. 2462 */ 2463 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 2464 goto done; 2465 2466 wcd938x_mbhc_moisture_detect_en(component, true); 2467 /* Read moisture comparator status */ 2468 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 2469 & 0x20) ? 0 : 1); 2470 2471 done: 2472 return ret; 2473 2474 } 2475 2476 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 2477 bool enable) 2478 { 2479 snd_soc_component_write_field(component, 2480 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 2481 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 2482 } 2483 2484 static const struct wcd_mbhc_cb mbhc_cb = { 2485 .clk_setup = wcd938x_mbhc_clk_setup, 2486 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 2487 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 2488 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 2489 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 2490 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 2491 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 2492 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 2493 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 2494 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 2495 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 2496 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 2497 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 2498 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 2499 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 2500 }; 2501 2502 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 2503 struct snd_ctl_elem_value *ucontrol) 2504 { 2505 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2506 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2507 2508 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 2509 2510 return 0; 2511 } 2512 2513 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2514 struct snd_ctl_elem_value *ucontrol) 2515 { 2516 uint32_t zl, zr; 2517 bool hphr; 2518 struct soc_mixer_control *mc; 2519 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 2520 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2521 2522 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2523 hphr = mc->shift; 2524 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 2525 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2526 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2527 2528 return 0; 2529 } 2530 2531 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2532 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2533 wcd938x_get_hph_type, NULL), 2534 }; 2535 2536 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2537 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2538 wcd938x_hph_impedance_get, NULL), 2539 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2540 wcd938x_hph_impedance_get, NULL), 2541 }; 2542 2543 static int wcd938x_mbhc_init(struct snd_soc_component *component) 2544 { 2545 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2546 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 2547 2548 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2549 WCD938X_IRQ_MBHC_SW_DET); 2550 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2551 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 2552 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2553 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 2554 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2555 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2556 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2557 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 2558 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2559 WCD938X_IRQ_HPHL_OCP_INT); 2560 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2561 WCD938X_IRQ_HPHR_OCP_INT); 2562 2563 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2564 if (IS_ERR(wcd938x->wcd_mbhc)) 2565 return PTR_ERR(wcd938x->wcd_mbhc); 2566 2567 snd_soc_add_component_controls(component, impedance_detect_controls, 2568 ARRAY_SIZE(impedance_detect_controls)); 2569 snd_soc_add_component_controls(component, hph_type_detect_controls, 2570 ARRAY_SIZE(hph_type_detect_controls)); 2571 2572 return 0; 2573 } 2574 2575 static void wcd938x_mbhc_deinit(struct snd_soc_component *component) 2576 { 2577 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2578 2579 wcd_mbhc_deinit(wcd938x->wcd_mbhc); 2580 } 2581 2582 /* END MBHC */ 2583 2584 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 2585 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 2586 wcd938x_get_compander, wcd938x_set_compander), 2587 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 2588 wcd938x_get_compander, wcd938x_set_compander), 2589 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 2590 wcd938x_get_swr_port, wcd938x_set_swr_port), 2591 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 2592 wcd938x_get_swr_port, wcd938x_set_swr_port), 2593 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 2594 wcd938x_get_swr_port, wcd938x_set_swr_port), 2595 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 2596 wcd938x_get_swr_port, wcd938x_set_swr_port), 2597 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 2598 wcd938x_get_swr_port, wcd938x_set_swr_port), 2599 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 2600 wcd938x_get_swr_port, wcd938x_set_swr_port), 2601 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain), 2602 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain), 2603 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 2604 2, 0x10, 0, ear_pa_gain), 2605 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 2606 wcd938x_get_swr_port, wcd938x_set_swr_port), 2607 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 2608 wcd938x_get_swr_port, wcd938x_set_swr_port), 2609 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 2610 wcd938x_get_swr_port, wcd938x_set_swr_port), 2611 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 2612 wcd938x_get_swr_port, wcd938x_set_swr_port), 2613 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 2614 wcd938x_get_swr_port, wcd938x_set_swr_port), 2615 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 2616 wcd938x_get_swr_port, wcd938x_set_swr_port), 2617 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 2618 wcd938x_get_swr_port, wcd938x_set_swr_port), 2619 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 2620 wcd938x_get_swr_port, wcd938x_set_swr_port), 2621 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 2622 wcd938x_get_swr_port, wcd938x_set_swr_port), 2623 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 2624 wcd938x_get_swr_port, wcd938x_set_swr_port), 2625 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 2626 wcd938x_get_swr_port, wcd938x_set_swr_port), 2627 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 2628 wcd938x_get_swr_port, wcd938x_set_swr_port), 2629 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 2630 wcd938x_get_swr_port, wcd938x_set_swr_port), 2631 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 2632 wcd938x_ldoh_get, wcd938x_ldoh_put), 2633 2634 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2635 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2636 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2637 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 2638 }; 2639 2640 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 2641 2642 /*input widgets*/ 2643 SND_SOC_DAPM_INPUT("AMIC1"), 2644 SND_SOC_DAPM_INPUT("AMIC2"), 2645 SND_SOC_DAPM_INPUT("AMIC3"), 2646 SND_SOC_DAPM_INPUT("AMIC4"), 2647 SND_SOC_DAPM_INPUT("AMIC5"), 2648 SND_SOC_DAPM_INPUT("AMIC6"), 2649 SND_SOC_DAPM_INPUT("AMIC7"), 2650 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 2651 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 2652 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 2653 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 2654 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 2655 2656 /*tx widgets*/ 2657 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2658 wcd938x_codec_enable_adc, 2659 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2660 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2661 wcd938x_codec_enable_adc, 2662 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2663 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2664 wcd938x_codec_enable_adc, 2665 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2666 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 2667 wcd938x_codec_enable_adc, 2668 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2669 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2670 wcd938x_codec_enable_dmic, 2671 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2672 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2673 wcd938x_codec_enable_dmic, 2674 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2675 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2676 wcd938x_codec_enable_dmic, 2677 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2678 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2679 wcd938x_codec_enable_dmic, 2680 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2681 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2682 wcd938x_codec_enable_dmic, 2683 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2684 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2685 wcd938x_codec_enable_dmic, 2686 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2687 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 2688 wcd938x_codec_enable_dmic, 2689 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2690 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 2691 wcd938x_codec_enable_dmic, 2692 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2693 2694 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2695 NULL, 0, wcd938x_adc_enable_req, 2696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2697 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 2698 NULL, 0, wcd938x_adc_enable_req, 2699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2700 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 2701 NULL, 0, wcd938x_adc_enable_req, 2702 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2703 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 2704 wcd938x_adc_enable_req, 2705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2706 2707 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2708 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 2709 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 2710 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 2711 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 2712 2713 /*tx mixers*/ 2714 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 2715 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 2716 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2717 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 2718 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 2719 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2720 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 2721 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 2722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2723 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 2724 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 2725 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2726 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 2727 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 2728 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2729 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 2730 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 2731 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2732 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 2733 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 2734 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2735 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 2736 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 2737 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2738 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 2739 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 2740 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2741 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 2742 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 2743 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2744 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 2745 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 2746 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2747 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 2748 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 2749 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2750 /* micbias widgets*/ 2751 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2752 wcd938x_codec_enable_micbias, 2753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2754 SND_SOC_DAPM_POST_PMD), 2755 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2756 wcd938x_codec_enable_micbias, 2757 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2758 SND_SOC_DAPM_POST_PMD), 2759 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2760 wcd938x_codec_enable_micbias, 2761 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2762 SND_SOC_DAPM_POST_PMD), 2763 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2764 wcd938x_codec_enable_micbias, 2765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2766 SND_SOC_DAPM_POST_PMD), 2767 2768 /* micbias pull up widgets*/ 2769 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2770 wcd938x_codec_enable_micbias_pullup, 2771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2772 SND_SOC_DAPM_POST_PMD), 2773 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2774 wcd938x_codec_enable_micbias_pullup, 2775 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2776 SND_SOC_DAPM_POST_PMD), 2777 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2778 wcd938x_codec_enable_micbias_pullup, 2779 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2780 SND_SOC_DAPM_POST_PMD), 2781 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2782 wcd938x_codec_enable_micbias_pullup, 2783 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2784 SND_SOC_DAPM_POST_PMD), 2785 2786 /*output widgets tx*/ 2787 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2788 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2789 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2790 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 2791 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2792 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2793 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2794 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2795 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2796 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2797 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 2798 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 2799 2800 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2801 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2802 SND_SOC_DAPM_INPUT("IN3_AUX"), 2803 2804 /*rx widgets*/ 2805 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 2806 wcd938x_codec_enable_ear_pa, 2807 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2808 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2809 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 2810 wcd938x_codec_enable_aux_pa, 2811 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2812 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2813 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 2814 wcd938x_codec_enable_hphl_pa, 2815 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2816 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2817 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 2818 wcd938x_codec_enable_hphr_pa, 2819 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2820 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2821 2822 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2823 wcd938x_codec_hphl_dac_event, 2824 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2825 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2826 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2827 wcd938x_codec_hphr_dac_event, 2828 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2829 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2830 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2831 wcd938x_codec_ear_dac_event, 2832 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2833 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2834 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2835 wcd938x_codec_aux_dac_event, 2836 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2837 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2838 2839 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2840 2841 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2842 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 2843 wcd938x_codec_enable_rxclk, 2844 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2845 SND_SOC_DAPM_POST_PMD), 2846 2847 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2848 2849 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2850 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2851 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2852 2853 /* rx mixer widgets*/ 2854 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2855 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2856 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2857 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2858 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2859 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2860 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2861 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2862 2863 /*output widgets rx*/ 2864 SND_SOC_DAPM_OUTPUT("EAR"), 2865 SND_SOC_DAPM_OUTPUT("AUX"), 2866 SND_SOC_DAPM_OUTPUT("HPHL"), 2867 SND_SOC_DAPM_OUTPUT("HPHR"), 2868 2869 }; 2870 2871 static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 2872 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 2873 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 2874 {"ADC1 REQ", NULL, "ADC1"}, 2875 {"ADC1", NULL, "AMIC1"}, 2876 2877 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 2878 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 2879 {"ADC2 REQ", NULL, "ADC2"}, 2880 {"ADC2", NULL, "HDR12 MUX"}, 2881 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 2882 {"HDR12 MUX", "HDR12", "AMIC1"}, 2883 {"ADC2 MUX", "INP3", "AMIC3"}, 2884 {"ADC2 MUX", "INP2", "AMIC2"}, 2885 2886 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 2887 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 2888 {"ADC3 REQ", NULL, "ADC3"}, 2889 {"ADC3", NULL, "HDR34 MUX"}, 2890 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 2891 {"HDR34 MUX", "HDR34", "AMIC5"}, 2892 {"ADC3 MUX", "INP4", "AMIC4"}, 2893 {"ADC3 MUX", "INP6", "AMIC6"}, 2894 2895 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 2896 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 2897 {"ADC4 REQ", NULL, "ADC4"}, 2898 {"ADC4", NULL, "ADC4 MUX"}, 2899 {"ADC4 MUX", "INP5", "AMIC5"}, 2900 {"ADC4 MUX", "INP7", "AMIC7"}, 2901 2902 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 2903 {"DMIC1_MIXER", "Switch", "DMIC1"}, 2904 2905 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 2906 {"DMIC2_MIXER", "Switch", "DMIC2"}, 2907 2908 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 2909 {"DMIC3_MIXER", "Switch", "DMIC3"}, 2910 2911 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 2912 {"DMIC4_MIXER", "Switch", "DMIC4"}, 2913 2914 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 2915 {"DMIC5_MIXER", "Switch", "DMIC5"}, 2916 2917 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 2918 {"DMIC6_MIXER", "Switch", "DMIC6"}, 2919 2920 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 2921 {"DMIC7_MIXER", "Switch", "DMIC7"}, 2922 2923 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 2924 {"DMIC8_MIXER", "Switch", "DMIC8"}, 2925 2926 {"IN1_HPHL", NULL, "VDD_BUCK"}, 2927 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 2928 2929 {"RX1", NULL, "IN1_HPHL"}, 2930 {"RX1", NULL, "RXCLK"}, 2931 {"RDAC1", NULL, "RX1"}, 2932 {"HPHL_RDAC", "Switch", "RDAC1"}, 2933 {"HPHL PGA", NULL, "HPHL_RDAC"}, 2934 {"HPHL", NULL, "HPHL PGA"}, 2935 2936 {"IN2_HPHR", NULL, "VDD_BUCK"}, 2937 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 2938 {"RX2", NULL, "IN2_HPHR"}, 2939 {"RDAC2", NULL, "RX2"}, 2940 {"RX2", NULL, "RXCLK"}, 2941 {"HPHR_RDAC", "Switch", "RDAC2"}, 2942 {"HPHR PGA", NULL, "HPHR_RDAC"}, 2943 {"HPHR", NULL, "HPHR PGA"}, 2944 2945 {"IN3_AUX", NULL, "VDD_BUCK"}, 2946 {"IN3_AUX", NULL, "CLS_H_PORT"}, 2947 {"RX3", NULL, "IN3_AUX"}, 2948 {"RDAC4", NULL, "RX3"}, 2949 {"RX3", NULL, "RXCLK"}, 2950 {"AUX_RDAC", "Switch", "RDAC4"}, 2951 {"AUX PGA", NULL, "AUX_RDAC"}, 2952 {"AUX", NULL, "AUX PGA"}, 2953 2954 {"RDAC3_MUX", "RX3", "RX3"}, 2955 {"RDAC3_MUX", "RX1", "RX1"}, 2956 {"RDAC3", NULL, "RDAC3_MUX"}, 2957 {"EAR_RDAC", "Switch", "RDAC3"}, 2958 {"EAR PGA", NULL, "EAR_RDAC"}, 2959 {"EAR", NULL, "EAR PGA"}, 2960 }; 2961 2962 static void wcd938x_set_micbias_data(struct device *dev, struct wcd938x_priv *wcd938x) 2963 { 2964 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 2965 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[0]); 2966 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 2967 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[1]); 2968 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 2969 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[2]); 2970 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 2971 WCD938X_MICB_VOUT_MASK, wcd938x->common.micb_vout[3]); 2972 } 2973 2974 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 2975 { 2976 return IRQ_HANDLED; 2977 } 2978 2979 static const struct irq_chip wcd_irq_chip = { 2980 .name = "WCD938x", 2981 }; 2982 2983 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 2984 irq_hw_number_t hw) 2985 { 2986 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 2987 irq_set_nested_thread(virq, 1); 2988 irq_set_noprobe(virq); 2989 2990 return 0; 2991 } 2992 2993 static const struct irq_domain_ops wcd_domain_ops = { 2994 .map = wcd_irq_chip_map, 2995 }; 2996 2997 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 2998 { 2999 3000 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 3001 if (!(wcd->virq)) { 3002 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 3003 return -EINVAL; 3004 } 3005 3006 return devm_regmap_add_irq_chip(dev, wcd->regmap, 3007 irq_create_mapping(wcd->virq, 0), 3008 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 3009 &wcd->irq_chip); 3010 } 3011 3012 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 3013 { 3014 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3015 struct device *dev = component->dev; 3016 unsigned int variant; 3017 int ret, i; 3018 3019 ret = sdw_slave_wait_for_init(wcd938x->tx_sdw_dev, 2000); 3020 if (ret) 3021 return ret; 3022 3023 snd_soc_component_init_regmap(component, wcd938x->regmap); 3024 3025 ret = pm_runtime_resume_and_get(dev); 3026 if (ret < 0) 3027 return ret; 3028 3029 variant = snd_soc_component_read_field(component, 3030 WCD938X_DIGITAL_EFUSE_REG_0, 3031 WCD938X_ID_MASK); 3032 3033 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 3034 if (IS_ERR(wcd938x->clsh_info)) { 3035 pm_runtime_put(dev); 3036 return PTR_ERR(wcd938x->clsh_info); 3037 } 3038 3039 wcd938x_io_init(wcd938x); 3040 /* Set all interrupts as edge triggered */ 3041 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 3042 regmap_write(wcd938x->regmap, 3043 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 3044 } 3045 3046 pm_runtime_put(dev); 3047 3048 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3049 WCD938X_IRQ_HPHR_PDM_WD_INT); 3050 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3051 WCD938X_IRQ_HPHL_PDM_WD_INT); 3052 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3053 WCD938X_IRQ_AUX_PDM_WD_INT); 3054 3055 /* Request for watchdog interrupt */ 3056 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3057 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3058 "HPHR PDM WD INT", wcd938x); 3059 if (ret) { 3060 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3061 goto err_free_clsh_ctrl; 3062 } 3063 3064 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3065 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3066 "HPHL PDM WD INT", wcd938x); 3067 if (ret) { 3068 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3069 goto err_free_hphr_pdm_wd_int; 3070 } 3071 3072 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3073 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3074 "AUX PDM WD INT", wcd938x); 3075 if (ret) { 3076 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3077 goto err_free_hphl_pdm_wd_int; 3078 } 3079 3080 /* Disable watchdog interrupt for HPH and AUX */ 3081 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 3082 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 3083 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 3084 3085 switch (variant) { 3086 case CHIPID_WCD9380: 3087 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 3088 ARRAY_SIZE(wcd9380_snd_controls)); 3089 if (ret < 0) { 3090 dev_err(component->dev, 3091 "%s: Failed to add snd ctrls for variant: %d\n", 3092 __func__, variant); 3093 goto err_free_aux_pdm_wd_int; 3094 } 3095 break; 3096 case CHIPID_WCD9385: 3097 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 3098 ARRAY_SIZE(wcd9385_snd_controls)); 3099 if (ret < 0) { 3100 dev_err(component->dev, 3101 "%s: Failed to add snd ctrls for variant: %d\n", 3102 __func__, variant); 3103 goto err_free_aux_pdm_wd_int; 3104 } 3105 break; 3106 default: 3107 break; 3108 } 3109 3110 ret = wcd938x_mbhc_init(component); 3111 if (ret) { 3112 dev_err(component->dev, "mbhc initialization failed\n"); 3113 goto err_free_aux_pdm_wd_int; 3114 } 3115 3116 return 0; 3117 3118 err_free_aux_pdm_wd_int: 3119 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3120 err_free_hphl_pdm_wd_int: 3121 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3122 err_free_hphr_pdm_wd_int: 3123 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3124 err_free_clsh_ctrl: 3125 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3126 3127 return ret; 3128 } 3129 3130 static void wcd938x_soc_codec_remove(struct snd_soc_component *component) 3131 { 3132 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3133 3134 wcd938x_mbhc_deinit(component); 3135 3136 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3137 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3138 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3139 3140 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3141 } 3142 3143 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 3144 struct snd_soc_jack *jack, void *data) 3145 { 3146 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 3147 3148 if (jack) 3149 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 3150 else 3151 wcd_mbhc_stop(wcd->wcd_mbhc); 3152 3153 return 0; 3154 } 3155 3156 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 3157 .name = "wcd938x_codec", 3158 .probe = wcd938x_soc_codec_probe, 3159 .remove = wcd938x_soc_codec_remove, 3160 .controls = wcd938x_snd_controls, 3161 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 3162 .dapm_widgets = wcd938x_dapm_widgets, 3163 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 3164 .dapm_routes = wcd938x_audio_map, 3165 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 3166 .set_jack = wcd938x_codec_set_jack, 3167 .endianness = 1, 3168 }; 3169 3170 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component) 3171 { 3172 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3173 struct device *dev = component->dev; 3174 int ret; 3175 3176 if (wcd938x->us_euro_mux) { 3177 if (wcd938x->mux_setup_done) 3178 mux_control_deselect(wcd938x->us_euro_mux); 3179 3180 ret = mux_control_try_select(wcd938x->us_euro_mux, !wcd938x->mux_state); 3181 if (ret) { 3182 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret); 3183 wcd938x->mux_setup_done = false; 3184 return false; 3185 } 3186 wcd938x->mux_setup_done = true; 3187 } else { 3188 gpiod_set_value(wcd938x->us_euro_gpio, !wcd938x->mux_state); 3189 } 3190 3191 wcd938x->mux_state = !wcd938x->mux_state; 3192 3193 return true; 3194 } 3195 3196 3197 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 3198 { 3199 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 3200 int ret; 3201 3202 wcd938x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 3203 if (IS_ERR(wcd938x->reset_gpio)) 3204 return dev_err_probe(dev, PTR_ERR(wcd938x->reset_gpio), 3205 "Failed to get reset gpio\n"); 3206 3207 if (of_property_present(dev->of_node, "mux-controls")) { 3208 wcd938x->us_euro_mux = devm_mux_control_get(dev, NULL); 3209 if (IS_ERR(wcd938x->us_euro_mux)) { 3210 ret = PTR_ERR(wcd938x->us_euro_mux); 3211 return dev_err_probe(dev, ret, "failed to get mux control\n"); 3212 } 3213 3214 ret = mux_control_try_select(wcd938x->us_euro_mux, wcd938x->mux_state); 3215 if (ret) { 3216 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret); 3217 return ret; 3218 } 3219 wcd938x->mux_setup_done = true; 3220 } else { 3221 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 3222 if (IS_ERR(wcd938x->us_euro_gpio)) 3223 return dev_err_probe(dev, PTR_ERR(wcd938x->us_euro_gpio), 3224 "us-euro swap Control GPIO not found\n"); 3225 } 3226 3227 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic; 3228 3229 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd938x_supplies), 3230 wcd938x_supplies); 3231 if (ret) 3232 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 3233 3234 ret = wcd_dt_parse_micbias_info(&wcd938x->common); 3235 if (ret) 3236 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 3237 3238 cfg->mbhc_micbias = MIC_BIAS_2; 3239 cfg->anc_micbias = MIC_BIAS_2; 3240 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 3241 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 3242 cfg->micb_mv = wcd938x->common.micb_mv[2]; 3243 cfg->linein_th = 5000; 3244 cfg->hs_thr = 1700; 3245 cfg->hph_thr = 50; 3246 3247 wcd_dt_parse_mbhc_data(dev, cfg); 3248 3249 return 0; 3250 } 3251 3252 static int wcd938x_reset(struct wcd938x_priv *wcd938x) 3253 { 3254 gpiod_set_value(wcd938x->reset_gpio, 1); 3255 /* 20us sleep required after pulling the reset gpio to LOW */ 3256 usleep_range(20, 30); 3257 gpiod_set_value(wcd938x->reset_gpio, 0); 3258 /* 20us sleep required after pulling the reset gpio to HIGH */ 3259 usleep_range(20, 30); 3260 3261 return 0; 3262 } 3263 3264 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 3265 struct snd_pcm_hw_params *params, 3266 struct snd_soc_dai *dai) 3267 { 3268 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3269 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3270 3271 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 3272 } 3273 3274 static int wcd938x_codec_free(struct snd_pcm_substream *substream, 3275 struct snd_soc_dai *dai) 3276 { 3277 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3278 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3279 3280 return wcd938x_sdw_free(wcd, substream, dai); 3281 } 3282 3283 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 3284 void *stream, int direction) 3285 { 3286 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3287 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3288 3289 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 3290 3291 } 3292 3293 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 3294 .hw_params = wcd938x_codec_hw_params, 3295 .hw_free = wcd938x_codec_free, 3296 .set_stream = wcd938x_codec_set_sdw_stream, 3297 }; 3298 3299 static struct snd_soc_dai_driver wcd938x_dais[] = { 3300 [AIF1_PB] = { 3301 .name = "wcd938x-sdw-rx", 3302 .playback = { 3303 .stream_name = "WCD AIF1 Playback", 3304 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 3305 .formats = WCD938X_FORMATS_S16_S24_LE, 3306 .rate_max = 192000, 3307 .rate_min = 8000, 3308 .channels_min = 1, 3309 .channels_max = 2, 3310 }, 3311 .ops = &wcd938x_sdw_dai_ops, 3312 }, 3313 [AIF1_CAP] = { 3314 .name = "wcd938x-sdw-tx", 3315 .capture = { 3316 .stream_name = "WCD AIF1 Capture", 3317 .rates = WCD938X_RATES_MASK, 3318 .formats = SNDRV_PCM_FMTBIT_S16_LE, 3319 .rate_min = 8000, 3320 .rate_max = 192000, 3321 .channels_min = 1, 3322 .channels_max = 4, 3323 }, 3324 .ops = &wcd938x_sdw_dai_ops, 3325 }, 3326 }; 3327 3328 static int wcd938x_bind(struct device *dev) 3329 { 3330 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3331 int ret; 3332 3333 ret = component_bind_all(dev, wcd938x); 3334 if (ret) { 3335 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 3336 __func__, ret); 3337 return ret; 3338 } 3339 3340 wcd938x->rxdev = of_sdw_find_device_by_node(wcd938x->rxnode); 3341 if (!wcd938x->rxdev) { 3342 dev_err(dev, "could not find slave with matching of node\n"); 3343 ret = -EINVAL; 3344 goto err_unbind; 3345 } 3346 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 3347 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 3348 3349 wcd938x->txdev = of_sdw_find_device_by_node(wcd938x->txnode); 3350 if (!wcd938x->txdev) { 3351 dev_err(dev, "could not find txslave with matching of node\n"); 3352 ret = -EINVAL; 3353 goto err_put_rxdev; 3354 } 3355 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 3356 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 3357 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 3358 3359 /* As TX is main CSR reg interface, which should not be suspended first. 3360 * expicilty add the dependency link */ 3361 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 3362 DL_FLAG_PM_RUNTIME)) { 3363 dev_err(dev, "could not devlink tx and rx\n"); 3364 ret = -EINVAL; 3365 goto err_put_txdev; 3366 } 3367 3368 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 3369 DL_FLAG_PM_RUNTIME)) { 3370 dev_err(dev, "could not devlink wcd and tx\n"); 3371 ret = -EINVAL; 3372 goto err_remove_rxtx_link; 3373 } 3374 3375 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 3376 DL_FLAG_PM_RUNTIME)) { 3377 dev_err(dev, "could not devlink wcd and rx\n"); 3378 ret = -EINVAL; 3379 goto err_remove_tx_link; 3380 } 3381 3382 wcd938x->regmap = wcd938x->sdw_priv[AIF1_CAP]->regmap; 3383 if (!wcd938x->regmap) { 3384 dev_err(dev, "could not get TX device regmap\n"); 3385 ret = -EINVAL; 3386 goto err_remove_rx_link; 3387 } 3388 3389 ret = wcd938x_irq_init(wcd938x, dev); 3390 if (ret) { 3391 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 3392 goto err_remove_rx_link; 3393 } 3394 3395 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 3396 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 3397 3398 wcd938x_set_micbias_data(dev, wcd938x); 3399 3400 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 3401 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 3402 if (ret) { 3403 dev_err(dev, "%s: Codec registration failed\n", 3404 __func__); 3405 goto err_remove_rx_link; 3406 } 3407 3408 return 0; 3409 3410 err_remove_rx_link: 3411 device_link_remove(dev, wcd938x->rxdev); 3412 err_remove_tx_link: 3413 device_link_remove(dev, wcd938x->txdev); 3414 err_remove_rxtx_link: 3415 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3416 err_put_txdev: 3417 put_device(wcd938x->txdev); 3418 err_put_rxdev: 3419 put_device(wcd938x->rxdev); 3420 err_unbind: 3421 component_unbind_all(dev, wcd938x); 3422 3423 return ret; 3424 } 3425 3426 static void wcd938x_unbind(struct device *dev) 3427 { 3428 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3429 3430 snd_soc_unregister_component(dev); 3431 device_link_remove(dev, wcd938x->txdev); 3432 device_link_remove(dev, wcd938x->rxdev); 3433 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3434 put_device(wcd938x->txdev); 3435 put_device(wcd938x->rxdev); 3436 component_unbind_all(dev, wcd938x); 3437 } 3438 3439 static const struct component_master_ops wcd938x_comp_ops = { 3440 .bind = wcd938x_bind, 3441 .unbind = wcd938x_unbind, 3442 }; 3443 3444 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 3445 struct device *dev, 3446 struct component_match **matchptr) 3447 { 3448 struct device_node *np; 3449 3450 np = dev->of_node; 3451 3452 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 3453 if (!wcd938x->rxnode) { 3454 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 3455 return -ENODEV; 3456 } 3457 3458 component_match_add_release(dev, matchptr, component_release_of, 3459 component_compare_of, wcd938x->rxnode); 3460 3461 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 3462 if (!wcd938x->txnode) { 3463 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 3464 return -ENODEV; 3465 } 3466 3467 component_match_add_release(dev, matchptr, component_release_of, 3468 component_compare_of, wcd938x->txnode); 3469 return 0; 3470 } 3471 3472 static int wcd938x_probe(struct platform_device *pdev) 3473 { 3474 struct component_match *match = NULL; 3475 struct wcd938x_priv *wcd938x = NULL; 3476 struct device *dev = &pdev->dev; 3477 int ret; 3478 3479 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 3480 GFP_KERNEL); 3481 if (!wcd938x) 3482 return -ENOMEM; 3483 3484 dev_set_drvdata(dev, wcd938x); 3485 mutex_init(&wcd938x->micb_lock); 3486 wcd938x->common.dev = dev; 3487 wcd938x->common.max_bias = 4; 3488 3489 ret = wcd938x_populate_dt_data(wcd938x, dev); 3490 if (ret) 3491 return ret; 3492 3493 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 3494 if (ret) 3495 return ret; 3496 3497 wcd938x_reset(wcd938x); 3498 3499 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 3500 if (ret) 3501 return ret; 3502 3503 pm_runtime_set_autosuspend_delay(dev, 1000); 3504 pm_runtime_use_autosuspend(dev); 3505 pm_runtime_mark_last_busy(dev); 3506 pm_runtime_set_active(dev); 3507 pm_runtime_enable(dev); 3508 pm_runtime_idle(dev); 3509 3510 return 0; 3511 } 3512 3513 static void wcd938x_remove(struct platform_device *pdev) 3514 { 3515 struct device *dev = &pdev->dev; 3516 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3517 3518 component_master_del(dev, &wcd938x_comp_ops); 3519 3520 pm_runtime_disable(dev); 3521 pm_runtime_set_suspended(dev); 3522 pm_runtime_dont_use_autosuspend(dev); 3523 3524 if (wcd938x->us_euro_mux && wcd938x->mux_setup_done) 3525 mux_control_deselect(wcd938x->us_euro_mux); 3526 } 3527 3528 #if defined(CONFIG_OF) 3529 static const struct of_device_id wcd938x_dt_match[] = { 3530 { .compatible = "qcom,wcd9380-codec" }, 3531 { .compatible = "qcom,wcd9385-codec" }, 3532 {} 3533 }; 3534 MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 3535 #endif 3536 3537 static struct platform_driver wcd938x_codec_driver = { 3538 .probe = wcd938x_probe, 3539 .remove = wcd938x_remove, 3540 .driver = { 3541 .name = "wcd938x_codec", 3542 .of_match_table = of_match_ptr(wcd938x_dt_match), 3543 .suppress_bind_attrs = true, 3544 }, 3545 }; 3546 3547 module_platform_driver(wcd938x_codec_driver); 3548 MODULE_DESCRIPTION("WCD938X Codec driver"); 3549 MODULE_LICENSE("GPL"); 3550