1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/slab.h> 6 #include <linux/platform_device.h> 7 #include <linux/device.h> 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/kernel.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/component.h> 13 #include <sound/tlv.h> 14 #include <linux/of.h> 15 #include <sound/jack.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <linux/regmap.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dapm.h> 21 #include <linux/mux/consumer.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd938x.h" 27 28 #define CHIPID_WCD9380 0x0 29 #define CHIPID_WCD9385 0x5 30 31 #define WCD938X_MAX_MICBIAS (4) 32 #define WCD938X_MBHC_MAX_BUTTONS (8) 33 #define TX_ADC_MAX (4) 34 35 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 36 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 37 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 38 /* Fractional Rates */ 39 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 40 SNDRV_PCM_RATE_176400) 41 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 42 SNDRV_PCM_FMTBIT_S24_LE) 43 #define SWR_CLK_RATE_0P6MHZ (600000) 44 #define SWR_CLK_RATE_1P2MHZ (1200000) 45 #define SWR_CLK_RATE_2P4MHZ (2400000) 46 #define SWR_CLK_RATE_4P8MHZ (4800000) 47 #define SWR_CLK_RATE_9P6MHZ (9600000) 48 #define SWR_CLK_RATE_11P2896MHZ (1128960) 49 50 #define EAR_RX_PATH_AUX (1) 51 52 #define ADC_MODE_VAL_HIFI 0x01 53 #define ADC_MODE_VAL_LO_HIF 0x02 54 #define ADC_MODE_VAL_NORMAL 0x03 55 #define ADC_MODE_VAL_LP 0x05 56 #define ADC_MODE_VAL_ULP1 0x09 57 #define ADC_MODE_VAL_ULP2 0x0B 58 59 /* Z value defined in milliohm */ 60 #define WCD938X_ZDET_VAL_32 (32000) 61 #define WCD938X_ZDET_VAL_400 (400000) 62 #define WCD938X_ZDET_VAL_1200 (1200000) 63 #define WCD938X_ZDET_VAL_100K (100000000) 64 /* Z floating defined in ohms */ 65 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 66 #define WCD938X_ZDET_NUM_MEASUREMENTS (900) 67 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 68 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 69 /* Z value compared in milliOhm */ 70 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 71 #define WCD938X_MBHC_ZDET_CONST (86 * 16384) 72 #define WCD_MBHC_HS_V_MAX 1600 73 74 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 75 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, snd_soc_get_volsw, \ 76 wcd938x_ear_pa_put_gain, tlv_array) 77 78 enum { 79 /* INTR_CTRL_INT_MASK_0 */ 80 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 81 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 82 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 83 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 84 WCD938X_IRQ_MBHC_SW_DET, 85 WCD938X_IRQ_HPHR_OCP_INT, 86 WCD938X_IRQ_HPHR_CNP_INT, 87 WCD938X_IRQ_HPHL_OCP_INT, 88 89 /* INTR_CTRL_INT_MASK_1 */ 90 WCD938X_IRQ_HPHL_CNP_INT, 91 WCD938X_IRQ_EAR_CNP_INT, 92 WCD938X_IRQ_EAR_SCD_INT, 93 WCD938X_IRQ_AUX_CNP_INT, 94 WCD938X_IRQ_AUX_SCD_INT, 95 WCD938X_IRQ_HPHL_PDM_WD_INT, 96 WCD938X_IRQ_HPHR_PDM_WD_INT, 97 WCD938X_IRQ_AUX_PDM_WD_INT, 98 99 /* INTR_CTRL_INT_MASK_2 */ 100 WCD938X_IRQ_LDORT_SCD_INT, 101 WCD938X_IRQ_MBHC_MOISTURE_INT, 102 WCD938X_IRQ_HPHL_SURGE_DET_INT, 103 WCD938X_IRQ_HPHR_SURGE_DET_INT, 104 WCD938X_NUM_IRQS, 105 }; 106 107 enum { 108 WCD_ADC1 = 0, 109 WCD_ADC2, 110 WCD_ADC3, 111 WCD_ADC4, 112 ALLOW_BUCK_DISABLE, 113 HPH_COMP_DELAY, 114 HPH_PA_DELAY, 115 AMIC2_BCS_ENABLE, 116 WCD_SUPPLIES_LPM_MODE, 117 }; 118 119 enum { 120 ADC_MODE_INVALID = 0, 121 ADC_MODE_HIFI, 122 ADC_MODE_LO_HIF, 123 ADC_MODE_NORMAL, 124 ADC_MODE_LP, 125 ADC_MODE_ULP1, 126 ADC_MODE_ULP2, 127 }; 128 129 enum { 130 AIF1_PB = 0, 131 AIF1_CAP, 132 NUM_CODEC_DAIS, 133 }; 134 135 static u8 tx_mode_bit[] = { 136 [ADC_MODE_INVALID] = 0x00, 137 [ADC_MODE_HIFI] = 0x01, 138 [ADC_MODE_LO_HIF] = 0x02, 139 [ADC_MODE_NORMAL] = 0x04, 140 [ADC_MODE_LP] = 0x08, 141 [ADC_MODE_ULP1] = 0x10, 142 [ADC_MODE_ULP2] = 0x20, 143 }; 144 145 struct wcd938x_priv { 146 struct sdw_slave *tx_sdw_dev; 147 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 148 struct device *txdev; 149 struct device *rxdev; 150 struct device_node *rxnode, *txnode; 151 struct regmap *regmap; 152 struct mutex micb_lock; 153 /* mbhc module */ 154 struct wcd_mbhc *wcd_mbhc; 155 struct wcd_mbhc_config mbhc_cfg; 156 struct wcd_mbhc_intr intr_ids; 157 struct wcd_clsh_ctrl *clsh_info; 158 struct irq_domain *virq; 159 struct regmap_irq_chip_data *irq_chip; 160 struct snd_soc_jack *jack; 161 unsigned long status_mask; 162 s32 micb_ref[WCD938X_MAX_MICBIAS]; 163 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 164 u32 hph_mode; 165 u32 tx_mode[TX_ADC_MAX]; 166 int flyback_cur_det_disable; 167 int ear_rx_path; 168 struct gpio_desc *reset_gpio; 169 struct gpio_desc *us_euro_gpio; 170 struct mux_control *us_euro_mux; 171 unsigned int mux_state; 172 u32 micb1_mv; 173 u32 micb2_mv; 174 u32 micb3_mv; 175 u32 micb4_mv; 176 int hphr_pdm_wd_int; 177 int hphl_pdm_wd_int; 178 int aux_pdm_wd_int; 179 bool comp1_enable; 180 bool comp2_enable; 181 bool ldoh; 182 bool mux_setup_done; 183 }; 184 185 static const char * const wcd938x_supplies[] = { 186 "vdd-rxtx", "vdd-io", "vdd-buck", "vdd-mic-bias", 187 }; 188 189 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 190 static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, 0); 191 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 192 193 struct wcd938x_mbhc_zdet_param { 194 u16 ldo_ctl; 195 u16 noff; 196 u16 nshift; 197 u16 btn5; 198 u16 btn6; 199 u16 btn7; 200 }; 201 202 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 203 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 204 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 205 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 206 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 207 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 208 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 209 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 210 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 211 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 212 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 213 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 214 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 215 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 216 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 217 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 218 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 219 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 220 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 221 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 222 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 223 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 224 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 225 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 226 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 227 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 228 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 229 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 230 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 231 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 232 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 233 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 234 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 235 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 236 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 237 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 238 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 239 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 240 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 241 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 242 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 243 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 244 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 245 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 246 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 247 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 248 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 249 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 250 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 251 }; 252 253 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 254 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 255 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 256 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 257 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 258 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 259 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 260 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 261 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 262 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 263 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 264 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 265 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 266 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 267 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 268 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 269 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 270 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 271 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 272 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 273 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 274 }; 275 276 static const struct regmap_irq_chip wcd938x_regmap_irq_chip = { 277 .name = "wcd938x", 278 .irqs = wcd938x_irqs, 279 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 280 .num_regs = 3, 281 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 282 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 283 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 284 .use_ack = 1, 285 .runtime_pm = true, 286 .irq_drv_data = NULL, 287 }; 288 289 static int wcd938x_get_clk_rate(int mode) 290 { 291 int rate; 292 293 switch (mode) { 294 case ADC_MODE_ULP2: 295 rate = SWR_CLK_RATE_0P6MHZ; 296 break; 297 case ADC_MODE_ULP1: 298 rate = SWR_CLK_RATE_1P2MHZ; 299 break; 300 case ADC_MODE_LP: 301 rate = SWR_CLK_RATE_4P8MHZ; 302 break; 303 case ADC_MODE_NORMAL: 304 case ADC_MODE_LO_HIF: 305 case ADC_MODE_HIFI: 306 case ADC_MODE_INVALID: 307 default: 308 rate = SWR_CLK_RATE_9P6MHZ; 309 break; 310 } 311 312 return rate; 313 } 314 315 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 316 { 317 u8 mask = (bank ? 0xF0 : 0x0F); 318 u8 val = 0; 319 320 switch (rate) { 321 case SWR_CLK_RATE_0P6MHZ: 322 val = (bank ? 0x60 : 0x06); 323 break; 324 case SWR_CLK_RATE_1P2MHZ: 325 val = (bank ? 0x50 : 0x05); 326 break; 327 case SWR_CLK_RATE_2P4MHZ: 328 val = (bank ? 0x30 : 0x03); 329 break; 330 case SWR_CLK_RATE_4P8MHZ: 331 val = (bank ? 0x10 : 0x01); 332 break; 333 case SWR_CLK_RATE_9P6MHZ: 334 default: 335 val = 0x00; 336 break; 337 } 338 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 339 mask, val); 340 341 return 0; 342 } 343 344 static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 345 { 346 struct regmap *rm = wcd938x->regmap; 347 348 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 349 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 350 /* 1 msec delay as per HW requirement */ 351 usleep_range(1000, 1010); 352 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 353 /* 1 msec delay as per HW requirement */ 354 usleep_range(1000, 1010); 355 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 356 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 357 0xF0, 0x80); 358 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 359 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 360 /* 10 msec delay as per HW requirement */ 361 usleep_range(10000, 10010); 362 363 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 364 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 365 0xF0, 0x00); 366 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 367 0x1F, 0x15); 368 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 369 0x1F, 0x15); 370 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 371 0xC0, 0x80); 372 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 373 0x02, 0x02); 374 375 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 376 0xFF, 0x14); 377 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 378 0x1F, 0x08); 379 380 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 381 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 382 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 383 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 384 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 385 386 /* Set Noise Filter Resistor value */ 387 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 388 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 389 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 390 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 391 392 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 393 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 394 395 return 0; 396 397 } 398 399 static int wcd938x_sdw_connect_port(const struct wcd938x_sdw_ch_info *ch_info, 400 struct sdw_port_config *port_config, 401 u8 enable) 402 { 403 u8 ch_mask, port_num; 404 405 port_num = ch_info->port_num; 406 ch_mask = ch_info->ch_mask; 407 408 port_config->num = port_num; 409 410 if (enable) 411 port_config->ch_mask |= ch_mask; 412 else 413 port_config->ch_mask &= ~ch_mask; 414 415 return 0; 416 } 417 418 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 419 { 420 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 421 &wcd->port_config[port_num - 1], 422 enable); 423 } 424 425 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 426 struct snd_kcontrol *kcontrol, 427 int event) 428 { 429 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 430 431 switch (event) { 432 case SND_SOC_DAPM_PRE_PMU: 433 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 434 WCD938X_ANA_RX_CLK_EN_MASK, 1); 435 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 436 WCD938X_RX_BIAS_EN_MASK, 1); 437 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 438 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 439 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 440 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 441 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 442 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 443 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 444 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 445 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 446 WCD938X_AUXPA_CLK_EN_MASK, 1); 447 break; 448 case SND_SOC_DAPM_POST_PMD: 449 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 450 WCD938X_VNEG_EN_MASK, 0); 451 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 452 WCD938X_VPOS_EN_MASK, 0); 453 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 454 WCD938X_RX_BIAS_EN_MASK, 0); 455 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 456 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 457 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 458 WCD938X_ANA_RX_CLK_EN_MASK, 0); 459 break; 460 } 461 return 0; 462 } 463 464 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 465 struct snd_kcontrol *kcontrol, 466 int event) 467 { 468 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 469 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 470 471 switch (event) { 472 case SND_SOC_DAPM_PRE_PMU: 473 snd_soc_component_write_field(component, 474 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 475 WCD938X_RXD0_CLK_EN_MASK, 0x01); 476 snd_soc_component_write_field(component, 477 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 478 WCD938X_HPHL_RX_EN_MASK, 1); 479 snd_soc_component_write_field(component, 480 WCD938X_HPH_RDAC_CLK_CTL1, 481 WCD938X_CHOP_CLK_EN_MASK, 0); 482 break; 483 case SND_SOC_DAPM_POST_PMU: 484 snd_soc_component_write_field(component, 485 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 486 WCD938X_HPH_RES_DIV_MASK, 0x02); 487 if (wcd938x->comp1_enable) { 488 snd_soc_component_write_field(component, 489 WCD938X_DIGITAL_CDC_COMP_CTL_0, 490 WCD938X_HPHL_COMP_EN_MASK, 1); 491 /* 5msec compander delay as per HW requirement */ 492 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 493 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 494 usleep_range(5000, 5010); 495 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 496 WCD938X_AUTOCHOP_TIMER_EN, 0); 497 } else { 498 snd_soc_component_write_field(component, 499 WCD938X_DIGITAL_CDC_COMP_CTL_0, 500 WCD938X_HPHL_COMP_EN_MASK, 0); 501 snd_soc_component_write_field(component, 502 WCD938X_HPH_L_EN, 503 WCD938X_GAIN_SRC_SEL_MASK, 504 WCD938X_GAIN_SRC_SEL_REGISTER); 505 506 } 507 break; 508 case SND_SOC_DAPM_POST_PMD: 509 snd_soc_component_write_field(component, 510 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 511 WCD938X_HPH_RES_DIV_MASK, 0x1); 512 break; 513 } 514 515 return 0; 516 } 517 518 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 519 struct snd_kcontrol *kcontrol, 520 int event) 521 { 522 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 523 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 524 525 switch (event) { 526 case SND_SOC_DAPM_PRE_PMU: 527 snd_soc_component_write_field(component, 528 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 529 WCD938X_RXD1_CLK_EN_MASK, 1); 530 snd_soc_component_write_field(component, 531 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 532 WCD938X_HPHR_RX_EN_MASK, 1); 533 snd_soc_component_write_field(component, 534 WCD938X_HPH_RDAC_CLK_CTL1, 535 WCD938X_CHOP_CLK_EN_MASK, 0); 536 break; 537 case SND_SOC_DAPM_POST_PMU: 538 snd_soc_component_write_field(component, 539 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 540 WCD938X_HPH_RES_DIV_MASK, 0x02); 541 if (wcd938x->comp2_enable) { 542 snd_soc_component_write_field(component, 543 WCD938X_DIGITAL_CDC_COMP_CTL_0, 544 WCD938X_HPHR_COMP_EN_MASK, 1); 545 /* 5msec compander delay as per HW requirement */ 546 if (!wcd938x->comp1_enable || 547 (snd_soc_component_read(component, 548 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 549 usleep_range(5000, 5010); 550 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 551 WCD938X_AUTOCHOP_TIMER_EN, 0); 552 } else { 553 snd_soc_component_write_field(component, 554 WCD938X_DIGITAL_CDC_COMP_CTL_0, 555 WCD938X_HPHR_COMP_EN_MASK, 0); 556 snd_soc_component_write_field(component, 557 WCD938X_HPH_R_EN, 558 WCD938X_GAIN_SRC_SEL_MASK, 559 WCD938X_GAIN_SRC_SEL_REGISTER); 560 } 561 break; 562 case SND_SOC_DAPM_POST_PMD: 563 snd_soc_component_write_field(component, 564 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 565 WCD938X_HPH_RES_DIV_MASK, 0x01); 566 break; 567 } 568 569 return 0; 570 } 571 572 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 573 struct snd_kcontrol *kcontrol, 574 int event) 575 { 576 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 577 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 578 579 switch (event) { 580 case SND_SOC_DAPM_PRE_PMU: 581 wcd938x->ear_rx_path = 582 snd_soc_component_read( 583 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 584 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 585 snd_soc_component_write_field(component, 586 WCD938X_EAR_EAR_DAC_CON, 587 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 588 snd_soc_component_write_field(component, 589 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 590 WCD938X_AUX_EN_MASK, 1); 591 snd_soc_component_write_field(component, 592 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 593 WCD938X_RXD2_CLK_EN_MASK, 1); 594 snd_soc_component_write_field(component, 595 WCD938X_ANA_EAR_COMPANDER_CTL, 596 WCD938X_GAIN_OVRD_REG_MASK, 1); 597 } else { 598 snd_soc_component_write_field(component, 599 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 600 WCD938X_HPHL_RX_EN_MASK, 1); 601 snd_soc_component_write_field(component, 602 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 603 WCD938X_RXD0_CLK_EN_MASK, 1); 604 if (wcd938x->comp1_enable) 605 snd_soc_component_write_field(component, 606 WCD938X_DIGITAL_CDC_COMP_CTL_0, 607 WCD938X_HPHL_COMP_EN_MASK, 1); 608 } 609 /* 5 msec delay as per HW requirement */ 610 usleep_range(5000, 5010); 611 if (wcd938x->flyback_cur_det_disable == 0) 612 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 613 WCD938X_EN_CUR_DET_MASK, 0); 614 wcd938x->flyback_cur_det_disable++; 615 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 616 WCD_CLSH_EVENT_PRE_DAC, 617 WCD_CLSH_STATE_EAR, 618 wcd938x->hph_mode); 619 break; 620 case SND_SOC_DAPM_POST_PMD: 621 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 622 snd_soc_component_write_field(component, 623 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 624 WCD938X_AUX_EN_MASK, 0); 625 snd_soc_component_write_field(component, 626 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 627 WCD938X_RXD2_CLK_EN_MASK, 0); 628 } else { 629 snd_soc_component_write_field(component, 630 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 631 WCD938X_HPHL_RX_EN_MASK, 0); 632 snd_soc_component_write_field(component, 633 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 634 WCD938X_RXD0_CLK_EN_MASK, 0); 635 if (wcd938x->comp1_enable) 636 snd_soc_component_write_field(component, 637 WCD938X_DIGITAL_CDC_COMP_CTL_0, 638 WCD938X_HPHL_COMP_EN_MASK, 0); 639 } 640 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 641 WCD938X_GAIN_OVRD_REG_MASK, 0); 642 snd_soc_component_write_field(component, 643 WCD938X_EAR_EAR_DAC_CON, 644 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 645 break; 646 } 647 return 0; 648 649 } 650 651 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 652 struct snd_kcontrol *kcontrol, 653 int event) 654 { 655 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 656 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 657 658 switch (event) { 659 case SND_SOC_DAPM_PRE_PMU: 660 snd_soc_component_write_field(component, 661 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 662 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 663 snd_soc_component_write_field(component, 664 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 665 WCD938X_RXD2_CLK_EN_MASK, 1); 666 snd_soc_component_write_field(component, 667 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 668 WCD938X_AUX_EN_MASK, 1); 669 if (wcd938x->flyback_cur_det_disable == 0) 670 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 671 WCD938X_EN_CUR_DET_MASK, 0); 672 wcd938x->flyback_cur_det_disable++; 673 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 674 WCD_CLSH_EVENT_PRE_DAC, 675 WCD_CLSH_STATE_AUX, 676 wcd938x->hph_mode); 677 break; 678 case SND_SOC_DAPM_POST_PMD: 679 snd_soc_component_write_field(component, 680 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 681 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 682 break; 683 } 684 return 0; 685 686 } 687 688 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 689 struct snd_kcontrol *kcontrol, int event) 690 { 691 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 692 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 693 int hph_mode = wcd938x->hph_mode; 694 695 switch (event) { 696 case SND_SOC_DAPM_PRE_PMU: 697 if (wcd938x->ldoh) 698 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 699 WCD938X_LDOH_EN_MASK, 1); 700 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 701 WCD_CLSH_STATE_HPHR, hph_mode); 702 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 703 704 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 705 hph_mode == CLS_H_ULP) { 706 snd_soc_component_write_field(component, 707 WCD938X_HPH_REFBUFF_LP_CTL, 708 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 709 } 710 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 711 WCD938X_HPHR_REF_EN_MASK, 1); 712 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 713 /* 100 usec delay as per HW requirement */ 714 usleep_range(100, 110); 715 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 716 snd_soc_component_write_field(component, 717 WCD938X_DIGITAL_PDM_WD_CTL1, 718 WCD938X_PDM_WD_EN_MASK, 0x3); 719 break; 720 case SND_SOC_DAPM_POST_PMU: 721 /* 722 * 7ms sleep is required if compander is enabled as per 723 * HW requirement. If compander is disabled, then 724 * 20ms delay is required. 725 */ 726 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 727 if (!wcd938x->comp2_enable) 728 usleep_range(20000, 20100); 729 else 730 usleep_range(7000, 7100); 731 732 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 733 hph_mode == CLS_H_ULP) 734 snd_soc_component_write_field(component, 735 WCD938X_HPH_REFBUFF_LP_CTL, 736 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 737 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 738 } 739 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 740 WCD938X_AUTOCHOP_TIMER_EN, 1); 741 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 742 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 743 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 744 WCD938X_REGULATOR_MODE_MASK, 745 WCD938X_REGULATOR_MODE_CLASS_AB); 746 enable_irq(wcd938x->hphr_pdm_wd_int); 747 break; 748 case SND_SOC_DAPM_PRE_PMD: 749 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 750 /* 751 * 7ms sleep is required if compander is enabled as per 752 * HW requirement. If compander is disabled, then 753 * 20ms delay is required. 754 */ 755 if (!wcd938x->comp2_enable) 756 usleep_range(20000, 20100); 757 else 758 usleep_range(7000, 7100); 759 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 760 WCD938X_HPHR_EN_MASK, 0); 761 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 762 WCD_EVENT_PRE_HPHR_PA_OFF); 763 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 764 break; 765 case SND_SOC_DAPM_POST_PMD: 766 /* 767 * 7ms sleep is required if compander is enabled as per 768 * HW requirement. If compander is disabled, then 769 * 20ms delay is required. 770 */ 771 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 772 if (!wcd938x->comp2_enable) 773 usleep_range(20000, 20100); 774 else 775 usleep_range(7000, 7100); 776 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 777 } 778 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 779 WCD_EVENT_POST_HPHR_PA_OFF); 780 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 781 WCD938X_HPHR_REF_EN_MASK, 0); 782 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 783 WCD938X_PDM_WD_EN_MASK, 0); 784 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 785 WCD_CLSH_STATE_HPHR, hph_mode); 786 if (wcd938x->ldoh) 787 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 788 WCD938X_LDOH_EN_MASK, 0); 789 break; 790 } 791 792 return 0; 793 } 794 795 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 796 struct snd_kcontrol *kcontrol, int event) 797 { 798 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 799 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 800 int hph_mode = wcd938x->hph_mode; 801 802 switch (event) { 803 case SND_SOC_DAPM_PRE_PMU: 804 if (wcd938x->ldoh) 805 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 806 WCD938X_LDOH_EN_MASK, 1); 807 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 808 WCD_CLSH_STATE_HPHL, hph_mode); 809 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 810 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 811 hph_mode == CLS_H_ULP) { 812 snd_soc_component_write_field(component, 813 WCD938X_HPH_REFBUFF_LP_CTL, 814 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 815 } 816 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 817 WCD938X_HPHL_REF_EN_MASK, 1); 818 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 819 /* 100 usec delay as per HW requirement */ 820 usleep_range(100, 110); 821 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 822 snd_soc_component_write_field(component, 823 WCD938X_DIGITAL_PDM_WD_CTL0, 824 WCD938X_PDM_WD_EN_MASK, 0x3); 825 break; 826 case SND_SOC_DAPM_POST_PMU: 827 /* 828 * 7ms sleep is required if compander is enabled as per 829 * HW requirement. If compander is disabled, then 830 * 20ms delay is required. 831 */ 832 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 833 if (!wcd938x->comp1_enable) 834 usleep_range(20000, 20100); 835 else 836 usleep_range(7000, 7100); 837 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 838 hph_mode == CLS_H_ULP) 839 snd_soc_component_write_field(component, 840 WCD938X_HPH_REFBUFF_LP_CTL, 841 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 842 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 843 } 844 845 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 846 WCD938X_AUTOCHOP_TIMER_EN, 1); 847 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 848 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 849 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 850 WCD938X_REGULATOR_MODE_MASK, 851 WCD938X_REGULATOR_MODE_CLASS_AB); 852 enable_irq(wcd938x->hphl_pdm_wd_int); 853 break; 854 case SND_SOC_DAPM_PRE_PMD: 855 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 856 /* 857 * 7ms sleep is required if compander is enabled as per 858 * HW requirement. If compander is disabled, then 859 * 20ms delay is required. 860 */ 861 if (!wcd938x->comp1_enable) 862 usleep_range(20000, 20100); 863 else 864 usleep_range(7000, 7100); 865 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 866 WCD938X_HPHL_EN_MASK, 0); 867 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 868 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 869 break; 870 case SND_SOC_DAPM_POST_PMD: 871 /* 872 * 7ms sleep is required if compander is enabled as per 873 * HW requirement. If compander is disabled, then 874 * 20ms delay is required. 875 */ 876 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 877 if (!wcd938x->comp1_enable) 878 usleep_range(21000, 21100); 879 else 880 usleep_range(7000, 7100); 881 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 882 } 883 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 884 WCD_EVENT_POST_HPHL_PA_OFF); 885 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 886 WCD938X_HPHL_REF_EN_MASK, 0); 887 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 888 WCD938X_PDM_WD_EN_MASK, 0); 889 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 890 WCD_CLSH_STATE_HPHL, hph_mode); 891 if (wcd938x->ldoh) 892 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 893 WCD938X_LDOH_EN_MASK, 0); 894 break; 895 } 896 897 return 0; 898 } 899 900 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 901 struct snd_kcontrol *kcontrol, int event) 902 { 903 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 904 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 905 int hph_mode = wcd938x->hph_mode; 906 907 switch (event) { 908 case SND_SOC_DAPM_PRE_PMU: 909 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 910 WCD938X_AUX_PDM_WD_EN_MASK, 1); 911 break; 912 case SND_SOC_DAPM_POST_PMU: 913 /* 1 msec delay as per HW requirement */ 914 usleep_range(1000, 1010); 915 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 916 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 917 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 918 WCD938X_REGULATOR_MODE_MASK, 919 WCD938X_REGULATOR_MODE_CLASS_AB); 920 enable_irq(wcd938x->aux_pdm_wd_int); 921 break; 922 case SND_SOC_DAPM_PRE_PMD: 923 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 924 break; 925 case SND_SOC_DAPM_POST_PMD: 926 /* 1 msec delay as per HW requirement */ 927 usleep_range(1000, 1010); 928 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 929 WCD938X_AUX_PDM_WD_EN_MASK, 0); 930 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 931 WCD_CLSH_EVENT_POST_PA, 932 WCD_CLSH_STATE_AUX, 933 hph_mode); 934 935 wcd938x->flyback_cur_det_disable--; 936 if (wcd938x->flyback_cur_det_disable == 0) 937 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 938 WCD938X_EN_CUR_DET_MASK, 1); 939 break; 940 } 941 return 0; 942 } 943 944 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 945 struct snd_kcontrol *kcontrol, int event) 946 { 947 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 948 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 949 int hph_mode = wcd938x->hph_mode; 950 951 switch (event) { 952 case SND_SOC_DAPM_PRE_PMU: 953 /* 954 * Enable watchdog interrupt for HPHL or AUX 955 * depending on mux value 956 */ 957 wcd938x->ear_rx_path = snd_soc_component_read(component, 958 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 959 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 960 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 961 WCD938X_AUX_PDM_WD_EN_MASK, 1); 962 else 963 snd_soc_component_write_field(component, 964 WCD938X_DIGITAL_PDM_WD_CTL0, 965 WCD938X_PDM_WD_EN_MASK, 0x3); 966 if (!wcd938x->comp1_enable) 967 snd_soc_component_write_field(component, 968 WCD938X_ANA_EAR_COMPANDER_CTL, 969 WCD938X_GAIN_OVRD_REG_MASK, 1); 970 971 break; 972 case SND_SOC_DAPM_POST_PMU: 973 /* 6 msec delay as per HW requirement */ 974 usleep_range(6000, 6010); 975 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 976 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 977 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 978 WCD938X_REGULATOR_MODE_MASK, 979 WCD938X_REGULATOR_MODE_CLASS_AB); 980 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 981 enable_irq(wcd938x->aux_pdm_wd_int); 982 else 983 enable_irq(wcd938x->hphl_pdm_wd_int); 984 break; 985 case SND_SOC_DAPM_PRE_PMD: 986 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 987 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 988 else 989 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 990 break; 991 case SND_SOC_DAPM_POST_PMD: 992 if (!wcd938x->comp1_enable) 993 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 994 WCD938X_GAIN_OVRD_REG_MASK, 0); 995 /* 7 msec delay as per HW requirement */ 996 usleep_range(7000, 7010); 997 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 998 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 999 WCD938X_AUX_PDM_WD_EN_MASK, 0); 1000 else 1001 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1002 WCD938X_PDM_WD_EN_MASK, 0); 1003 1004 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1005 WCD_CLSH_STATE_EAR, hph_mode); 1006 1007 wcd938x->flyback_cur_det_disable--; 1008 if (wcd938x->flyback_cur_det_disable == 0) 1009 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1010 WCD938X_EN_CUR_DET_MASK, 1); 1011 break; 1012 } 1013 1014 return 0; 1015 } 1016 1017 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 1018 struct snd_kcontrol *kcontrol, 1019 int event) 1020 { 1021 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1022 u16 dmic_clk_reg, dmic_clk_en_reg; 1023 u8 dmic_sel_mask, dmic_clk_mask; 1024 1025 switch (w->shift) { 1026 case 0: 1027 case 1: 1028 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1029 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 1030 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 1031 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 1032 break; 1033 case 2: 1034 case 3: 1035 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1036 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 1037 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 1038 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 1039 break; 1040 case 4: 1041 case 5: 1042 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1043 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 1044 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 1045 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 1046 break; 1047 case 6: 1048 case 7: 1049 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1050 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 1051 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 1052 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 1053 break; 1054 default: 1055 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 1056 __func__); 1057 return -EINVAL; 1058 } 1059 1060 switch (event) { 1061 case SND_SOC_DAPM_PRE_PMU: 1062 snd_soc_component_write_field(component, 1063 WCD938X_DIGITAL_CDC_AMIC_CTL, 1064 dmic_sel_mask, 1065 WCD938X_AMIC1_IN_SEL_DMIC); 1066 /* 250us sleep as per HW requirement */ 1067 usleep_range(250, 260); 1068 /* Setting DMIC clock rate to 2.4MHz */ 1069 snd_soc_component_write_field(component, dmic_clk_reg, 1070 dmic_clk_mask, 1071 WCD938X_DMIC4_RATE_2P4MHZ); 1072 snd_soc_component_write_field(component, dmic_clk_en_reg, 1073 WCD938X_DMIC_CLK_EN_MASK, 1); 1074 /* enable clock scaling */ 1075 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 1076 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 1077 break; 1078 case SND_SOC_DAPM_POST_PMD: 1079 snd_soc_component_write_field(component, 1080 WCD938X_DIGITAL_CDC_AMIC_CTL, 1081 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 1082 snd_soc_component_write_field(component, dmic_clk_en_reg, 1083 WCD938X_DMIC_CLK_EN_MASK, 0); 1084 break; 1085 } 1086 return 0; 1087 } 1088 1089 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 1090 struct snd_kcontrol *kcontrol, int event) 1091 { 1092 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1093 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1094 int bank; 1095 int rate; 1096 1097 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1; 1098 bank = bank ? 0 : 1; 1099 1100 switch (event) { 1101 case SND_SOC_DAPM_PRE_PMU: 1102 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1103 int i = 0, mode = 0; 1104 1105 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 1106 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 1107 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 1108 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 1109 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 1110 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 1111 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 1112 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 1113 1114 if (mode != 0) { 1115 for (i = 0; i < ADC_MODE_ULP2; i++) { 1116 if (mode & (1 << i)) { 1117 i++; 1118 break; 1119 } 1120 } 1121 } 1122 rate = wcd938x_get_clk_rate(i); 1123 wcd938x_set_swr_clk_rate(component, rate, bank); 1124 /* Copy clk settings to active bank */ 1125 wcd938x_set_swr_clk_rate(component, rate, !bank); 1126 } 1127 break; 1128 case SND_SOC_DAPM_POST_PMD: 1129 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1130 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 1131 wcd938x_set_swr_clk_rate(component, rate, !bank); 1132 wcd938x_set_swr_clk_rate(component, rate, bank); 1133 } 1134 break; 1135 } 1136 1137 return 0; 1138 } 1139 1140 static int wcd938x_get_adc_mode(int val) 1141 { 1142 int ret = 0; 1143 1144 switch (val) { 1145 case ADC_MODE_INVALID: 1146 ret = ADC_MODE_VAL_NORMAL; 1147 break; 1148 case ADC_MODE_HIFI: 1149 ret = ADC_MODE_VAL_HIFI; 1150 break; 1151 case ADC_MODE_LO_HIF: 1152 ret = ADC_MODE_VAL_LO_HIF; 1153 break; 1154 case ADC_MODE_NORMAL: 1155 ret = ADC_MODE_VAL_NORMAL; 1156 break; 1157 case ADC_MODE_LP: 1158 ret = ADC_MODE_VAL_LP; 1159 break; 1160 case ADC_MODE_ULP1: 1161 ret = ADC_MODE_VAL_ULP1; 1162 break; 1163 case ADC_MODE_ULP2: 1164 ret = ADC_MODE_VAL_ULP2; 1165 break; 1166 default: 1167 ret = -EINVAL; 1168 break; 1169 } 1170 return ret; 1171 } 1172 1173 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 1174 struct snd_kcontrol *kcontrol, int event) 1175 { 1176 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1177 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1178 1179 switch (event) { 1180 case SND_SOC_DAPM_PRE_PMU: 1181 snd_soc_component_write_field(component, 1182 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1183 WCD938X_ANA_TX_CLK_EN_MASK, 1); 1184 snd_soc_component_write_field(component, 1185 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1186 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1187 set_bit(w->shift, &wcd938x->status_mask); 1188 break; 1189 case SND_SOC_DAPM_POST_PMD: 1190 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1191 WCD938X_ANA_TX_CLK_EN_MASK, 0); 1192 clear_bit(w->shift, &wcd938x->status_mask); 1193 break; 1194 } 1195 1196 return 0; 1197 } 1198 1199 static void wcd938x_tx_channel_config(struct snd_soc_component *component, 1200 int channel, int mode) 1201 { 1202 int reg, mask; 1203 1204 switch (channel) { 1205 case 0: 1206 reg = WCD938X_ANA_TX_CH2; 1207 mask = WCD938X_HPF1_INIT_MASK; 1208 break; 1209 case 1: 1210 reg = WCD938X_ANA_TX_CH2; 1211 mask = WCD938X_HPF2_INIT_MASK; 1212 break; 1213 case 2: 1214 reg = WCD938X_ANA_TX_CH4; 1215 mask = WCD938X_HPF3_INIT_MASK; 1216 break; 1217 case 3: 1218 reg = WCD938X_ANA_TX_CH4; 1219 mask = WCD938X_HPF4_INIT_MASK; 1220 break; 1221 default: 1222 return; 1223 } 1224 1225 snd_soc_component_write_field(component, reg, mask, mode); 1226 } 1227 1228 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 1229 struct snd_kcontrol *kcontrol, int event) 1230 { 1231 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1232 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1233 int mode; 1234 1235 switch (event) { 1236 case SND_SOC_DAPM_PRE_PMU: 1237 snd_soc_component_write_field(component, 1238 WCD938X_DIGITAL_CDC_REQ_CTL, 1239 WCD938X_FS_RATE_4P8_MASK, 1); 1240 snd_soc_component_write_field(component, 1241 WCD938X_DIGITAL_CDC_REQ_CTL, 1242 WCD938X_NO_NOTCH_MASK, 0); 1243 wcd938x_tx_channel_config(component, w->shift, 1); 1244 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 1245 if (mode < 0) { 1246 dev_info(component->dev, "Invalid ADC mode\n"); 1247 return -EINVAL; 1248 } 1249 switch (w->shift) { 1250 case 0: 1251 snd_soc_component_write_field(component, 1252 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1253 WCD938X_TXD0_MODE_MASK, mode); 1254 snd_soc_component_write_field(component, 1255 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1256 WCD938X_TXD0_CLK_EN_MASK, 1); 1257 break; 1258 case 1: 1259 snd_soc_component_write_field(component, 1260 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1261 WCD938X_TXD1_MODE_MASK, mode); 1262 snd_soc_component_write_field(component, 1263 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1264 WCD938X_TXD1_CLK_EN_MASK, 1); 1265 break; 1266 case 2: 1267 snd_soc_component_write_field(component, 1268 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1269 WCD938X_TXD2_MODE_MASK, mode); 1270 snd_soc_component_write_field(component, 1271 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1272 WCD938X_TXD2_CLK_EN_MASK, 1); 1273 break; 1274 case 3: 1275 snd_soc_component_write_field(component, 1276 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1277 WCD938X_TXD3_MODE_MASK, mode); 1278 snd_soc_component_write_field(component, 1279 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1280 WCD938X_TXD3_CLK_EN_MASK, 1); 1281 break; 1282 default: 1283 break; 1284 } 1285 1286 wcd938x_tx_channel_config(component, w->shift, 0); 1287 break; 1288 case SND_SOC_DAPM_POST_PMD: 1289 switch (w->shift) { 1290 case 0: 1291 snd_soc_component_write_field(component, 1292 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1293 WCD938X_TXD0_MODE_MASK, 0); 1294 snd_soc_component_write_field(component, 1295 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1296 WCD938X_TXD0_CLK_EN_MASK, 0); 1297 break; 1298 case 1: 1299 snd_soc_component_write_field(component, 1300 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1301 WCD938X_TXD1_MODE_MASK, 0); 1302 snd_soc_component_write_field(component, 1303 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1304 WCD938X_TXD1_CLK_EN_MASK, 0); 1305 break; 1306 case 2: 1307 snd_soc_component_write_field(component, 1308 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1309 WCD938X_TXD2_MODE_MASK, 0); 1310 snd_soc_component_write_field(component, 1311 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1312 WCD938X_TXD2_CLK_EN_MASK, 0); 1313 break; 1314 case 3: 1315 snd_soc_component_write_field(component, 1316 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1317 WCD938X_TXD3_MODE_MASK, 0); 1318 snd_soc_component_write_field(component, 1319 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1320 WCD938X_TXD3_CLK_EN_MASK, 0); 1321 break; 1322 default: 1323 break; 1324 } 1325 snd_soc_component_write_field(component, 1326 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1327 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 1328 break; 1329 } 1330 1331 return 0; 1332 } 1333 1334 static int wcd938x_micbias_control(struct snd_soc_component *component, 1335 int micb_num, int req, bool is_dapm) 1336 { 1337 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1338 int micb_index = micb_num - 1; 1339 u16 micb_reg; 1340 1341 switch (micb_num) { 1342 case MIC_BIAS_1: 1343 micb_reg = WCD938X_ANA_MICB1; 1344 break; 1345 case MIC_BIAS_2: 1346 micb_reg = WCD938X_ANA_MICB2; 1347 break; 1348 case MIC_BIAS_3: 1349 micb_reg = WCD938X_ANA_MICB3; 1350 break; 1351 case MIC_BIAS_4: 1352 micb_reg = WCD938X_ANA_MICB4; 1353 break; 1354 default: 1355 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 1356 __func__, micb_num); 1357 return -EINVAL; 1358 } 1359 1360 switch (req) { 1361 case MICB_PULLUP_ENABLE: 1362 wcd938x->pullup_ref[micb_index]++; 1363 if ((wcd938x->pullup_ref[micb_index] == 1) && 1364 (wcd938x->micb_ref[micb_index] == 0)) 1365 snd_soc_component_write_field(component, micb_reg, 1366 WCD938X_MICB_EN_MASK, 1367 WCD938X_MICB_PULL_UP); 1368 break; 1369 case MICB_PULLUP_DISABLE: 1370 if (wcd938x->pullup_ref[micb_index] > 0) 1371 wcd938x->pullup_ref[micb_index]--; 1372 1373 if ((wcd938x->pullup_ref[micb_index] == 0) && 1374 (wcd938x->micb_ref[micb_index] == 0)) 1375 snd_soc_component_write_field(component, micb_reg, 1376 WCD938X_MICB_EN_MASK, 0); 1377 break; 1378 case MICB_ENABLE: 1379 wcd938x->micb_ref[micb_index]++; 1380 if (wcd938x->micb_ref[micb_index] == 1) { 1381 snd_soc_component_write_field(component, 1382 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1383 WCD938X_TX_CLK_EN_MASK, 0xF); 1384 snd_soc_component_write_field(component, 1385 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1386 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1387 snd_soc_component_write_field(component, 1388 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 1389 WCD938X_TX_SC_CLK_EN_MASK, 1); 1390 1391 snd_soc_component_write_field(component, micb_reg, 1392 WCD938X_MICB_EN_MASK, 1393 WCD938X_MICB_ENABLE); 1394 if (micb_num == MIC_BIAS_2) 1395 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1396 WCD_EVENT_POST_MICBIAS_2_ON); 1397 } 1398 if (micb_num == MIC_BIAS_2 && is_dapm) 1399 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1400 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1401 1402 1403 break; 1404 case MICB_DISABLE: 1405 if (wcd938x->micb_ref[micb_index] > 0) 1406 wcd938x->micb_ref[micb_index]--; 1407 1408 if ((wcd938x->micb_ref[micb_index] == 0) && 1409 (wcd938x->pullup_ref[micb_index] > 0)) 1410 snd_soc_component_write_field(component, micb_reg, 1411 WCD938X_MICB_EN_MASK, 1412 WCD938X_MICB_PULL_UP); 1413 else if ((wcd938x->micb_ref[micb_index] == 0) && 1414 (wcd938x->pullup_ref[micb_index] == 0)) { 1415 if (micb_num == MIC_BIAS_2) 1416 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1417 WCD_EVENT_PRE_MICBIAS_2_OFF); 1418 1419 snd_soc_component_write_field(component, micb_reg, 1420 WCD938X_MICB_EN_MASK, 0); 1421 if (micb_num == MIC_BIAS_2) 1422 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1423 WCD_EVENT_POST_MICBIAS_2_OFF); 1424 } 1425 if (is_dapm && micb_num == MIC_BIAS_2) 1426 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1427 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1428 break; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1435 struct snd_kcontrol *kcontrol, 1436 int event) 1437 { 1438 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1439 int micb_num = w->shift; 1440 1441 switch (event) { 1442 case SND_SOC_DAPM_PRE_PMU: 1443 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 1444 break; 1445 case SND_SOC_DAPM_POST_PMU: 1446 /* 1 msec delay as per HW requirement */ 1447 usleep_range(1000, 1100); 1448 break; 1449 case SND_SOC_DAPM_POST_PMD: 1450 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 1451 break; 1452 } 1453 1454 return 0; 1455 } 1456 1457 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1458 struct snd_kcontrol *kcontrol, 1459 int event) 1460 { 1461 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1462 int micb_num = w->shift; 1463 1464 switch (event) { 1465 case SND_SOC_DAPM_PRE_PMU: 1466 wcd938x_micbias_control(component, micb_num, 1467 MICB_PULLUP_ENABLE, true); 1468 break; 1469 case SND_SOC_DAPM_POST_PMU: 1470 /* 1 msec delay as per HW requirement */ 1471 usleep_range(1000, 1100); 1472 break; 1473 case SND_SOC_DAPM_POST_PMD: 1474 wcd938x_micbias_control(component, micb_num, 1475 MICB_PULLUP_DISABLE, true); 1476 break; 1477 } 1478 1479 return 0; 1480 } 1481 1482 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 1483 struct snd_ctl_elem_value *ucontrol) 1484 { 1485 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1486 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1487 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1488 int path = e->shift_l; 1489 1490 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path]; 1491 1492 return 0; 1493 } 1494 1495 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 1496 struct snd_ctl_elem_value *ucontrol) 1497 { 1498 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1499 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1500 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1501 int path = e->shift_l; 1502 1503 if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0]) 1504 return 0; 1505 1506 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 1507 1508 return 1; 1509 } 1510 1511 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1512 struct snd_ctl_elem_value *ucontrol) 1513 { 1514 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1515 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1516 1517 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode; 1518 1519 return 0; 1520 } 1521 1522 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1523 struct snd_ctl_elem_value *ucontrol) 1524 { 1525 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1526 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1527 1528 if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0]) 1529 return 0; 1530 1531 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 1532 1533 return 1; 1534 } 1535 1536 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 1537 struct snd_ctl_elem_value *ucontrol) 1538 { 1539 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1540 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1541 1542 if (wcd938x->comp1_enable) { 1543 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 1544 return -EINVAL; 1545 } 1546 1547 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1548 WCD938X_EAR_GAIN_MASK, 1549 ucontrol->value.integer.value[0]); 1550 1551 return 1; 1552 } 1553 1554 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 1555 struct snd_ctl_elem_value *ucontrol) 1556 { 1557 1558 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1559 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1560 struct soc_mixer_control *mc; 1561 bool hphr; 1562 1563 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1564 hphr = mc->shift; 1565 1566 if (hphr) 1567 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 1568 else 1569 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 1570 1571 return 0; 1572 } 1573 1574 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 1575 struct snd_ctl_elem_value *ucontrol) 1576 { 1577 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1578 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1579 struct wcd938x_sdw_priv *wcd; 1580 int value = ucontrol->value.integer.value[0]; 1581 int portidx; 1582 struct soc_mixer_control *mc; 1583 bool hphr; 1584 1585 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1586 hphr = mc->shift; 1587 1588 wcd = wcd938x->sdw_priv[AIF1_PB]; 1589 1590 if (hphr) 1591 wcd938x->comp2_enable = value; 1592 else 1593 wcd938x->comp1_enable = value; 1594 1595 portidx = wcd->ch_info[mc->reg].port_num; 1596 1597 if (value) 1598 wcd938x_connect_port(wcd, portidx, mc->reg, true); 1599 else 1600 wcd938x_connect_port(wcd, portidx, mc->reg, false); 1601 1602 return 1; 1603 } 1604 1605 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 1606 struct snd_ctl_elem_value *ucontrol) 1607 { 1608 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1609 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1610 1611 ucontrol->value.integer.value[0] = wcd938x->ldoh; 1612 1613 return 0; 1614 } 1615 1616 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 1617 struct snd_ctl_elem_value *ucontrol) 1618 { 1619 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1620 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1621 1622 if (wcd938x->ldoh == ucontrol->value.integer.value[0]) 1623 return 0; 1624 1625 wcd938x->ldoh = ucontrol->value.integer.value[0]; 1626 1627 return 1; 1628 } 1629 1630 static const char * const tx_mode_mux_text_wcd9380[] = { 1631 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1632 }; 1633 1634 static const char * const tx_mode_mux_text[] = { 1635 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1636 "ADC_ULP1", "ADC_ULP2", 1637 }; 1638 1639 static const char * const rx_hph_mode_mux_text_wcd9380[] = { 1640 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 1641 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 1642 "CLS_AB_LOHIFI", 1643 }; 1644 1645 static const char * const rx_hph_mode_mux_text[] = { 1646 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 1647 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 1648 }; 1649 1650 static const char * const adc2_mux_text[] = { 1651 "INP2", "INP3" 1652 }; 1653 1654 static const char * const adc3_mux_text[] = { 1655 "INP4", "INP6" 1656 }; 1657 1658 static const char * const adc4_mux_text[] = { 1659 "INP5", "INP7" 1660 }; 1661 1662 static const char * const rdac3_mux_text[] = { 1663 "RX1", "RX3" 1664 }; 1665 1666 static const char * const hdr12_mux_text[] = { 1667 "NO_HDR12", "HDR12" 1668 }; 1669 1670 static const char * const hdr34_mux_text[] = { 1671 "NO_HDR34", "HDR34" 1672 }; 1673 1674 static const struct soc_enum tx0_mode_enum_wcd9380 = 1675 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1676 tx_mode_mux_text_wcd9380); 1677 1678 static const struct soc_enum tx1_mode_enum_wcd9380 = 1679 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1680 tx_mode_mux_text_wcd9380); 1681 1682 static const struct soc_enum tx2_mode_enum_wcd9380 = 1683 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1684 tx_mode_mux_text_wcd9380); 1685 1686 static const struct soc_enum tx3_mode_enum_wcd9380 = 1687 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1688 tx_mode_mux_text_wcd9380); 1689 1690 static const struct soc_enum tx0_mode_enum_wcd9385 = 1691 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 1692 tx_mode_mux_text); 1693 1694 static const struct soc_enum tx1_mode_enum_wcd9385 = 1695 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 1696 tx_mode_mux_text); 1697 1698 static const struct soc_enum tx2_mode_enum_wcd9385 = 1699 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 1700 tx_mode_mux_text); 1701 1702 static const struct soc_enum tx3_mode_enum_wcd9385 = 1703 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 1704 tx_mode_mux_text); 1705 1706 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 1707 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 1708 rx_hph_mode_mux_text_wcd9380); 1709 1710 static const struct soc_enum rx_hph_mode_mux_enum = 1711 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 1712 rx_hph_mode_mux_text); 1713 1714 static const struct soc_enum adc2_enum = 1715 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 1716 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 1717 1718 static const struct soc_enum adc3_enum = 1719 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 1720 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 1721 1722 static const struct soc_enum adc4_enum = 1723 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 1724 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 1725 1726 static const struct soc_enum hdr12_enum = 1727 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 1728 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 1729 1730 static const struct soc_enum hdr34_enum = 1731 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 1732 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 1733 1734 static const struct soc_enum rdac3_enum = 1735 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 1736 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 1737 1738 static const struct snd_kcontrol_new adc1_switch[] = { 1739 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1740 }; 1741 1742 static const struct snd_kcontrol_new adc2_switch[] = { 1743 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1744 }; 1745 1746 static const struct snd_kcontrol_new adc3_switch[] = { 1747 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1748 }; 1749 1750 static const struct snd_kcontrol_new adc4_switch[] = { 1751 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1752 }; 1753 1754 static const struct snd_kcontrol_new dmic1_switch[] = { 1755 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1756 }; 1757 1758 static const struct snd_kcontrol_new dmic2_switch[] = { 1759 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1760 }; 1761 1762 static const struct snd_kcontrol_new dmic3_switch[] = { 1763 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1764 }; 1765 1766 static const struct snd_kcontrol_new dmic4_switch[] = { 1767 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1768 }; 1769 1770 static const struct snd_kcontrol_new dmic5_switch[] = { 1771 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1772 }; 1773 1774 static const struct snd_kcontrol_new dmic6_switch[] = { 1775 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1776 }; 1777 1778 static const struct snd_kcontrol_new dmic7_switch[] = { 1779 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1780 }; 1781 1782 static const struct snd_kcontrol_new dmic8_switch[] = { 1783 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1784 }; 1785 1786 static const struct snd_kcontrol_new ear_rdac_switch[] = { 1787 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1788 }; 1789 1790 static const struct snd_kcontrol_new aux_rdac_switch[] = { 1791 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1792 }; 1793 1794 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 1795 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1796 }; 1797 1798 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 1799 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1800 }; 1801 1802 static const struct snd_kcontrol_new tx_adc2_mux = 1803 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 1804 1805 static const struct snd_kcontrol_new tx_adc3_mux = 1806 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 1807 1808 static const struct snd_kcontrol_new tx_adc4_mux = 1809 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 1810 1811 static const struct snd_kcontrol_new tx_hdr12_mux = 1812 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 1813 1814 static const struct snd_kcontrol_new tx_hdr34_mux = 1815 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 1816 1817 static const struct snd_kcontrol_new rx_rdac3_mux = 1818 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 1819 1820 static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 1821 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 1822 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1823 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 1824 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1825 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 1826 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1827 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 1828 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1829 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 1830 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1831 }; 1832 1833 static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 1834 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 1835 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1836 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 1837 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1838 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 1839 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1840 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 1841 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1842 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 1843 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1844 }; 1845 1846 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 1847 struct snd_ctl_elem_value *ucontrol) 1848 { 1849 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1850 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1851 struct wcd938x_sdw_priv *wcd; 1852 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1853 int dai_id = mixer->shift; 1854 int portidx, ch_idx = mixer->reg; 1855 1856 1857 wcd = wcd938x->sdw_priv[dai_id]; 1858 portidx = wcd->ch_info[ch_idx].port_num; 1859 1860 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1861 1862 return 0; 1863 } 1864 1865 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 1866 struct snd_ctl_elem_value *ucontrol) 1867 { 1868 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1869 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1870 struct wcd938x_sdw_priv *wcd; 1871 struct soc_mixer_control *mixer = 1872 (struct soc_mixer_control *)kcontrol->private_value; 1873 int ch_idx = mixer->reg; 1874 int portidx; 1875 int dai_id = mixer->shift; 1876 bool enable; 1877 1878 wcd = wcd938x->sdw_priv[dai_id]; 1879 1880 portidx = wcd->ch_info[ch_idx].port_num; 1881 if (ucontrol->value.integer.value[0]) 1882 enable = true; 1883 else 1884 enable = false; 1885 1886 wcd->port_enable[portidx] = enable; 1887 1888 wcd938x_connect_port(wcd, portidx, ch_idx, enable); 1889 1890 return 1; 1891 1892 } 1893 1894 /* MBHC related */ 1895 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 1896 bool enable) 1897 { 1898 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 1899 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 1900 } 1901 1902 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1903 bool enable) 1904 { 1905 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 1906 WCD938X_ANA_MBHC_BIAS_EN, enable); 1907 } 1908 1909 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 1910 int *btn_low, int *btn_high, 1911 int num_btn, bool is_micbias) 1912 { 1913 int i, vth; 1914 1915 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1916 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1917 __func__, num_btn); 1918 return; 1919 } 1920 1921 for (i = 0; i < num_btn; i++) { 1922 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1923 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 1924 WCD938X_MBHC_BTN_VTH_MASK, vth); 1925 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 1926 __func__, i, btn_high[i], vth); 1927 } 1928 } 1929 1930 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1931 { 1932 u8 val; 1933 1934 if (micb_num == MIC_BIAS_2) { 1935 val = snd_soc_component_read_field(component, 1936 WCD938X_ANA_MICB2, 1937 WCD938X_MICB_EN_MASK); 1938 if (val == WCD938X_MICB_ENABLE) 1939 return true; 1940 } 1941 return false; 1942 } 1943 1944 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1945 int pull_up_cur) 1946 { 1947 /* Default pull up current to 2uA */ 1948 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1949 pull_up_cur = HS_PULLUP_I_2P0_UA; 1950 1951 snd_soc_component_write_field(component, 1952 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 1953 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 1954 } 1955 1956 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 1957 int micb_num, int req) 1958 { 1959 return wcd938x_micbias_control(component, micb_num, req, false); 1960 } 1961 1962 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1963 bool enable) 1964 { 1965 if (enable) { 1966 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1967 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1968 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1969 WCD938X_RAMP_EN_MASK, 1); 1970 } else { 1971 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1972 WCD938X_RAMP_EN_MASK, 0); 1973 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1974 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 1975 } 1976 } 1977 1978 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv) 1979 { 1980 /* min micbias voltage is 1V and maximum is 2.85V */ 1981 if (micb_mv < 1000 || micb_mv > 2850) 1982 return -EINVAL; 1983 1984 return (micb_mv - 1000) / 50; 1985 } 1986 1987 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1988 int req_volt, int micb_num) 1989 { 1990 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1991 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1992 1993 switch (micb_num) { 1994 case MIC_BIAS_1: 1995 micb_reg = WCD938X_ANA_MICB1; 1996 break; 1997 case MIC_BIAS_2: 1998 micb_reg = WCD938X_ANA_MICB2; 1999 break; 2000 case MIC_BIAS_3: 2001 micb_reg = WCD938X_ANA_MICB3; 2002 break; 2003 case MIC_BIAS_4: 2004 micb_reg = WCD938X_ANA_MICB4; 2005 break; 2006 default: 2007 return -EINVAL; 2008 } 2009 mutex_lock(&wcd938x->micb_lock); 2010 /* 2011 * If requested micbias voltage is same as current micbias 2012 * voltage, then just return. Otherwise, adjust voltage as 2013 * per requested value. If micbias is already enabled, then 2014 * to avoid slow micbias ramp-up or down enable pull-up 2015 * momentarily, change the micbias value and then re-enable 2016 * micbias. 2017 */ 2018 micb_en = snd_soc_component_read_field(component, micb_reg, 2019 WCD938X_MICB_EN_MASK); 2020 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2021 WCD938X_MICB_VOUT_MASK); 2022 2023 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt); 2024 if (req_vout_ctl < 0) { 2025 ret = -EINVAL; 2026 goto exit; 2027 } 2028 2029 if (cur_vout_ctl == req_vout_ctl) { 2030 ret = 0; 2031 goto exit; 2032 } 2033 2034 if (micb_en == WCD938X_MICB_ENABLE) 2035 snd_soc_component_write_field(component, micb_reg, 2036 WCD938X_MICB_EN_MASK, 2037 WCD938X_MICB_PULL_UP); 2038 2039 snd_soc_component_write_field(component, micb_reg, 2040 WCD938X_MICB_VOUT_MASK, 2041 req_vout_ctl); 2042 2043 if (micb_en == WCD938X_MICB_ENABLE) { 2044 snd_soc_component_write_field(component, micb_reg, 2045 WCD938X_MICB_EN_MASK, 2046 WCD938X_MICB_ENABLE); 2047 /* 2048 * Add 2ms delay as per HW requirement after enabling 2049 * micbias 2050 */ 2051 usleep_range(2000, 2100); 2052 } 2053 exit: 2054 mutex_unlock(&wcd938x->micb_lock); 2055 return ret; 2056 } 2057 2058 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2059 int micb_num, bool req_en) 2060 { 2061 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2062 int micb_mv; 2063 2064 if (micb_num != MIC_BIAS_2) 2065 return -EINVAL; 2066 /* 2067 * If device tree micbias level is already above the minimum 2068 * voltage needed to detect threshold microphone, then do 2069 * not change the micbias, just return. 2070 */ 2071 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2072 return 0; 2073 2074 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv; 2075 2076 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2077 } 2078 2079 static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component, 2080 s16 *d1_a, u16 noff, 2081 int32_t *zdet) 2082 { 2083 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2084 int i; 2085 int val, val1; 2086 s16 c1; 2087 s32 x1, d1; 2088 int32_t denom; 2089 static const int minCode_param[] = { 2090 3277, 1639, 820, 410, 205, 103, 52, 26 2091 }; 2092 2093 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 2094 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 2095 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 2096 if (val & 0x80) 2097 break; 2098 } 2099 val = val << 0x8; 2100 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 2101 val |= val1; 2102 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 2103 x1 = WCD938X_MBHC_GET_X1(val); 2104 c1 = WCD938X_MBHC_GET_C1(val); 2105 /* If ramp is not complete, give additional 5ms */ 2106 if ((c1 < 2) && x1) 2107 usleep_range(5000, 5050); 2108 2109 if (!c1 || !x1) { 2110 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 2111 c1, x1); 2112 goto ramp_down; 2113 } 2114 d1 = d1_a[c1]; 2115 denom = (x1 * d1) - (1 << (14 - noff)); 2116 if (denom > 0) 2117 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 2118 else if (x1 < minCode_param[noff]) 2119 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 2120 2121 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 2122 __func__, d1, c1, x1, *zdet); 2123 ramp_down: 2124 i = 0; 2125 while (x1) { 2126 regmap_read(wcd938x->regmap, 2127 WCD938X_ANA_MBHC_RESULT_1, &val); 2128 regmap_read(wcd938x->regmap, 2129 WCD938X_ANA_MBHC_RESULT_2, &val1); 2130 val = val << 0x08; 2131 val |= val1; 2132 x1 = WCD938X_MBHC_GET_X1(val); 2133 i++; 2134 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 2135 break; 2136 } 2137 } 2138 2139 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 2140 struct wcd938x_mbhc_zdet_param *zdet_param, 2141 int32_t *zl, int32_t *zr, s16 *d1_a) 2142 { 2143 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2144 int32_t zdet = 0; 2145 2146 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2147 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2148 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 2149 WCD938X_VTH_MASK, zdet_param->btn5); 2150 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 2151 WCD938X_VTH_MASK, zdet_param->btn6); 2152 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 2153 WCD938X_VTH_MASK, zdet_param->btn7); 2154 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2155 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2156 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 2157 0x0F, zdet_param->nshift); 2158 2159 if (!zl) 2160 goto z_right; 2161 /* Start impedance measurement for HPH_L */ 2162 regmap_update_bits(wcd938x->regmap, 2163 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 2164 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2165 __func__, zdet_param->noff); 2166 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2167 regmap_update_bits(wcd938x->regmap, 2168 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 2169 2170 *zl = zdet; 2171 2172 z_right: 2173 if (!zr) 2174 return; 2175 /* Start impedance measurement for HPH_R */ 2176 regmap_update_bits(wcd938x->regmap, 2177 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 2178 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2179 __func__, zdet_param->noff); 2180 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2181 regmap_update_bits(wcd938x->regmap, 2182 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 2183 2184 *zr = zdet; 2185 } 2186 2187 static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2188 int32_t *z_val, int flag_l_r) 2189 { 2190 s16 q1; 2191 int q1_cal; 2192 2193 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 2194 q1 = snd_soc_component_read(component, 2195 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 2196 else 2197 q1 = snd_soc_component_read(component, 2198 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 2199 if (q1 & 0x80) 2200 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2201 else 2202 q1_cal = (10000 + (q1 * 25)); 2203 if (q1_cal > 0) 2204 *z_val = ((*z_val) * 10000) / q1_cal; 2205 } 2206 2207 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2208 uint32_t *zl, uint32_t *zr) 2209 { 2210 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2211 s16 reg0, reg1, reg2, reg3, reg4; 2212 int32_t z1L, z1R, z1Ls; 2213 int zMono, z_diff1, z_diff2; 2214 bool is_fsm_disable = false; 2215 struct wcd938x_mbhc_zdet_param zdet_param[] = { 2216 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2217 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2218 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2219 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2220 }; 2221 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 2222 s16 d1_a[][4] = { 2223 {0, 30, 90, 30}, 2224 {0, 30, 30, 5}, 2225 {0, 30, 30, 5}, 2226 {0, 30, 30, 5}, 2227 }; 2228 s16 *d1 = NULL; 2229 2230 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 2231 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 2232 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 2233 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 2234 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 2235 2236 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 2237 is_fsm_disable = true; 2238 regmap_update_bits(wcd938x->regmap, 2239 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 2240 } 2241 2242 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2243 if (wcd938x->mbhc_cfg.hphl_swh) 2244 regmap_update_bits(wcd938x->regmap, 2245 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 2246 2247 /* Turn off 100k pull down on HPHL */ 2248 regmap_update_bits(wcd938x->regmap, 2249 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 2250 2251 /* Disable surge protection before impedance detection. 2252 * This is done to give correct value for high impedance. 2253 */ 2254 regmap_update_bits(wcd938x->regmap, 2255 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 2256 /* 1ms delay needed after disable surge protection */ 2257 usleep_range(1000, 1010); 2258 2259 /* First get impedance on Left */ 2260 d1 = d1_a[1]; 2261 zdet_param_ptr = &zdet_param[1]; 2262 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2263 2264 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2265 goto left_ch_impedance; 2266 2267 /* Second ramp for left ch */ 2268 if (z1L < WCD938X_ZDET_VAL_32) { 2269 zdet_param_ptr = &zdet_param[0]; 2270 d1 = d1_a[0]; 2271 } else if ((z1L > WCD938X_ZDET_VAL_400) && 2272 (z1L <= WCD938X_ZDET_VAL_1200)) { 2273 zdet_param_ptr = &zdet_param[2]; 2274 d1 = d1_a[2]; 2275 } else if (z1L > WCD938X_ZDET_VAL_1200) { 2276 zdet_param_ptr = &zdet_param[3]; 2277 d1 = d1_a[3]; 2278 } 2279 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2280 2281 left_ch_impedance: 2282 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2283 (z1L > WCD938X_ZDET_VAL_100K)) { 2284 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 2285 zdet_param_ptr = &zdet_param[1]; 2286 d1 = d1_a[1]; 2287 } else { 2288 *zl = z1L/1000; 2289 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 2290 } 2291 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2292 __func__, *zl); 2293 2294 /* Start of right impedance ramp and calculation */ 2295 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2296 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2297 if (((z1R > WCD938X_ZDET_VAL_1200) && 2298 (zdet_param_ptr->noff == 0x6)) || 2299 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 2300 goto right_ch_impedance; 2301 /* Second ramp for right ch */ 2302 if (z1R < WCD938X_ZDET_VAL_32) { 2303 zdet_param_ptr = &zdet_param[0]; 2304 d1 = d1_a[0]; 2305 } else if ((z1R > WCD938X_ZDET_VAL_400) && 2306 (z1R <= WCD938X_ZDET_VAL_1200)) { 2307 zdet_param_ptr = &zdet_param[2]; 2308 d1 = d1_a[2]; 2309 } else if (z1R > WCD938X_ZDET_VAL_1200) { 2310 zdet_param_ptr = &zdet_param[3]; 2311 d1 = d1_a[3]; 2312 } 2313 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2314 } 2315 right_ch_impedance: 2316 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2317 (z1R > WCD938X_ZDET_VAL_100K)) { 2318 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 2319 } else { 2320 *zr = z1R/1000; 2321 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 2322 } 2323 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2324 __func__, *zr); 2325 2326 /* Mono/stereo detection */ 2327 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 2328 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 2329 dev_dbg(component->dev, 2330 "%s: plug type is invalid or extension cable\n", 2331 __func__); 2332 goto zdet_complete; 2333 } 2334 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2335 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2336 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2337 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2338 dev_dbg(component->dev, 2339 "%s: Mono plug type with one ch floating or shorted to GND\n", 2340 __func__); 2341 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2342 goto zdet_complete; 2343 } 2344 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2345 WCD938X_HPHPA_GND_OVR_MASK, 1); 2346 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2347 WCD938X_HPHPA_GND_R_MASK, 1); 2348 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 2349 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2350 else 2351 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2352 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2353 WCD938X_HPHPA_GND_R_MASK, 0); 2354 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2355 WCD938X_HPHPA_GND_OVR_MASK, 0); 2356 z1Ls /= 1000; 2357 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2358 /* Parallel of left Z and 9 ohm pull down resistor */ 2359 zMono = ((*zl) * 9) / ((*zl) + 9); 2360 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2361 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2362 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2363 dev_dbg(component->dev, "%s: stereo plug type detected\n", 2364 __func__); 2365 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 2366 } else { 2367 dev_dbg(component->dev, "%s: MONO plug type detected\n", 2368 __func__); 2369 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2370 } 2371 2372 /* Enable surge protection again after impedance detection */ 2373 regmap_update_bits(wcd938x->regmap, 2374 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 2375 zdet_complete: 2376 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 2377 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 2378 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 2379 /* Turn on 100k pull down on HPHL */ 2380 regmap_update_bits(wcd938x->regmap, 2381 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 2382 2383 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2384 if (wcd938x->mbhc_cfg.hphl_swh) 2385 regmap_update_bits(wcd938x->regmap, 2386 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 2387 2388 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2389 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 2390 if (is_fsm_disable) 2391 regmap_update_bits(wcd938x->regmap, 2392 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 2393 } 2394 2395 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2396 bool enable) 2397 { 2398 if (enable) { 2399 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2400 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 2401 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2402 WCD938X_MBHC_GND_DET_EN_MASK, 1); 2403 } else { 2404 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2405 WCD938X_MBHC_GND_DET_EN_MASK, 0); 2406 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2407 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 2408 } 2409 } 2410 2411 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2412 bool enable) 2413 { 2414 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2415 WCD938X_HPHPA_GND_R_MASK, enable); 2416 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2417 WCD938X_HPHPA_GND_L_MASK, enable); 2418 } 2419 2420 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 2421 { 2422 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2423 2424 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2425 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2426 WCD938X_M_RTH_CTL_MASK, R_OFF); 2427 return; 2428 } 2429 2430 /* Do not enable moisture detection if jack type is NC */ 2431 if (!wcd938x->mbhc_cfg.hphl_swh) { 2432 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2433 __func__); 2434 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2435 WCD938X_M_RTH_CTL_MASK, R_OFF); 2436 return; 2437 } 2438 2439 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2440 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2441 } 2442 2443 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 2444 { 2445 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2446 2447 if (enable) 2448 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2449 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2450 else 2451 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2452 WCD938X_M_RTH_CTL_MASK, R_OFF); 2453 } 2454 2455 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 2456 { 2457 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2458 bool ret = false; 2459 2460 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2461 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2462 WCD938X_M_RTH_CTL_MASK, R_OFF); 2463 goto done; 2464 } 2465 2466 /* Do not enable moisture detection if jack type is NC */ 2467 if (!wcd938x->mbhc_cfg.hphl_swh) { 2468 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2469 __func__); 2470 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2471 WCD938X_M_RTH_CTL_MASK, R_OFF); 2472 goto done; 2473 } 2474 2475 /* 2476 * If moisture_en is already enabled, then skip to plug type 2477 * detection. 2478 */ 2479 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 2480 goto done; 2481 2482 wcd938x_mbhc_moisture_detect_en(component, true); 2483 /* Read moisture comparator status */ 2484 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 2485 & 0x20) ? 0 : 1); 2486 2487 done: 2488 return ret; 2489 2490 } 2491 2492 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 2493 bool enable) 2494 { 2495 snd_soc_component_write_field(component, 2496 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 2497 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 2498 } 2499 2500 static const struct wcd_mbhc_cb mbhc_cb = { 2501 .clk_setup = wcd938x_mbhc_clk_setup, 2502 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 2503 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 2504 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 2505 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 2506 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 2507 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 2508 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 2509 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 2510 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 2511 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 2512 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 2513 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 2514 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 2515 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 2516 }; 2517 2518 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 2519 struct snd_ctl_elem_value *ucontrol) 2520 { 2521 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2522 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2523 2524 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 2525 2526 return 0; 2527 } 2528 2529 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2530 struct snd_ctl_elem_value *ucontrol) 2531 { 2532 uint32_t zl, zr; 2533 bool hphr; 2534 struct soc_mixer_control *mc; 2535 struct snd_soc_component *component = 2536 snd_soc_kcontrol_component(kcontrol); 2537 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2538 2539 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2540 hphr = mc->shift; 2541 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 2542 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2543 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2544 2545 return 0; 2546 } 2547 2548 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2549 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2550 wcd938x_get_hph_type, NULL), 2551 }; 2552 2553 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2554 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2555 wcd938x_hph_impedance_get, NULL), 2556 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2557 wcd938x_hph_impedance_get, NULL), 2558 }; 2559 2560 static int wcd938x_mbhc_init(struct snd_soc_component *component) 2561 { 2562 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2563 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 2564 2565 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2566 WCD938X_IRQ_MBHC_SW_DET); 2567 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2568 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 2569 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2570 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 2571 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2572 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2573 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2574 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 2575 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2576 WCD938X_IRQ_HPHL_OCP_INT); 2577 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2578 WCD938X_IRQ_HPHR_OCP_INT); 2579 2580 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2581 if (IS_ERR(wcd938x->wcd_mbhc)) 2582 return PTR_ERR(wcd938x->wcd_mbhc); 2583 2584 snd_soc_add_component_controls(component, impedance_detect_controls, 2585 ARRAY_SIZE(impedance_detect_controls)); 2586 snd_soc_add_component_controls(component, hph_type_detect_controls, 2587 ARRAY_SIZE(hph_type_detect_controls)); 2588 2589 return 0; 2590 } 2591 2592 static void wcd938x_mbhc_deinit(struct snd_soc_component *component) 2593 { 2594 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2595 2596 wcd_mbhc_deinit(wcd938x->wcd_mbhc); 2597 } 2598 2599 /* END MBHC */ 2600 2601 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 2602 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 2603 wcd938x_get_compander, wcd938x_set_compander), 2604 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 2605 wcd938x_get_compander, wcd938x_set_compander), 2606 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 2607 wcd938x_get_swr_port, wcd938x_set_swr_port), 2608 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 2609 wcd938x_get_swr_port, wcd938x_set_swr_port), 2610 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 2611 wcd938x_get_swr_port, wcd938x_set_swr_port), 2612 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 2613 wcd938x_get_swr_port, wcd938x_set_swr_port), 2614 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 2615 wcd938x_get_swr_port, wcd938x_set_swr_port), 2616 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 2617 wcd938x_get_swr_port, wcd938x_set_swr_port), 2618 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain), 2619 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain), 2620 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 2621 2, 0x10, 0, ear_pa_gain), 2622 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 2623 wcd938x_get_swr_port, wcd938x_set_swr_port), 2624 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 2625 wcd938x_get_swr_port, wcd938x_set_swr_port), 2626 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 2627 wcd938x_get_swr_port, wcd938x_set_swr_port), 2628 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 2629 wcd938x_get_swr_port, wcd938x_set_swr_port), 2630 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 2631 wcd938x_get_swr_port, wcd938x_set_swr_port), 2632 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 2633 wcd938x_get_swr_port, wcd938x_set_swr_port), 2634 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 2635 wcd938x_get_swr_port, wcd938x_set_swr_port), 2636 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 2637 wcd938x_get_swr_port, wcd938x_set_swr_port), 2638 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 2639 wcd938x_get_swr_port, wcd938x_set_swr_port), 2640 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 2641 wcd938x_get_swr_port, wcd938x_set_swr_port), 2642 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 2643 wcd938x_get_swr_port, wcd938x_set_swr_port), 2644 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 2645 wcd938x_get_swr_port, wcd938x_set_swr_port), 2646 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 2647 wcd938x_get_swr_port, wcd938x_set_swr_port), 2648 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 2649 wcd938x_ldoh_get, wcd938x_ldoh_put), 2650 2651 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2652 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2653 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2654 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 2655 }; 2656 2657 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 2658 2659 /*input widgets*/ 2660 SND_SOC_DAPM_INPUT("AMIC1"), 2661 SND_SOC_DAPM_INPUT("AMIC2"), 2662 SND_SOC_DAPM_INPUT("AMIC3"), 2663 SND_SOC_DAPM_INPUT("AMIC4"), 2664 SND_SOC_DAPM_INPUT("AMIC5"), 2665 SND_SOC_DAPM_INPUT("AMIC6"), 2666 SND_SOC_DAPM_INPUT("AMIC7"), 2667 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 2668 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 2669 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 2670 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 2671 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 2672 2673 /*tx widgets*/ 2674 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2675 wcd938x_codec_enable_adc, 2676 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2677 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2678 wcd938x_codec_enable_adc, 2679 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2680 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2681 wcd938x_codec_enable_adc, 2682 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2683 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 2684 wcd938x_codec_enable_adc, 2685 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2686 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2687 wcd938x_codec_enable_dmic, 2688 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2689 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2690 wcd938x_codec_enable_dmic, 2691 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2692 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2693 wcd938x_codec_enable_dmic, 2694 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2695 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2696 wcd938x_codec_enable_dmic, 2697 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2698 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2699 wcd938x_codec_enable_dmic, 2700 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2701 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2702 wcd938x_codec_enable_dmic, 2703 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2704 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 2705 wcd938x_codec_enable_dmic, 2706 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2707 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 2708 wcd938x_codec_enable_dmic, 2709 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2710 2711 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2712 NULL, 0, wcd938x_adc_enable_req, 2713 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2714 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 2715 NULL, 0, wcd938x_adc_enable_req, 2716 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2717 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 2718 NULL, 0, wcd938x_adc_enable_req, 2719 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2720 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 2721 wcd938x_adc_enable_req, 2722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2723 2724 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2725 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 2726 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 2727 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 2728 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 2729 2730 /*tx mixers*/ 2731 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 2732 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 2733 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2734 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 2735 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 2736 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2737 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 2738 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 2739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2740 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 2741 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 2742 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2743 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 2744 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 2745 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2746 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 2747 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 2748 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2749 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 2750 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 2751 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2752 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 2753 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 2754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2755 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 2756 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 2757 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2758 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 2759 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 2760 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2761 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 2762 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 2763 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2764 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 2765 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 2766 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2767 /* micbias widgets*/ 2768 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2769 wcd938x_codec_enable_micbias, 2770 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2771 SND_SOC_DAPM_POST_PMD), 2772 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2773 wcd938x_codec_enable_micbias, 2774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2775 SND_SOC_DAPM_POST_PMD), 2776 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2777 wcd938x_codec_enable_micbias, 2778 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2779 SND_SOC_DAPM_POST_PMD), 2780 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2781 wcd938x_codec_enable_micbias, 2782 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2783 SND_SOC_DAPM_POST_PMD), 2784 2785 /* micbias pull up widgets*/ 2786 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2787 wcd938x_codec_enable_micbias_pullup, 2788 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2789 SND_SOC_DAPM_POST_PMD), 2790 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2791 wcd938x_codec_enable_micbias_pullup, 2792 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2793 SND_SOC_DAPM_POST_PMD), 2794 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2795 wcd938x_codec_enable_micbias_pullup, 2796 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2797 SND_SOC_DAPM_POST_PMD), 2798 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2799 wcd938x_codec_enable_micbias_pullup, 2800 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2801 SND_SOC_DAPM_POST_PMD), 2802 2803 /*output widgets tx*/ 2804 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2805 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2806 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2807 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 2808 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2809 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2810 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2811 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2812 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2813 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2814 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 2815 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 2816 2817 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2818 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2819 SND_SOC_DAPM_INPUT("IN3_AUX"), 2820 2821 /*rx widgets*/ 2822 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 2823 wcd938x_codec_enable_ear_pa, 2824 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2825 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2826 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 2827 wcd938x_codec_enable_aux_pa, 2828 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2829 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2830 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 2831 wcd938x_codec_enable_hphl_pa, 2832 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2833 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2834 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 2835 wcd938x_codec_enable_hphr_pa, 2836 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2837 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2838 2839 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2840 wcd938x_codec_hphl_dac_event, 2841 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2842 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2843 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2844 wcd938x_codec_hphr_dac_event, 2845 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2846 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2847 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2848 wcd938x_codec_ear_dac_event, 2849 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2850 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2851 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2852 wcd938x_codec_aux_dac_event, 2853 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2854 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2855 2856 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2857 2858 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2859 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 2860 wcd938x_codec_enable_rxclk, 2861 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2862 SND_SOC_DAPM_POST_PMD), 2863 2864 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2865 2866 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2867 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2868 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2869 2870 /* rx mixer widgets*/ 2871 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2872 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2873 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2874 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2875 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2876 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2877 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2878 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2879 2880 /*output widgets rx*/ 2881 SND_SOC_DAPM_OUTPUT("EAR"), 2882 SND_SOC_DAPM_OUTPUT("AUX"), 2883 SND_SOC_DAPM_OUTPUT("HPHL"), 2884 SND_SOC_DAPM_OUTPUT("HPHR"), 2885 2886 }; 2887 2888 static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 2889 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 2890 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 2891 {"ADC1 REQ", NULL, "ADC1"}, 2892 {"ADC1", NULL, "AMIC1"}, 2893 2894 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 2895 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 2896 {"ADC2 REQ", NULL, "ADC2"}, 2897 {"ADC2", NULL, "HDR12 MUX"}, 2898 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 2899 {"HDR12 MUX", "HDR12", "AMIC1"}, 2900 {"ADC2 MUX", "INP3", "AMIC3"}, 2901 {"ADC2 MUX", "INP2", "AMIC2"}, 2902 2903 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 2904 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 2905 {"ADC3 REQ", NULL, "ADC3"}, 2906 {"ADC3", NULL, "HDR34 MUX"}, 2907 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 2908 {"HDR34 MUX", "HDR34", "AMIC5"}, 2909 {"ADC3 MUX", "INP4", "AMIC4"}, 2910 {"ADC3 MUX", "INP6", "AMIC6"}, 2911 2912 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 2913 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 2914 {"ADC4 REQ", NULL, "ADC4"}, 2915 {"ADC4", NULL, "ADC4 MUX"}, 2916 {"ADC4 MUX", "INP5", "AMIC5"}, 2917 {"ADC4 MUX", "INP7", "AMIC7"}, 2918 2919 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 2920 {"DMIC1_MIXER", "Switch", "DMIC1"}, 2921 2922 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 2923 {"DMIC2_MIXER", "Switch", "DMIC2"}, 2924 2925 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 2926 {"DMIC3_MIXER", "Switch", "DMIC3"}, 2927 2928 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 2929 {"DMIC4_MIXER", "Switch", "DMIC4"}, 2930 2931 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 2932 {"DMIC5_MIXER", "Switch", "DMIC5"}, 2933 2934 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 2935 {"DMIC6_MIXER", "Switch", "DMIC6"}, 2936 2937 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 2938 {"DMIC7_MIXER", "Switch", "DMIC7"}, 2939 2940 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 2941 {"DMIC8_MIXER", "Switch", "DMIC8"}, 2942 2943 {"IN1_HPHL", NULL, "VDD_BUCK"}, 2944 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 2945 2946 {"RX1", NULL, "IN1_HPHL"}, 2947 {"RX1", NULL, "RXCLK"}, 2948 {"RDAC1", NULL, "RX1"}, 2949 {"HPHL_RDAC", "Switch", "RDAC1"}, 2950 {"HPHL PGA", NULL, "HPHL_RDAC"}, 2951 {"HPHL", NULL, "HPHL PGA"}, 2952 2953 {"IN2_HPHR", NULL, "VDD_BUCK"}, 2954 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 2955 {"RX2", NULL, "IN2_HPHR"}, 2956 {"RDAC2", NULL, "RX2"}, 2957 {"RX2", NULL, "RXCLK"}, 2958 {"HPHR_RDAC", "Switch", "RDAC2"}, 2959 {"HPHR PGA", NULL, "HPHR_RDAC"}, 2960 {"HPHR", NULL, "HPHR PGA"}, 2961 2962 {"IN3_AUX", NULL, "VDD_BUCK"}, 2963 {"IN3_AUX", NULL, "CLS_H_PORT"}, 2964 {"RX3", NULL, "IN3_AUX"}, 2965 {"RDAC4", NULL, "RX3"}, 2966 {"RX3", NULL, "RXCLK"}, 2967 {"AUX_RDAC", "Switch", "RDAC4"}, 2968 {"AUX PGA", NULL, "AUX_RDAC"}, 2969 {"AUX", NULL, "AUX PGA"}, 2970 2971 {"RDAC3_MUX", "RX3", "RX3"}, 2972 {"RDAC3_MUX", "RX1", "RX1"}, 2973 {"RDAC3", NULL, "RDAC3_MUX"}, 2974 {"EAR_RDAC", "Switch", "RDAC3"}, 2975 {"EAR PGA", NULL, "EAR_RDAC"}, 2976 {"EAR", NULL, "EAR PGA"}, 2977 }; 2978 2979 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x) 2980 { 2981 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2982 2983 /* set micbias voltage */ 2984 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv); 2985 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv); 2986 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv); 2987 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv); 2988 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0) 2989 return -EINVAL; 2990 2991 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 2992 WCD938X_MICB_VOUT_MASK, vout_ctl_1); 2993 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 2994 WCD938X_MICB_VOUT_MASK, vout_ctl_2); 2995 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 2996 WCD938X_MICB_VOUT_MASK, vout_ctl_3); 2997 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 2998 WCD938X_MICB_VOUT_MASK, vout_ctl_4); 2999 3000 return 0; 3001 } 3002 3003 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 3004 { 3005 return IRQ_HANDLED; 3006 } 3007 3008 static const struct irq_chip wcd_irq_chip = { 3009 .name = "WCD938x", 3010 }; 3011 3012 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 3013 irq_hw_number_t hw) 3014 { 3015 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 3016 irq_set_nested_thread(virq, 1); 3017 irq_set_noprobe(virq); 3018 3019 return 0; 3020 } 3021 3022 static const struct irq_domain_ops wcd_domain_ops = { 3023 .map = wcd_irq_chip_map, 3024 }; 3025 3026 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 3027 { 3028 3029 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 3030 if (!(wcd->virq)) { 3031 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 3032 return -EINVAL; 3033 } 3034 3035 return devm_regmap_add_irq_chip(dev, wcd->regmap, 3036 irq_create_mapping(wcd->virq, 0), 3037 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 3038 &wcd->irq_chip); 3039 } 3040 3041 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 3042 { 3043 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3044 struct sdw_slave *tx_sdw_dev = wcd938x->tx_sdw_dev; 3045 struct device *dev = component->dev; 3046 unsigned long time_left; 3047 unsigned int variant; 3048 int ret, i; 3049 3050 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 3051 msecs_to_jiffies(2000)); 3052 if (!time_left) { 3053 dev_err(dev, "soundwire device init timeout\n"); 3054 return -ETIMEDOUT; 3055 } 3056 3057 snd_soc_component_init_regmap(component, wcd938x->regmap); 3058 3059 ret = pm_runtime_resume_and_get(dev); 3060 if (ret < 0) 3061 return ret; 3062 3063 variant = snd_soc_component_read_field(component, 3064 WCD938X_DIGITAL_EFUSE_REG_0, 3065 WCD938X_ID_MASK); 3066 3067 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 3068 if (IS_ERR(wcd938x->clsh_info)) { 3069 pm_runtime_put(dev); 3070 return PTR_ERR(wcd938x->clsh_info); 3071 } 3072 3073 wcd938x_io_init(wcd938x); 3074 /* Set all interrupts as edge triggered */ 3075 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 3076 regmap_write(wcd938x->regmap, 3077 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 3078 } 3079 3080 pm_runtime_put(dev); 3081 3082 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3083 WCD938X_IRQ_HPHR_PDM_WD_INT); 3084 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3085 WCD938X_IRQ_HPHL_PDM_WD_INT); 3086 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3087 WCD938X_IRQ_AUX_PDM_WD_INT); 3088 3089 /* Request for watchdog interrupt */ 3090 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3091 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3092 "HPHR PDM WD INT", wcd938x); 3093 if (ret) { 3094 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3095 goto err_free_clsh_ctrl; 3096 } 3097 3098 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3099 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3100 "HPHL PDM WD INT", wcd938x); 3101 if (ret) { 3102 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3103 goto err_free_hphr_pdm_wd_int; 3104 } 3105 3106 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3107 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3108 "AUX PDM WD INT", wcd938x); 3109 if (ret) { 3110 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3111 goto err_free_hphl_pdm_wd_int; 3112 } 3113 3114 /* Disable watchdog interrupt for HPH and AUX */ 3115 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 3116 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 3117 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 3118 3119 switch (variant) { 3120 case CHIPID_WCD9380: 3121 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 3122 ARRAY_SIZE(wcd9380_snd_controls)); 3123 if (ret < 0) { 3124 dev_err(component->dev, 3125 "%s: Failed to add snd ctrls for variant: %d\n", 3126 __func__, variant); 3127 goto err_free_aux_pdm_wd_int; 3128 } 3129 break; 3130 case CHIPID_WCD9385: 3131 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 3132 ARRAY_SIZE(wcd9385_snd_controls)); 3133 if (ret < 0) { 3134 dev_err(component->dev, 3135 "%s: Failed to add snd ctrls for variant: %d\n", 3136 __func__, variant); 3137 goto err_free_aux_pdm_wd_int; 3138 } 3139 break; 3140 default: 3141 break; 3142 } 3143 3144 ret = wcd938x_mbhc_init(component); 3145 if (ret) { 3146 dev_err(component->dev, "mbhc initialization failed\n"); 3147 goto err_free_aux_pdm_wd_int; 3148 } 3149 3150 return 0; 3151 3152 err_free_aux_pdm_wd_int: 3153 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3154 err_free_hphl_pdm_wd_int: 3155 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3156 err_free_hphr_pdm_wd_int: 3157 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3158 err_free_clsh_ctrl: 3159 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3160 3161 return ret; 3162 } 3163 3164 static void wcd938x_soc_codec_remove(struct snd_soc_component *component) 3165 { 3166 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3167 3168 wcd938x_mbhc_deinit(component); 3169 3170 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3171 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3172 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3173 3174 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3175 } 3176 3177 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 3178 struct snd_soc_jack *jack, void *data) 3179 { 3180 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 3181 3182 if (jack) 3183 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 3184 else 3185 wcd_mbhc_stop(wcd->wcd_mbhc); 3186 3187 return 0; 3188 } 3189 3190 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 3191 .name = "wcd938x_codec", 3192 .probe = wcd938x_soc_codec_probe, 3193 .remove = wcd938x_soc_codec_remove, 3194 .controls = wcd938x_snd_controls, 3195 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 3196 .dapm_widgets = wcd938x_dapm_widgets, 3197 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 3198 .dapm_routes = wcd938x_audio_map, 3199 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 3200 .set_jack = wcd938x_codec_set_jack, 3201 .endianness = 1, 3202 }; 3203 3204 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd) 3205 { 3206 struct device_node *np = dev->of_node; 3207 u32 prop_val = 0; 3208 int rc = 0; 3209 3210 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 3211 if (!rc) 3212 wcd->micb1_mv = prop_val/1000; 3213 else 3214 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__); 3215 3216 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 3217 if (!rc) 3218 wcd->micb2_mv = prop_val/1000; 3219 else 3220 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__); 3221 3222 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 3223 if (!rc) 3224 wcd->micb3_mv = prop_val/1000; 3225 else 3226 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__); 3227 3228 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val); 3229 if (!rc) 3230 wcd->micb4_mv = prop_val/1000; 3231 else 3232 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__); 3233 } 3234 3235 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component) 3236 { 3237 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3238 struct device *dev = component->dev; 3239 int ret; 3240 3241 if (wcd938x->us_euro_mux) { 3242 if (wcd938x->mux_setup_done) 3243 mux_control_deselect(wcd938x->us_euro_mux); 3244 3245 ret = mux_control_try_select(wcd938x->us_euro_mux, !wcd938x->mux_state); 3246 if (ret) { 3247 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret); 3248 wcd938x->mux_setup_done = false; 3249 return false; 3250 } 3251 wcd938x->mux_setup_done = true; 3252 } else { 3253 gpiod_set_value(wcd938x->us_euro_gpio, !wcd938x->mux_state); 3254 } 3255 3256 wcd938x->mux_state = !wcd938x->mux_state; 3257 3258 return true; 3259 } 3260 3261 3262 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 3263 { 3264 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 3265 int ret; 3266 3267 wcd938x->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 3268 if (IS_ERR(wcd938x->reset_gpio)) 3269 return dev_err_probe(dev, PTR_ERR(wcd938x->reset_gpio), 3270 "Failed to get reset gpio\n"); 3271 3272 if (of_property_present(dev->of_node, "mux-controls")) { 3273 wcd938x->us_euro_mux = devm_mux_control_get(dev, NULL); 3274 if (IS_ERR(wcd938x->us_euro_mux)) { 3275 ret = PTR_ERR(wcd938x->us_euro_mux); 3276 return dev_err_probe(dev, ret, "failed to get mux control\n"); 3277 } 3278 3279 ret = mux_control_try_select(wcd938x->us_euro_mux, wcd938x->mux_state); 3280 if (ret) { 3281 dev_err(dev, "Error (%d) Unable to select us/euro mux state\n", ret); 3282 return ret; 3283 } 3284 wcd938x->mux_setup_done = true; 3285 } else { 3286 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", GPIOD_OUT_LOW); 3287 if (IS_ERR(wcd938x->us_euro_gpio)) 3288 return dev_err_probe(dev, PTR_ERR(wcd938x->us_euro_gpio), 3289 "us-euro swap Control GPIO not found\n"); 3290 } 3291 3292 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic; 3293 3294 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd938x_supplies), 3295 wcd938x_supplies); 3296 if (ret) 3297 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 3298 3299 wcd938x_dt_parse_micbias_info(dev, wcd938x); 3300 3301 cfg->mbhc_micbias = MIC_BIAS_2; 3302 cfg->anc_micbias = MIC_BIAS_2; 3303 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 3304 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 3305 cfg->micb_mv = wcd938x->micb2_mv; 3306 cfg->linein_th = 5000; 3307 cfg->hs_thr = 1700; 3308 cfg->hph_thr = 50; 3309 3310 wcd_dt_parse_mbhc_data(dev, cfg); 3311 3312 return 0; 3313 } 3314 3315 static int wcd938x_reset(struct wcd938x_priv *wcd938x) 3316 { 3317 gpiod_set_value(wcd938x->reset_gpio, 1); 3318 /* 20us sleep required after pulling the reset gpio to LOW */ 3319 usleep_range(20, 30); 3320 gpiod_set_value(wcd938x->reset_gpio, 0); 3321 /* 20us sleep required after pulling the reset gpio to HIGH */ 3322 usleep_range(20, 30); 3323 3324 return 0; 3325 } 3326 3327 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 3328 struct snd_pcm_hw_params *params, 3329 struct snd_soc_dai *dai) 3330 { 3331 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3332 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3333 3334 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 3335 } 3336 3337 static int wcd938x_codec_free(struct snd_pcm_substream *substream, 3338 struct snd_soc_dai *dai) 3339 { 3340 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3341 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3342 3343 return wcd938x_sdw_free(wcd, substream, dai); 3344 } 3345 3346 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 3347 void *stream, int direction) 3348 { 3349 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3350 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3351 3352 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 3353 3354 } 3355 3356 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 3357 .hw_params = wcd938x_codec_hw_params, 3358 .hw_free = wcd938x_codec_free, 3359 .set_stream = wcd938x_codec_set_sdw_stream, 3360 }; 3361 3362 static struct snd_soc_dai_driver wcd938x_dais[] = { 3363 [AIF1_PB] = { 3364 .name = "wcd938x-sdw-rx", 3365 .playback = { 3366 .stream_name = "WCD AIF1 Playback", 3367 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 3368 .formats = WCD938X_FORMATS_S16_S24_LE, 3369 .rate_max = 192000, 3370 .rate_min = 8000, 3371 .channels_min = 1, 3372 .channels_max = 2, 3373 }, 3374 .ops = &wcd938x_sdw_dai_ops, 3375 }, 3376 [AIF1_CAP] = { 3377 .name = "wcd938x-sdw-tx", 3378 .capture = { 3379 .stream_name = "WCD AIF1 Capture", 3380 .rates = WCD938X_RATES_MASK, 3381 .formats = SNDRV_PCM_FMTBIT_S16_LE, 3382 .rate_min = 8000, 3383 .rate_max = 192000, 3384 .channels_min = 1, 3385 .channels_max = 4, 3386 }, 3387 .ops = &wcd938x_sdw_dai_ops, 3388 }, 3389 }; 3390 3391 static int wcd938x_bind(struct device *dev) 3392 { 3393 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3394 int ret; 3395 3396 ret = component_bind_all(dev, wcd938x); 3397 if (ret) { 3398 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 3399 __func__, ret); 3400 return ret; 3401 } 3402 3403 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode); 3404 if (!wcd938x->rxdev) { 3405 dev_err(dev, "could not find slave with matching of node\n"); 3406 ret = -EINVAL; 3407 goto err_unbind; 3408 } 3409 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 3410 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 3411 3412 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode); 3413 if (!wcd938x->txdev) { 3414 dev_err(dev, "could not find txslave with matching of node\n"); 3415 ret = -EINVAL; 3416 goto err_put_rxdev; 3417 } 3418 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 3419 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 3420 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 3421 3422 /* As TX is main CSR reg interface, which should not be suspended first. 3423 * expicilty add the dependency link */ 3424 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 3425 DL_FLAG_PM_RUNTIME)) { 3426 dev_err(dev, "could not devlink tx and rx\n"); 3427 ret = -EINVAL; 3428 goto err_put_txdev; 3429 } 3430 3431 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 3432 DL_FLAG_PM_RUNTIME)) { 3433 dev_err(dev, "could not devlink wcd and tx\n"); 3434 ret = -EINVAL; 3435 goto err_remove_rxtx_link; 3436 } 3437 3438 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 3439 DL_FLAG_PM_RUNTIME)) { 3440 dev_err(dev, "could not devlink wcd and rx\n"); 3441 ret = -EINVAL; 3442 goto err_remove_tx_link; 3443 } 3444 3445 wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL); 3446 if (!wcd938x->regmap) { 3447 dev_err(dev, "could not get TX device regmap\n"); 3448 ret = -EINVAL; 3449 goto err_remove_rx_link; 3450 } 3451 3452 ret = wcd938x_irq_init(wcd938x, dev); 3453 if (ret) { 3454 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 3455 goto err_remove_rx_link; 3456 } 3457 3458 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 3459 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 3460 3461 ret = wcd938x_set_micbias_data(wcd938x); 3462 if (ret < 0) { 3463 dev_err(dev, "%s: bad micbias pdata\n", __func__); 3464 goto err_remove_rx_link; 3465 } 3466 3467 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 3468 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 3469 if (ret) { 3470 dev_err(dev, "%s: Codec registration failed\n", 3471 __func__); 3472 goto err_remove_rx_link; 3473 } 3474 3475 return 0; 3476 3477 err_remove_rx_link: 3478 device_link_remove(dev, wcd938x->rxdev); 3479 err_remove_tx_link: 3480 device_link_remove(dev, wcd938x->txdev); 3481 err_remove_rxtx_link: 3482 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3483 err_put_txdev: 3484 put_device(wcd938x->txdev); 3485 err_put_rxdev: 3486 put_device(wcd938x->rxdev); 3487 err_unbind: 3488 component_unbind_all(dev, wcd938x); 3489 3490 return ret; 3491 } 3492 3493 static void wcd938x_unbind(struct device *dev) 3494 { 3495 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3496 3497 snd_soc_unregister_component(dev); 3498 device_link_remove(dev, wcd938x->txdev); 3499 device_link_remove(dev, wcd938x->rxdev); 3500 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3501 put_device(wcd938x->txdev); 3502 put_device(wcd938x->rxdev); 3503 component_unbind_all(dev, wcd938x); 3504 } 3505 3506 static const struct component_master_ops wcd938x_comp_ops = { 3507 .bind = wcd938x_bind, 3508 .unbind = wcd938x_unbind, 3509 }; 3510 3511 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 3512 struct device *dev, 3513 struct component_match **matchptr) 3514 { 3515 struct device_node *np; 3516 3517 np = dev->of_node; 3518 3519 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 3520 if (!wcd938x->rxnode) { 3521 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 3522 return -ENODEV; 3523 } 3524 3525 of_node_get(wcd938x->rxnode); 3526 component_match_add_release(dev, matchptr, component_release_of, 3527 component_compare_of, wcd938x->rxnode); 3528 3529 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 3530 if (!wcd938x->txnode) { 3531 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 3532 return -ENODEV; 3533 } 3534 of_node_get(wcd938x->txnode); 3535 component_match_add_release(dev, matchptr, component_release_of, 3536 component_compare_of, wcd938x->txnode); 3537 return 0; 3538 } 3539 3540 static int wcd938x_probe(struct platform_device *pdev) 3541 { 3542 struct component_match *match = NULL; 3543 struct wcd938x_priv *wcd938x = NULL; 3544 struct device *dev = &pdev->dev; 3545 int ret; 3546 3547 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 3548 GFP_KERNEL); 3549 if (!wcd938x) 3550 return -ENOMEM; 3551 3552 dev_set_drvdata(dev, wcd938x); 3553 mutex_init(&wcd938x->micb_lock); 3554 3555 ret = wcd938x_populate_dt_data(wcd938x, dev); 3556 if (ret) 3557 return ret; 3558 3559 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 3560 if (ret) 3561 return ret; 3562 3563 wcd938x_reset(wcd938x); 3564 3565 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 3566 if (ret) 3567 return ret; 3568 3569 pm_runtime_set_autosuspend_delay(dev, 1000); 3570 pm_runtime_use_autosuspend(dev); 3571 pm_runtime_mark_last_busy(dev); 3572 pm_runtime_set_active(dev); 3573 pm_runtime_enable(dev); 3574 pm_runtime_idle(dev); 3575 3576 return 0; 3577 } 3578 3579 static void wcd938x_remove(struct platform_device *pdev) 3580 { 3581 struct device *dev = &pdev->dev; 3582 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3583 3584 component_master_del(dev, &wcd938x_comp_ops); 3585 3586 pm_runtime_disable(dev); 3587 pm_runtime_set_suspended(dev); 3588 pm_runtime_dont_use_autosuspend(dev); 3589 3590 if (wcd938x->us_euro_mux && wcd938x->mux_setup_done) 3591 mux_control_deselect(wcd938x->us_euro_mux); 3592 } 3593 3594 #if defined(CONFIG_OF) 3595 static const struct of_device_id wcd938x_dt_match[] = { 3596 { .compatible = "qcom,wcd9380-codec" }, 3597 { .compatible = "qcom,wcd9385-codec" }, 3598 {} 3599 }; 3600 MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 3601 #endif 3602 3603 static struct platform_driver wcd938x_codec_driver = { 3604 .probe = wcd938x_probe, 3605 .remove = wcd938x_remove, 3606 .driver = { 3607 .name = "wcd938x_codec", 3608 .of_match_table = of_match_ptr(wcd938x_dt_match), 3609 .suppress_bind_attrs = true, 3610 }, 3611 }; 3612 3613 module_platform_driver(wcd938x_codec_driver); 3614 MODULE_DESCRIPTION("WCD938X Codec driver"); 3615 MODULE_LICENSE("GPL"); 3616