1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/slab.h> 6 #include <linux/platform_device.h> 7 #include <linux/device.h> 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/kernel.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/component.h> 13 #include <sound/tlv.h> 14 #include <linux/of_gpio.h> 15 #include <linux/of.h> 16 #include <sound/jack.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <linux/regmap.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dapm.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "wcd-clsh-v2.h" 25 #include "wcd-mbhc-v2.h" 26 #include "wcd938x.h" 27 28 #define WCD938X_MAX_MICBIAS (4) 29 #define WCD938X_MAX_SUPPLY (4) 30 #define WCD938X_MBHC_MAX_BUTTONS (8) 31 #define TX_ADC_MAX (4) 32 33 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 34 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 35 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 36 /* Fractional Rates */ 37 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 38 SNDRV_PCM_RATE_176400) 39 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 40 SNDRV_PCM_FMTBIT_S24_LE) 41 #define SWR_CLK_RATE_0P6MHZ (600000) 42 #define SWR_CLK_RATE_1P2MHZ (1200000) 43 #define SWR_CLK_RATE_2P4MHZ (2400000) 44 #define SWR_CLK_RATE_4P8MHZ (4800000) 45 #define SWR_CLK_RATE_9P6MHZ (9600000) 46 #define SWR_CLK_RATE_11P2896MHZ (1128960) 47 48 #define EAR_RX_PATH_AUX (1) 49 50 #define ADC_MODE_VAL_HIFI 0x01 51 #define ADC_MODE_VAL_LO_HIF 0x02 52 #define ADC_MODE_VAL_NORMAL 0x03 53 #define ADC_MODE_VAL_LP 0x05 54 #define ADC_MODE_VAL_ULP1 0x09 55 #define ADC_MODE_VAL_ULP2 0x0B 56 57 /* Z value defined in milliohm */ 58 #define WCD938X_ZDET_VAL_32 (32000) 59 #define WCD938X_ZDET_VAL_400 (400000) 60 #define WCD938X_ZDET_VAL_1200 (1200000) 61 #define WCD938X_ZDET_VAL_100K (100000000) 62 /* Z floating defined in ohms */ 63 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE) 64 #define WCD938X_ZDET_NUM_MEASUREMENTS (900) 65 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 66 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF) 67 /* Z value compared in milliOhm */ 68 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 69 #define WCD938X_MBHC_ZDET_CONST (86 * 16384) 70 #define WCD_MBHC_HS_V_MAX 1600 71 72 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 73 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, snd_soc_get_volsw, \ 74 wcd938x_ear_pa_put_gain, tlv_array) 75 76 enum { 77 WCD9380 = 0, 78 WCD9385 = 5, 79 }; 80 81 enum { 82 /* INTR_CTRL_INT_MASK_0 */ 83 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0, 84 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 85 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 86 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 87 WCD938X_IRQ_MBHC_SW_DET, 88 WCD938X_IRQ_HPHR_OCP_INT, 89 WCD938X_IRQ_HPHR_CNP_INT, 90 WCD938X_IRQ_HPHL_OCP_INT, 91 92 /* INTR_CTRL_INT_MASK_1 */ 93 WCD938X_IRQ_HPHL_CNP_INT, 94 WCD938X_IRQ_EAR_CNP_INT, 95 WCD938X_IRQ_EAR_SCD_INT, 96 WCD938X_IRQ_AUX_CNP_INT, 97 WCD938X_IRQ_AUX_SCD_INT, 98 WCD938X_IRQ_HPHL_PDM_WD_INT, 99 WCD938X_IRQ_HPHR_PDM_WD_INT, 100 WCD938X_IRQ_AUX_PDM_WD_INT, 101 102 /* INTR_CTRL_INT_MASK_2 */ 103 WCD938X_IRQ_LDORT_SCD_INT, 104 WCD938X_IRQ_MBHC_MOISTURE_INT, 105 WCD938X_IRQ_HPHL_SURGE_DET_INT, 106 WCD938X_IRQ_HPHR_SURGE_DET_INT, 107 WCD938X_NUM_IRQS, 108 }; 109 110 enum { 111 WCD_ADC1 = 0, 112 WCD_ADC2, 113 WCD_ADC3, 114 WCD_ADC4, 115 ALLOW_BUCK_DISABLE, 116 HPH_COMP_DELAY, 117 HPH_PA_DELAY, 118 AMIC2_BCS_ENABLE, 119 WCD_SUPPLIES_LPM_MODE, 120 }; 121 122 enum { 123 ADC_MODE_INVALID = 0, 124 ADC_MODE_HIFI, 125 ADC_MODE_LO_HIF, 126 ADC_MODE_NORMAL, 127 ADC_MODE_LP, 128 ADC_MODE_ULP1, 129 ADC_MODE_ULP2, 130 }; 131 132 enum { 133 AIF1_PB = 0, 134 AIF1_CAP, 135 NUM_CODEC_DAIS, 136 }; 137 138 static u8 tx_mode_bit[] = { 139 [ADC_MODE_INVALID] = 0x00, 140 [ADC_MODE_HIFI] = 0x01, 141 [ADC_MODE_LO_HIF] = 0x02, 142 [ADC_MODE_NORMAL] = 0x04, 143 [ADC_MODE_LP] = 0x08, 144 [ADC_MODE_ULP1] = 0x10, 145 [ADC_MODE_ULP2] = 0x20, 146 }; 147 148 struct wcd938x_priv { 149 struct sdw_slave *tx_sdw_dev; 150 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS]; 151 struct device *txdev; 152 struct device *rxdev; 153 struct device_node *rxnode, *txnode; 154 struct regmap *regmap; 155 struct mutex micb_lock; 156 /* mbhc module */ 157 struct wcd_mbhc *wcd_mbhc; 158 struct wcd_mbhc_config mbhc_cfg; 159 struct wcd_mbhc_intr intr_ids; 160 struct wcd_clsh_ctrl *clsh_info; 161 struct irq_domain *virq; 162 struct regmap_irq_chip *wcd_regmap_irq_chip; 163 struct regmap_irq_chip_data *irq_chip; 164 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY]; 165 struct snd_soc_jack *jack; 166 unsigned long status_mask; 167 s32 micb_ref[WCD938X_MAX_MICBIAS]; 168 s32 pullup_ref[WCD938X_MAX_MICBIAS]; 169 u32 hph_mode; 170 u32 tx_mode[TX_ADC_MAX]; 171 int flyback_cur_det_disable; 172 int ear_rx_path; 173 int variant; 174 int reset_gpio; 175 struct gpio_desc *us_euro_gpio; 176 u32 micb1_mv; 177 u32 micb2_mv; 178 u32 micb3_mv; 179 u32 micb4_mv; 180 int hphr_pdm_wd_int; 181 int hphl_pdm_wd_int; 182 int aux_pdm_wd_int; 183 bool comp1_enable; 184 bool comp2_enable; 185 bool ldoh; 186 }; 187 188 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800); 189 static const DECLARE_TLV_DB_SCALE(line_gain, -3000, 150, 0); 190 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000); 191 192 struct wcd938x_mbhc_zdet_param { 193 u16 ldo_ctl; 194 u16 noff; 195 u16 nshift; 196 u16 btn5; 197 u16 btn6; 198 u16 btn7; 199 }; 200 201 static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 202 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80), 203 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40), 204 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20), 205 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 206 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08), 207 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F), 208 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04), 209 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10), 210 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08), 211 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01), 212 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06), 213 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80), 214 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 215 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03), 216 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03), 217 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08), 218 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 219 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20), 220 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80), 221 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40), 222 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10), 223 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07), 224 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70), 225 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF), 226 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0), 227 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF), 228 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40), 229 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80), 230 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0), 231 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10), 232 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02), 233 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01), 234 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70), 235 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20), 236 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40), 237 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10), 238 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01), 239 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01), 240 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80), 241 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20), 242 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08), 243 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40), 244 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80), 245 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF), 246 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F), 247 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10), 248 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04), 249 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02), 250 }; 251 252 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = { 253 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01), 254 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02), 255 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04), 256 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08), 257 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10), 258 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20), 259 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40), 260 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80), 261 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01), 262 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02), 263 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04), 264 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08), 265 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10), 266 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20), 267 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40), 268 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80), 269 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01), 270 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02), 271 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04), 272 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08), 273 }; 274 275 static struct regmap_irq_chip wcd938x_regmap_irq_chip = { 276 .name = "wcd938x", 277 .irqs = wcd938x_irqs, 278 .num_irqs = ARRAY_SIZE(wcd938x_irqs), 279 .num_regs = 3, 280 .status_base = WCD938X_DIGITAL_INTR_STATUS_0, 281 .mask_base = WCD938X_DIGITAL_INTR_MASK_0, 282 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, 283 .use_ack = 1, 284 .runtime_pm = true, 285 .irq_drv_data = NULL, 286 }; 287 288 static int wcd938x_get_clk_rate(int mode) 289 { 290 int rate; 291 292 switch (mode) { 293 case ADC_MODE_ULP2: 294 rate = SWR_CLK_RATE_0P6MHZ; 295 break; 296 case ADC_MODE_ULP1: 297 rate = SWR_CLK_RATE_1P2MHZ; 298 break; 299 case ADC_MODE_LP: 300 rate = SWR_CLK_RATE_4P8MHZ; 301 break; 302 case ADC_MODE_NORMAL: 303 case ADC_MODE_LO_HIF: 304 case ADC_MODE_HIFI: 305 case ADC_MODE_INVALID: 306 default: 307 rate = SWR_CLK_RATE_9P6MHZ; 308 break; 309 } 310 311 return rate; 312 } 313 314 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank) 315 { 316 u8 mask = (bank ? 0xF0 : 0x0F); 317 u8 val = 0; 318 319 switch (rate) { 320 case SWR_CLK_RATE_0P6MHZ: 321 val = (bank ? 0x60 : 0x06); 322 break; 323 case SWR_CLK_RATE_1P2MHZ: 324 val = (bank ? 0x50 : 0x05); 325 break; 326 case SWR_CLK_RATE_2P4MHZ: 327 val = (bank ? 0x30 : 0x03); 328 break; 329 case SWR_CLK_RATE_4P8MHZ: 330 val = (bank ? 0x10 : 0x01); 331 break; 332 case SWR_CLK_RATE_9P6MHZ: 333 default: 334 val = 0x00; 335 break; 336 } 337 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE, 338 mask, val); 339 340 return 0; 341 } 342 343 static int wcd938x_io_init(struct wcd938x_priv *wcd938x) 344 { 345 struct regmap *rm = wcd938x->regmap; 346 347 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E); 348 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80); 349 /* 1 msec delay as per HW requirement */ 350 usleep_range(1000, 1010); 351 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40); 352 /* 1 msec delay as per HW requirement */ 353 usleep_range(1000, 1010); 354 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00); 355 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ, 356 0xF0, 0x80); 357 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80); 358 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40); 359 /* 10 msec delay as per HW requirement */ 360 usleep_range(10000, 10010); 361 362 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00); 363 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 364 0xF0, 0x00); 365 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 366 0x1F, 0x15); 367 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 368 0x1F, 0x15); 369 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL, 370 0xC0, 0x80); 371 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL, 372 0x02, 0x02); 373 374 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 375 0xFF, 0x14); 376 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 377 0x1F, 0x08); 378 379 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55); 380 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44); 381 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11); 382 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00); 383 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00); 384 385 /* Set Noise Filter Resistor value */ 386 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0); 387 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0); 388 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0); 389 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0); 390 391 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00); 392 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 393 394 return 0; 395 396 } 397 398 static int wcd938x_sdw_connect_port(const struct wcd938x_sdw_ch_info *ch_info, 399 struct sdw_port_config *port_config, 400 u8 enable) 401 { 402 u8 ch_mask, port_num; 403 404 port_num = ch_info->port_num; 405 ch_mask = ch_info->ch_mask; 406 407 port_config->num = port_num; 408 409 if (enable) 410 port_config->ch_mask |= ch_mask; 411 else 412 port_config->ch_mask &= ~ch_mask; 413 414 return 0; 415 } 416 417 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable) 418 { 419 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id], 420 &wcd->port_config[port_num - 1], 421 enable); 422 } 423 424 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w, 425 struct snd_kcontrol *kcontrol, 426 int event) 427 { 428 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 429 430 switch (event) { 431 case SND_SOC_DAPM_PRE_PMU: 432 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 433 WCD938X_ANA_RX_CLK_EN_MASK, 1); 434 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 435 WCD938X_RX_BIAS_EN_MASK, 1); 436 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL, 437 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 438 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL, 439 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 440 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL, 441 WCD938X_DEM_DITHER_ENABLE_MASK, 0); 442 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 443 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1); 444 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA, 445 WCD938X_AUXPA_CLK_EN_MASK, 1); 446 break; 447 case SND_SOC_DAPM_POST_PMD: 448 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 449 WCD938X_VNEG_EN_MASK, 0); 450 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 451 WCD938X_VPOS_EN_MASK, 0); 452 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 453 WCD938X_RX_BIAS_EN_MASK, 0); 454 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 455 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0); 456 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 457 WCD938X_ANA_RX_CLK_EN_MASK, 0); 458 break; 459 } 460 return 0; 461 } 462 463 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 464 struct snd_kcontrol *kcontrol, 465 int event) 466 { 467 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 468 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 469 470 switch (event) { 471 case SND_SOC_DAPM_PRE_PMU: 472 snd_soc_component_write_field(component, 473 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 474 WCD938X_RXD0_CLK_EN_MASK, 0x01); 475 snd_soc_component_write_field(component, 476 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 477 WCD938X_HPHL_RX_EN_MASK, 1); 478 snd_soc_component_write_field(component, 479 WCD938X_HPH_RDAC_CLK_CTL1, 480 WCD938X_CHOP_CLK_EN_MASK, 0); 481 break; 482 case SND_SOC_DAPM_POST_PMU: 483 snd_soc_component_write_field(component, 484 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 485 WCD938X_HPH_RES_DIV_MASK, 0x02); 486 if (wcd938x->comp1_enable) { 487 snd_soc_component_write_field(component, 488 WCD938X_DIGITAL_CDC_COMP_CTL_0, 489 WCD938X_HPHL_COMP_EN_MASK, 1); 490 /* 5msec compander delay as per HW requirement */ 491 if (!wcd938x->comp2_enable || (snd_soc_component_read(component, 492 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01)) 493 usleep_range(5000, 5010); 494 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 495 WCD938X_AUTOCHOP_TIMER_EN, 0); 496 } else { 497 snd_soc_component_write_field(component, 498 WCD938X_DIGITAL_CDC_COMP_CTL_0, 499 WCD938X_HPHL_COMP_EN_MASK, 0); 500 snd_soc_component_write_field(component, 501 WCD938X_HPH_L_EN, 502 WCD938X_GAIN_SRC_SEL_MASK, 503 WCD938X_GAIN_SRC_SEL_REGISTER); 504 505 } 506 break; 507 case SND_SOC_DAPM_POST_PMD: 508 snd_soc_component_write_field(component, 509 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 510 WCD938X_HPH_RES_DIV_MASK, 0x1); 511 break; 512 } 513 514 return 0; 515 } 516 517 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 518 struct snd_kcontrol *kcontrol, 519 int event) 520 { 521 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 522 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 523 524 switch (event) { 525 case SND_SOC_DAPM_PRE_PMU: 526 snd_soc_component_write_field(component, 527 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 528 WCD938X_RXD1_CLK_EN_MASK, 1); 529 snd_soc_component_write_field(component, 530 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 531 WCD938X_HPHR_RX_EN_MASK, 1); 532 snd_soc_component_write_field(component, 533 WCD938X_HPH_RDAC_CLK_CTL1, 534 WCD938X_CHOP_CLK_EN_MASK, 0); 535 break; 536 case SND_SOC_DAPM_POST_PMU: 537 snd_soc_component_write_field(component, 538 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 539 WCD938X_HPH_RES_DIV_MASK, 0x02); 540 if (wcd938x->comp2_enable) { 541 snd_soc_component_write_field(component, 542 WCD938X_DIGITAL_CDC_COMP_CTL_0, 543 WCD938X_HPHR_COMP_EN_MASK, 1); 544 /* 5msec compander delay as per HW requirement */ 545 if (!wcd938x->comp1_enable || 546 (snd_soc_component_read(component, 547 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02)) 548 usleep_range(5000, 5010); 549 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 550 WCD938X_AUTOCHOP_TIMER_EN, 0); 551 } else { 552 snd_soc_component_write_field(component, 553 WCD938X_DIGITAL_CDC_COMP_CTL_0, 554 WCD938X_HPHR_COMP_EN_MASK, 0); 555 snd_soc_component_write_field(component, 556 WCD938X_HPH_R_EN, 557 WCD938X_GAIN_SRC_SEL_MASK, 558 WCD938X_GAIN_SRC_SEL_REGISTER); 559 } 560 break; 561 case SND_SOC_DAPM_POST_PMD: 562 snd_soc_component_write_field(component, 563 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 564 WCD938X_HPH_RES_DIV_MASK, 0x01); 565 break; 566 } 567 568 return 0; 569 } 570 571 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 572 struct snd_kcontrol *kcontrol, 573 int event) 574 { 575 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 576 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 577 578 switch (event) { 579 case SND_SOC_DAPM_PRE_PMU: 580 wcd938x->ear_rx_path = 581 snd_soc_component_read( 582 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 583 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 584 snd_soc_component_write_field(component, 585 WCD938X_EAR_EAR_DAC_CON, 586 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0); 587 snd_soc_component_write_field(component, 588 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 589 WCD938X_AUX_EN_MASK, 1); 590 snd_soc_component_write_field(component, 591 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 592 WCD938X_RXD2_CLK_EN_MASK, 1); 593 snd_soc_component_write_field(component, 594 WCD938X_ANA_EAR_COMPANDER_CTL, 595 WCD938X_GAIN_OVRD_REG_MASK, 1); 596 } else { 597 snd_soc_component_write_field(component, 598 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 599 WCD938X_HPHL_RX_EN_MASK, 1); 600 snd_soc_component_write_field(component, 601 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 602 WCD938X_RXD0_CLK_EN_MASK, 1); 603 if (wcd938x->comp1_enable) 604 snd_soc_component_write_field(component, 605 WCD938X_DIGITAL_CDC_COMP_CTL_0, 606 WCD938X_HPHL_COMP_EN_MASK, 1); 607 } 608 /* 5 msec delay as per HW requirement */ 609 usleep_range(5000, 5010); 610 if (wcd938x->flyback_cur_det_disable == 0) 611 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 612 WCD938X_EN_CUR_DET_MASK, 0); 613 wcd938x->flyback_cur_det_disable++; 614 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 615 WCD_CLSH_EVENT_PRE_DAC, 616 WCD_CLSH_STATE_EAR, 617 wcd938x->hph_mode); 618 break; 619 case SND_SOC_DAPM_POST_PMD: 620 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) { 621 snd_soc_component_write_field(component, 622 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 623 WCD938X_AUX_EN_MASK, 0); 624 snd_soc_component_write_field(component, 625 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 626 WCD938X_RXD2_CLK_EN_MASK, 0); 627 } else { 628 snd_soc_component_write_field(component, 629 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 630 WCD938X_HPHL_RX_EN_MASK, 0); 631 snd_soc_component_write_field(component, 632 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 633 WCD938X_RXD0_CLK_EN_MASK, 0); 634 if (wcd938x->comp1_enable) 635 snd_soc_component_write_field(component, 636 WCD938X_DIGITAL_CDC_COMP_CTL_0, 637 WCD938X_HPHL_COMP_EN_MASK, 0); 638 } 639 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 640 WCD938X_GAIN_OVRD_REG_MASK, 0); 641 snd_soc_component_write_field(component, 642 WCD938X_EAR_EAR_DAC_CON, 643 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1); 644 break; 645 } 646 return 0; 647 648 } 649 650 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w, 651 struct snd_kcontrol *kcontrol, 652 int event) 653 { 654 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 655 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 656 657 switch (event) { 658 case SND_SOC_DAPM_PRE_PMU: 659 snd_soc_component_write_field(component, 660 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 661 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1); 662 snd_soc_component_write_field(component, 663 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 664 WCD938X_RXD2_CLK_EN_MASK, 1); 665 snd_soc_component_write_field(component, 666 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 667 WCD938X_AUX_EN_MASK, 1); 668 if (wcd938x->flyback_cur_det_disable == 0) 669 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 670 WCD938X_EN_CUR_DET_MASK, 0); 671 wcd938x->flyback_cur_det_disable++; 672 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 673 WCD_CLSH_EVENT_PRE_DAC, 674 WCD_CLSH_STATE_AUX, 675 wcd938x->hph_mode); 676 break; 677 case SND_SOC_DAPM_POST_PMD: 678 snd_soc_component_write_field(component, 679 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 680 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0); 681 break; 682 } 683 return 0; 684 685 } 686 687 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 688 struct snd_kcontrol *kcontrol, int event) 689 { 690 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 691 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 692 int hph_mode = wcd938x->hph_mode; 693 694 switch (event) { 695 case SND_SOC_DAPM_PRE_PMU: 696 if (wcd938x->ldoh) 697 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 698 WCD938X_LDOH_EN_MASK, 1); 699 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 700 WCD_CLSH_STATE_HPHR, hph_mode); 701 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 702 703 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 704 hph_mode == CLS_H_ULP) { 705 snd_soc_component_write_field(component, 706 WCD938X_HPH_REFBUFF_LP_CTL, 707 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 708 } 709 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 710 WCD938X_HPHR_REF_EN_MASK, 1); 711 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 712 /* 100 usec delay as per HW requirement */ 713 usleep_range(100, 110); 714 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 715 snd_soc_component_write_field(component, 716 WCD938X_DIGITAL_PDM_WD_CTL1, 717 WCD938X_PDM_WD_EN_MASK, 0x3); 718 break; 719 case SND_SOC_DAPM_POST_PMU: 720 /* 721 * 7ms sleep is required if compander is enabled as per 722 * HW requirement. If compander is disabled, then 723 * 20ms delay is required. 724 */ 725 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 726 if (!wcd938x->comp2_enable) 727 usleep_range(20000, 20100); 728 else 729 usleep_range(7000, 7100); 730 731 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 732 hph_mode == CLS_H_ULP) 733 snd_soc_component_write_field(component, 734 WCD938X_HPH_REFBUFF_LP_CTL, 735 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 736 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 737 } 738 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 739 WCD938X_AUTOCHOP_TIMER_EN, 1); 740 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 741 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 742 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 743 WCD938X_REGULATOR_MODE_MASK, 744 WCD938X_REGULATOR_MODE_CLASS_AB); 745 enable_irq(wcd938x->hphr_pdm_wd_int); 746 break; 747 case SND_SOC_DAPM_PRE_PMD: 748 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 749 /* 750 * 7ms sleep is required if compander is enabled as per 751 * HW requirement. If compander is disabled, then 752 * 20ms delay is required. 753 */ 754 if (!wcd938x->comp2_enable) 755 usleep_range(20000, 20100); 756 else 757 usleep_range(7000, 7100); 758 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 759 WCD938X_HPHR_EN_MASK, 0); 760 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 761 WCD_EVENT_PRE_HPHR_PA_OFF); 762 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 763 break; 764 case SND_SOC_DAPM_POST_PMD: 765 /* 766 * 7ms sleep is required if compander is enabled as per 767 * HW requirement. If compander is disabled, then 768 * 20ms delay is required. 769 */ 770 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 771 if (!wcd938x->comp2_enable) 772 usleep_range(20000, 20100); 773 else 774 usleep_range(7000, 7100); 775 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 776 } 777 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 778 WCD_EVENT_POST_HPHR_PA_OFF); 779 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 780 WCD938X_HPHR_REF_EN_MASK, 0); 781 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1, 782 WCD938X_PDM_WD_EN_MASK, 0); 783 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 784 WCD_CLSH_STATE_HPHR, hph_mode); 785 if (wcd938x->ldoh) 786 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 787 WCD938X_LDOH_EN_MASK, 0); 788 break; 789 } 790 791 return 0; 792 } 793 794 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 795 struct snd_kcontrol *kcontrol, int event) 796 { 797 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 798 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 799 int hph_mode = wcd938x->hph_mode; 800 801 switch (event) { 802 case SND_SOC_DAPM_PRE_PMU: 803 if (wcd938x->ldoh) 804 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 805 WCD938X_LDOH_EN_MASK, 1); 806 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC, 807 WCD_CLSH_STATE_HPHL, hph_mode); 808 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI); 809 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 810 hph_mode == CLS_H_ULP) { 811 snd_soc_component_write_field(component, 812 WCD938X_HPH_REFBUFF_LP_CTL, 813 WCD938X_PREREF_FLIT_BYPASS_MASK, 1); 814 } 815 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 816 WCD938X_HPHL_REF_EN_MASK, 1); 817 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode); 818 /* 100 usec delay as per HW requirement */ 819 usleep_range(100, 110); 820 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 821 snd_soc_component_write_field(component, 822 WCD938X_DIGITAL_PDM_WD_CTL0, 823 WCD938X_PDM_WD_EN_MASK, 0x3); 824 break; 825 case SND_SOC_DAPM_POST_PMU: 826 /* 827 * 7ms sleep is required if compander is enabled as per 828 * HW requirement. If compander is disabled, then 829 * 20ms delay is required. 830 */ 831 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 832 if (!wcd938x->comp1_enable) 833 usleep_range(20000, 20100); 834 else 835 usleep_range(7000, 7100); 836 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || 837 hph_mode == CLS_H_ULP) 838 snd_soc_component_write_field(component, 839 WCD938X_HPH_REFBUFF_LP_CTL, 840 WCD938X_PREREF_FLIT_BYPASS_MASK, 0); 841 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 842 } 843 844 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1, 845 WCD938X_AUTOCHOP_TIMER_EN, 1); 846 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 847 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 848 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 849 WCD938X_REGULATOR_MODE_MASK, 850 WCD938X_REGULATOR_MODE_CLASS_AB); 851 enable_irq(wcd938x->hphl_pdm_wd_int); 852 break; 853 case SND_SOC_DAPM_PRE_PMD: 854 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 855 /* 856 * 7ms sleep is required if compander is enabled as per 857 * HW requirement. If compander is disabled, then 858 * 20ms delay is required. 859 */ 860 if (!wcd938x->comp1_enable) 861 usleep_range(20000, 20100); 862 else 863 usleep_range(7000, 7100); 864 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 865 WCD938X_HPHL_EN_MASK, 0); 866 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF); 867 set_bit(HPH_PA_DELAY, &wcd938x->status_mask); 868 break; 869 case SND_SOC_DAPM_POST_PMD: 870 /* 871 * 7ms sleep is required if compander is enabled as per 872 * HW requirement. If compander is disabled, then 873 * 20ms delay is required. 874 */ 875 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) { 876 if (!wcd938x->comp1_enable) 877 usleep_range(21000, 21100); 878 else 879 usleep_range(7000, 7100); 880 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask); 881 } 882 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 883 WCD_EVENT_POST_HPHL_PA_OFF); 884 snd_soc_component_write_field(component, WCD938X_ANA_HPH, 885 WCD938X_HPHL_REF_EN_MASK, 0); 886 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 887 WCD938X_PDM_WD_EN_MASK, 0); 888 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 889 WCD_CLSH_STATE_HPHL, hph_mode); 890 if (wcd938x->ldoh) 891 snd_soc_component_write_field(component, WCD938X_LDOH_MODE, 892 WCD938X_LDOH_EN_MASK, 0); 893 break; 894 } 895 896 return 0; 897 } 898 899 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w, 900 struct snd_kcontrol *kcontrol, int event) 901 { 902 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 903 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 904 int hph_mode = wcd938x->hph_mode; 905 906 switch (event) { 907 case SND_SOC_DAPM_PRE_PMU: 908 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 909 WCD938X_AUX_PDM_WD_EN_MASK, 1); 910 break; 911 case SND_SOC_DAPM_POST_PMU: 912 /* 1 msec delay as per HW requirement */ 913 usleep_range(1000, 1010); 914 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 915 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 916 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 917 WCD938X_REGULATOR_MODE_MASK, 918 WCD938X_REGULATOR_MODE_CLASS_AB); 919 enable_irq(wcd938x->aux_pdm_wd_int); 920 break; 921 case SND_SOC_DAPM_PRE_PMD: 922 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 923 break; 924 case SND_SOC_DAPM_POST_PMD: 925 /* 1 msec delay as per HW requirement */ 926 usleep_range(1000, 1010); 927 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 928 WCD938X_AUX_PDM_WD_EN_MASK, 0); 929 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, 930 WCD_CLSH_EVENT_POST_PA, 931 WCD_CLSH_STATE_AUX, 932 hph_mode); 933 934 wcd938x->flyback_cur_det_disable--; 935 if (wcd938x->flyback_cur_det_disable == 0) 936 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 937 WCD938X_EN_CUR_DET_MASK, 1); 938 break; 939 } 940 return 0; 941 } 942 943 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 944 struct snd_kcontrol *kcontrol, int event) 945 { 946 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 947 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 948 int hph_mode = wcd938x->hph_mode; 949 950 switch (event) { 951 case SND_SOC_DAPM_PRE_PMU: 952 /* 953 * Enable watchdog interrupt for HPHL or AUX 954 * depending on mux value 955 */ 956 wcd938x->ear_rx_path = snd_soc_component_read(component, 957 WCD938X_DIGITAL_CDC_EAR_PATH_CTL); 958 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 959 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 960 WCD938X_AUX_PDM_WD_EN_MASK, 1); 961 else 962 snd_soc_component_write_field(component, 963 WCD938X_DIGITAL_PDM_WD_CTL0, 964 WCD938X_PDM_WD_EN_MASK, 0x3); 965 if (!wcd938x->comp1_enable) 966 snd_soc_component_write_field(component, 967 WCD938X_ANA_EAR_COMPANDER_CTL, 968 WCD938X_GAIN_OVRD_REG_MASK, 1); 969 970 break; 971 case SND_SOC_DAPM_POST_PMU: 972 /* 6 msec delay as per HW requirement */ 973 usleep_range(6000, 6010); 974 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI || 975 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI) 976 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES, 977 WCD938X_REGULATOR_MODE_MASK, 978 WCD938X_REGULATOR_MODE_CLASS_AB); 979 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 980 enable_irq(wcd938x->aux_pdm_wd_int); 981 else 982 enable_irq(wcd938x->hphl_pdm_wd_int); 983 break; 984 case SND_SOC_DAPM_PRE_PMD: 985 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 986 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 987 else 988 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 989 break; 990 case SND_SOC_DAPM_POST_PMD: 991 if (!wcd938x->comp1_enable) 992 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 993 WCD938X_GAIN_OVRD_REG_MASK, 0); 994 /* 7 msec delay as per HW requirement */ 995 usleep_range(7000, 7010); 996 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) 997 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2, 998 WCD938X_AUX_PDM_WD_EN_MASK, 0); 999 else 1000 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0, 1001 WCD938X_PDM_WD_EN_MASK, 0); 1002 1003 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA, 1004 WCD_CLSH_STATE_EAR, hph_mode); 1005 1006 wcd938x->flyback_cur_det_disable--; 1007 if (wcd938x->flyback_cur_det_disable == 0) 1008 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN, 1009 WCD938X_EN_CUR_DET_MASK, 1); 1010 break; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 1017 struct snd_kcontrol *kcontrol, 1018 int event) 1019 { 1020 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1021 u16 dmic_clk_reg, dmic_clk_en_reg; 1022 u8 dmic_sel_mask, dmic_clk_mask; 1023 1024 switch (w->shift) { 1025 case 0: 1026 case 1: 1027 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1028 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL; 1029 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK; 1030 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK; 1031 break; 1032 case 2: 1033 case 3: 1034 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2; 1035 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL; 1036 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK; 1037 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK; 1038 break; 1039 case 4: 1040 case 5: 1041 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1042 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL; 1043 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK; 1044 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK; 1045 break; 1046 case 6: 1047 case 7: 1048 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4; 1049 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL; 1050 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK; 1051 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK; 1052 break; 1053 default: 1054 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 1055 __func__); 1056 return -EINVAL; 1057 } 1058 1059 switch (event) { 1060 case SND_SOC_DAPM_PRE_PMU: 1061 snd_soc_component_write_field(component, 1062 WCD938X_DIGITAL_CDC_AMIC_CTL, 1063 dmic_sel_mask, 1064 WCD938X_AMIC1_IN_SEL_DMIC); 1065 /* 250us sleep as per HW requirement */ 1066 usleep_range(250, 260); 1067 /* Setting DMIC clock rate to 2.4MHz */ 1068 snd_soc_component_write_field(component, dmic_clk_reg, 1069 dmic_clk_mask, 1070 WCD938X_DMIC4_RATE_2P4MHZ); 1071 snd_soc_component_write_field(component, dmic_clk_en_reg, 1072 WCD938X_DMIC_CLK_EN_MASK, 1); 1073 /* enable clock scaling */ 1074 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL, 1075 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3); 1076 break; 1077 case SND_SOC_DAPM_POST_PMD: 1078 snd_soc_component_write_field(component, 1079 WCD938X_DIGITAL_CDC_AMIC_CTL, 1080 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC); 1081 snd_soc_component_write_field(component, dmic_clk_en_reg, 1082 WCD938X_DMIC_CLK_EN_MASK, 0); 1083 break; 1084 } 1085 return 0; 1086 } 1087 1088 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w, 1089 struct snd_kcontrol *kcontrol, int event) 1090 { 1091 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1092 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1093 int bank; 1094 int rate; 1095 1096 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1; 1097 bank = bank ? 0 : 1; 1098 1099 switch (event) { 1100 case SND_SOC_DAPM_PRE_PMU: 1101 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1102 int i = 0, mode = 0; 1103 1104 if (test_bit(WCD_ADC1, &wcd938x->status_mask)) 1105 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]]; 1106 if (test_bit(WCD_ADC2, &wcd938x->status_mask)) 1107 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]]; 1108 if (test_bit(WCD_ADC3, &wcd938x->status_mask)) 1109 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]]; 1110 if (test_bit(WCD_ADC4, &wcd938x->status_mask)) 1111 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]]; 1112 1113 if (mode != 0) { 1114 for (i = 0; i < ADC_MODE_ULP2; i++) { 1115 if (mode & (1 << i)) { 1116 i++; 1117 break; 1118 } 1119 } 1120 } 1121 rate = wcd938x_get_clk_rate(i); 1122 wcd938x_set_swr_clk_rate(component, rate, bank); 1123 /* Copy clk settings to active bank */ 1124 wcd938x_set_swr_clk_rate(component, rate, !bank); 1125 } 1126 break; 1127 case SND_SOC_DAPM_POST_PMD: 1128 if (strnstr(w->name, "ADC", sizeof("ADC"))) { 1129 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID); 1130 wcd938x_set_swr_clk_rate(component, rate, !bank); 1131 wcd938x_set_swr_clk_rate(component, rate, bank); 1132 } 1133 break; 1134 } 1135 1136 return 0; 1137 } 1138 1139 static int wcd938x_get_adc_mode(int val) 1140 { 1141 int ret = 0; 1142 1143 switch (val) { 1144 case ADC_MODE_INVALID: 1145 ret = ADC_MODE_VAL_NORMAL; 1146 break; 1147 case ADC_MODE_HIFI: 1148 ret = ADC_MODE_VAL_HIFI; 1149 break; 1150 case ADC_MODE_LO_HIF: 1151 ret = ADC_MODE_VAL_LO_HIF; 1152 break; 1153 case ADC_MODE_NORMAL: 1154 ret = ADC_MODE_VAL_NORMAL; 1155 break; 1156 case ADC_MODE_LP: 1157 ret = ADC_MODE_VAL_LP; 1158 break; 1159 case ADC_MODE_ULP1: 1160 ret = ADC_MODE_VAL_ULP1; 1161 break; 1162 case ADC_MODE_ULP2: 1163 ret = ADC_MODE_VAL_ULP2; 1164 break; 1165 default: 1166 ret = -EINVAL; 1167 break; 1168 } 1169 return ret; 1170 } 1171 1172 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w, 1173 struct snd_kcontrol *kcontrol, int event) 1174 { 1175 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1176 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1177 1178 switch (event) { 1179 case SND_SOC_DAPM_PRE_PMU: 1180 snd_soc_component_write_field(component, 1181 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1182 WCD938X_ANA_TX_CLK_EN_MASK, 1); 1183 snd_soc_component_write_field(component, 1184 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1185 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1186 set_bit(w->shift, &wcd938x->status_mask); 1187 break; 1188 case SND_SOC_DAPM_POST_PMD: 1189 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1190 WCD938X_ANA_TX_CLK_EN_MASK, 0); 1191 clear_bit(w->shift, &wcd938x->status_mask); 1192 break; 1193 } 1194 1195 return 0; 1196 } 1197 1198 static void wcd938x_tx_channel_config(struct snd_soc_component *component, 1199 int channel, int mode) 1200 { 1201 int reg, mask; 1202 1203 switch (channel) { 1204 case 0: 1205 reg = WCD938X_ANA_TX_CH2; 1206 mask = WCD938X_HPF1_INIT_MASK; 1207 break; 1208 case 1: 1209 reg = WCD938X_ANA_TX_CH2; 1210 mask = WCD938X_HPF2_INIT_MASK; 1211 break; 1212 case 2: 1213 reg = WCD938X_ANA_TX_CH4; 1214 mask = WCD938X_HPF3_INIT_MASK; 1215 break; 1216 case 3: 1217 reg = WCD938X_ANA_TX_CH4; 1218 mask = WCD938X_HPF4_INIT_MASK; 1219 break; 1220 default: 1221 return; 1222 } 1223 1224 snd_soc_component_write_field(component, reg, mask, mode); 1225 } 1226 1227 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w, 1228 struct snd_kcontrol *kcontrol, int event) 1229 { 1230 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1231 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1232 int mode; 1233 1234 switch (event) { 1235 case SND_SOC_DAPM_PRE_PMU: 1236 snd_soc_component_write_field(component, 1237 WCD938X_DIGITAL_CDC_REQ_CTL, 1238 WCD938X_FS_RATE_4P8_MASK, 1); 1239 snd_soc_component_write_field(component, 1240 WCD938X_DIGITAL_CDC_REQ_CTL, 1241 WCD938X_NO_NOTCH_MASK, 0); 1242 wcd938x_tx_channel_config(component, w->shift, 1); 1243 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]); 1244 if (mode < 0) { 1245 dev_info(component->dev, "Invalid ADC mode\n"); 1246 return -EINVAL; 1247 } 1248 switch (w->shift) { 1249 case 0: 1250 snd_soc_component_write_field(component, 1251 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1252 WCD938X_TXD0_MODE_MASK, mode); 1253 snd_soc_component_write_field(component, 1254 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1255 WCD938X_TXD0_CLK_EN_MASK, 1); 1256 break; 1257 case 1: 1258 snd_soc_component_write_field(component, 1259 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1260 WCD938X_TXD1_MODE_MASK, mode); 1261 snd_soc_component_write_field(component, 1262 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1263 WCD938X_TXD1_CLK_EN_MASK, 1); 1264 break; 1265 case 2: 1266 snd_soc_component_write_field(component, 1267 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1268 WCD938X_TXD2_MODE_MASK, mode); 1269 snd_soc_component_write_field(component, 1270 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1271 WCD938X_TXD2_CLK_EN_MASK, 1); 1272 break; 1273 case 3: 1274 snd_soc_component_write_field(component, 1275 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1276 WCD938X_TXD3_MODE_MASK, mode); 1277 snd_soc_component_write_field(component, 1278 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1279 WCD938X_TXD3_CLK_EN_MASK, 1); 1280 break; 1281 default: 1282 break; 1283 } 1284 1285 wcd938x_tx_channel_config(component, w->shift, 0); 1286 break; 1287 case SND_SOC_DAPM_POST_PMD: 1288 switch (w->shift) { 1289 case 0: 1290 snd_soc_component_write_field(component, 1291 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1292 WCD938X_TXD0_MODE_MASK, 0); 1293 snd_soc_component_write_field(component, 1294 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1295 WCD938X_TXD0_CLK_EN_MASK, 0); 1296 break; 1297 case 1: 1298 snd_soc_component_write_field(component, 1299 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 1300 WCD938X_TXD1_MODE_MASK, 0); 1301 snd_soc_component_write_field(component, 1302 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1303 WCD938X_TXD1_CLK_EN_MASK, 0); 1304 break; 1305 case 2: 1306 snd_soc_component_write_field(component, 1307 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1308 WCD938X_TXD2_MODE_MASK, 0); 1309 snd_soc_component_write_field(component, 1310 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1311 WCD938X_TXD2_CLK_EN_MASK, 0); 1312 break; 1313 case 3: 1314 snd_soc_component_write_field(component, 1315 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 1316 WCD938X_TXD3_MODE_MASK, 0); 1317 snd_soc_component_write_field(component, 1318 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1319 WCD938X_TXD3_CLK_EN_MASK, 0); 1320 break; 1321 default: 1322 break; 1323 } 1324 snd_soc_component_write_field(component, 1325 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1326 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0); 1327 break; 1328 } 1329 1330 return 0; 1331 } 1332 1333 static int wcd938x_micbias_control(struct snd_soc_component *component, 1334 int micb_num, int req, bool is_dapm) 1335 { 1336 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1337 int micb_index = micb_num - 1; 1338 u16 micb_reg; 1339 1340 switch (micb_num) { 1341 case MIC_BIAS_1: 1342 micb_reg = WCD938X_ANA_MICB1; 1343 break; 1344 case MIC_BIAS_2: 1345 micb_reg = WCD938X_ANA_MICB2; 1346 break; 1347 case MIC_BIAS_3: 1348 micb_reg = WCD938X_ANA_MICB3; 1349 break; 1350 case MIC_BIAS_4: 1351 micb_reg = WCD938X_ANA_MICB4; 1352 break; 1353 default: 1354 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 1355 __func__, micb_num); 1356 return -EINVAL; 1357 } 1358 1359 switch (req) { 1360 case MICB_PULLUP_ENABLE: 1361 wcd938x->pullup_ref[micb_index]++; 1362 if ((wcd938x->pullup_ref[micb_index] == 1) && 1363 (wcd938x->micb_ref[micb_index] == 0)) 1364 snd_soc_component_write_field(component, micb_reg, 1365 WCD938X_MICB_EN_MASK, 1366 WCD938X_MICB_PULL_UP); 1367 break; 1368 case MICB_PULLUP_DISABLE: 1369 if (wcd938x->pullup_ref[micb_index] > 0) 1370 wcd938x->pullup_ref[micb_index]--; 1371 1372 if ((wcd938x->pullup_ref[micb_index] == 0) && 1373 (wcd938x->micb_ref[micb_index] == 0)) 1374 snd_soc_component_write_field(component, micb_reg, 1375 WCD938X_MICB_EN_MASK, 0); 1376 break; 1377 case MICB_ENABLE: 1378 wcd938x->micb_ref[micb_index]++; 1379 if (wcd938x->micb_ref[micb_index] == 1) { 1380 snd_soc_component_write_field(component, 1381 WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 1382 WCD938X_TX_CLK_EN_MASK, 0xF); 1383 snd_soc_component_write_field(component, 1384 WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 1385 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1); 1386 snd_soc_component_write_field(component, 1387 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 1388 WCD938X_TX_SC_CLK_EN_MASK, 1); 1389 1390 snd_soc_component_write_field(component, micb_reg, 1391 WCD938X_MICB_EN_MASK, 1392 WCD938X_MICB_ENABLE); 1393 if (micb_num == MIC_BIAS_2) 1394 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1395 WCD_EVENT_POST_MICBIAS_2_ON); 1396 } 1397 if (micb_num == MIC_BIAS_2 && is_dapm) 1398 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1399 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 1400 1401 1402 break; 1403 case MICB_DISABLE: 1404 if (wcd938x->micb_ref[micb_index] > 0) 1405 wcd938x->micb_ref[micb_index]--; 1406 1407 if ((wcd938x->micb_ref[micb_index] == 0) && 1408 (wcd938x->pullup_ref[micb_index] > 0)) 1409 snd_soc_component_write_field(component, micb_reg, 1410 WCD938X_MICB_EN_MASK, 1411 WCD938X_MICB_PULL_UP); 1412 else if ((wcd938x->micb_ref[micb_index] == 0) && 1413 (wcd938x->pullup_ref[micb_index] == 0)) { 1414 if (micb_num == MIC_BIAS_2) 1415 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1416 WCD_EVENT_PRE_MICBIAS_2_OFF); 1417 1418 snd_soc_component_write_field(component, micb_reg, 1419 WCD938X_MICB_EN_MASK, 0); 1420 if (micb_num == MIC_BIAS_2) 1421 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1422 WCD_EVENT_POST_MICBIAS_2_OFF); 1423 } 1424 if (is_dapm && micb_num == MIC_BIAS_2) 1425 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, 1426 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 1427 break; 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 1434 struct snd_kcontrol *kcontrol, 1435 int event) 1436 { 1437 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1438 int micb_num = w->shift; 1439 1440 switch (event) { 1441 case SND_SOC_DAPM_PRE_PMU: 1442 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true); 1443 break; 1444 case SND_SOC_DAPM_POST_PMU: 1445 /* 1 msec delay as per HW requirement */ 1446 usleep_range(1000, 1100); 1447 break; 1448 case SND_SOC_DAPM_POST_PMD: 1449 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true); 1450 break; 1451 } 1452 1453 return 0; 1454 } 1455 1456 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w, 1457 struct snd_kcontrol *kcontrol, 1458 int event) 1459 { 1460 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1461 int micb_num = w->shift; 1462 1463 switch (event) { 1464 case SND_SOC_DAPM_PRE_PMU: 1465 wcd938x_micbias_control(component, micb_num, 1466 MICB_PULLUP_ENABLE, true); 1467 break; 1468 case SND_SOC_DAPM_POST_PMU: 1469 /* 1 msec delay as per HW requirement */ 1470 usleep_range(1000, 1100); 1471 break; 1472 case SND_SOC_DAPM_POST_PMD: 1473 wcd938x_micbias_control(component, micb_num, 1474 MICB_PULLUP_DISABLE, true); 1475 break; 1476 } 1477 1478 return 0; 1479 } 1480 1481 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol, 1482 struct snd_ctl_elem_value *ucontrol) 1483 { 1484 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1485 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1486 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1487 int path = e->shift_l; 1488 1489 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path]; 1490 1491 return 0; 1492 } 1493 1494 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol, 1495 struct snd_ctl_elem_value *ucontrol) 1496 { 1497 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1498 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1499 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1500 int path = e->shift_l; 1501 1502 if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0]) 1503 return 0; 1504 1505 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0]; 1506 1507 return 1; 1508 } 1509 1510 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol, 1511 struct snd_ctl_elem_value *ucontrol) 1512 { 1513 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1514 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1515 1516 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode; 1517 1518 return 0; 1519 } 1520 1521 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol, 1522 struct snd_ctl_elem_value *ucontrol) 1523 { 1524 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1525 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1526 1527 if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0]) 1528 return 0; 1529 1530 wcd938x->hph_mode = ucontrol->value.enumerated.item[0]; 1531 1532 return 1; 1533 } 1534 1535 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol, 1536 struct snd_ctl_elem_value *ucontrol) 1537 { 1538 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1539 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1540 1541 if (wcd938x->comp1_enable) { 1542 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n"); 1543 return -EINVAL; 1544 } 1545 1546 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL, 1547 WCD938X_EAR_GAIN_MASK, 1548 ucontrol->value.integer.value[0]); 1549 1550 return 1; 1551 } 1552 1553 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol, 1554 struct snd_ctl_elem_value *ucontrol) 1555 { 1556 1557 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1558 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1559 struct soc_mixer_control *mc; 1560 bool hphr; 1561 1562 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1563 hphr = mc->shift; 1564 1565 if (hphr) 1566 ucontrol->value.integer.value[0] = wcd938x->comp2_enable; 1567 else 1568 ucontrol->value.integer.value[0] = wcd938x->comp1_enable; 1569 1570 return 0; 1571 } 1572 1573 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol, 1574 struct snd_ctl_elem_value *ucontrol) 1575 { 1576 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1577 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1578 struct wcd938x_sdw_priv *wcd; 1579 int value = ucontrol->value.integer.value[0]; 1580 int portidx; 1581 struct soc_mixer_control *mc; 1582 bool hphr; 1583 1584 mc = (struct soc_mixer_control *)(kcontrol->private_value); 1585 hphr = mc->shift; 1586 1587 wcd = wcd938x->sdw_priv[AIF1_PB]; 1588 1589 if (hphr) 1590 wcd938x->comp2_enable = value; 1591 else 1592 wcd938x->comp1_enable = value; 1593 1594 portidx = wcd->ch_info[mc->reg].port_num; 1595 1596 if (value) 1597 wcd938x_connect_port(wcd, portidx, mc->reg, true); 1598 else 1599 wcd938x_connect_port(wcd, portidx, mc->reg, false); 1600 1601 return 1; 1602 } 1603 1604 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol, 1605 struct snd_ctl_elem_value *ucontrol) 1606 { 1607 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1608 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1609 1610 ucontrol->value.integer.value[0] = wcd938x->ldoh; 1611 1612 return 0; 1613 } 1614 1615 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol, 1616 struct snd_ctl_elem_value *ucontrol) 1617 { 1618 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1619 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1620 1621 if (wcd938x->ldoh == ucontrol->value.integer.value[0]) 1622 return 0; 1623 1624 wcd938x->ldoh = ucontrol->value.integer.value[0]; 1625 1626 return 1; 1627 } 1628 1629 static const char * const tx_mode_mux_text_wcd9380[] = { 1630 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1631 }; 1632 1633 static const char * const tx_mode_mux_text[] = { 1634 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP", 1635 "ADC_ULP1", "ADC_ULP2", 1636 }; 1637 1638 static const char * const rx_hph_mode_mux_text_wcd9380[] = { 1639 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB", 1640 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP", 1641 "CLS_AB_LOHIFI", 1642 }; 1643 1644 static const char * const rx_hph_mode_mux_text[] = { 1645 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI", 1646 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI", 1647 }; 1648 1649 static const char * const adc2_mux_text[] = { 1650 "INP2", "INP3" 1651 }; 1652 1653 static const char * const adc3_mux_text[] = { 1654 "INP4", "INP6" 1655 }; 1656 1657 static const char * const adc4_mux_text[] = { 1658 "INP5", "INP7" 1659 }; 1660 1661 static const char * const rdac3_mux_text[] = { 1662 "RX1", "RX3" 1663 }; 1664 1665 static const char * const hdr12_mux_text[] = { 1666 "NO_HDR12", "HDR12" 1667 }; 1668 1669 static const char * const hdr34_mux_text[] = { 1670 "NO_HDR34", "HDR34" 1671 }; 1672 1673 static const struct soc_enum tx0_mode_enum_wcd9380 = 1674 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1675 tx_mode_mux_text_wcd9380); 1676 1677 static const struct soc_enum tx1_mode_enum_wcd9380 = 1678 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1679 tx_mode_mux_text_wcd9380); 1680 1681 static const struct soc_enum tx2_mode_enum_wcd9380 = 1682 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1683 tx_mode_mux_text_wcd9380); 1684 1685 static const struct soc_enum tx3_mode_enum_wcd9380 = 1686 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380), 1687 tx_mode_mux_text_wcd9380); 1688 1689 static const struct soc_enum tx0_mode_enum_wcd9385 = 1690 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text), 1691 tx_mode_mux_text); 1692 1693 static const struct soc_enum tx1_mode_enum_wcd9385 = 1694 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text), 1695 tx_mode_mux_text); 1696 1697 static const struct soc_enum tx2_mode_enum_wcd9385 = 1698 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text), 1699 tx_mode_mux_text); 1700 1701 static const struct soc_enum tx3_mode_enum_wcd9385 = 1702 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text), 1703 tx_mode_mux_text); 1704 1705 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 = 1706 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380), 1707 rx_hph_mode_mux_text_wcd9380); 1708 1709 static const struct soc_enum rx_hph_mode_mux_enum = 1710 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 1711 rx_hph_mode_mux_text); 1712 1713 static const struct soc_enum adc2_enum = 1714 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7, 1715 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 1716 1717 static const struct soc_enum adc3_enum = 1718 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6, 1719 ARRAY_SIZE(adc3_mux_text), adc3_mux_text); 1720 1721 static const struct soc_enum adc4_enum = 1722 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5, 1723 ARRAY_SIZE(adc4_mux_text), adc4_mux_text); 1724 1725 static const struct soc_enum hdr12_enum = 1726 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4, 1727 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text); 1728 1729 static const struct soc_enum hdr34_enum = 1730 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3, 1731 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text); 1732 1733 static const struct soc_enum rdac3_enum = 1734 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0, 1735 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text); 1736 1737 static const struct snd_kcontrol_new adc1_switch[] = { 1738 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1739 }; 1740 1741 static const struct snd_kcontrol_new adc2_switch[] = { 1742 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1743 }; 1744 1745 static const struct snd_kcontrol_new adc3_switch[] = { 1746 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1747 }; 1748 1749 static const struct snd_kcontrol_new adc4_switch[] = { 1750 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1751 }; 1752 1753 static const struct snd_kcontrol_new dmic1_switch[] = { 1754 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1755 }; 1756 1757 static const struct snd_kcontrol_new dmic2_switch[] = { 1758 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1759 }; 1760 1761 static const struct snd_kcontrol_new dmic3_switch[] = { 1762 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1763 }; 1764 1765 static const struct snd_kcontrol_new dmic4_switch[] = { 1766 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1767 }; 1768 1769 static const struct snd_kcontrol_new dmic5_switch[] = { 1770 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1771 }; 1772 1773 static const struct snd_kcontrol_new dmic6_switch[] = { 1774 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1775 }; 1776 1777 static const struct snd_kcontrol_new dmic7_switch[] = { 1778 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1779 }; 1780 1781 static const struct snd_kcontrol_new dmic8_switch[] = { 1782 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1783 }; 1784 1785 static const struct snd_kcontrol_new ear_rdac_switch[] = { 1786 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1787 }; 1788 1789 static const struct snd_kcontrol_new aux_rdac_switch[] = { 1790 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1791 }; 1792 1793 static const struct snd_kcontrol_new hphl_rdac_switch[] = { 1794 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1795 }; 1796 1797 static const struct snd_kcontrol_new hphr_rdac_switch[] = { 1798 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0) 1799 }; 1800 1801 static const struct snd_kcontrol_new tx_adc2_mux = 1802 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); 1803 1804 static const struct snd_kcontrol_new tx_adc3_mux = 1805 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum); 1806 1807 static const struct snd_kcontrol_new tx_adc4_mux = 1808 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum); 1809 1810 static const struct snd_kcontrol_new tx_hdr12_mux = 1811 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum); 1812 1813 static const struct snd_kcontrol_new tx_hdr34_mux = 1814 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum); 1815 1816 static const struct snd_kcontrol_new rx_rdac3_mux = 1817 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum); 1818 1819 static const struct snd_kcontrol_new wcd9380_snd_controls[] = { 1820 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380, 1821 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1822 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380, 1823 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1824 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380, 1825 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1826 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380, 1827 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1828 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380, 1829 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1830 }; 1831 1832 static const struct snd_kcontrol_new wcd9385_snd_controls[] = { 1833 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 1834 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put), 1835 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385, 1836 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1837 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385, 1838 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1839 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385, 1840 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1841 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385, 1842 wcd938x_tx_mode_get, wcd938x_tx_mode_put), 1843 }; 1844 1845 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol, 1846 struct snd_ctl_elem_value *ucontrol) 1847 { 1848 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1849 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1850 struct wcd938x_sdw_priv *wcd; 1851 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1852 int dai_id = mixer->shift; 1853 int portidx, ch_idx = mixer->reg; 1854 1855 1856 wcd = wcd938x->sdw_priv[dai_id]; 1857 portidx = wcd->ch_info[ch_idx].port_num; 1858 1859 ucontrol->value.integer.value[0] = wcd->port_enable[portidx]; 1860 1861 return 0; 1862 } 1863 1864 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol, 1865 struct snd_ctl_elem_value *ucontrol) 1866 { 1867 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 1868 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp); 1869 struct wcd938x_sdw_priv *wcd; 1870 struct soc_mixer_control *mixer = 1871 (struct soc_mixer_control *)kcontrol->private_value; 1872 int ch_idx = mixer->reg; 1873 int portidx; 1874 int dai_id = mixer->shift; 1875 bool enable; 1876 1877 wcd = wcd938x->sdw_priv[dai_id]; 1878 1879 portidx = wcd->ch_info[ch_idx].port_num; 1880 if (ucontrol->value.integer.value[0]) 1881 enable = true; 1882 else 1883 enable = false; 1884 1885 wcd->port_enable[portidx] = enable; 1886 1887 wcd938x_connect_port(wcd, portidx, ch_idx, enable); 1888 1889 return 1; 1890 1891 } 1892 1893 /* MBHC related */ 1894 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component, 1895 bool enable) 1896 { 1897 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1, 1898 WCD938X_MBHC_CTL_RCO_EN_MASK, enable); 1899 } 1900 1901 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 1902 bool enable) 1903 { 1904 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT, 1905 WCD938X_ANA_MBHC_BIAS_EN, enable); 1906 } 1907 1908 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component, 1909 int *btn_low, int *btn_high, 1910 int num_btn, bool is_micbias) 1911 { 1912 int i, vth; 1913 1914 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 1915 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 1916 __func__, num_btn); 1917 return; 1918 } 1919 1920 for (i = 0; i < num_btn; i++) { 1921 vth = ((btn_high[i] * 2) / 25) & 0x3F; 1922 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i, 1923 WCD938X_MBHC_BTN_VTH_MASK, vth); 1924 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n", 1925 __func__, i, btn_high[i], vth); 1926 } 1927 } 1928 1929 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 1930 { 1931 u8 val; 1932 1933 if (micb_num == MIC_BIAS_2) { 1934 val = snd_soc_component_read_field(component, 1935 WCD938X_ANA_MICB2, 1936 WCD938X_MICB_EN_MASK); 1937 if (val == WCD938X_MICB_ENABLE) 1938 return true; 1939 } 1940 return false; 1941 } 1942 1943 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 1944 int pull_up_cur) 1945 { 1946 /* Default pull up current to 2uA */ 1947 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA) 1948 pull_up_cur = HS_PULLUP_I_2P0_UA; 1949 1950 snd_soc_component_write_field(component, 1951 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 1952 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur); 1953 } 1954 1955 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component, 1956 int micb_num, int req) 1957 { 1958 return wcd938x_micbias_control(component, micb_num, req, false); 1959 } 1960 1961 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component, 1962 bool enable) 1963 { 1964 if (enable) { 1965 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1966 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C); 1967 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1968 WCD938X_RAMP_EN_MASK, 1); 1969 } else { 1970 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1971 WCD938X_RAMP_EN_MASK, 0); 1972 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP, 1973 WCD938X_RAMP_SHIFT_CTRL_MASK, 0); 1974 } 1975 } 1976 1977 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv) 1978 { 1979 /* min micbias voltage is 1V and maximum is 2.85V */ 1980 if (micb_mv < 1000 || micb_mv > 2850) 1981 return -EINVAL; 1982 1983 return (micb_mv - 1000) / 50; 1984 } 1985 1986 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 1987 int req_volt, int micb_num) 1988 { 1989 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 1990 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 1991 1992 switch (micb_num) { 1993 case MIC_BIAS_1: 1994 micb_reg = WCD938X_ANA_MICB1; 1995 break; 1996 case MIC_BIAS_2: 1997 micb_reg = WCD938X_ANA_MICB2; 1998 break; 1999 case MIC_BIAS_3: 2000 micb_reg = WCD938X_ANA_MICB3; 2001 break; 2002 case MIC_BIAS_4: 2003 micb_reg = WCD938X_ANA_MICB4; 2004 break; 2005 default: 2006 return -EINVAL; 2007 } 2008 mutex_lock(&wcd938x->micb_lock); 2009 /* 2010 * If requested micbias voltage is same as current micbias 2011 * voltage, then just return. Otherwise, adjust voltage as 2012 * per requested value. If micbias is already enabled, then 2013 * to avoid slow micbias ramp-up or down enable pull-up 2014 * momentarily, change the micbias value and then re-enable 2015 * micbias. 2016 */ 2017 micb_en = snd_soc_component_read_field(component, micb_reg, 2018 WCD938X_MICB_EN_MASK); 2019 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2020 WCD938X_MICB_VOUT_MASK); 2021 2022 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt); 2023 if (req_vout_ctl < 0) { 2024 ret = -EINVAL; 2025 goto exit; 2026 } 2027 2028 if (cur_vout_ctl == req_vout_ctl) { 2029 ret = 0; 2030 goto exit; 2031 } 2032 2033 if (micb_en == WCD938X_MICB_ENABLE) 2034 snd_soc_component_write_field(component, micb_reg, 2035 WCD938X_MICB_EN_MASK, 2036 WCD938X_MICB_PULL_UP); 2037 2038 snd_soc_component_write_field(component, micb_reg, 2039 WCD938X_MICB_VOUT_MASK, 2040 req_vout_ctl); 2041 2042 if (micb_en == WCD938X_MICB_ENABLE) { 2043 snd_soc_component_write_field(component, micb_reg, 2044 WCD938X_MICB_EN_MASK, 2045 WCD938X_MICB_ENABLE); 2046 /* 2047 * Add 2ms delay as per HW requirement after enabling 2048 * micbias 2049 */ 2050 usleep_range(2000, 2100); 2051 } 2052 exit: 2053 mutex_unlock(&wcd938x->micb_lock); 2054 return ret; 2055 } 2056 2057 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2058 int micb_num, bool req_en) 2059 { 2060 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2061 int micb_mv; 2062 2063 if (micb_num != MIC_BIAS_2) 2064 return -EINVAL; 2065 /* 2066 * If device tree micbias level is already above the minimum 2067 * voltage needed to detect threshold microphone, then do 2068 * not change the micbias, just return. 2069 */ 2070 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2071 return 0; 2072 2073 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv; 2074 2075 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2076 } 2077 2078 static void wcd938x_mbhc_get_result_params(struct snd_soc_component *component, 2079 s16 *d1_a, u16 noff, 2080 int32_t *zdet) 2081 { 2082 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2083 int i; 2084 int val, val1; 2085 s16 c1; 2086 s32 x1, d1; 2087 int32_t denom; 2088 static const int minCode_param[] = { 2089 3277, 1639, 820, 410, 205, 103, 52, 26 2090 }; 2091 2092 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20); 2093 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) { 2094 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val); 2095 if (val & 0x80) 2096 break; 2097 } 2098 val = val << 0x8; 2099 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1); 2100 val |= val1; 2101 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00); 2102 x1 = WCD938X_MBHC_GET_X1(val); 2103 c1 = WCD938X_MBHC_GET_C1(val); 2104 /* If ramp is not complete, give additional 5ms */ 2105 if ((c1 < 2) && x1) 2106 usleep_range(5000, 5050); 2107 2108 if (!c1 || !x1) { 2109 dev_err(component->dev, "Impedance detect ramp error, c1=%d, x1=0x%x\n", 2110 c1, x1); 2111 goto ramp_down; 2112 } 2113 d1 = d1_a[c1]; 2114 denom = (x1 * d1) - (1 << (14 - noff)); 2115 if (denom > 0) 2116 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom; 2117 else if (x1 < minCode_param[noff]) 2118 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE; 2119 2120 dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d (milliohm)\n", 2121 __func__, d1, c1, x1, *zdet); 2122 ramp_down: 2123 i = 0; 2124 while (x1) { 2125 regmap_read(wcd938x->regmap, 2126 WCD938X_ANA_MBHC_RESULT_1, &val); 2127 regmap_read(wcd938x->regmap, 2128 WCD938X_ANA_MBHC_RESULT_2, &val1); 2129 val = val << 0x08; 2130 val |= val1; 2131 x1 = WCD938X_MBHC_GET_X1(val); 2132 i++; 2133 if (i == WCD938X_ZDET_NUM_MEASUREMENTS) 2134 break; 2135 } 2136 } 2137 2138 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component, 2139 struct wcd938x_mbhc_zdet_param *zdet_param, 2140 int32_t *zl, int32_t *zr, s16 *d1_a) 2141 { 2142 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2143 int32_t zdet = 0; 2144 2145 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2146 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2147 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5, 2148 WCD938X_VTH_MASK, zdet_param->btn5); 2149 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6, 2150 WCD938X_VTH_MASK, zdet_param->btn6); 2151 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7, 2152 WCD938X_VTH_MASK, zdet_param->btn7); 2153 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, 2154 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2155 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 2156 0x0F, zdet_param->nshift); 2157 2158 if (!zl) 2159 goto z_right; 2160 /* Start impedance measurement for HPH_L */ 2161 regmap_update_bits(wcd938x->regmap, 2162 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80); 2163 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n", 2164 __func__, zdet_param->noff); 2165 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2166 regmap_update_bits(wcd938x->regmap, 2167 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00); 2168 2169 *zl = zdet; 2170 2171 z_right: 2172 if (!zr) 2173 return; 2174 /* Start impedance measurement for HPH_R */ 2175 regmap_update_bits(wcd938x->regmap, 2176 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40); 2177 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n", 2178 __func__, zdet_param->noff); 2179 wcd938x_mbhc_get_result_params(component, d1_a, zdet_param->noff, &zdet); 2180 regmap_update_bits(wcd938x->regmap, 2181 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00); 2182 2183 *zr = zdet; 2184 } 2185 2186 static void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2187 int32_t *z_val, int flag_l_r) 2188 { 2189 s16 q1; 2190 int q1_cal; 2191 2192 if (*z_val < (WCD938X_ZDET_VAL_400/1000)) 2193 q1 = snd_soc_component_read(component, 2194 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r)); 2195 else 2196 q1 = snd_soc_component_read(component, 2197 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r)); 2198 if (q1 & 0x80) 2199 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2200 else 2201 q1_cal = (10000 + (q1 * 25)); 2202 if (q1_cal > 0) 2203 *z_val = ((*z_val) * 10000) / q1_cal; 2204 } 2205 2206 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2207 uint32_t *zl, uint32_t *zr) 2208 { 2209 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2210 s16 reg0, reg1, reg2, reg3, reg4; 2211 int32_t z1L, z1R, z1Ls; 2212 int zMono, z_diff1, z_diff2; 2213 bool is_fsm_disable = false; 2214 struct wcd938x_mbhc_zdet_param zdet_param[] = { 2215 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2216 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2217 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2218 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2219 }; 2220 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL; 2221 s16 d1_a[][4] = { 2222 {0, 30, 90, 30}, 2223 {0, 30, 30, 5}, 2224 {0, 30, 30, 5}, 2225 {0, 30, 30, 5}, 2226 }; 2227 s16 *d1 = NULL; 2228 2229 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5); 2230 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6); 2231 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7); 2232 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK); 2233 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL); 2234 2235 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) { 2236 is_fsm_disable = true; 2237 regmap_update_bits(wcd938x->regmap, 2238 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00); 2239 } 2240 2241 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2242 if (wcd938x->mbhc_cfg.hphl_swh) 2243 regmap_update_bits(wcd938x->regmap, 2244 WCD938X_ANA_MBHC_MECH, 0x80, 0x00); 2245 2246 /* Turn off 100k pull down on HPHL */ 2247 regmap_update_bits(wcd938x->regmap, 2248 WCD938X_ANA_MBHC_MECH, 0x01, 0x00); 2249 2250 /* Disable surge protection before impedance detection. 2251 * This is done to give correct value for high impedance. 2252 */ 2253 regmap_update_bits(wcd938x->regmap, 2254 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00); 2255 /* 1ms delay needed after disable surge protection */ 2256 usleep_range(1000, 1010); 2257 2258 /* First get impedance on Left */ 2259 d1 = d1_a[1]; 2260 zdet_param_ptr = &zdet_param[1]; 2261 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2262 2263 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2264 goto left_ch_impedance; 2265 2266 /* Second ramp for left ch */ 2267 if (z1L < WCD938X_ZDET_VAL_32) { 2268 zdet_param_ptr = &zdet_param[0]; 2269 d1 = d1_a[0]; 2270 } else if ((z1L > WCD938X_ZDET_VAL_400) && 2271 (z1L <= WCD938X_ZDET_VAL_1200)) { 2272 zdet_param_ptr = &zdet_param[2]; 2273 d1 = d1_a[2]; 2274 } else if (z1L > WCD938X_ZDET_VAL_1200) { 2275 zdet_param_ptr = &zdet_param[3]; 2276 d1 = d1_a[3]; 2277 } 2278 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2279 2280 left_ch_impedance: 2281 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2282 (z1L > WCD938X_ZDET_VAL_100K)) { 2283 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE; 2284 zdet_param_ptr = &zdet_param[1]; 2285 d1 = d1_a[1]; 2286 } else { 2287 *zl = z1L/1000; 2288 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0); 2289 } 2290 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2291 __func__, *zl); 2292 2293 /* Start of right impedance ramp and calculation */ 2294 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2295 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2296 if (((z1R > WCD938X_ZDET_VAL_1200) && 2297 (zdet_param_ptr->noff == 0x6)) || 2298 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE)) 2299 goto right_ch_impedance; 2300 /* Second ramp for right ch */ 2301 if (z1R < WCD938X_ZDET_VAL_32) { 2302 zdet_param_ptr = &zdet_param[0]; 2303 d1 = d1_a[0]; 2304 } else if ((z1R > WCD938X_ZDET_VAL_400) && 2305 (z1R <= WCD938X_ZDET_VAL_1200)) { 2306 zdet_param_ptr = &zdet_param[2]; 2307 d1 = d1_a[2]; 2308 } else if (z1R > WCD938X_ZDET_VAL_1200) { 2309 zdet_param_ptr = &zdet_param[3]; 2310 d1 = d1_a[3]; 2311 } 2312 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2313 } 2314 right_ch_impedance: 2315 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2316 (z1R > WCD938X_ZDET_VAL_100K)) { 2317 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE; 2318 } else { 2319 *zr = z1R/1000; 2320 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1); 2321 } 2322 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2323 __func__, *zr); 2324 2325 /* Mono/stereo detection */ 2326 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) && 2327 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) { 2328 dev_dbg(component->dev, 2329 "%s: plug type is invalid or extension cable\n", 2330 __func__); 2331 goto zdet_complete; 2332 } 2333 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2334 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) || 2335 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2336 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2337 dev_dbg(component->dev, 2338 "%s: Mono plug type with one ch floating or shorted to GND\n", 2339 __func__); 2340 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2341 goto zdet_complete; 2342 } 2343 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2344 WCD938X_HPHPA_GND_OVR_MASK, 1); 2345 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2346 WCD938X_HPHPA_GND_R_MASK, 1); 2347 if (*zl < (WCD938X_ZDET_VAL_32/1000)) 2348 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2349 else 2350 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2351 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2352 WCD938X_HPHPA_GND_R_MASK, 0); 2353 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST, 2354 WCD938X_HPHPA_GND_OVR_MASK, 0); 2355 z1Ls /= 1000; 2356 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2357 /* Parallel of left Z and 9 ohm pull down resistor */ 2358 zMono = ((*zl) * 9) / ((*zl) + 9); 2359 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2360 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2361 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2362 dev_dbg(component->dev, "%s: stereo plug type detected\n", 2363 __func__); 2364 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO); 2365 } else { 2366 dev_dbg(component->dev, "%s: MONO plug type detected\n", 2367 __func__); 2368 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO); 2369 } 2370 2371 /* Enable surge protection again after impedance detection */ 2372 regmap_update_bits(wcd938x->regmap, 2373 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0); 2374 zdet_complete: 2375 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0); 2376 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1); 2377 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2); 2378 /* Turn on 100k pull down on HPHL */ 2379 regmap_update_bits(wcd938x->regmap, 2380 WCD938X_ANA_MBHC_MECH, 0x01, 0x01); 2381 2382 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2383 if (wcd938x->mbhc_cfg.hphl_swh) 2384 regmap_update_bits(wcd938x->regmap, 2385 WCD938X_ANA_MBHC_MECH, 0x80, 0x80); 2386 2387 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2388 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3); 2389 if (is_fsm_disable) 2390 regmap_update_bits(wcd938x->regmap, 2391 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80); 2392 } 2393 2394 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2395 bool enable) 2396 { 2397 if (enable) { 2398 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2399 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1); 2400 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2401 WCD938X_MBHC_GND_DET_EN_MASK, 1); 2402 } else { 2403 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2404 WCD938X_MBHC_GND_DET_EN_MASK, 0); 2405 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH, 2406 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0); 2407 } 2408 } 2409 2410 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2411 bool enable) 2412 { 2413 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2414 WCD938X_HPHPA_GND_R_MASK, enable); 2415 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2, 2416 WCD938X_HPHPA_GND_L_MASK, enable); 2417 } 2418 2419 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component) 2420 { 2421 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2422 2423 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2424 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2425 WCD938X_M_RTH_CTL_MASK, R_OFF); 2426 return; 2427 } 2428 2429 /* Do not enable moisture detection if jack type is NC */ 2430 if (!wcd938x->mbhc_cfg.hphl_swh) { 2431 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2432 __func__); 2433 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2434 WCD938X_M_RTH_CTL_MASK, R_OFF); 2435 return; 2436 } 2437 2438 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2439 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2440 } 2441 2442 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable) 2443 { 2444 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2445 2446 if (enable) 2447 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2448 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref); 2449 else 2450 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2451 WCD938X_M_RTH_CTL_MASK, R_OFF); 2452 } 2453 2454 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component) 2455 { 2456 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2457 bool ret = false; 2458 2459 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) { 2460 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2461 WCD938X_M_RTH_CTL_MASK, R_OFF); 2462 goto done; 2463 } 2464 2465 /* Do not enable moisture detection if jack type is NC */ 2466 if (!wcd938x->mbhc_cfg.hphl_swh) { 2467 dev_dbg(component->dev, "%s: disable moisture detection for NC\n", 2468 __func__); 2469 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2, 2470 WCD938X_M_RTH_CTL_MASK, R_OFF); 2471 goto done; 2472 } 2473 2474 /* 2475 * If moisture_en is already enabled, then skip to plug type 2476 * detection. 2477 */ 2478 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK)) 2479 goto done; 2480 2481 wcd938x_mbhc_moisture_detect_en(component, true); 2482 /* Read moisture comparator status */ 2483 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS) 2484 & 0x20) ? 0 : 1); 2485 2486 done: 2487 return ret; 2488 2489 } 2490 2491 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component, 2492 bool enable) 2493 { 2494 snd_soc_component_write_field(component, 2495 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 2496 WCD938X_MOISTURE_EN_POLLING_MASK, enable); 2497 } 2498 2499 static const struct wcd_mbhc_cb mbhc_cb = { 2500 .clk_setup = wcd938x_mbhc_clk_setup, 2501 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control, 2502 .set_btn_thr = wcd938x_mbhc_program_btn_thr, 2503 .micbias_enable_status = wcd938x_mbhc_micb_en_status, 2504 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control, 2505 .mbhc_micbias_control = wcd938x_mbhc_request_micbias, 2506 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control, 2507 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic, 2508 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance, 2509 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl, 2510 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl, 2511 .mbhc_moisture_config = wcd938x_mbhc_moisture_config, 2512 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status, 2513 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl, 2514 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en, 2515 }; 2516 2517 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol, 2518 struct snd_ctl_elem_value *ucontrol) 2519 { 2520 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2521 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2522 2523 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc); 2524 2525 return 0; 2526 } 2527 2528 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2529 struct snd_ctl_elem_value *ucontrol) 2530 { 2531 uint32_t zl, zr; 2532 bool hphr; 2533 struct soc_mixer_control *mc; 2534 struct snd_soc_component *component = 2535 snd_soc_kcontrol_component(kcontrol); 2536 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2537 2538 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2539 hphr = mc->shift; 2540 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr); 2541 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2542 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2543 2544 return 0; 2545 } 2546 2547 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 2548 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 2549 wcd938x_get_hph_type, NULL), 2550 }; 2551 2552 static const struct snd_kcontrol_new impedance_detect_controls[] = { 2553 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 2554 wcd938x_hph_impedance_get, NULL), 2555 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 2556 wcd938x_hph_impedance_get, NULL), 2557 }; 2558 2559 static int wcd938x_mbhc_init(struct snd_soc_component *component) 2560 { 2561 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2562 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids; 2563 2564 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2565 WCD938X_IRQ_MBHC_SW_DET); 2566 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2567 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET); 2568 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2569 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET); 2570 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2571 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 2572 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip, 2573 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET); 2574 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2575 WCD938X_IRQ_HPHL_OCP_INT); 2576 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip, 2577 WCD938X_IRQ_HPHR_OCP_INT); 2578 2579 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 2580 if (IS_ERR(wcd938x->wcd_mbhc)) 2581 return PTR_ERR(wcd938x->wcd_mbhc); 2582 2583 snd_soc_add_component_controls(component, impedance_detect_controls, 2584 ARRAY_SIZE(impedance_detect_controls)); 2585 snd_soc_add_component_controls(component, hph_type_detect_controls, 2586 ARRAY_SIZE(hph_type_detect_controls)); 2587 2588 return 0; 2589 } 2590 2591 static void wcd938x_mbhc_deinit(struct snd_soc_component *component) 2592 { 2593 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 2594 2595 wcd_mbhc_deinit(wcd938x->wcd_mbhc); 2596 } 2597 2598 /* END MBHC */ 2599 2600 static const struct snd_kcontrol_new wcd938x_snd_controls[] = { 2601 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0, 2602 wcd938x_get_compander, wcd938x_set_compander), 2603 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0, 2604 wcd938x_get_compander, wcd938x_set_compander), 2605 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0, 2606 wcd938x_get_swr_port, wcd938x_set_swr_port), 2607 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0, 2608 wcd938x_get_swr_port, wcd938x_set_swr_port), 2609 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0, 2610 wcd938x_get_swr_port, wcd938x_set_swr_port), 2611 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0, 2612 wcd938x_get_swr_port, wcd938x_set_swr_port), 2613 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0, 2614 wcd938x_get_swr_port, wcd938x_set_swr_port), 2615 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0, 2616 wcd938x_get_swr_port, wcd938x_set_swr_port), 2617 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 1, line_gain), 2618 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 1, line_gain), 2619 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL, 2620 2, 0x10, 0, ear_pa_gain), 2621 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0, 2622 wcd938x_get_swr_port, wcd938x_set_swr_port), 2623 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0, 2624 wcd938x_get_swr_port, wcd938x_set_swr_port), 2625 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0, 2626 wcd938x_get_swr_port, wcd938x_set_swr_port), 2627 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0, 2628 wcd938x_get_swr_port, wcd938x_set_swr_port), 2629 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0, 2630 wcd938x_get_swr_port, wcd938x_set_swr_port), 2631 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0, 2632 wcd938x_get_swr_port, wcd938x_set_swr_port), 2633 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0, 2634 wcd938x_get_swr_port, wcd938x_set_swr_port), 2635 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0, 2636 wcd938x_get_swr_port, wcd938x_set_swr_port), 2637 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0, 2638 wcd938x_get_swr_port, wcd938x_set_swr_port), 2639 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0, 2640 wcd938x_get_swr_port, wcd938x_set_swr_port), 2641 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0, 2642 wcd938x_get_swr_port, wcd938x_set_swr_port), 2643 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0, 2644 wcd938x_get_swr_port, wcd938x_set_swr_port), 2645 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0, 2646 wcd938x_get_swr_port, wcd938x_set_swr_port), 2647 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0, 2648 wcd938x_ldoh_get, wcd938x_ldoh_put), 2649 2650 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain), 2651 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain), 2652 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain), 2653 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain), 2654 }; 2655 2656 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { 2657 2658 /*input widgets*/ 2659 SND_SOC_DAPM_INPUT("AMIC1"), 2660 SND_SOC_DAPM_INPUT("AMIC2"), 2661 SND_SOC_DAPM_INPUT("AMIC3"), 2662 SND_SOC_DAPM_INPUT("AMIC4"), 2663 SND_SOC_DAPM_INPUT("AMIC5"), 2664 SND_SOC_DAPM_INPUT("AMIC6"), 2665 SND_SOC_DAPM_INPUT("AMIC7"), 2666 SND_SOC_DAPM_MIC("Analog Mic1", NULL), 2667 SND_SOC_DAPM_MIC("Analog Mic2", NULL), 2668 SND_SOC_DAPM_MIC("Analog Mic3", NULL), 2669 SND_SOC_DAPM_MIC("Analog Mic4", NULL), 2670 SND_SOC_DAPM_MIC("Analog Mic5", NULL), 2671 2672 /*tx widgets*/ 2673 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0, 2674 wcd938x_codec_enable_adc, 2675 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2676 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0, 2677 wcd938x_codec_enable_adc, 2678 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2679 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0, 2680 wcd938x_codec_enable_adc, 2681 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2682 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0, 2683 wcd938x_codec_enable_adc, 2684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2685 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 2686 wcd938x_codec_enable_dmic, 2687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2688 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0, 2689 wcd938x_codec_enable_dmic, 2690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2691 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0, 2692 wcd938x_codec_enable_dmic, 2693 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2694 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0, 2695 wcd938x_codec_enable_dmic, 2696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2697 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0, 2698 wcd938x_codec_enable_dmic, 2699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2700 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0, 2701 wcd938x_codec_enable_dmic, 2702 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2703 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0, 2704 wcd938x_codec_enable_dmic, 2705 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2706 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0, 2707 wcd938x_codec_enable_dmic, 2708 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2709 2710 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, 2711 NULL, 0, wcd938x_adc_enable_req, 2712 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2713 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, 2714 NULL, 0, wcd938x_adc_enable_req, 2715 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2716 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, 2717 NULL, 0, wcd938x_adc_enable_req, 2718 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2719 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0, 2720 wcd938x_adc_enable_req, 2721 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2722 2723 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 2724 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux), 2725 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux), 2726 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux), 2727 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux), 2728 2729 /*tx mixers*/ 2730 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch, 2731 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl, 2732 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2733 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch, 2734 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl, 2735 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2736 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch, 2737 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl, 2738 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2739 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch, 2740 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, 2741 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2742 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch, 2743 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, 2744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2745 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch, 2746 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, 2747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2748 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch, 2749 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, 2750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2751 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch, 2752 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, 2753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2754 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch, 2755 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, 2756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2757 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch, 2758 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, 2759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2760 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch, 2761 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, 2762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2763 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch, 2764 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, 2765 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2766 /* micbias widgets*/ 2767 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2768 wcd938x_codec_enable_micbias, 2769 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2770 SND_SOC_DAPM_POST_PMD), 2771 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2772 wcd938x_codec_enable_micbias, 2773 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2774 SND_SOC_DAPM_POST_PMD), 2775 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2776 wcd938x_codec_enable_micbias, 2777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2778 SND_SOC_DAPM_POST_PMD), 2779 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2780 wcd938x_codec_enable_micbias, 2781 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2782 SND_SOC_DAPM_POST_PMD), 2783 2784 /* micbias pull up widgets*/ 2785 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 2786 wcd938x_codec_enable_micbias_pullup, 2787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2788 SND_SOC_DAPM_POST_PMD), 2789 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 2790 wcd938x_codec_enable_micbias_pullup, 2791 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2792 SND_SOC_DAPM_POST_PMD), 2793 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 2794 wcd938x_codec_enable_micbias_pullup, 2795 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2796 SND_SOC_DAPM_POST_PMD), 2797 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 2798 wcd938x_codec_enable_micbias_pullup, 2799 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2800 SND_SOC_DAPM_POST_PMD), 2801 2802 /*output widgets tx*/ 2803 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"), 2804 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"), 2805 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"), 2806 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"), 2807 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"), 2808 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"), 2809 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"), 2810 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"), 2811 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"), 2812 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"), 2813 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"), 2814 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"), 2815 2816 SND_SOC_DAPM_INPUT("IN1_HPHL"), 2817 SND_SOC_DAPM_INPUT("IN2_HPHR"), 2818 SND_SOC_DAPM_INPUT("IN3_AUX"), 2819 2820 /*rx widgets*/ 2821 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0, 2822 wcd938x_codec_enable_ear_pa, 2823 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2824 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2825 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0, 2826 wcd938x_codec_enable_aux_pa, 2827 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2828 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2829 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0, 2830 wcd938x_codec_enable_hphl_pa, 2831 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2832 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2833 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0, 2834 wcd938x_codec_enable_hphr_pa, 2835 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2836 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2837 2838 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0, 2839 wcd938x_codec_hphl_dac_event, 2840 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2841 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2842 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0, 2843 wcd938x_codec_hphr_dac_event, 2844 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2845 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2846 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0, 2847 wcd938x_codec_ear_dac_event, 2848 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2849 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2850 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0, 2851 wcd938x_codec_aux_dac_event, 2852 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2853 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 2854 2855 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux), 2856 2857 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0), 2858 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0, 2859 wcd938x_codec_enable_rxclk, 2860 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2861 SND_SOC_DAPM_POST_PMD), 2862 2863 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0), 2864 2865 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2866 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2867 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0), 2868 2869 /* rx mixer widgets*/ 2870 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0, 2871 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)), 2872 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0, 2873 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)), 2874 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0, 2875 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)), 2876 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0, 2877 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)), 2878 2879 /*output widgets rx*/ 2880 SND_SOC_DAPM_OUTPUT("EAR"), 2881 SND_SOC_DAPM_OUTPUT("AUX"), 2882 SND_SOC_DAPM_OUTPUT("HPHL"), 2883 SND_SOC_DAPM_OUTPUT("HPHR"), 2884 2885 }; 2886 2887 static const struct snd_soc_dapm_route wcd938x_audio_map[] = { 2888 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"}, 2889 {"ADC1_MIXER", "Switch", "ADC1 REQ"}, 2890 {"ADC1 REQ", NULL, "ADC1"}, 2891 {"ADC1", NULL, "AMIC1"}, 2892 2893 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"}, 2894 {"ADC2_MIXER", "Switch", "ADC2 REQ"}, 2895 {"ADC2 REQ", NULL, "ADC2"}, 2896 {"ADC2", NULL, "HDR12 MUX"}, 2897 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"}, 2898 {"HDR12 MUX", "HDR12", "AMIC1"}, 2899 {"ADC2 MUX", "INP3", "AMIC3"}, 2900 {"ADC2 MUX", "INP2", "AMIC2"}, 2901 2902 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"}, 2903 {"ADC3_MIXER", "Switch", "ADC3 REQ"}, 2904 {"ADC3 REQ", NULL, "ADC3"}, 2905 {"ADC3", NULL, "HDR34 MUX"}, 2906 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"}, 2907 {"HDR34 MUX", "HDR34", "AMIC5"}, 2908 {"ADC3 MUX", "INP4", "AMIC4"}, 2909 {"ADC3 MUX", "INP6", "AMIC6"}, 2910 2911 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"}, 2912 {"ADC4_MIXER", "Switch", "ADC4 REQ"}, 2913 {"ADC4 REQ", NULL, "ADC4"}, 2914 {"ADC4", NULL, "ADC4 MUX"}, 2915 {"ADC4 MUX", "INP5", "AMIC5"}, 2916 {"ADC4 MUX", "INP7", "AMIC7"}, 2917 2918 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"}, 2919 {"DMIC1_MIXER", "Switch", "DMIC1"}, 2920 2921 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"}, 2922 {"DMIC2_MIXER", "Switch", "DMIC2"}, 2923 2924 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"}, 2925 {"DMIC3_MIXER", "Switch", "DMIC3"}, 2926 2927 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"}, 2928 {"DMIC4_MIXER", "Switch", "DMIC4"}, 2929 2930 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"}, 2931 {"DMIC5_MIXER", "Switch", "DMIC5"}, 2932 2933 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"}, 2934 {"DMIC6_MIXER", "Switch", "DMIC6"}, 2935 2936 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"}, 2937 {"DMIC7_MIXER", "Switch", "DMIC7"}, 2938 2939 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"}, 2940 {"DMIC8_MIXER", "Switch", "DMIC8"}, 2941 2942 {"IN1_HPHL", NULL, "VDD_BUCK"}, 2943 {"IN1_HPHL", NULL, "CLS_H_PORT"}, 2944 2945 {"RX1", NULL, "IN1_HPHL"}, 2946 {"RX1", NULL, "RXCLK"}, 2947 {"RDAC1", NULL, "RX1"}, 2948 {"HPHL_RDAC", "Switch", "RDAC1"}, 2949 {"HPHL PGA", NULL, "HPHL_RDAC"}, 2950 {"HPHL", NULL, "HPHL PGA"}, 2951 2952 {"IN2_HPHR", NULL, "VDD_BUCK"}, 2953 {"IN2_HPHR", NULL, "CLS_H_PORT"}, 2954 {"RX2", NULL, "IN2_HPHR"}, 2955 {"RDAC2", NULL, "RX2"}, 2956 {"RX2", NULL, "RXCLK"}, 2957 {"HPHR_RDAC", "Switch", "RDAC2"}, 2958 {"HPHR PGA", NULL, "HPHR_RDAC"}, 2959 {"HPHR", NULL, "HPHR PGA"}, 2960 2961 {"IN3_AUX", NULL, "VDD_BUCK"}, 2962 {"IN3_AUX", NULL, "CLS_H_PORT"}, 2963 {"RX3", NULL, "IN3_AUX"}, 2964 {"RDAC4", NULL, "RX3"}, 2965 {"RX3", NULL, "RXCLK"}, 2966 {"AUX_RDAC", "Switch", "RDAC4"}, 2967 {"AUX PGA", NULL, "AUX_RDAC"}, 2968 {"AUX", NULL, "AUX PGA"}, 2969 2970 {"RDAC3_MUX", "RX3", "RX3"}, 2971 {"RDAC3_MUX", "RX1", "RX1"}, 2972 {"RDAC3", NULL, "RDAC3_MUX"}, 2973 {"EAR_RDAC", "Switch", "RDAC3"}, 2974 {"EAR PGA", NULL, "EAR_RDAC"}, 2975 {"EAR", NULL, "EAR PGA"}, 2976 }; 2977 2978 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x) 2979 { 2980 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2981 2982 /* set micbias voltage */ 2983 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv); 2984 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv); 2985 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv); 2986 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv); 2987 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0) 2988 return -EINVAL; 2989 2990 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 2991 WCD938X_MICB_VOUT_MASK, vout_ctl_1); 2992 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 2993 WCD938X_MICB_VOUT_MASK, vout_ctl_2); 2994 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 2995 WCD938X_MICB_VOUT_MASK, vout_ctl_3); 2996 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 2997 WCD938X_MICB_VOUT_MASK, vout_ctl_4); 2998 2999 return 0; 3000 } 3001 3002 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data) 3003 { 3004 return IRQ_HANDLED; 3005 } 3006 3007 static const struct irq_chip wcd_irq_chip = { 3008 .name = "WCD938x", 3009 }; 3010 3011 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq, 3012 irq_hw_number_t hw) 3013 { 3014 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq); 3015 irq_set_nested_thread(virq, 1); 3016 irq_set_noprobe(virq); 3017 3018 return 0; 3019 } 3020 3021 static const struct irq_domain_ops wcd_domain_ops = { 3022 .map = wcd_irq_chip_map, 3023 }; 3024 3025 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev) 3026 { 3027 3028 wcd->virq = irq_domain_create_linear(NULL, 1, &wcd_domain_ops, NULL); 3029 if (!(wcd->virq)) { 3030 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__); 3031 return -EINVAL; 3032 } 3033 3034 return devm_regmap_add_irq_chip(dev, wcd->regmap, 3035 irq_create_mapping(wcd->virq, 0), 3036 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip, 3037 &wcd->irq_chip); 3038 } 3039 3040 static int wcd938x_soc_codec_probe(struct snd_soc_component *component) 3041 { 3042 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3043 struct sdw_slave *tx_sdw_dev = wcd938x->tx_sdw_dev; 3044 struct device *dev = component->dev; 3045 unsigned long time_left; 3046 int ret, i; 3047 3048 time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete, 3049 msecs_to_jiffies(2000)); 3050 if (!time_left) { 3051 dev_err(dev, "soundwire device init timeout\n"); 3052 return -ETIMEDOUT; 3053 } 3054 3055 snd_soc_component_init_regmap(component, wcd938x->regmap); 3056 3057 ret = pm_runtime_resume_and_get(dev); 3058 if (ret < 0) 3059 return ret; 3060 3061 wcd938x->variant = snd_soc_component_read_field(component, 3062 WCD938X_DIGITAL_EFUSE_REG_0, 3063 WCD938X_ID_MASK); 3064 3065 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X); 3066 if (IS_ERR(wcd938x->clsh_info)) { 3067 pm_runtime_put(dev); 3068 return PTR_ERR(wcd938x->clsh_info); 3069 } 3070 3071 wcd938x_io_init(wcd938x); 3072 /* Set all interrupts as edge triggered */ 3073 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) { 3074 regmap_write(wcd938x->regmap, 3075 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0); 3076 } 3077 3078 pm_runtime_put(dev); 3079 3080 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3081 WCD938X_IRQ_HPHR_PDM_WD_INT); 3082 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3083 WCD938X_IRQ_HPHL_PDM_WD_INT); 3084 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip, 3085 WCD938X_IRQ_AUX_PDM_WD_INT); 3086 3087 /* Request for watchdog interrupt */ 3088 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3089 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3090 "HPHR PDM WD INT", wcd938x); 3091 if (ret) { 3092 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret); 3093 goto err_free_clsh_ctrl; 3094 } 3095 3096 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3097 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3098 "HPHL PDM WD INT", wcd938x); 3099 if (ret) { 3100 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret); 3101 goto err_free_hphr_pdm_wd_int; 3102 } 3103 3104 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq, 3105 IRQF_ONESHOT | IRQF_TRIGGER_RISING, 3106 "AUX PDM WD INT", wcd938x); 3107 if (ret) { 3108 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret); 3109 goto err_free_hphl_pdm_wd_int; 3110 } 3111 3112 /* Disable watchdog interrupt for HPH and AUX */ 3113 disable_irq_nosync(wcd938x->hphr_pdm_wd_int); 3114 disable_irq_nosync(wcd938x->hphl_pdm_wd_int); 3115 disable_irq_nosync(wcd938x->aux_pdm_wd_int); 3116 3117 switch (wcd938x->variant) { 3118 case WCD9380: 3119 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls, 3120 ARRAY_SIZE(wcd9380_snd_controls)); 3121 if (ret < 0) { 3122 dev_err(component->dev, 3123 "%s: Failed to add snd ctrls for variant: %d\n", 3124 __func__, wcd938x->variant); 3125 goto err_free_aux_pdm_wd_int; 3126 } 3127 break; 3128 case WCD9385: 3129 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls, 3130 ARRAY_SIZE(wcd9385_snd_controls)); 3131 if (ret < 0) { 3132 dev_err(component->dev, 3133 "%s: Failed to add snd ctrls for variant: %d\n", 3134 __func__, wcd938x->variant); 3135 goto err_free_aux_pdm_wd_int; 3136 } 3137 break; 3138 default: 3139 break; 3140 } 3141 3142 ret = wcd938x_mbhc_init(component); 3143 if (ret) { 3144 dev_err(component->dev, "mbhc initialization failed\n"); 3145 goto err_free_aux_pdm_wd_int; 3146 } 3147 3148 return 0; 3149 3150 err_free_aux_pdm_wd_int: 3151 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3152 err_free_hphl_pdm_wd_int: 3153 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3154 err_free_hphr_pdm_wd_int: 3155 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3156 err_free_clsh_ctrl: 3157 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3158 3159 return ret; 3160 } 3161 3162 static void wcd938x_soc_codec_remove(struct snd_soc_component *component) 3163 { 3164 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component); 3165 3166 wcd938x_mbhc_deinit(component); 3167 3168 free_irq(wcd938x->aux_pdm_wd_int, wcd938x); 3169 free_irq(wcd938x->hphl_pdm_wd_int, wcd938x); 3170 free_irq(wcd938x->hphr_pdm_wd_int, wcd938x); 3171 3172 wcd_clsh_ctrl_free(wcd938x->clsh_info); 3173 } 3174 3175 static int wcd938x_codec_set_jack(struct snd_soc_component *comp, 3176 struct snd_soc_jack *jack, void *data) 3177 { 3178 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev); 3179 3180 if (jack) 3181 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack); 3182 else 3183 wcd_mbhc_stop(wcd->wcd_mbhc); 3184 3185 return 0; 3186 } 3187 3188 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = { 3189 .name = "wcd938x_codec", 3190 .probe = wcd938x_soc_codec_probe, 3191 .remove = wcd938x_soc_codec_remove, 3192 .controls = wcd938x_snd_controls, 3193 .num_controls = ARRAY_SIZE(wcd938x_snd_controls), 3194 .dapm_widgets = wcd938x_dapm_widgets, 3195 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets), 3196 .dapm_routes = wcd938x_audio_map, 3197 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map), 3198 .set_jack = wcd938x_codec_set_jack, 3199 .endianness = 1, 3200 }; 3201 3202 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd) 3203 { 3204 struct device_node *np = dev->of_node; 3205 u32 prop_val = 0; 3206 int rc = 0; 3207 3208 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val); 3209 if (!rc) 3210 wcd->micb1_mv = prop_val/1000; 3211 else 3212 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__); 3213 3214 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val); 3215 if (!rc) 3216 wcd->micb2_mv = prop_val/1000; 3217 else 3218 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__); 3219 3220 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val); 3221 if (!rc) 3222 wcd->micb3_mv = prop_val/1000; 3223 else 3224 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__); 3225 3226 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val); 3227 if (!rc) 3228 wcd->micb4_mv = prop_val/1000; 3229 else 3230 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__); 3231 } 3232 3233 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component, bool active) 3234 { 3235 int value; 3236 3237 struct wcd938x_priv *wcd938x; 3238 3239 wcd938x = snd_soc_component_get_drvdata(component); 3240 3241 value = gpiod_get_value(wcd938x->us_euro_gpio); 3242 3243 gpiod_set_value(wcd938x->us_euro_gpio, !value); 3244 3245 return true; 3246 } 3247 3248 3249 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev) 3250 { 3251 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg; 3252 int ret; 3253 3254 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0); 3255 if (wcd938x->reset_gpio < 0) 3256 return dev_err_probe(dev, wcd938x->reset_gpio, 3257 "Failed to get reset gpio\n"); 3258 3259 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro", 3260 GPIOD_OUT_LOW); 3261 if (IS_ERR(wcd938x->us_euro_gpio)) 3262 return dev_err_probe(dev, PTR_ERR(wcd938x->us_euro_gpio), 3263 "us-euro swap Control GPIO not found\n"); 3264 3265 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic; 3266 3267 wcd938x->supplies[0].supply = "vdd-rxtx"; 3268 wcd938x->supplies[1].supply = "vdd-io"; 3269 wcd938x->supplies[2].supply = "vdd-buck"; 3270 wcd938x->supplies[3].supply = "vdd-mic-bias"; 3271 3272 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies); 3273 if (ret) 3274 return dev_err_probe(dev, ret, "Failed to get supplies\n"); 3275 3276 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3277 if (ret) { 3278 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3279 return dev_err_probe(dev, ret, "Failed to enable supplies\n"); 3280 } 3281 3282 wcd938x_dt_parse_micbias_info(dev, wcd938x); 3283 3284 cfg->mbhc_micbias = MIC_BIAS_2; 3285 cfg->anc_micbias = MIC_BIAS_2; 3286 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 3287 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS; 3288 cfg->micb_mv = wcd938x->micb2_mv; 3289 cfg->linein_th = 5000; 3290 cfg->hs_thr = 1700; 3291 cfg->hph_thr = 50; 3292 3293 wcd_dt_parse_mbhc_data(dev, cfg); 3294 3295 return 0; 3296 } 3297 3298 static int wcd938x_reset(struct wcd938x_priv *wcd938x) 3299 { 3300 gpio_direction_output(wcd938x->reset_gpio, 0); 3301 /* 20us sleep required after pulling the reset gpio to LOW */ 3302 usleep_range(20, 30); 3303 gpio_set_value(wcd938x->reset_gpio, 1); 3304 /* 20us sleep required after pulling the reset gpio to HIGH */ 3305 usleep_range(20, 30); 3306 3307 return 0; 3308 } 3309 3310 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream, 3311 struct snd_pcm_hw_params *params, 3312 struct snd_soc_dai *dai) 3313 { 3314 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3315 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3316 3317 return wcd938x_sdw_hw_params(wcd, substream, params, dai); 3318 } 3319 3320 static int wcd938x_codec_free(struct snd_pcm_substream *substream, 3321 struct snd_soc_dai *dai) 3322 { 3323 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3324 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3325 3326 return wcd938x_sdw_free(wcd, substream, dai); 3327 } 3328 3329 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai, 3330 void *stream, int direction) 3331 { 3332 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev); 3333 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id]; 3334 3335 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction); 3336 3337 } 3338 3339 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = { 3340 .hw_params = wcd938x_codec_hw_params, 3341 .hw_free = wcd938x_codec_free, 3342 .set_stream = wcd938x_codec_set_sdw_stream, 3343 }; 3344 3345 static struct snd_soc_dai_driver wcd938x_dais[] = { 3346 [AIF1_PB] = { 3347 .name = "wcd938x-sdw-rx", 3348 .playback = { 3349 .stream_name = "WCD AIF1 Playback", 3350 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK, 3351 .formats = WCD938X_FORMATS_S16_S24_LE, 3352 .rate_max = 192000, 3353 .rate_min = 8000, 3354 .channels_min = 1, 3355 .channels_max = 2, 3356 }, 3357 .ops = &wcd938x_sdw_dai_ops, 3358 }, 3359 [AIF1_CAP] = { 3360 .name = "wcd938x-sdw-tx", 3361 .capture = { 3362 .stream_name = "WCD AIF1 Capture", 3363 .rates = WCD938X_RATES_MASK, 3364 .formats = SNDRV_PCM_FMTBIT_S16_LE, 3365 .rate_min = 8000, 3366 .rate_max = 192000, 3367 .channels_min = 1, 3368 .channels_max = 4, 3369 }, 3370 .ops = &wcd938x_sdw_dai_ops, 3371 }, 3372 }; 3373 3374 static int wcd938x_bind(struct device *dev) 3375 { 3376 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3377 int ret; 3378 3379 ret = component_bind_all(dev, wcd938x); 3380 if (ret) { 3381 dev_err(dev, "%s: Slave bind failed, ret = %d\n", 3382 __func__, ret); 3383 return ret; 3384 } 3385 3386 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode); 3387 if (!wcd938x->rxdev) { 3388 dev_err(dev, "could not find slave with matching of node\n"); 3389 ret = -EINVAL; 3390 goto err_unbind; 3391 } 3392 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev); 3393 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x; 3394 3395 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode); 3396 if (!wcd938x->txdev) { 3397 dev_err(dev, "could not find txslave with matching of node\n"); 3398 ret = -EINVAL; 3399 goto err_put_rxdev; 3400 } 3401 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev); 3402 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x; 3403 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev); 3404 3405 /* As TX is main CSR reg interface, which should not be suspended first. 3406 * expicilty add the dependency link */ 3407 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS | 3408 DL_FLAG_PM_RUNTIME)) { 3409 dev_err(dev, "could not devlink tx and rx\n"); 3410 ret = -EINVAL; 3411 goto err_put_txdev; 3412 } 3413 3414 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS | 3415 DL_FLAG_PM_RUNTIME)) { 3416 dev_err(dev, "could not devlink wcd and tx\n"); 3417 ret = -EINVAL; 3418 goto err_remove_rxtx_link; 3419 } 3420 3421 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS | 3422 DL_FLAG_PM_RUNTIME)) { 3423 dev_err(dev, "could not devlink wcd and rx\n"); 3424 ret = -EINVAL; 3425 goto err_remove_tx_link; 3426 } 3427 3428 wcd938x->regmap = dev_get_regmap(&wcd938x->tx_sdw_dev->dev, NULL); 3429 if (!wcd938x->regmap) { 3430 dev_err(dev, "could not get TX device regmap\n"); 3431 ret = -EINVAL; 3432 goto err_remove_rx_link; 3433 } 3434 3435 ret = wcd938x_irq_init(wcd938x, dev); 3436 if (ret) { 3437 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret); 3438 goto err_remove_rx_link; 3439 } 3440 3441 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq; 3442 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq; 3443 3444 ret = wcd938x_set_micbias_data(wcd938x); 3445 if (ret < 0) { 3446 dev_err(dev, "%s: bad micbias pdata\n", __func__); 3447 goto err_remove_rx_link; 3448 } 3449 3450 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x, 3451 wcd938x_dais, ARRAY_SIZE(wcd938x_dais)); 3452 if (ret) { 3453 dev_err(dev, "%s: Codec registration failed\n", 3454 __func__); 3455 goto err_remove_rx_link; 3456 } 3457 3458 return 0; 3459 3460 err_remove_rx_link: 3461 device_link_remove(dev, wcd938x->rxdev); 3462 err_remove_tx_link: 3463 device_link_remove(dev, wcd938x->txdev); 3464 err_remove_rxtx_link: 3465 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3466 err_put_txdev: 3467 put_device(wcd938x->txdev); 3468 err_put_rxdev: 3469 put_device(wcd938x->rxdev); 3470 err_unbind: 3471 component_unbind_all(dev, wcd938x); 3472 3473 return ret; 3474 } 3475 3476 static void wcd938x_unbind(struct device *dev) 3477 { 3478 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3479 3480 snd_soc_unregister_component(dev); 3481 device_link_remove(dev, wcd938x->txdev); 3482 device_link_remove(dev, wcd938x->rxdev); 3483 device_link_remove(wcd938x->rxdev, wcd938x->txdev); 3484 put_device(wcd938x->txdev); 3485 put_device(wcd938x->rxdev); 3486 component_unbind_all(dev, wcd938x); 3487 } 3488 3489 static const struct component_master_ops wcd938x_comp_ops = { 3490 .bind = wcd938x_bind, 3491 .unbind = wcd938x_unbind, 3492 }; 3493 3494 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x, 3495 struct device *dev, 3496 struct component_match **matchptr) 3497 { 3498 struct device_node *np; 3499 3500 np = dev->of_node; 3501 3502 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0); 3503 if (!wcd938x->rxnode) { 3504 dev_err(dev, "%s: Rx-device node not defined\n", __func__); 3505 return -ENODEV; 3506 } 3507 3508 of_node_get(wcd938x->rxnode); 3509 component_match_add_release(dev, matchptr, component_release_of, 3510 component_compare_of, wcd938x->rxnode); 3511 3512 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0); 3513 if (!wcd938x->txnode) { 3514 dev_err(dev, "%s: Tx-device node not defined\n", __func__); 3515 return -ENODEV; 3516 } 3517 of_node_get(wcd938x->txnode); 3518 component_match_add_release(dev, matchptr, component_release_of, 3519 component_compare_of, wcd938x->txnode); 3520 return 0; 3521 } 3522 3523 static int wcd938x_probe(struct platform_device *pdev) 3524 { 3525 struct component_match *match = NULL; 3526 struct wcd938x_priv *wcd938x = NULL; 3527 struct device *dev = &pdev->dev; 3528 int ret; 3529 3530 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv), 3531 GFP_KERNEL); 3532 if (!wcd938x) 3533 return -ENOMEM; 3534 3535 dev_set_drvdata(dev, wcd938x); 3536 mutex_init(&wcd938x->micb_lock); 3537 3538 ret = wcd938x_populate_dt_data(wcd938x, dev); 3539 if (ret) 3540 return ret; 3541 3542 ret = wcd938x_add_slave_components(wcd938x, dev, &match); 3543 if (ret) 3544 goto err_disable_regulators; 3545 3546 wcd938x_reset(wcd938x); 3547 3548 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match); 3549 if (ret) 3550 goto err_disable_regulators; 3551 3552 pm_runtime_set_autosuspend_delay(dev, 1000); 3553 pm_runtime_use_autosuspend(dev); 3554 pm_runtime_mark_last_busy(dev); 3555 pm_runtime_set_active(dev); 3556 pm_runtime_enable(dev); 3557 pm_runtime_idle(dev); 3558 3559 return 0; 3560 3561 err_disable_regulators: 3562 regulator_bulk_disable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3563 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3564 3565 return ret; 3566 } 3567 3568 static void wcd938x_remove(struct platform_device *pdev) 3569 { 3570 struct device *dev = &pdev->dev; 3571 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev); 3572 3573 component_master_del(dev, &wcd938x_comp_ops); 3574 3575 pm_runtime_disable(dev); 3576 pm_runtime_set_suspended(dev); 3577 pm_runtime_dont_use_autosuspend(dev); 3578 3579 regulator_bulk_disable(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3580 regulator_bulk_free(WCD938X_MAX_SUPPLY, wcd938x->supplies); 3581 } 3582 3583 #if defined(CONFIG_OF) 3584 static const struct of_device_id wcd938x_dt_match[] = { 3585 { .compatible = "qcom,wcd9380-codec" }, 3586 { .compatible = "qcom,wcd9385-codec" }, 3587 {} 3588 }; 3589 MODULE_DEVICE_TABLE(of, wcd938x_dt_match); 3590 #endif 3591 3592 static struct platform_driver wcd938x_codec_driver = { 3593 .probe = wcd938x_probe, 3594 .remove = wcd938x_remove, 3595 .driver = { 3596 .name = "wcd938x_codec", 3597 .of_match_table = of_match_ptr(wcd938x_dt_match), 3598 .suppress_bind_attrs = true, 3599 }, 3600 }; 3601 3602 module_platform_driver(wcd938x_codec_driver); 3603 MODULE_DESCRIPTION("WCD938X Codec driver"); 3604 MODULE_LICENSE("GPL"); 3605