xref: /linux/sound/soc/codecs/wcd937x.h (revision fcb3ad4366b9c810cbb9da34c076a9a52d8aa1e0)
1 /* SPDX-License-Identifier: GPL-2.0-only
2  * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  */
4 
5 #ifndef _WCD937X_REGISTERS_H
6 #define _WCD937X_REGISTERS_H
7 
8 #include <linux/soundwire/sdw.h>
9 #include <linux/soundwire/sdw_type.h>
10 
11 #define WCD937X_BASE_ADDRESS			0x3000
12 #define WCD937X_ANA_BIAS			0x3001
13 #define WCD937X_ANA_RX_SUPPLIES			0x3008
14 #define WCD937X_ANA_HPH				0x3009
15 #define WCD937X_ANA_EAR				0x300A
16 #define WCD937X_ANA_EAR_COMPANDER_CTL		0x300B
17 #define WCD937X_EAR_GAIN_MASK			GENMASK(6, 2)
18 #define WCD937X_ANA_TX_CH1			0x300E
19 #define WCD937X_ANA_TX_CH2			0x300F
20 #define WCD937X_ANA_TX_CH3			0x3010
21 #define WCD937X_ANA_TX_CH3_HPF			0x3011
22 #define WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC	0x3012
23 #define WCD937X_ANA_MICB3_DSP_EN_LOGIC		0x3013
24 #define WCD937X_ANA_MBHC_MECH			0x3014
25 #define WCD937X_MBHC_L_DET_EN_MASK		BIT(7)
26 #define WCD937X_MBHC_L_DET_EN			BIT(7)
27 #define WCD937X_MBHC_GND_DET_EN_MASK		BIT(6)
28 #define WCD937X_MBHC_MECH_DETECT_TYPE_MASK	BIT(5)
29 #define WCD937X_MBHC_MECH_DETECT_TYPE_INS	1
30 #define WCD937X_MBHC_HPHL_PLUG_TYPE_MASK	BIT(4)
31 #define WCD937X_MBHC_HPHL_PLUG_TYPE_NO		1
32 #define WCD937X_MBHC_GND_PLUG_TYPE_MASK		BIT(3)
33 #define WCD937X_MBHC_GND_PLUG_TYPE_NO		1
34 #define WCD937X_MBHC_HSL_PULLUP_COMP_EN		BIT(2)
35 #define WCD937X_MBHC_HSG_PULLUP_COMP_EN		BIT(1)
36 #define WCD937X_MBHC_HPHL_100K_TO_GND_EN	BIT(0)
37 #define WCD937X_ANA_MBHC_ELECT			0x3015
38 #define WCD937X_ANA_MBHC_BD_ISRC_CTL_MASK	GENMASK(6, 4)
39 #define WCD937X_ANA_MBHC_BD_ISRC_100UA		GENMASK(5, 4)
40 #define WCD937X_ANA_MBHC_BD_ISRC_OFF		0
41 #define WCD937X_ANA_MBHC_BIAS_EN_MASK		BIT(0)
42 #define WCD937X_ANA_MBHC_BIAS_EN		BIT(0)
43 #define WCD937X_ANA_MBHC_ZDET			0x3016
44 #define WCD937X_ANA_MBHC_RESULT_1		0x3017
45 #define WCD937X_ANA_MBHC_RESULT_2		0x3018
46 #define WCD937X_ANA_MBHC_RESULT_3		0x3019
47 #define WCD937X_MBHC_BTN_RESULT_MASK		GENMASK(2, 0)
48 #define WCD937X_ANA_MBHC_BTN0			0x301A
49 #define WCD937X_MBHC_BTN_VTH_MASK		GENMASK(7, 2)
50 #define WCD937X_ANA_MBHC_BTN1			0x301B
51 #define WCD937X_ANA_MBHC_BTN2			0x301C
52 #define WCD937X_ANA_MBHC_BTN3			0x301D
53 #define WCD937X_ANA_MBHC_BTN4			0x301E
54 #define WCD937X_ANA_MBHC_BTN5			0x301F
55 #define WCD937X_VTH_MASK			GENMASK(7, 2)
56 #define WCD937X_ANA_MBHC_BTN6			0x3020
57 #define WCD937X_ANA_MBHC_BTN7			0x3021
58 #define WCD937X_ANA_MICB1			0x3022
59 #define WCD937X_MICB_VOUT_MASK			GENMASK(5, 0)
60 #define WCD937X_MICB_EN_MASK			GENMASK(7, 6)
61 #define WCD937X_MICB_DISABLE			0
62 #define WCD937X_MICB_ENABLE			1
63 #define WCD937X_MICB_PULL_UP			2
64 #define WCD937X_MICB_PULL_DOWN			3
65 #define WCD937X_ANA_MICB2			0x3023
66 #define WCD937X_ANA_MICB2_ENABLE		BIT(6)
67 #define WCD937X_ANA_MICB2_ENABLE_MASK		GENMASK(7, 6)
68 #define WCD937X_ANA_MICB2_VOUT_MASK		GENMASK(5, 0)
69 #define WCD937X_ANA_MICB2_RAMP			0x3024
70 #define WCD937X_RAMP_EN_MASK			BIT(7)
71 #define WCD937X_RAMP_SHIFT_CTRL_MASK		GENMASK(4, 2)
72 #define WCD937X_ANA_MICB3			0x3025
73 #define WCD937X_ANA_MICB_EN			GENMASK(7, 6)
74 #define WCD937X_MICB_DISABLE			0
75 #define WCD937X_MICB_ENABLE			1
76 #define WCD937X_MICB_PULL_UP			2
77 #define WCD937X_ANA_MICB_VOUT			GENMASK(5, 0)
78 #define WCD937X_BIAS_CTL			0x3028
79 #define WCD937X_BIAS_VBG_FINE_ADJ		0x3029
80 #define WCD937X_LDOL_VDDCX_ADJUST		0x3040
81 #define WCD937X_LDOL_DISABLE_LDOL		0x3041
82 #define WCD937X_MBHC_CTL_CLK			0x3056
83 #define WCD937X_MBHC_CTL_ANA			0x3057
84 #define WCD937X_MBHC_CTL_SPARE_1		0x3058
85 #define WCD937X_MBHC_CTL_SPARE_2		0x3059
86 #define WCD937X_MBHC_CTL_BCS			0x305A
87 #define WCD937X_MBHC_MOISTURE_DET_FSM_STATUS	0x305B
88 #define WCD937X_MBHC_TEST_CTL			0x305C
89 #define WCD937X_LDOH_MODE			0x3067
90 #define WCD937X_LDOH_BIAS			0x3068
91 #define WCD937X_LDOH_STB_LOADS			0x3069
92 #define WCD937X_LDOH_SLOWRAMP			0x306A
93 #define WCD937X_MICB1_TEST_CTL_1		0x306B
94 #define WCD937X_MICB1_TEST_CTL_2		0x306C
95 #define WCD937X_MICB1_TEST_CTL_3		0x306D
96 #define WCD937X_MICB2_TEST_CTL_1		0x306E
97 #define WCD937X_MICB2_TEST_CTL_2		0x306F
98 #define WCD937X_MICB2_TEST_CTL_3		0x3070
99 #define WCD937X_MICB3_TEST_CTL_1		0x3071
100 #define WCD937X_MICB3_TEST_CTL_2		0x3072
101 #define WCD937X_MICB3_TEST_CTL_3		0x3073
102 #define WCD937X_TX_COM_ADC_VCM			0x3077
103 #define WCD937X_TX_COM_BIAS_ATEST		0x3078
104 #define WCD937X_TX_COM_ADC_INT1_IB		0x3079
105 #define WCD937X_TX_COM_ADC_INT2_IB		0x307A
106 #define WCD937X_TX_COM_TXFE_DIV_CTL		0x307B
107 #define WCD937X_TX_COM_TXFE_DIV_START		0x307C
108 #define WCD937X_TX_COM_TXFE_DIV_STOP_9P6M	0x307D
109 #define WCD937X_TX_COM_TXFE_DIV_STOP_12P288M	0x307E
110 #define WCD937X_TX_1_2_TEST_EN			0x307F
111 #define WCD937X_TX_1_2_ADC_IB			0x3080
112 #define WCD937X_TX_1_2_ATEST_REFCTL		0x3081
113 #define WCD937X_TX_1_2_TEST_CTL			0x3082
114 #define WCD937X_TX_1_2_TEST_BLK_EN		0x3083
115 #define WCD937X_TX_1_2_TXFE_CLKDIV		0x3084
116 #define WCD937X_TX_1_2_SAR2_ERR			0x3085
117 #define WCD937X_TX_1_2_SAR1_ERR			0x3086
118 #define WCD937X_TX_3_TEST_EN			0x3087
119 #define WCD937X_TX_3_ADC_IB			0x3088
120 #define WCD937X_TX_3_ATEST_REFCTL		0x3089
121 #define WCD937X_TX_3_TEST_CTL			0x308A
122 #define WCD937X_TX_3_TEST_BLK_EN		0x308B
123 #define WCD937X_TX_3_TXFE_CLKDIV		0x308C
124 #define WCD937X_TX_3_SPARE_MONO			0x308D
125 #define WCD937X_TX_3_SAR1_ERR			0x308E
126 #define WCD937X_CLASSH_MODE_1			0x3097
127 #define WCD937X_CLASSH_MODE_2			0x3098
128 #define WCD937X_CLASSH_MODE_3			0x3099
129 #define WCD937X_CLASSH_CTRL_VCL_1		0x309A
130 #define WCD937X_CLASSH_CTRL_VCL_2		0x309B
131 #define WCD937X_CLASSH_CTRL_CCL_1		0x309C
132 #define WCD937X_CLASSH_CTRL_CCL_2		0x309D
133 #define WCD937X_CLASSH_CTRL_CCL_3		0x309E
134 #define WCD937X_CLASSH_CTRL_CCL_4		0x309F
135 #define WCD937X_CLASSH_CTRL_CCL_5		0x30A0
136 #define WCD937X_CLASSH_BUCK_TMUX_A_D		0x30A1
137 #define WCD937X_CLASSH_BUCK_SW_DRV_CNTL		0x30A2
138 #define WCD937X_CLASSH_SPARE			0x30A3
139 #define WCD937X_FLYBACK_EN			0x30A4
140 #define WCD937X_FLYBACK_VNEG_CTRL_1		0x30A5
141 #define WCD937X_FLYBACK_VNEG_CTRL_2		0x30A6
142 #define WCD937X_FLYBACK_VNEG_CTRL_3		0x30A7
143 #define WCD937X_FLYBACK_VNEG_CTRL_4		0x30A8
144 #define WCD937X_FLYBACK_VNEG_CTRL_5		0x30A9
145 #define WCD937X_FLYBACK_VNEG_CTRL_6		0x30AA
146 #define WCD937X_FLYBACK_VNEG_CTRL_7		0x30AB
147 #define WCD937X_FLYBACK_VNEG_CTRL_8		0x30AC
148 #define WCD937X_FLYBACK_VNEG_CTRL_9		0x30AD
149 #define WCD937X_FLYBACK_VNEGDAC_CTRL_1		0x30AE
150 #define WCD937X_FLYBACK_VNEGDAC_CTRL_2		0x30AF
151 #define WCD937X_FLYBACK_VNEGDAC_CTRL_3		0x30B0
152 #define WCD937X_FLYBACK_CTRL_1			0x30B1
153 #define WCD937X_FLYBACK_TEST_CTL		0x30B2
154 #define WCD937X_RX_AUX_SW_CTL			0x30B3
155 #define WCD937X_RX_PA_AUX_IN_CONN		0x30B4
156 #define WCD937X_RX_TIMER_DIV			0x30B5
157 #define WCD937X_RX_OCP_CTL			0x30B6
158 #define WCD937X_RX_OCP_COUNT			0x30B7
159 #define WCD937X_RX_BIAS_EAR_DAC			0x30B8
160 #define WCD937X_RX_BIAS_EAR_AMP			0x30B9
161 #define WCD937X_RX_BIAS_HPH_LDO			0x30BA
162 #define WCD937X_RX_BIAS_HPH_PA			0x30BB
163 #define WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2	0x30BC
164 #define WCD937X_RX_BIAS_HPH_RDAC_LDO		0x30BD
165 #define WCD937X_RX_BIAS_HPH_CNP1		0x30BE
166 #define WCD937X_RX_BIAS_HPH_LOWPOWER		0x30BF
167 #define WCD937X_RX_BIAS_AUX_DAC			0x30C0
168 #define WCD937X_RX_BIAS_AUX_AMP			0x30C1
169 #define WCD937X_RX_BIAS_VNEGDAC_BLEEDER		0x30C2
170 #define WCD937X_RX_BIAS_MISC			0x30C3
171 #define WCD937X_RX_BIAS_BUCK_RST		0x30C4
172 #define WCD937X_RX_BIAS_BUCK_VREF_ERRAMP	0x30C5
173 #define WCD937X_RX_BIAS_FLYB_ERRAMP		0x30C6
174 #define WCD937X_RX_BIAS_FLYB_BUFF		0x30C7
175 #define WCD937X_RX_BIAS_FLYB_MID_RST		0x30C8
176 #define WCD937X_HPH_L_STATUS			0x30C9
177 #define WCD937X_HPH_R_STATUS			0x30CA
178 #define WCD937X_HPH_CNP_EN			0x30CB
179 #define WCD937X_HPH_CNP_WG_CTL			0x30CC
180 #define WCD937X_HPH_CNP_WG_TIME			0x30CD
181 #define WCD937X_HPH_OCP_CTL			0x30CE
182 #define WCD937X_HPH_AUTO_CHOP			0x30CF
183 #define WCD937X_HPH_CHOP_CTL			0x30D0
184 #define WCD937X_HPH_PA_CTL1			0x30D1
185 #define WCD937X_HPH_PA_CTL2			0x30D2
186 #define WCD937X_HPHPA_GND_R_MASK		BIT(6)
187 #define WCD937X_HPHPA_GND_L_MASK		BIT(4)
188 #define WCD937X_HPH_L_EN			0x30D3
189 #define WCD937X_HPH_L_TEST			0x30D4
190 #define WCD937X_HPH_L_ATEST			0x30D5
191 #define WCD937X_HPH_R_EN			0x30D6
192 #define WCD937X_GAIN_SRC_SEL_MASK		BIT(5)
193 #define WCD937X_GAIN_SRC_SEL_REGISTER		1
194 #define WCD937X_HPH_R_TEST			0x30D7
195 #define WCD937X_HPH_R_ATEST			0x30D8
196 #define WCD937X_HPH_RDAC_CLK_CTL1		0x30D9
197 #define WCD937X_HPHPA_GND_OVR_MASK		BIT(1)
198 #define WCD937X_CHOP_CLK_EN_MASK		BIT(7)
199 #define WCD937X_HPH_RDAC_CLK_CTL2		0x30DA
200 #define WCD937X_HPH_RDAC_LDO_CTL		0x30DB
201 #define WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL	0x30DC
202 #define WCD937X_HPH_REFBUFF_UHQA_CTL		0x30DD
203 #define WCD937X_HPH_REFBUFF_LP_CTL		0x30DE
204 #define WCD937X_PREREF_FLIT_BYPASS_MASK		BIT(0)
205 #define WCD937X_HPH_L_DAC_CTL			0x30DF
206 #define WCD937X_HPH_R_DAC_CTL			0x30E0
207 #define WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL	0x30E1
208 #define WCD937X_HPH_SURGE_HPHLR_SURGE_EN	0x30E2
209 #define WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1	0x30E3
210 #define WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS	0x30E4
211 #define WCD937X_EAR_EAR_EN_REG			0x30E9
212 #define WCD937X_EAR_EAR_PA_CON			0x30EA
213 #define WCD937X_EAR_EAR_SP_CON			0x30EB
214 #define WCD937X_EAR_EAR_DAC_CON			0x30EC
215 #define WCD937X_EAR_EAR_CNP_FSM_CON		0x30ED
216 #define WCD937X_EAR_TEST_CTL			0x30EE
217 #define WCD937X_EAR_STATUS_REG_1		0x30EF
218 #define WCD937X_EAR_STATUS_REG_2		0x30F0
219 #define WCD937X_ANA_NEW_PAGE_REGISTER		0x3100
220 #define WCD937X_HPH_NEW_ANA_HPH2		0x3101
221 #define WCD937X_HPH_NEW_ANA_HPH3		0x3102
222 #define WCD937X_SLEEP_CTL			0x3103
223 #define WCD937X_SLEEP_WATCHDOG_CTL		0x3104
224 #define WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL	0x311F
225 #define WCD937X_MBHC_NEW_CTL_1			0x3120
226 #define WCD937X_MBHC_CTL_RCO_EN_MASK		BIT(7)
227 #define WCD937X_MBHC_CTL_RCO_EN			BIT(7)
228 #define WCD937X_MBHC_BTN_DBNC_MASK		GENMASK(1, 0)
229 #define WCD937X_MBHC_BTN_DBNC_T_16_MS		0x2
230 #define WCD937X_MBHC_NEW_CTL_2			0x3121
231 #define WCD937X_MBHC_NEW_PLUG_DETECT_CTL	0x3122
232 #define WCD937X_MBHC_NEW_ZDET_ANA_CTL		0x3123
233 #define WCD937X_M_RTH_CTL_MASK			GENMASK(3, 2)
234 #define WCD937X_MBHC_HS_VREF_CTL_MASK		GENMASK(1, 0)
235 #define WCD937X_MBHC_HS_VREF_1P5_V		0x1
236 #define WCD937X_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS	0x6
237 #define WCD937X_ZDET_RANGE_CTL_MASK		GENMASK(3, 0)
238 #define WCD937X_ZDET_MAXV_CTL_MASK		GENMASK(6, 4)
239 #define WCD937X_MBHC_NEW_ZDET_RAMP_CTL		0x3124
240 #define WCD937X_MBHC_NEW_FSM_STATUS		0x3125
241 #define WCD937X_MBHC_NEW_ADC_RESULT		0x3126
242 #define WCD937X_TX_NEW_TX_CH2_SEL		0x3127
243 #define WCD937X_AUX_AUXPA			0x3128
244 #define WCD937X_AUXPA_CLK_EN_MASK		BIT(4)
245 #define WCD937X_AUXPA_CLK_EN_MASK		BIT(4)
246 #define WCD937X_LDORXTX_MODE			0x3129
247 #define WCD937X_LDORXTX_CONFIG			0x312A
248 #define WCD937X_DIE_CRACK_DIE_CRK_DET_EN	0x312C
249 #define WCD937X_DIE_CRACK_DIE_CRK_DET_OUT	0x312D
250 #define WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL	0x3132
251 #define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L	0x3133
252 #define WCD937X_HPH_NEW_INT_RDAC_VREF_CTL	0x3134
253 #define WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL	0x3135
254 #define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R	0x3136
255 #define WCD937X_HPH_NEW_INT_PA_MISC1		0x3137
256 #define WCD937X_HPH_NEW_INT_PA_MISC2		0x3138
257 #define WCD937X_HPH_NEW_INT_PA_RDAC_MISC	0x3139
258 #define WCD937X_HPH_NEW_INT_HPH_TIMER1		0x313A
259 #define WCD937X_HPH_NEW_INT_HPH_TIMER2		0x313B
260 #define WCD937X_HPH_NEW_INT_HPH_TIMER3		0x313C
261 #define WCD937X_HPH_NEW_INT_HPH_TIMER4		0x313D
262 #define WCD937X_HPH_NEW_INT_PA_RDAC_MISC2	0x313E
263 #define WCD937X_HPH_NEW_INT_PA_RDAC_MISC3	0x313F
264 #define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI	0x3145
265 #define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP	0x3146
266 #define WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP	0x3147
267 #define WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL			0x31AF
268 #define WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL			0x31B0
269 #define WCD937X_MOISTURE_EN_POLLING_MASK	BIT(2)
270 #define WCD937X_HSDET_PULLUP_C_MASK		GENMASK(4, 0)
271 #define WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT	0x31B1
272 #define WCD937X_MBHC_NEW_INT_SPARE_2		0x31B2
273 #define WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON	0x31B7
274 #define WCD937X_EAR_INT_NEW_CNP_VCM_CON1	0x31B8
275 #define WCD937X_EAR_INT_NEW_CNP_VCM_CON2	0x31B9
276 #define WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS	0x31BA
277 #define WCD937X_AUX_INT_EN_REG			0x31BD
278 #define WCD937X_AUX_INT_PA_CTRL			0x31BE
279 #define WCD937X_AUX_INT_SP_CTRL			0x31BF
280 #define WCD937X_AUX_INT_DAC_CTRL		0x31C0
281 #define WCD937X_AUX_INT_CLK_CTRL		0x31C1
282 #define WCD937X_AUX_INT_TEST_CTRL		0x31C2
283 #define WCD937X_AUX_INT_STATUS_REG		0x31C3
284 #define WCD937X_AUX_INT_MISC			0x31C4
285 #define WCD937X_LDORXTX_INT_BIAS		0x31C5
286 #define WCD937X_LDORXTX_INT_STB_LOADS_DTEST	0x31C6
287 #define WCD937X_LDORXTX_INT_TEST0		0x31C7
288 #define WCD937X_LDORXTX_INT_STARTUP_TIMER	0x31C8
289 #define WCD937X_LDORXTX_INT_TEST1		0x31C9
290 #define WCD937X_LDORXTX_INT_STATUS		0x31CA
291 #define WCD937X_SLEEP_INT_WATCHDOG_CTL_1	0x31D0
292 #define WCD937X_SLEEP_INT_WATCHDOG_CTL_2	0x31D1
293 #define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1	0x31D3
294 #define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2	0x31D4
295 #define WCD937X_DIGITAL_PAGE_REGISTER		0x3400
296 #define WCD937X_DIGITAL_CHIP_ID0		0x3401
297 #define WCD937X_DIGITAL_CHIP_ID1		0x3402
298 #define WCD937X_DIGITAL_CHIP_ID2		0x3403
299 #define WCD937X_DIGITAL_CHIP_ID3		0x3404
300 #define WCD937X_DIGITAL_CDC_RST_CTL		0x3406
301 #define WCD937X_DIGITAL_TOP_CLK_CFG		0x3407
302 #define WCD937X_DIGITAL_CDC_ANA_CLK_CTL		0x3408
303 #define WCD937X_DIGITAL_CDC_DIG_CLK_CTL		0x3409
304 #define WCD937X_DIGITAL_SWR_RST_EN		0x340A
305 #define WCD937X_DIGITAL_CDC_PATH_MODE		0x340B
306 #define WCD937X_DIGITAL_CDC_RX_RST		0x340C
307 #define WCD937X_DIGITAL_CDC_RX0_CTL		0x340D
308 #define WCD937X_DIGITAL_CDC_RX1_CTL		0x340E
309 #define WCD937X_DIGITAL_CDC_RX2_CTL		0x340F
310 #define WCD937X_DIGITAL_DEM_BYPASS_DATA0	0x3410
311 #define WCD937X_DIGITAL_DEM_BYPASS_DATA1	0x3411
312 #define WCD937X_DIGITAL_DEM_BYPASS_DATA2	0x3412
313 #define WCD937X_DIGITAL_DEM_BYPASS_DATA3	0x3413
314 #define WCD937X_DIGITAL_CDC_COMP_CTL_0		0x3414
315 #define WCD937X_DIGITAL_CDC_RX_DELAY_CTL	0x3417
316 #define WCD937X_DIGITAL_CDC_HPH_DSM_A1_0	0x3418
317 #define WCD937X_DIGITAL_CDC_HPH_DSM_A1_1	0x3419
318 #define WCD937X_DIGITAL_CDC_HPH_DSM_A2_0	0x341A
319 #define WCD937X_DIGITAL_CDC_HPH_DSM_A2_1	0x341B
320 #define WCD937X_DIGITAL_CDC_HPH_DSM_A3_0	0x341C
321 #define WCD937X_DIGITAL_CDC_HPH_DSM_A3_1	0x341D
322 #define WCD937X_DIGITAL_CDC_HPH_DSM_A4_0	0x341E
323 #define WCD937X_DIGITAL_CDC_HPH_DSM_A4_1	0x341F
324 #define WCD937X_DIGITAL_CDC_HPH_DSM_A5_0	0x3420
325 #define WCD937X_DIGITAL_CDC_HPH_DSM_A5_1	0x3421
326 #define WCD937X_DIGITAL_CDC_HPH_DSM_A6_0	0x3422
327 #define WCD937X_DIGITAL_CDC_HPH_DSM_A7_0	0x3423
328 #define WCD937X_DIGITAL_CDC_HPH_DSM_C_0		0x3424
329 #define WCD937X_DIGITAL_CDC_HPH_DSM_C_1		0x3425
330 #define WCD937X_DIGITAL_CDC_HPH_DSM_C_2		0x3426
331 #define WCD937X_DIGITAL_CDC_HPH_DSM_C_3		0x3427
332 #define WCD937X_DIGITAL_CDC_HPH_DSM_R1		0x3428
333 #define WCD937X_DIGITAL_CDC_HPH_DSM_R2		0x3429
334 #define WCD937X_DIGITAL_CDC_HPH_DSM_R3		0x342A
335 #define WCD937X_DIGITAL_CDC_HPH_DSM_R4		0x342B
336 #define WCD937X_DIGITAL_CDC_HPH_DSM_R5		0x342C
337 #define WCD937X_DIGITAL_CDC_HPH_DSM_R6		0x342D
338 #define WCD937X_DIGITAL_CDC_HPH_DSM_R7		0x342E
339 #define WCD937X_DIGITAL_CDC_AUX_DSM_A1_0	0x342F
340 #define WCD937X_DIGITAL_CDC_AUX_DSM_A1_1	0x3430
341 #define WCD937X_DIGITAL_CDC_AUX_DSM_A2_0	0x3431
342 #define WCD937X_DIGITAL_CDC_AUX_DSM_A2_1	0x3432
343 #define WCD937X_DIGITAL_CDC_AUX_DSM_A3_0	0x3433
344 #define WCD937X_DIGITAL_CDC_AUX_DSM_A3_1	0x3434
345 #define WCD937X_DIGITAL_CDC_AUX_DSM_A4_0	0x3435
346 #define WCD937X_DIGITAL_CDC_AUX_DSM_A4_1	0x3436
347 #define WCD937X_DIGITAL_CDC_AUX_DSM_A5_0	0x3437
348 #define WCD937X_DIGITAL_CDC_AUX_DSM_A5_1	0x3438
349 #define WCD937X_DIGITAL_CDC_AUX_DSM_A6_0	0x3439
350 #define WCD937X_DIGITAL_CDC_AUX_DSM_A7_0	0x343A
351 #define WCD937X_DIGITAL_CDC_AUX_DSM_C_0		0x343B
352 #define WCD937X_DIGITAL_CDC_AUX_DSM_C_1		0x343C
353 #define WCD937X_DIGITAL_CDC_AUX_DSM_C_2		0x343D
354 #define WCD937X_DIGITAL_CDC_AUX_DSM_C_3		0x343E
355 #define WCD937X_DIGITAL_CDC_AUX_DSM_R1		0x343F
356 #define WCD937X_DIGITAL_CDC_AUX_DSM_R2		0x3440
357 #define WCD937X_DIGITAL_CDC_AUX_DSM_R3		0x3441
358 #define WCD937X_DIGITAL_CDC_AUX_DSM_R4		0x3442
359 #define WCD937X_DIGITAL_CDC_AUX_DSM_R5		0x3443
360 #define WCD937X_DIGITAL_CDC_AUX_DSM_R6		0x3444
361 #define WCD937X_DIGITAL_CDC_AUX_DSM_R7		0x3445
362 #define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0	0x3446
363 #define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1	0x3447
364 #define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0	0x3448
365 #define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1	0x3449
366 #define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2	0x344A
367 #define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0	0x344B
368 #define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1	0x344C
369 #define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2	0x344D
370 #define WCD937X_DIGITAL_CDC_HPH_GAIN_CTL	0x344E
371 #define WCD937X_DIGITAL_CDC_AUX_GAIN_CTL	0x344F
372 #define WCD937X_DIGITAL_CDC_EAR_PATH_CTL	0x3450
373 #define WCD937X_DIGITAL_CDC_SWR_CLH		0x3451
374 #define WCD937X_DIGITAL_SWR_CLH_BYP		0x3452
375 #define WCD937X_DIGITAL_CDC_TX0_CTL		0x3453
376 #define WCD937X_DIGITAL_CDC_TX1_CTL		0x3454
377 #define WCD937X_DIGITAL_CDC_TX2_CTL		0x3455
378 #define WCD937X_DIGITAL_CDC_TX_RST		0x3456
379 #define WCD937X_DIGITAL_CDC_REQ_CTL		0x3457
380 #define WCD937X_DIGITAL_CDC_AMIC_CTL		0x345A
381 #define WCD937X_DIGITAL_CDC_DMIC_CTL		0x345B
382 #define WCD937X_DIGITAL_CDC_DMIC1_CTL		0x345C
383 #define WCD937X_DIGITAL_CDC_DMIC2_CTL		0x345D
384 #define WCD937X_DIGITAL_CDC_DMIC3_CTL		0x345E
385 #define WCD937X_DIGITAL_EFUSE_CTL		0x345F
386 #define WCD937X_DIGITAL_EFUSE_PRG_CTL		0x3460
387 #define WCD937X_DIGITAL_EFUSE_TEST_CTL_0	0x3461
388 #define WCD937X_DIGITAL_EFUSE_TEST_CTL_1	0x3462
389 #define WCD937X_DIGITAL_EFUSE_T_DATA_0		0x3463
390 #define WCD937X_DIGITAL_EFUSE_T_DATA_1		0x3464
391 #define WCD937X_DIGITAL_PDM_WD_CTL0		0x3465
392 #define WCD937X_DIGITAL_PDM_WD_CTL1		0x3466
393 #define WCD937X_DIGITAL_PDM_WD_CTL2		0x3467
394 #define WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF	BIT(2)
395 #define WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL	BIT(1)
396 #define WCD937X_DIGITAL_PDM_WD_CTL2_EN		BIT(0)
397 #define WCD937X_DIGITAL_PDM_WD_CTL2_MASK	GENMASK(2, 0)
398 #define WCD937X_DIGITAL_INTR_MODE		0x346A
399 #define WCD937X_DIGITAL_INTR_MASK_0		0x346B
400 #define WCD937X_DIGITAL_INTR_MASK_1		0x346C
401 #define WCD937X_DIGITAL_INTR_MASK_2		0x346D
402 #define WCD937X_DIGITAL_INTR_STATUS_0		0x346E
403 #define WCD937X_DIGITAL_INTR_STATUS_1		0x346F
404 #define WCD937X_DIGITAL_INTR_STATUS_2		0x3470
405 #define WCD937X_DIGITAL_INTR_CLEAR_0		0x3471
406 #define WCD937X_DIGITAL_INTR_CLEAR_1		0x3472
407 #define WCD937X_DIGITAL_INTR_CLEAR_2		0x3473
408 #define WCD937X_DIGITAL_INTR_LEVEL_0		0x3474
409 #define WCD937X_DIGITAL_INTR_LEVEL_1		0x3475
410 #define WCD937X_DIGITAL_INTR_LEVEL_2		0x3476
411 #define WCD937X_DIGITAL_INTR_SET_0		0x3477
412 #define WCD937X_DIGITAL_INTR_SET_1		0x3478
413 #define WCD937X_DIGITAL_INTR_SET_2		0x3479
414 #define WCD937X_DIGITAL_INTR_TEST_0		0x347A
415 #define WCD937X_DIGITAL_INTR_TEST_1		0x347B
416 #define WCD937X_DIGITAL_INTR_TEST_2		0x347C
417 #define WCD937X_DIGITAL_CDC_CONN_RX0_CTL	0x347F
418 #define WCD937X_DIGITAL_CDC_CONN_RX1_CTL	0x3480
419 #define WCD937X_DIGITAL_CDC_CONN_RX2_CTL	0x3481
420 #define WCD937X_DIGITAL_CDC_CONN_TX_CTL		0x3482
421 #define WCD937X_DIGITAL_LOOP_BACK_MODE		0x3483
422 #define WCD937X_DIGITAL_SWR_DAC_TEST		0x3484
423 #define WCD937X_DIGITAL_SWR_HM_TEST_RX_0	0x3485
424 #define WCD937X_DIGITAL_SWR_HM_TEST_TX_0	0x3491
425 #define WCD937X_DIGITAL_SWR_HM_TEST_RX_1	0x3492
426 #define WCD937X_DIGITAL_SWR_HM_TEST_TX_1	0x3493
427 #define WCD937X_DIGITAL_SWR_HM_TEST		0x3494
428 #define WCD937X_DIGITAL_PAD_CTL_PDM_RX0		0x3495
429 #define WCD937X_DIGITAL_PAD_CTL_PDM_RX1		0x3496
430 #define WCD937X_DIGITAL_PAD_CTL_PDM_TX0		0x3497
431 #define WCD937X_DIGITAL_PAD_CTL_PDM_TX1		0x3498
432 #define WCD937X_DIGITAL_PAD_INP_DIS_0		0x3499
433 #define WCD937X_DIGITAL_PAD_INP_DIS_1		0x349A
434 #define WCD937X_DIGITAL_DRIVE_STRENGTH_0	0x349B
435 #define WCD937X_DIGITAL_DRIVE_STRENGTH_1	0x349C
436 #define WCD937X_DIGITAL_DRIVE_STRENGTH_2	0x349D
437 #define WCD937X_DIGITAL_RX_DATA_EDGE_CTL	0x349E
438 #define WCD937X_DIGITAL_TX_DATA_EDGE_CTL	0x349F
439 #define WCD937X_DIGITAL_GPIO_MODE		0x34A0
440 #define WCD937X_DIGITAL_PIN_CTL_OE		0x34A1
441 #define WCD937X_DIGITAL_PIN_CTL_DATA_0		0x34A2
442 #define WCD937X_DIGITAL_PIN_CTL_DATA_1		0x34A3
443 #define WCD937X_DIGITAL_PIN_STATUS_0		0x34A4
444 #define WCD937X_DIGITAL_PIN_STATUS_1		0x34A5
445 #define WCD937X_DIGITAL_DIG_DEBUG_CTL		0x34A6
446 #define WCD937X_DIGITAL_DIG_DEBUG_EN		0x34A7
447 #define WCD937X_DIGITAL_ANA_CSR_DBG_ADD		0x34A8
448 #define WCD937X_DIGITAL_ANA_CSR_DBG_CTL		0x34A9
449 #define WCD937X_DIGITAL_SSP_DBG			0x34AA
450 #define WCD937X_DIGITAL_MODE_STATUS_0		0x34AB
451 #define WCD937X_DIGITAL_MODE_STATUS_1		0x34AC
452 #define WCD937X_DIGITAL_SPARE_0			0x34AD
453 #define WCD937X_DIGITAL_SPARE_1			0x34AE
454 #define WCD937X_DIGITAL_SPARE_2			0x34AF
455 #define WCD937X_DIGITAL_EFUSE_REG_0		0x34B0
456 #define WCD937X_DIGITAL_EFUSE_REG_1		0x34B1
457 #define WCD937X_DIGITAL_EFUSE_REG_2		0x34B2
458 #define WCD937X_DIGITAL_EFUSE_REG_3		0x34B3
459 #define WCD937X_DIGITAL_EFUSE_REG_4		0x34B4
460 #define WCD937X_DIGITAL_EFUSE_REG_5		0x34B5
461 #define WCD937X_DIGITAL_EFUSE_REG_6		0x34B6
462 #define WCD937X_DIGITAL_EFUSE_REG_7		0x34B7
463 #define WCD937X_DIGITAL_EFUSE_REG_8		0x34B8
464 #define WCD937X_DIGITAL_EFUSE_REG_9		0x34B9
465 #define WCD937X_DIGITAL_EFUSE_REG_10		0x34BA
466 #define WCD937X_DIGITAL_EFUSE_REG_11		0x34BB
467 #define WCD937X_DIGITAL_EFUSE_REG_12		0x34BC
468 #define WCD937X_DIGITAL_EFUSE_REG_13		0x34BD
469 #define WCD937X_DIGITAL_EFUSE_REG_14		0x34BE
470 #define WCD937X_DIGITAL_EFUSE_REG_15		0x34BF
471 #define WCD937X_DIGITAL_EFUSE_REG_16		0x34C0
472 #define WCD937X_DIGITAL_EFUSE_REG_17		0x34C1
473 #define WCD937X_DIGITAL_EFUSE_REG_18		0x34C2
474 #define WCD937X_DIGITAL_EFUSE_REG_19		0x34C3
475 #define WCD937X_DIGITAL_EFUSE_REG_20		0x34C4
476 #define WCD937X_DIGITAL_EFUSE_REG_21		0x34C5
477 #define WCD937X_DIGITAL_EFUSE_REG_22		0x34C6
478 #define WCD937X_DIGITAL_EFUSE_REG_23		0x34C7
479 #define WCD937X_DIGITAL_EFUSE_REG_24		0x34C8
480 #define WCD937X_DIGITAL_EFUSE_REG_25		0x34C9
481 #define WCD937X_DIGITAL_EFUSE_REG_26		0x34CA
482 #define WCD937X_DIGITAL_EFUSE_REG_27		0x34CB
483 #define WCD937X_DIGITAL_EFUSE_REG_28		0x34CC
484 #define WCD937X_DIGITAL_EFUSE_REG_29		0x34CD
485 #define WCD937X_DIGITAL_EFUSE_REG_30		0x34CE
486 #define WCD937X_DIGITAL_EFUSE_REG_31		0x34CF
487 #define WCD937X_MAX_REGISTER			(WCD937X_DIGITAL_EFUSE_REG_31)
488 
489 #define WCD937X_MAX_MICBIAS			3
490 #define WCD937X_MAX_BULK_SUPPLY			4
491 #define WCD937X_MAX_SWR_CH_IDS			15
492 
493 enum wcd937x_tx_sdw_ports {
494 	WCD937X_ADC_1_PORT = 1,
495 	WCD937X_ADC_2_3_PORT,
496 	WCD937X_DMIC_0_3_MBHC_PORT,
497 	WCD937X_DMIC_4_6_PORT,
498 	WCD937X_MAX_TX_SWR_PORTS = WCD937X_DMIC_4_6_PORT,
499 };
500 
501 enum wcd937x_rx_sdw_ports {
502 	WCD937X_HPH_PORT = 1,
503 	WCD937X_CLSH_PORT,
504 	WCD937X_COMP_PORT,
505 	WCD937X_LO_PORT,
506 	WCD937X_DSD_PORT,
507 	WCD937X_MAX_SWR_PORTS = WCD937X_DSD_PORT,
508 };
509 
510 struct wcd937x_sdw_ch_info {
511 	int port_num;
512 	unsigned int ch_mask;
513 };
514 
515 #define WCD_SDW_CH(id, pn, cmask)	\
516 	[id] = {			\
517 		.port_num = pn,		\
518 		.ch_mask = cmask,	\
519 	}
520 
521 struct wcd937x_priv;
522 struct wcd937x_sdw_priv {
523 	struct sdw_slave *sdev;
524 	struct sdw_stream_config sconfig;
525 	struct sdw_stream_runtime *sruntime;
526 	struct sdw_port_config port_config[WCD937X_MAX_SWR_PORTS];
527 	const struct wcd937x_sdw_ch_info *ch_info;
528 	bool port_enable[WCD937X_MAX_SWR_CH_IDS];
529 	int active_ports;
530 	bool is_tx;
531 	struct wcd937x_priv *wcd937x;
532 	struct irq_domain *slave_irq;
533 	struct regmap *regmap;
534 };
535 
536 #if IS_ENABLED(CONFIG_SND_SOC_WCD937X_SDW)
537 int wcd937x_sdw_free(struct wcd937x_sdw_priv *wcd,
538 		     struct snd_pcm_substream *substream,
539 		     struct snd_soc_dai *dai);
540 int wcd937x_sdw_set_sdw_stream(struct wcd937x_sdw_priv *wcd,
541 			       struct snd_soc_dai *dai,
542 			       void *stream, int direction);
543 int wcd937x_sdw_hw_params(struct wcd937x_sdw_priv *wcd,
544 			  struct snd_pcm_substream *substream,
545 			  struct snd_pcm_hw_params *params,
546 			  struct snd_soc_dai *dai);
547 
548 struct device *wcd937x_sdw_device_get(struct device_node *np);
549 
550 #else
551 int wcd937x_sdw_free(struct wcd937x_sdw_priv *wcd,
552 		     struct snd_pcm_substream *substream,
553 		     struct snd_soc_dai *dai)
554 {
555 	return -EOPNOTSUPP;
556 }
557 
558 int wcd937x_sdw_set_sdw_stream(struct wcd937x_sdw_priv *wcd,
559 			       struct snd_soc_dai *dai,
560 			       void *stream, int direction)
561 {
562 	return -EOPNOTSUPP;
563 }
564 
565 int wcd937x_sdw_hw_params(struct wcd937x_sdw_priv *wcd,
566 			  struct snd_pcm_substream *substream,
567 			  struct snd_pcm_hw_params *params,
568 			  struct snd_soc_dai *dai)
569 {
570 	return -EOPNOTSUPP;
571 }
572 #endif
573 
574 enum {
575 	/* INTR_CTRL_INT_MASK_0 */
576 	WCD937X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
577 	WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET,
578 	WCD937X_IRQ_MBHC_ELECT_INS_REM_DET,
579 	WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
580 	WCD937X_IRQ_MBHC_SW_DET,
581 	WCD937X_IRQ_HPHR_OCP_INT,
582 	WCD937X_IRQ_HPHR_CNP_INT,
583 	WCD937X_IRQ_HPHL_OCP_INT,
584 
585 	/* INTR_CTRL_INT_MASK_1 */
586 	WCD937X_IRQ_HPHL_CNP_INT,
587 	WCD937X_IRQ_EAR_CNP_INT,
588 	WCD937X_IRQ_EAR_SCD_INT,
589 	WCD937X_IRQ_AUX_CNP_INT,
590 	WCD937X_IRQ_AUX_SCD_INT,
591 	WCD937X_IRQ_HPHL_PDM_WD_INT,
592 	WCD937X_IRQ_HPHR_PDM_WD_INT,
593 	WCD937X_IRQ_AUX_PDM_WD_INT,
594 
595 	/* INTR_CTRL_INT_MASK_2 */
596 	WCD937X_IRQ_LDORT_SCD_INT,
597 	WCD937X_IRQ_MBHC_MOISTURE_INT,
598 	WCD937X_IRQ_HPHL_SURGE_DET_INT,
599 	WCD937X_IRQ_HPHR_SURGE_DET_INT,
600 	WCD937X_NUM_IRQS,
601 };
602 
603 enum wcd937x_tx_sdw_channels {
604 	WCD937X_ADC1,
605 	WCD937X_ADC2,
606 	WCD937X_ADC3,
607 	WCD937X_DMIC0,
608 	WCD937X_DMIC1,
609 	WCD937X_MBHC,
610 	WCD937X_DMIC2,
611 	WCD937X_DMIC3,
612 	WCD937X_DMIC4,
613 	WCD937X_DMIC5,
614 	WCD937X_DMIC6,
615 };
616 
617 enum wcd937x_rx_sdw_channels {
618 	WCD937X_HPH_L,
619 	WCD937X_HPH_R,
620 	WCD937X_CLSH,
621 	WCD937X_COMP_L,
622 	WCD937X_COMP_R,
623 	WCD937X_LO,
624 	WCD937X_DSD_R,
625 	WCD937X_DSD_L,
626 };
627 
628 #endif
629