1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/clk-provider.h> 6 #include <linux/interrupt.h> 7 #include <linux/kernel.h> 8 #include <linux/mfd/wcd934x/registers.h> 9 #include <linux/mfd/wcd934x/wcd934x.h> 10 #include <linux/module.h> 11 #include <linux/mutex.h> 12 #include <linux/of_clk.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/slimbus.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dapm.h> 21 #include <sound/tlv.h> 22 #include "wcd-clsh-v2.h" 23 #include "wcd-mbhc-v2.h" 24 25 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 26 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 27 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 28 /* Fractional Rates */ 29 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 30 SNDRV_PCM_RATE_176400) 31 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 32 SNDRV_PCM_FMTBIT_S24_LE) 33 34 /* slave port water mark level 35 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 36 */ 37 #define SLAVE_PORT_WATER_MARK_6BYTES 0 38 #define SLAVE_PORT_WATER_MARK_9BYTES 1 39 #define SLAVE_PORT_WATER_MARK_12BYTES 2 40 #define SLAVE_PORT_WATER_MARK_15BYTES 3 41 #define SLAVE_PORT_WATER_MARK_SHIFT 1 42 #define SLAVE_PORT_ENABLE 1 43 #define SLAVE_PORT_DISABLE 0 44 #define WCD934X_SLIM_WATER_MARK_VAL \ 45 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 46 (SLAVE_PORT_ENABLE)) 47 48 #define WCD934X_SLIM_NUM_PORT_REG 3 49 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2) 50 #define WCD934X_SLIM_IRQ_OVERFLOW BIT(0) 51 #define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1) 52 #define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2) 53 54 #define WCD934X_MCLK_CLK_12P288MHZ 12288000 55 #define WCD934X_MCLK_CLK_9P6MHZ 9600000 56 57 /* Only valid for 9.6 MHz mclk */ 58 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000 59 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000 60 61 /* Only valid for 12.288 MHz mclk */ 62 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000 63 64 #define WCD934X_DMIC_CLK_DIV_2 0x0 65 #define WCD934X_DMIC_CLK_DIV_3 0x1 66 #define WCD934X_DMIC_CLK_DIV_4 0x2 67 #define WCD934X_DMIC_CLK_DIV_6 0x3 68 #define WCD934X_DMIC_CLK_DIV_8 0x4 69 #define WCD934X_DMIC_CLK_DIV_16 0x5 70 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02 71 72 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 73 #define CF_MIN_3DB_4HZ 0x0 74 #define CF_MIN_3DB_75HZ 0x1 75 #define CF_MIN_3DB_150HZ 0x2 76 77 #define WCD934X_RX_START 16 78 #define WCD934X_NUM_INTERPOLATORS 9 79 #define WCD934X_RX_PATH_CTL_OFFSET 20 80 #define WCD934X_MAX_VALID_ADC_MUX 13 81 #define WCD934X_INVALID_ADC_MUX 9 82 83 #define WCD934X_SLIM_RX_CH(p) \ 84 {.port = p + WCD934X_RX_START, .shift = p,} 85 86 #define WCD934X_SLIM_TX_CH(p) \ 87 {.port = p, .shift = p,} 88 89 /* Feature masks to distinguish codec version */ 90 #define DSD_DISABLED_MASK 0 91 #define SLNQ_DISABLED_MASK 1 92 93 #define DSD_DISABLED BIT(DSD_DISABLED_MASK) 94 #define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK) 95 96 /* As fine version info cannot be retrieved before wcd probe. 97 * Define three coarse versions for possible future use before wcd probe. 98 */ 99 #define WCD_VERSION_WCD9340_1_0 0x400 100 #define WCD_VERSION_WCD9341_1_0 0x410 101 #define WCD_VERSION_WCD9340_1_1 0x401 102 #define WCD_VERSION_WCD9341_1_1 0x411 103 #define WCD934X_AMIC_PWR_LEVEL_LP 0 104 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1 105 #define WCD934X_AMIC_PWR_LEVEL_HP 2 106 #define WCD934X_AMIC_PWR_LEVEL_HYBRID 3 107 #define WCD934X_AMIC_PWR_LVL_MASK 0x60 108 #define WCD934X_AMIC_PWR_LVL_SHIFT 0x5 109 110 #define WCD934X_DEC_PWR_LVL_MASK 0x06 111 #define WCD934X_DEC_PWR_LVL_LP 0x02 112 #define WCD934X_DEC_PWR_LVL_HP 0x04 113 #define WCD934X_DEC_PWR_LVL_DF 0x00 114 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF 115 116 #define WCD934X_DEF_MICBIAS_MV 1800 117 #define WCD934X_MAX_MICBIAS_MV 2850 118 119 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 120 121 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \ 122 { \ 123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 124 .info = wcd934x_iir_filter_info, \ 125 .get = wcd934x_get_iir_band_audio_mixer, \ 126 .put = wcd934x_put_iir_band_audio_mixer, \ 127 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 128 .iir_idx = iidx, \ 129 .band_idx = bidx, \ 130 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \ 131 } \ 132 } 133 134 /* Z value defined in milliohm */ 135 #define WCD934X_ZDET_VAL_32 32000 136 #define WCD934X_ZDET_VAL_400 400000 137 #define WCD934X_ZDET_VAL_1200 1200000 138 #define WCD934X_ZDET_VAL_100K 100000000 139 /* Z floating defined in ohms */ 140 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE 141 142 #define WCD934X_ZDET_NUM_MEASUREMENTS 900 143 #define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14) 144 #define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF) 145 /* Z value compared in milliOhm */ 146 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000)) 147 #define WCD934X_MBHC_ZDET_CONST (86 * 16384) 148 #define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM 149 #define WCD934X_MBHC_MAX_BUTTONS (8) 150 #define WCD_MBHC_HS_V_MAX 1600 151 152 #define WCD934X_INTERPOLATOR_PATH(id) \ 153 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 154 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 155 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 156 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 157 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 158 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 159 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 160 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 161 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \ 162 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \ 163 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 164 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 165 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 166 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 167 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 168 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 169 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 170 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 171 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \ 172 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \ 173 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 174 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 175 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 176 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 177 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 178 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 179 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 180 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 181 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \ 182 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \ 183 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 184 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 185 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 186 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 187 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 188 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 189 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 190 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 191 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 192 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 193 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 194 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \ 195 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \ 196 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \ 197 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \ 198 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \ 199 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \ 200 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \ 201 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"} 202 203 #define WCD934X_INTERPOLATOR_MIX2(id) \ 204 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 205 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"} 206 207 #define WCD934X_SLIM_RX_AIF_PATH(id) \ 208 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \ 209 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \ 210 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \ 211 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \ 212 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"} 213 214 #define WCD934X_ADC_MUX(id) \ 215 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \ 216 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \ 217 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 218 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 219 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 220 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 221 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 222 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 223 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 224 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 225 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 226 {"AMIC MUX" #id, "ADC4", "ADC4"} 227 228 #define WCD934X_IIR_INP_MUX(id) \ 229 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 230 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 231 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 232 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 233 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 234 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 235 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 236 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 237 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \ 238 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \ 239 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \ 240 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \ 241 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \ 242 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \ 243 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \ 244 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \ 245 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \ 246 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \ 247 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \ 248 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \ 249 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \ 250 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \ 251 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \ 252 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \ 253 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \ 254 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \ 255 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \ 256 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \ 257 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \ 258 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \ 259 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \ 260 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \ 261 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \ 262 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \ 263 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \ 264 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \ 265 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \ 266 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \ 267 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \ 268 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \ 269 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \ 270 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \ 271 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \ 272 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \ 273 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \ 274 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \ 275 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \ 276 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \ 277 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \ 278 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \ 279 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \ 280 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \ 281 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \ 282 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \ 283 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \ 284 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \ 285 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \ 286 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \ 287 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \ 288 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \ 289 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \ 290 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \ 291 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \ 292 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \ 293 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \ 294 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \ 295 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \ 296 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \ 297 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \ 298 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \ 299 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \ 300 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"} 301 302 #define WCD934X_SLIM_TX_AIF_PATH(id) \ 303 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 304 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 305 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \ 306 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"} 307 308 #define WCD934X_MAX_MICBIAS MIC_BIAS_4 309 310 enum { 311 SIDO_SOURCE_INTERNAL, 312 SIDO_SOURCE_RCO_BG, 313 }; 314 315 enum { 316 INTERP_EAR = 0, 317 INTERP_HPHL, 318 INTERP_HPHR, 319 INTERP_LO1, 320 INTERP_LO2, 321 INTERP_LO3_NA, /* LO3 not avalible in Tavil */ 322 INTERP_LO4_NA, 323 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */ 324 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */ 325 INTERP_MAX, 326 }; 327 328 enum { 329 WCD934X_RX0 = 0, 330 WCD934X_RX1, 331 WCD934X_RX2, 332 WCD934X_RX3, 333 WCD934X_RX4, 334 WCD934X_RX5, 335 WCD934X_RX6, 336 WCD934X_RX7, 337 WCD934X_RX8, 338 WCD934X_RX9, 339 WCD934X_RX10, 340 WCD934X_RX11, 341 WCD934X_RX12, 342 WCD934X_RX_MAX, 343 }; 344 345 enum { 346 WCD934X_TX0 = 0, 347 WCD934X_TX1, 348 WCD934X_TX2, 349 WCD934X_TX3, 350 WCD934X_TX4, 351 WCD934X_TX5, 352 WCD934X_TX6, 353 WCD934X_TX7, 354 WCD934X_TX8, 355 WCD934X_TX9, 356 WCD934X_TX10, 357 WCD934X_TX11, 358 WCD934X_TX12, 359 WCD934X_TX13, 360 WCD934X_TX14, 361 WCD934X_TX15, 362 WCD934X_TX_MAX, 363 }; 364 365 struct wcd934x_slim_ch { 366 u32 ch_num; 367 u16 port; 368 u16 shift; 369 struct list_head list; 370 }; 371 372 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = { 373 WCD934X_SLIM_TX_CH(0), 374 WCD934X_SLIM_TX_CH(1), 375 WCD934X_SLIM_TX_CH(2), 376 WCD934X_SLIM_TX_CH(3), 377 WCD934X_SLIM_TX_CH(4), 378 WCD934X_SLIM_TX_CH(5), 379 WCD934X_SLIM_TX_CH(6), 380 WCD934X_SLIM_TX_CH(7), 381 WCD934X_SLIM_TX_CH(8), 382 WCD934X_SLIM_TX_CH(9), 383 WCD934X_SLIM_TX_CH(10), 384 WCD934X_SLIM_TX_CH(11), 385 WCD934X_SLIM_TX_CH(12), 386 WCD934X_SLIM_TX_CH(13), 387 WCD934X_SLIM_TX_CH(14), 388 WCD934X_SLIM_TX_CH(15), 389 }; 390 391 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = { 392 WCD934X_SLIM_RX_CH(0), /* 16 */ 393 WCD934X_SLIM_RX_CH(1), /* 17 */ 394 WCD934X_SLIM_RX_CH(2), 395 WCD934X_SLIM_RX_CH(3), 396 WCD934X_SLIM_RX_CH(4), 397 WCD934X_SLIM_RX_CH(5), 398 WCD934X_SLIM_RX_CH(6), 399 WCD934X_SLIM_RX_CH(7), 400 WCD934X_SLIM_RX_CH(8), 401 WCD934X_SLIM_RX_CH(9), 402 WCD934X_SLIM_RX_CH(10), 403 WCD934X_SLIM_RX_CH(11), 404 WCD934X_SLIM_RX_CH(12), 405 }; 406 407 /* Codec supports 2 IIR filters */ 408 enum { 409 IIR0 = 0, 410 IIR1, 411 IIR_MAX, 412 }; 413 414 /* Each IIR has 5 Filter Stages */ 415 enum { 416 BAND1 = 0, 417 BAND2, 418 BAND3, 419 BAND4, 420 BAND5, 421 BAND_MAX, 422 }; 423 424 enum { 425 COMPANDER_1, /* HPH_L */ 426 COMPANDER_2, /* HPH_R */ 427 COMPANDER_3, /* LO1_DIFF */ 428 COMPANDER_4, /* LO2_DIFF */ 429 COMPANDER_5, /* LO3_SE - not used in Tavil */ 430 COMPANDER_6, /* LO4_SE - not used in Tavil */ 431 COMPANDER_7, /* SWR SPK CH1 */ 432 COMPANDER_8, /* SWR SPK CH2 */ 433 COMPANDER_MAX, 434 }; 435 436 enum { 437 AIF1_PB = 0, 438 AIF1_CAP, 439 AIF2_PB, 440 AIF2_CAP, 441 AIF3_PB, 442 AIF3_CAP, 443 AIF4_PB, 444 AIF4_VIFEED, 445 AIF4_MAD_TX, 446 NUM_CODEC_DAIS, 447 }; 448 449 enum { 450 INTn_1_INP_SEL_ZERO = 0, 451 INTn_1_INP_SEL_DEC0, 452 INTn_1_INP_SEL_DEC1, 453 INTn_1_INP_SEL_IIR0, 454 INTn_1_INP_SEL_IIR1, 455 INTn_1_INP_SEL_RX0, 456 INTn_1_INP_SEL_RX1, 457 INTn_1_INP_SEL_RX2, 458 INTn_1_INP_SEL_RX3, 459 INTn_1_INP_SEL_RX4, 460 INTn_1_INP_SEL_RX5, 461 INTn_1_INP_SEL_RX6, 462 INTn_1_INP_SEL_RX7, 463 }; 464 465 enum { 466 INTn_2_INP_SEL_ZERO = 0, 467 INTn_2_INP_SEL_RX0, 468 INTn_2_INP_SEL_RX1, 469 INTn_2_INP_SEL_RX2, 470 INTn_2_INP_SEL_RX3, 471 INTn_2_INP_SEL_RX4, 472 INTn_2_INP_SEL_RX5, 473 INTn_2_INP_SEL_RX6, 474 INTn_2_INP_SEL_RX7, 475 INTn_2_INP_SEL_PROXIMITY, 476 }; 477 478 enum { 479 INTERP_MAIN_PATH, 480 INTERP_MIX_PATH, 481 }; 482 483 struct interp_sample_rate { 484 int sample_rate; 485 int rate_val; 486 }; 487 488 static struct interp_sample_rate sr_val_tbl[] = { 489 {8000, 0x0}, 490 {16000, 0x1}, 491 {32000, 0x3}, 492 {48000, 0x4}, 493 {96000, 0x5}, 494 {192000, 0x6}, 495 {384000, 0x7}, 496 {44100, 0x9}, 497 {88200, 0xA}, 498 {176400, 0xB}, 499 {352800, 0xC}, 500 }; 501 502 struct wcd934x_mbhc_zdet_param { 503 u16 ldo_ctl; 504 u16 noff; 505 u16 nshift; 506 u16 btn5; 507 u16 btn6; 508 u16 btn7; 509 }; 510 511 struct wcd_slim_codec_dai_data { 512 struct list_head slim_ch_list; 513 struct slim_stream_config sconfig; 514 struct slim_stream_runtime *sruntime; 515 }; 516 517 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = { 518 { 519 .name = "WCD9335-IFC-DEV", 520 .range_min = 0x0, 521 .range_max = 0xffff, 522 .selector_reg = 0x800, 523 .selector_mask = 0xfff, 524 .selector_shift = 0, 525 .window_start = 0x800, 526 .window_len = 0x400, 527 }, 528 }; 529 530 static struct regmap_config wcd934x_ifc_regmap_config = { 531 .reg_bits = 16, 532 .val_bits = 8, 533 .max_register = 0xffff, 534 .ranges = wcd934x_ifc_ranges, 535 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges), 536 }; 537 538 struct wcd934x_codec { 539 struct device *dev; 540 struct clk_hw hw; 541 struct clk *extclk; 542 struct regmap *regmap; 543 struct regmap *if_regmap; 544 struct slim_device *sdev; 545 struct slim_device *sidev; 546 struct wcd_clsh_ctrl *clsh_ctrl; 547 struct snd_soc_component *component; 548 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX]; 549 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX]; 550 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 551 int rate; 552 u32 version; 553 u32 hph_mode; 554 int num_rx_port; 555 int num_tx_port; 556 u32 tx_port_value[WCD934X_TX_MAX]; 557 u32 rx_port_value[WCD934X_RX_MAX]; 558 int sido_input_src; 559 int dmic_0_1_clk_cnt; 560 int dmic_2_3_clk_cnt; 561 int dmic_4_5_clk_cnt; 562 int dmic_sample_rate; 563 int comp_enabled[COMPANDER_MAX]; 564 int sysclk_users; 565 struct mutex sysclk_mutex; 566 /* mbhc module */ 567 struct wcd_mbhc *mbhc; 568 struct wcd_mbhc_config mbhc_cfg; 569 struct wcd_mbhc_intr intr_ids; 570 bool mbhc_started; 571 struct mutex micb_lock; 572 u32 micb_ref[WCD934X_MAX_MICBIAS]; 573 u32 pullup_ref[WCD934X_MAX_MICBIAS]; 574 u32 micb1_mv; 575 u32 micb2_mv; 576 u32 micb3_mv; 577 u32 micb4_mv; 578 }; 579 580 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw) 581 582 struct wcd_iir_filter_ctl { 583 unsigned int iir_idx; 584 unsigned int band_idx; 585 struct soc_bytes_ext bytes_ext; 586 }; 587 588 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 589 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 590 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 591 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 592 593 /* Cutoff frequency for high pass filter */ 594 static const char * const cf_text[] = { 595 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 596 }; 597 598 static const char * const rx_cf_text[] = { 599 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 600 "CF_NEG_3DB_0P48HZ" 601 }; 602 603 static const char * const rx_hph_mode_mux_text[] = { 604 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 605 "Class-H Hi-Fi Low Power" 606 }; 607 608 static const char *const slim_rx_mux_text[] = { 609 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 610 }; 611 612 static const char * const rx_int0_7_mix_mux_text[] = { 613 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 614 "RX6", "RX7", "PROXIMITY" 615 }; 616 617 static const char * const rx_int_mix_mux_text[] = { 618 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 619 "RX6", "RX7" 620 }; 621 622 static const char * const rx_prim_mix_text[] = { 623 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 624 "RX3", "RX4", "RX5", "RX6", "RX7" 625 }; 626 627 static const char * const rx_sidetone_mix_text[] = { 628 "ZERO", "SRC0", "SRC1", "SRC_SUM" 629 }; 630 631 static const char * const iir_inp_mux_text[] = { 632 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", 633 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7" 634 }; 635 636 static const char * const rx_int_dem_inp_mux_text[] = { 637 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 638 }; 639 640 static const char * const rx_int0_1_interp_mux_text[] = { 641 "ZERO", "RX INT0_1 MIX1", 642 }; 643 644 static const char * const rx_int1_1_interp_mux_text[] = { 645 "ZERO", "RX INT1_1 MIX1", 646 }; 647 648 static const char * const rx_int2_1_interp_mux_text[] = { 649 "ZERO", "RX INT2_1 MIX1", 650 }; 651 652 static const char * const rx_int3_1_interp_mux_text[] = { 653 "ZERO", "RX INT3_1 MIX1", 654 }; 655 656 static const char * const rx_int4_1_interp_mux_text[] = { 657 "ZERO", "RX INT4_1 MIX1", 658 }; 659 660 static const char * const rx_int7_1_interp_mux_text[] = { 661 "ZERO", "RX INT7_1 MIX1", 662 }; 663 664 static const char * const rx_int8_1_interp_mux_text[] = { 665 "ZERO", "RX INT8_1 MIX1", 666 }; 667 668 static const char * const rx_int0_2_interp_mux_text[] = { 669 "ZERO", "RX INT0_2 MUX", 670 }; 671 672 static const char * const rx_int1_2_interp_mux_text[] = { 673 "ZERO", "RX INT1_2 MUX", 674 }; 675 676 static const char * const rx_int2_2_interp_mux_text[] = { 677 "ZERO", "RX INT2_2 MUX", 678 }; 679 680 static const char * const rx_int3_2_interp_mux_text[] = { 681 "ZERO", "RX INT3_2 MUX", 682 }; 683 684 static const char * const rx_int4_2_interp_mux_text[] = { 685 "ZERO", "RX INT4_2 MUX", 686 }; 687 688 static const char * const rx_int7_2_interp_mux_text[] = { 689 "ZERO", "RX INT7_2 MUX", 690 }; 691 692 static const char * const rx_int8_2_interp_mux_text[] = { 693 "ZERO", "RX INT8_2 MUX", 694 }; 695 696 static const char * const dmic_mux_text[] = { 697 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5" 698 }; 699 700 static const char * const amic_mux_text[] = { 701 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4" 702 }; 703 704 static const char * const amic4_5_sel_text[] = { 705 "AMIC4", "AMIC5" 706 }; 707 708 static const char * const adc_mux_text[] = { 709 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 710 }; 711 712 static const char * const cdc_if_tx0_mux_text[] = { 713 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 714 }; 715 716 static const char * const cdc_if_tx1_mux_text[] = { 717 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 718 }; 719 720 static const char * const cdc_if_tx2_mux_text[] = { 721 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 722 }; 723 724 static const char * const cdc_if_tx3_mux_text[] = { 725 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 726 }; 727 728 static const char * const cdc_if_tx4_mux_text[] = { 729 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 730 }; 731 732 static const char * const cdc_if_tx5_mux_text[] = { 733 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 734 }; 735 736 static const char * const cdc_if_tx6_mux_text[] = { 737 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 738 }; 739 740 static const char * const cdc_if_tx7_mux_text[] = { 741 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 742 }; 743 744 static const char * const cdc_if_tx8_mux_text[] = { 745 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 746 }; 747 748 static const char * const cdc_if_tx9_mux_text[] = { 749 "ZERO", "DEC7", "DEC7_192" 750 }; 751 752 static const char * const cdc_if_tx10_mux_text[] = { 753 "ZERO", "DEC6", "DEC6_192" 754 }; 755 756 static const char * const cdc_if_tx11_mux_text[] = { 757 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST" 758 }; 759 760 static const char * const cdc_if_tx11_inp1_mux_text[] = { 761 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", 762 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12" 763 }; 764 765 static const char * const cdc_if_tx13_mux_text[] = { 766 "CDC_DEC_5", "MAD_BRDCST" 767 }; 768 769 static const char * const cdc_if_tx13_inp1_mux_text[] = { 770 "ZERO", "DEC5", "DEC5_192" 771 }; 772 773 static const struct soc_enum cf_dec0_enum = 774 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 775 776 static const struct soc_enum cf_dec1_enum = 777 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 778 779 static const struct soc_enum cf_dec2_enum = 780 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 781 782 static const struct soc_enum cf_dec3_enum = 783 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 784 785 static const struct soc_enum cf_dec4_enum = 786 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 787 788 static const struct soc_enum cf_dec5_enum = 789 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 790 791 static const struct soc_enum cf_dec6_enum = 792 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 793 794 static const struct soc_enum cf_dec7_enum = 795 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 796 797 static const struct soc_enum cf_dec8_enum = 798 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 799 800 static const struct soc_enum cf_int0_1_enum = 801 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 802 803 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2, 804 rx_cf_text); 805 806 static const struct soc_enum cf_int1_1_enum = 807 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 808 809 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2, 810 rx_cf_text); 811 812 static const struct soc_enum cf_int2_1_enum = 813 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 814 815 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2, 816 rx_cf_text); 817 818 static const struct soc_enum cf_int3_1_enum = 819 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 820 821 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2, 822 rx_cf_text); 823 824 static const struct soc_enum cf_int4_1_enum = 825 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 826 827 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2, 828 rx_cf_text); 829 830 static const struct soc_enum cf_int7_1_enum = 831 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 832 833 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2, 834 rx_cf_text); 835 836 static const struct soc_enum cf_int8_1_enum = 837 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 838 839 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2, 840 rx_cf_text); 841 842 static const struct soc_enum rx_hph_mode_mux_enum = 843 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 844 rx_hph_mode_mux_text); 845 846 static const struct soc_enum slim_rx_mux_enum = 847 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 848 849 static const struct soc_enum rx_int0_2_mux_chain_enum = 850 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 851 rx_int0_7_mix_mux_text); 852 853 static const struct soc_enum rx_int1_2_mux_chain_enum = 854 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 855 rx_int_mix_mux_text); 856 857 static const struct soc_enum rx_int2_2_mux_chain_enum = 858 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 859 rx_int_mix_mux_text); 860 861 static const struct soc_enum rx_int3_2_mux_chain_enum = 862 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 863 rx_int_mix_mux_text); 864 865 static const struct soc_enum rx_int4_2_mux_chain_enum = 866 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 867 rx_int_mix_mux_text); 868 869 static const struct soc_enum rx_int7_2_mux_chain_enum = 870 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 871 rx_int0_7_mix_mux_text); 872 873 static const struct soc_enum rx_int8_2_mux_chain_enum = 874 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 875 rx_int_mix_mux_text); 876 877 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 878 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 879 rx_prim_mix_text); 880 881 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 882 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 883 rx_prim_mix_text); 884 885 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 886 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 887 rx_prim_mix_text); 888 889 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 890 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 891 rx_prim_mix_text); 892 893 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 894 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 895 rx_prim_mix_text); 896 897 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 898 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 899 rx_prim_mix_text); 900 901 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 902 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 903 rx_prim_mix_text); 904 905 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 906 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 907 rx_prim_mix_text); 908 909 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 910 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 911 rx_prim_mix_text); 912 913 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 914 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 915 rx_prim_mix_text); 916 917 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 918 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 919 rx_prim_mix_text); 920 921 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 922 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 923 rx_prim_mix_text); 924 925 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 926 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 927 rx_prim_mix_text); 928 929 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 930 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 931 rx_prim_mix_text); 932 933 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 934 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 935 rx_prim_mix_text); 936 937 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 938 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 939 rx_prim_mix_text); 940 941 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 942 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 943 rx_prim_mix_text); 944 945 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 946 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 947 rx_prim_mix_text); 948 949 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 950 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 951 rx_prim_mix_text); 952 953 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 954 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 955 rx_prim_mix_text); 956 957 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 958 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 959 rx_prim_mix_text); 960 961 static const struct soc_enum rx_int0_mix2_inp_mux_enum = 962 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4, 963 rx_sidetone_mix_text); 964 965 static const struct soc_enum rx_int1_mix2_inp_mux_enum = 966 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4, 967 rx_sidetone_mix_text); 968 969 static const struct soc_enum rx_int2_mix2_inp_mux_enum = 970 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4, 971 rx_sidetone_mix_text); 972 973 static const struct soc_enum rx_int3_mix2_inp_mux_enum = 974 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4, 975 rx_sidetone_mix_text); 976 977 static const struct soc_enum rx_int4_mix2_inp_mux_enum = 978 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4, 979 rx_sidetone_mix_text); 980 981 static const struct soc_enum rx_int7_mix2_inp_mux_enum = 982 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4, 983 rx_sidetone_mix_text); 984 985 static const struct soc_enum iir0_inp0_mux_enum = 986 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 987 0, 18, iir_inp_mux_text); 988 989 static const struct soc_enum iir0_inp1_mux_enum = 990 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 991 0, 18, iir_inp_mux_text); 992 993 static const struct soc_enum iir0_inp2_mux_enum = 994 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 995 0, 18, iir_inp_mux_text); 996 997 static const struct soc_enum iir0_inp3_mux_enum = 998 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 999 0, 18, iir_inp_mux_text); 1000 1001 static const struct soc_enum iir1_inp0_mux_enum = 1002 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 1003 0, 18, iir_inp_mux_text); 1004 1005 static const struct soc_enum iir1_inp1_mux_enum = 1006 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 1007 0, 18, iir_inp_mux_text); 1008 1009 static const struct soc_enum iir1_inp2_mux_enum = 1010 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 1011 0, 18, iir_inp_mux_text); 1012 1013 static const struct soc_enum iir1_inp3_mux_enum = 1014 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 1015 0, 18, iir_inp_mux_text); 1016 1017 static const struct soc_enum rx_int0_dem_inp_mux_enum = 1018 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0, 1019 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1020 rx_int_dem_inp_mux_text); 1021 1022 static const struct soc_enum rx_int1_dem_inp_mux_enum = 1023 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0, 1024 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1025 rx_int_dem_inp_mux_text); 1026 1027 static const struct soc_enum rx_int2_dem_inp_mux_enum = 1028 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0, 1029 ARRAY_SIZE(rx_int_dem_inp_mux_text), 1030 rx_int_dem_inp_mux_text); 1031 1032 static const struct soc_enum tx_adc_mux0_enum = 1033 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 1034 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1035 static const struct soc_enum tx_adc_mux1_enum = 1036 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 1037 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1038 static const struct soc_enum tx_adc_mux2_enum = 1039 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 1040 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1041 static const struct soc_enum tx_adc_mux3_enum = 1042 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 1043 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1044 static const struct soc_enum tx_adc_mux4_enum = 1045 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2, 1046 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1047 static const struct soc_enum tx_adc_mux5_enum = 1048 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2, 1049 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1050 static const struct soc_enum tx_adc_mux6_enum = 1051 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2, 1052 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1053 static const struct soc_enum tx_adc_mux7_enum = 1054 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2, 1055 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1056 static const struct soc_enum tx_adc_mux8_enum = 1057 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4, 1058 ARRAY_SIZE(adc_mux_text), adc_mux_text); 1059 1060 static const struct soc_enum rx_int0_1_interp_mux_enum = 1061 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1062 rx_int0_1_interp_mux_text); 1063 1064 static const struct soc_enum rx_int1_1_interp_mux_enum = 1065 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1066 rx_int1_1_interp_mux_text); 1067 1068 static const struct soc_enum rx_int2_1_interp_mux_enum = 1069 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, 1070 rx_int2_1_interp_mux_text); 1071 1072 static const struct soc_enum rx_int3_1_interp_mux_enum = 1073 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text); 1074 1075 static const struct soc_enum rx_int4_1_interp_mux_enum = 1076 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text); 1077 1078 static const struct soc_enum rx_int7_1_interp_mux_enum = 1079 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text); 1080 1081 static const struct soc_enum rx_int8_1_interp_mux_enum = 1082 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text); 1083 1084 static const struct soc_enum rx_int0_2_interp_mux_enum = 1085 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text); 1086 1087 static const struct soc_enum rx_int1_2_interp_mux_enum = 1088 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text); 1089 1090 static const struct soc_enum rx_int2_2_interp_mux_enum = 1091 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text); 1092 1093 static const struct soc_enum rx_int3_2_interp_mux_enum = 1094 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text); 1095 1096 static const struct soc_enum rx_int4_2_interp_mux_enum = 1097 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text); 1098 1099 static const struct soc_enum rx_int7_2_interp_mux_enum = 1100 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text); 1101 1102 static const struct soc_enum rx_int8_2_interp_mux_enum = 1103 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text); 1104 1105 static const struct soc_enum tx_dmic_mux0_enum = 1106 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7, 1107 dmic_mux_text); 1108 1109 static const struct soc_enum tx_dmic_mux1_enum = 1110 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7, 1111 dmic_mux_text); 1112 1113 static const struct soc_enum tx_dmic_mux2_enum = 1114 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7, 1115 dmic_mux_text); 1116 1117 static const struct soc_enum tx_dmic_mux3_enum = 1118 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7, 1119 dmic_mux_text); 1120 1121 static const struct soc_enum tx_dmic_mux4_enum = 1122 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 1123 dmic_mux_text); 1124 1125 static const struct soc_enum tx_dmic_mux5_enum = 1126 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 1127 dmic_mux_text); 1128 1129 static const struct soc_enum tx_dmic_mux6_enum = 1130 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 1131 dmic_mux_text); 1132 1133 static const struct soc_enum tx_dmic_mux7_enum = 1134 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 1135 dmic_mux_text); 1136 1137 static const struct soc_enum tx_dmic_mux8_enum = 1138 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 1139 dmic_mux_text); 1140 1141 static const struct soc_enum tx_amic_mux0_enum = 1142 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5, 1143 amic_mux_text); 1144 static const struct soc_enum tx_amic_mux1_enum = 1145 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5, 1146 amic_mux_text); 1147 static const struct soc_enum tx_amic_mux2_enum = 1148 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5, 1149 amic_mux_text); 1150 static const struct soc_enum tx_amic_mux3_enum = 1151 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5, 1152 amic_mux_text); 1153 static const struct soc_enum tx_amic_mux4_enum = 1154 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5, 1155 amic_mux_text); 1156 static const struct soc_enum tx_amic_mux5_enum = 1157 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5, 1158 amic_mux_text); 1159 static const struct soc_enum tx_amic_mux6_enum = 1160 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5, 1161 amic_mux_text); 1162 static const struct soc_enum tx_amic_mux7_enum = 1163 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5, 1164 amic_mux_text); 1165 static const struct soc_enum tx_amic_mux8_enum = 1166 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5, 1167 amic_mux_text); 1168 1169 static const struct soc_enum tx_amic4_5_enum = 1170 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text); 1171 1172 static const struct soc_enum cdc_if_tx0_mux_enum = 1173 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 1174 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text); 1175 static const struct soc_enum cdc_if_tx1_mux_enum = 1176 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 1177 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text); 1178 static const struct soc_enum cdc_if_tx2_mux_enum = 1179 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 1180 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text); 1181 static const struct soc_enum cdc_if_tx3_mux_enum = 1182 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 1183 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text); 1184 static const struct soc_enum cdc_if_tx4_mux_enum = 1185 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 1186 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text); 1187 static const struct soc_enum cdc_if_tx5_mux_enum = 1188 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 1189 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text); 1190 static const struct soc_enum cdc_if_tx6_mux_enum = 1191 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 1192 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text); 1193 static const struct soc_enum cdc_if_tx7_mux_enum = 1194 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 1195 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text); 1196 static const struct soc_enum cdc_if_tx8_mux_enum = 1197 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 1198 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text); 1199 static const struct soc_enum cdc_if_tx9_mux_enum = 1200 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2, 1201 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text); 1202 static const struct soc_enum cdc_if_tx10_mux_enum = 1203 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4, 1204 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text); 1205 static const struct soc_enum cdc_if_tx11_inp1_mux_enum = 1206 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0, 1207 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text), 1208 cdc_if_tx11_inp1_mux_text); 1209 static const struct soc_enum cdc_if_tx11_mux_enum = 1210 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0, 1211 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text); 1212 static const struct soc_enum cdc_if_tx13_inp1_mux_enum = 1213 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4, 1214 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text), 1215 cdc_if_tx13_inp1_mux_text); 1216 static const struct soc_enum cdc_if_tx13_mux_enum = 1217 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0, 1218 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text); 1219 1220 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = { 1221 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80), 1222 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40), 1223 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20), 1224 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30), 1225 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08), 1226 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0), 1227 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04), 1228 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10), 1229 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08), 1230 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01), 1231 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06), 1232 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80), 1233 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F), 1234 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03), 1235 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03), 1236 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08), 1237 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1238 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20), 1239 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80), 1240 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40), 1241 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10), 1242 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07), 1243 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70), 1244 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF), 1245 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0), 1246 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF), 1247 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40), 1248 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80), 1249 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0), 1250 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10), 1251 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02), 1252 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01), 1253 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70), 1254 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20), 1255 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40), 1256 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10), 1257 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01), 1258 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01), 1259 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04), 1260 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08), 1261 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08), 1262 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40), 1263 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80), 1264 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF), 1265 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F), 1266 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10), 1267 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04), 1268 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02), 1269 }; 1270 1271 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src) 1272 { 1273 if (sido_src == wcd->sido_input_src) 1274 return 0; 1275 1276 if (sido_src == SIDO_SOURCE_RCO_BG) { 1277 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO, 1278 WCD934X_ANA_RCO_BG_EN_MASK, 1279 WCD934X_ANA_RCO_BG_ENABLE); 1280 usleep_range(100, 110); 1281 } 1282 wcd->sido_input_src = sido_src; 1283 1284 return 0; 1285 } 1286 1287 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd) 1288 { 1289 mutex_lock(&wcd->sysclk_mutex); 1290 1291 if (++wcd->sysclk_users != 1) { 1292 mutex_unlock(&wcd->sysclk_mutex); 1293 return 0; 1294 } 1295 mutex_unlock(&wcd->sysclk_mutex); 1296 1297 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1298 WCD934X_ANA_BIAS_EN_MASK, 1299 WCD934X_ANA_BIAS_EN); 1300 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1301 WCD934X_ANA_PRECHRG_EN_MASK, 1302 WCD934X_ANA_PRECHRG_EN); 1303 /* 1304 * 1ms delay is required after pre-charge is enabled 1305 * as per HW requirement 1306 */ 1307 usleep_range(1000, 1100); 1308 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1309 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1310 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1311 WCD934X_ANA_PRECHRG_MODE_MASK, 0); 1312 1313 /* 1314 * In data clock contrl register is changed 1315 * to CLK_SYS_MCLK_PRG 1316 */ 1317 1318 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1319 WCD934X_EXT_CLK_BUF_EN_MASK, 1320 WCD934X_EXT_CLK_BUF_EN); 1321 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1322 WCD934X_EXT_CLK_DIV_RATIO_MASK, 1323 WCD934X_EXT_CLK_DIV_BY_2); 1324 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1325 WCD934X_MCLK_SRC_MASK, 1326 WCD934X_MCLK_SRC_EXT_CLK); 1327 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1328 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN); 1329 regmap_update_bits(wcd->regmap, 1330 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 1331 WCD934X_CDC_FS_MCLK_CNT_EN_MASK, 1332 WCD934X_CDC_FS_MCLK_CNT_ENABLE); 1333 regmap_update_bits(wcd->regmap, 1334 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 1335 WCD934X_MCLK_EN_MASK, 1336 WCD934X_MCLK_EN); 1337 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE, 1338 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0); 1339 /* 1340 * 10us sleep is required after clock is enabled 1341 * as per HW requirement 1342 */ 1343 usleep_range(10, 15); 1344 1345 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1346 1347 return 0; 1348 } 1349 1350 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd) 1351 { 1352 mutex_lock(&wcd->sysclk_mutex); 1353 if (--wcd->sysclk_users != 0) { 1354 mutex_unlock(&wcd->sysclk_mutex); 1355 return 0; 1356 } 1357 mutex_unlock(&wcd->sysclk_mutex); 1358 1359 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG, 1360 WCD934X_EXT_CLK_BUF_EN_MASK | 1361 WCD934X_MCLK_EN_MASK, 0x0); 1362 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1363 WCD934X_ANA_BIAS_EN_MASK, 0); 1364 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS, 1365 WCD934X_ANA_PRECHRG_EN_MASK, 0); 1366 1367 return 0; 1368 } 1369 1370 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable) 1371 { 1372 int ret = 0; 1373 1374 if (enable) { 1375 ret = clk_prepare_enable(wcd->extclk); 1376 1377 if (ret) { 1378 dev_err(wcd->dev, "%s: ext clk enable failed\n", 1379 __func__); 1380 return ret; 1381 } 1382 ret = wcd934x_enable_ana_bias_and_sysclk(wcd); 1383 } else { 1384 int val; 1385 1386 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1387 &val); 1388 1389 /* Don't disable clock if soundwire using it.*/ 1390 if (val & WCD934X_CDC_SWR_CLK_EN_MASK) 1391 return 0; 1392 1393 wcd934x_disable_ana_bias_and_syclk(wcd); 1394 clk_disable_unprepare(wcd->extclk); 1395 } 1396 1397 return ret; 1398 } 1399 1400 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w, 1401 struct snd_kcontrol *kc, int event) 1402 { 1403 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 1404 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1405 1406 switch (event) { 1407 case SND_SOC_DAPM_PRE_PMU: 1408 return __wcd934x_cdc_mclk_enable(wcd, true); 1409 case SND_SOC_DAPM_POST_PMD: 1410 return __wcd934x_cdc_mclk_enable(wcd, false); 1411 } 1412 1413 return 0; 1414 } 1415 1416 static int wcd934x_get_version(struct wcd934x_codec *wcd) 1417 { 1418 int val1, val2, ver, ret; 1419 struct regmap *regmap; 1420 u16 id_minor; 1421 u32 version_mask = 0; 1422 1423 regmap = wcd->regmap; 1424 ver = 0; 1425 1426 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 1427 (u8 *)&id_minor, sizeof(u16)); 1428 1429 if (ret) 1430 return ret; 1431 1432 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1); 1433 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2); 1434 1435 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK; 1436 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK; 1437 1438 switch (version_mask) { 1439 case DSD_DISABLED | SLNQ_DISABLED: 1440 if (id_minor == 0) 1441 ver = WCD_VERSION_WCD9340_1_0; 1442 else if (id_minor == 0x01) 1443 ver = WCD_VERSION_WCD9340_1_1; 1444 break; 1445 case SLNQ_DISABLED: 1446 if (id_minor == 0) 1447 ver = WCD_VERSION_WCD9341_1_0; 1448 else if (id_minor == 0x01) 1449 ver = WCD_VERSION_WCD9341_1_1; 1450 break; 1451 } 1452 1453 wcd->version = ver; 1454 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver); 1455 1456 return 0; 1457 } 1458 1459 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd) 1460 { 1461 int rc, val; 1462 1463 __wcd934x_cdc_mclk_enable(wcd, true); 1464 1465 regmap_update_bits(wcd->regmap, 1466 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1467 WCD934X_EFUSE_SENSE_STATE_MASK, 1468 WCD934X_EFUSE_SENSE_STATE_DEF); 1469 regmap_update_bits(wcd->regmap, 1470 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 1471 WCD934X_EFUSE_SENSE_EN_MASK, 1472 WCD934X_EFUSE_SENSE_ENABLE); 1473 /* 1474 * 5ms sleep required after enabling efuse control 1475 * before checking the status. 1476 */ 1477 usleep_range(5000, 5500); 1478 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG); 1479 1480 rc = regmap_read(wcd->regmap, 1481 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val); 1482 if (rc || (!(val & 0x01))) 1483 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n", 1484 __func__, val, rc); 1485 1486 __wcd934x_cdc_mclk_enable(wcd, false); 1487 } 1488 1489 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable) 1490 { 1491 if (enable) { 1492 __wcd934x_cdc_mclk_enable(wcd, true); 1493 regmap_update_bits(wcd->regmap, 1494 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1495 WCD934X_CDC_SWR_CLK_EN_MASK, 1496 WCD934X_CDC_SWR_CLK_ENABLE); 1497 } else { 1498 regmap_update_bits(wcd->regmap, 1499 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 1500 WCD934X_CDC_SWR_CLK_EN_MASK, 0); 1501 __wcd934x_cdc_mclk_enable(wcd, false); 1502 } 1503 1504 return 0; 1505 } 1506 1507 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1508 u8 rate_val, u32 rate) 1509 { 1510 struct snd_soc_component *comp = dai->component; 1511 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 1512 struct wcd934x_slim_ch *ch; 1513 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1514 int inp, j; 1515 1516 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1517 inp = ch->shift + INTn_1_INP_SEL_RX0; 1518 /* 1519 * Loop through all interpolator MUX inputs and find out 1520 * to which interpolator input, the slim rx port 1521 * is connected 1522 */ 1523 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1524 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1525 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1526 continue; 1527 1528 cfg0 = snd_soc_component_read(comp, 1529 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1530 cfg1 = snd_soc_component_read(comp, 1531 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1532 1533 inp0_sel = cfg0 & 1534 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1535 inp1_sel = (cfg0 >> 4) & 1536 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1537 inp2_sel = (cfg1 >> 4) & 1538 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1539 1540 if ((inp0_sel == inp) || (inp1_sel == inp) || 1541 (inp2_sel == inp)) { 1542 /* rate is in Hz */ 1543 /* 1544 * Ear and speaker primary path does not support 1545 * native sample rates 1546 */ 1547 if ((j == INTERP_EAR || j == INTERP_SPKR1 || 1548 j == INTERP_SPKR2) && rate == 44100) 1549 dev_err(wcd->dev, 1550 "Cannot set 44.1KHz on INT%d\n", 1551 j); 1552 else 1553 snd_soc_component_update_bits(comp, 1554 WCD934X_CDC_RX_PATH_CTL(j), 1555 WCD934X_CDC_MIX_PCM_RATE_MASK, 1556 rate_val); 1557 } 1558 } 1559 } 1560 1561 return 0; 1562 } 1563 1564 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1565 int rate_val, u32 rate) 1566 { 1567 struct snd_soc_component *component = dai->component; 1568 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 1569 struct wcd934x_slim_ch *ch; 1570 int val, j; 1571 1572 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1573 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) { 1574 /* Interpolators 5 and 6 are not aviliable in Tavil */ 1575 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA) 1576 continue; 1577 val = snd_soc_component_read(component, 1578 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1579 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1580 1581 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) { 1582 /* 1583 * Ear mix path supports only 48, 96, 192, 1584 * 384KHz only 1585 */ 1586 if ((j == INTERP_EAR) && 1587 (rate_val < 0x4 || 1588 rate_val > 0x7)) { 1589 dev_err(component->dev, 1590 "Invalid rate for AIF_PB DAI(%d)\n", 1591 dai->id); 1592 return -EINVAL; 1593 } 1594 1595 snd_soc_component_update_bits(component, 1596 WCD934X_CDC_RX_PATH_MIX_CTL(j), 1597 WCD934X_CDC_MIX_PCM_RATE_MASK, 1598 rate_val); 1599 } 1600 } 1601 } 1602 1603 return 0; 1604 } 1605 1606 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai, 1607 u32 sample_rate) 1608 { 1609 int rate_val = 0; 1610 int i, ret; 1611 1612 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { 1613 if (sample_rate == sr_val_tbl[i].sample_rate) { 1614 rate_val = sr_val_tbl[i].rate_val; 1615 break; 1616 } 1617 } 1618 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { 1619 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate); 1620 return -EINVAL; 1621 } 1622 1623 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val, 1624 sample_rate); 1625 if (ret) 1626 return ret; 1627 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val, 1628 sample_rate); 1629 1630 return ret; 1631 } 1632 1633 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai, 1634 u8 rate_val, u32 rate) 1635 { 1636 struct snd_soc_component *comp = dai->component; 1637 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 1638 u8 shift = 0, shift_val = 0, tx_mux_sel; 1639 struct wcd934x_slim_ch *ch; 1640 int tx_port, tx_port_reg; 1641 int decimator = -1; 1642 1643 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1644 tx_port = ch->port; 1645 /* Find the SB TX MUX input - which decimator is connected */ 1646 switch (tx_port) { 1647 case 0 ... 3: 1648 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0; 1649 shift = (tx_port << 1); 1650 shift_val = 0x03; 1651 break; 1652 case 4 ... 7: 1653 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1; 1654 shift = ((tx_port - 4) << 1); 1655 shift_val = 0x03; 1656 break; 1657 case 8 ... 10: 1658 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2; 1659 shift = ((tx_port - 8) << 1); 1660 shift_val = 0x03; 1661 break; 1662 case 11: 1663 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1664 shift = 0; 1665 shift_val = 0x0F; 1666 break; 1667 case 13: 1668 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3; 1669 shift = 4; 1670 shift_val = 0x03; 1671 break; 1672 default: 1673 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1674 tx_port, dai->id); 1675 return -EINVAL; 1676 } 1677 1678 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1679 (shift_val << shift); 1680 1681 tx_mux_sel = tx_mux_sel >> shift; 1682 switch (tx_port) { 1683 case 0 ... 8: 1684 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1685 decimator = tx_port; 1686 break; 1687 case 9 ... 10: 1688 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1689 decimator = ((tx_port == 9) ? 7 : 6); 1690 break; 1691 case 11: 1692 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1693 decimator = tx_mux_sel - 1; 1694 break; 1695 case 13: 1696 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1697 decimator = 5; 1698 break; 1699 default: 1700 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n", 1701 tx_port); 1702 return -EINVAL; 1703 } 1704 1705 snd_soc_component_update_bits(comp, 1706 WCD934X_CDC_TX_PATH_CTL(decimator), 1707 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1708 rate_val); 1709 } 1710 1711 return 0; 1712 } 1713 1714 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd, 1715 struct wcd_slim_codec_dai_data *dai_data, 1716 int direction) 1717 { 1718 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1719 struct slim_stream_config *cfg = &dai_data->sconfig; 1720 struct wcd934x_slim_ch *ch; 1721 u16 payload = 0; 1722 int ret, i; 1723 1724 cfg->ch_count = 0; 1725 cfg->direction = direction; 1726 cfg->port_mask = 0; 1727 1728 /* Configure slave interface device */ 1729 list_for_each_entry(ch, slim_ch_list, list) { 1730 cfg->ch_count++; 1731 payload |= 1 << ch->shift; 1732 cfg->port_mask |= BIT(ch->port); 1733 } 1734 1735 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1736 if (!cfg->chs) 1737 return -ENOMEM; 1738 1739 i = 0; 1740 list_for_each_entry(ch, slim_ch_list, list) { 1741 cfg->chs[i++] = ch->ch_num; 1742 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1743 /* write to interface device */ 1744 ret = regmap_write(wcd->if_regmap, 1745 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1746 payload); 1747 1748 if (ret < 0) 1749 goto err; 1750 1751 /* configure the slave port for water mark and enable*/ 1752 ret = regmap_write(wcd->if_regmap, 1753 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port), 1754 WCD934X_SLIM_WATER_MARK_VAL); 1755 if (ret < 0) 1756 goto err; 1757 } else { 1758 ret = regmap_write(wcd->if_regmap, 1759 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1760 payload & 0x00FF); 1761 if (ret < 0) 1762 goto err; 1763 1764 /* ports 8,9 */ 1765 ret = regmap_write(wcd->if_regmap, 1766 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1767 (payload & 0xFF00) >> 8); 1768 if (ret < 0) 1769 goto err; 1770 1771 /* configure the slave port for water mark and enable*/ 1772 ret = regmap_write(wcd->if_regmap, 1773 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port), 1774 WCD934X_SLIM_WATER_MARK_VAL); 1775 1776 if (ret < 0) 1777 goto err; 1778 } 1779 } 1780 1781 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM"); 1782 1783 return 0; 1784 1785 err: 1786 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1787 kfree(cfg->chs); 1788 cfg->chs = NULL; 1789 1790 return ret; 1791 } 1792 1793 static int wcd934x_hw_params(struct snd_pcm_substream *substream, 1794 struct snd_pcm_hw_params *params, 1795 struct snd_soc_dai *dai) 1796 { 1797 struct wcd934x_codec *wcd; 1798 int ret, tx_fs_rate = 0; 1799 1800 wcd = snd_soc_component_get_drvdata(dai->component); 1801 1802 switch (substream->stream) { 1803 case SNDRV_PCM_STREAM_PLAYBACK: 1804 ret = wcd934x_set_interpolator_rate(dai, params_rate(params)); 1805 if (ret) { 1806 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1807 params_rate(params)); 1808 return ret; 1809 } 1810 switch (params_width(params)) { 1811 case 16 ... 24: 1812 wcd->dai[dai->id].sconfig.bps = params_width(params); 1813 break; 1814 default: 1815 dev_err(wcd->dev, "Invalid format 0x%x\n", 1816 params_width(params)); 1817 return -EINVAL; 1818 } 1819 break; 1820 1821 case SNDRV_PCM_STREAM_CAPTURE: 1822 switch (params_rate(params)) { 1823 case 8000: 1824 tx_fs_rate = 0; 1825 break; 1826 case 16000: 1827 tx_fs_rate = 1; 1828 break; 1829 case 32000: 1830 tx_fs_rate = 3; 1831 break; 1832 case 48000: 1833 tx_fs_rate = 4; 1834 break; 1835 case 96000: 1836 tx_fs_rate = 5; 1837 break; 1838 case 192000: 1839 tx_fs_rate = 6; 1840 break; 1841 case 384000: 1842 tx_fs_rate = 7; 1843 break; 1844 default: 1845 dev_err(wcd->dev, "Invalid TX sample rate: %d\n", 1846 params_rate(params)); 1847 return -EINVAL; 1848 1849 } 1850 1851 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate, 1852 params_rate(params)); 1853 if (ret < 0) { 1854 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1855 return ret; 1856 } 1857 switch (params_width(params)) { 1858 case 16 ... 32: 1859 wcd->dai[dai->id].sconfig.bps = params_width(params); 1860 break; 1861 default: 1862 dev_err(wcd->dev, "Invalid format 0x%x\n", 1863 params_width(params)); 1864 return -EINVAL; 1865 } 1866 break; 1867 default: 1868 dev_err(wcd->dev, "Invalid stream type %d\n", 1869 substream->stream); 1870 return -EINVAL; 1871 } 1872 1873 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1874 1875 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1876 } 1877 1878 static int wcd934x_hw_free(struct snd_pcm_substream *substream, 1879 struct snd_soc_dai *dai) 1880 { 1881 struct wcd_slim_codec_dai_data *dai_data; 1882 struct wcd934x_codec *wcd; 1883 1884 wcd = snd_soc_component_get_drvdata(dai->component); 1885 1886 dai_data = &wcd->dai[dai->id]; 1887 1888 kfree(dai_data->sconfig.chs); 1889 1890 return 0; 1891 } 1892 1893 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd, 1894 struct snd_soc_dai *dai) 1895 { 1896 struct wcd_slim_codec_dai_data *dai_data; 1897 struct wcd934x_codec *wcd; 1898 struct slim_stream_config *cfg; 1899 1900 wcd = snd_soc_component_get_drvdata(dai->component); 1901 1902 dai_data = &wcd->dai[dai->id]; 1903 1904 switch (cmd) { 1905 case SNDRV_PCM_TRIGGER_START: 1906 case SNDRV_PCM_TRIGGER_RESUME: 1907 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1908 cfg = &dai_data->sconfig; 1909 slim_stream_prepare(dai_data->sruntime, cfg); 1910 slim_stream_enable(dai_data->sruntime); 1911 break; 1912 case SNDRV_PCM_TRIGGER_STOP: 1913 case SNDRV_PCM_TRIGGER_SUSPEND: 1914 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1915 slim_stream_disable(dai_data->sruntime); 1916 slim_stream_unprepare(dai_data->sruntime); 1917 break; 1918 default: 1919 break; 1920 } 1921 1922 return 0; 1923 } 1924 1925 static int wcd934x_set_channel_map(struct snd_soc_dai *dai, 1926 unsigned int tx_num, 1927 const unsigned int *tx_slot, 1928 unsigned int rx_num, 1929 const unsigned int *rx_slot) 1930 { 1931 struct wcd934x_codec *wcd; 1932 int i; 1933 1934 wcd = snd_soc_component_get_drvdata(dai->component); 1935 1936 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) { 1937 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n", 1938 tx_num, rx_num); 1939 return -EINVAL; 1940 } 1941 1942 if (!tx_slot || !rx_slot) { 1943 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1944 tx_slot, rx_slot); 1945 return -EINVAL; 1946 } 1947 1948 wcd->num_rx_port = rx_num; 1949 for (i = 0; i < rx_num; i++) { 1950 wcd->rx_chs[i].ch_num = rx_slot[i]; 1951 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 1952 } 1953 1954 wcd->num_tx_port = tx_num; 1955 for (i = 0; i < tx_num; i++) { 1956 wcd->tx_chs[i].ch_num = tx_slot[i]; 1957 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 1958 } 1959 1960 return 0; 1961 } 1962 1963 static int wcd934x_get_channel_map(struct snd_soc_dai *dai, 1964 unsigned int *tx_num, unsigned int *tx_slot, 1965 unsigned int *rx_num, unsigned int *rx_slot) 1966 { 1967 struct wcd934x_slim_ch *ch; 1968 struct wcd934x_codec *wcd; 1969 int i = 0; 1970 1971 wcd = snd_soc_component_get_drvdata(dai->component); 1972 1973 switch (dai->id) { 1974 case AIF1_PB: 1975 case AIF2_PB: 1976 case AIF3_PB: 1977 case AIF4_PB: 1978 if (!rx_slot || !rx_num) { 1979 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 1980 rx_slot, rx_num); 1981 return -EINVAL; 1982 } 1983 1984 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1985 rx_slot[i++] = ch->ch_num; 1986 1987 *rx_num = i; 1988 break; 1989 case AIF1_CAP: 1990 case AIF2_CAP: 1991 case AIF3_CAP: 1992 if (!tx_slot || !tx_num) { 1993 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 1994 tx_slot, tx_num); 1995 return -EINVAL; 1996 } 1997 1998 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 1999 tx_slot[i++] = ch->ch_num; 2000 2001 *tx_num = i; 2002 break; 2003 default: 2004 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2005 break; 2006 } 2007 2008 return 0; 2009 } 2010 2011 static const struct snd_soc_dai_ops wcd934x_dai_ops = { 2012 .hw_params = wcd934x_hw_params, 2013 .hw_free = wcd934x_hw_free, 2014 .trigger = wcd934x_trigger, 2015 .set_channel_map = wcd934x_set_channel_map, 2016 .get_channel_map = wcd934x_get_channel_map, 2017 }; 2018 2019 static struct snd_soc_dai_driver wcd934x_slim_dais[] = { 2020 [0] = { 2021 .name = "wcd934x_rx1", 2022 .id = AIF1_PB, 2023 .playback = { 2024 .stream_name = "AIF1 Playback", 2025 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2026 .formats = WCD934X_FORMATS_S16_S24_LE, 2027 .rate_max = 192000, 2028 .rate_min = 8000, 2029 .channels_min = 1, 2030 .channels_max = 2, 2031 }, 2032 .ops = &wcd934x_dai_ops, 2033 }, 2034 [1] = { 2035 .name = "wcd934x_tx1", 2036 .id = AIF1_CAP, 2037 .capture = { 2038 .stream_name = "AIF1 Capture", 2039 .rates = WCD934X_RATES_MASK, 2040 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2041 .rate_min = 8000, 2042 .rate_max = 192000, 2043 .channels_min = 1, 2044 .channels_max = 4, 2045 }, 2046 .ops = &wcd934x_dai_ops, 2047 }, 2048 [2] = { 2049 .name = "wcd934x_rx2", 2050 .id = AIF2_PB, 2051 .playback = { 2052 .stream_name = "AIF2 Playback", 2053 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2054 .formats = WCD934X_FORMATS_S16_S24_LE, 2055 .rate_min = 8000, 2056 .rate_max = 192000, 2057 .channels_min = 1, 2058 .channels_max = 2, 2059 }, 2060 .ops = &wcd934x_dai_ops, 2061 }, 2062 [3] = { 2063 .name = "wcd934x_tx2", 2064 .id = AIF2_CAP, 2065 .capture = { 2066 .stream_name = "AIF2 Capture", 2067 .rates = WCD934X_RATES_MASK, 2068 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2069 .rate_min = 8000, 2070 .rate_max = 192000, 2071 .channels_min = 1, 2072 .channels_max = 4, 2073 }, 2074 .ops = &wcd934x_dai_ops, 2075 }, 2076 [4] = { 2077 .name = "wcd934x_rx3", 2078 .id = AIF3_PB, 2079 .playback = { 2080 .stream_name = "AIF3 Playback", 2081 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2082 .formats = WCD934X_FORMATS_S16_S24_LE, 2083 .rate_min = 8000, 2084 .rate_max = 192000, 2085 .channels_min = 1, 2086 .channels_max = 2, 2087 }, 2088 .ops = &wcd934x_dai_ops, 2089 }, 2090 [5] = { 2091 .name = "wcd934x_tx3", 2092 .id = AIF3_CAP, 2093 .capture = { 2094 .stream_name = "AIF3 Capture", 2095 .rates = WCD934X_RATES_MASK, 2096 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2097 .rate_min = 8000, 2098 .rate_max = 192000, 2099 .channels_min = 1, 2100 .channels_max = 4, 2101 }, 2102 .ops = &wcd934x_dai_ops, 2103 }, 2104 [6] = { 2105 .name = "wcd934x_rx4", 2106 .id = AIF4_PB, 2107 .playback = { 2108 .stream_name = "AIF4 Playback", 2109 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK, 2110 .formats = WCD934X_FORMATS_S16_S24_LE, 2111 .rate_min = 8000, 2112 .rate_max = 192000, 2113 .channels_min = 1, 2114 .channels_max = 2, 2115 }, 2116 .ops = &wcd934x_dai_ops, 2117 }, 2118 }; 2119 2120 static int swclk_gate_enable(struct clk_hw *hw) 2121 { 2122 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true); 2123 } 2124 2125 static void swclk_gate_disable(struct clk_hw *hw) 2126 { 2127 wcd934x_swrm_clock(to_wcd934x_codec(hw), false); 2128 } 2129 2130 static int swclk_gate_is_enabled(struct clk_hw *hw) 2131 { 2132 struct wcd934x_codec *wcd = to_wcd934x_codec(hw); 2133 int ret, val; 2134 2135 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val); 2136 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK; 2137 2138 return ret; 2139 } 2140 2141 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2142 unsigned long parent_rate) 2143 { 2144 return parent_rate / 2; 2145 } 2146 2147 static const struct clk_ops swclk_gate_ops = { 2148 .prepare = swclk_gate_enable, 2149 .unprepare = swclk_gate_disable, 2150 .is_enabled = swclk_gate_is_enabled, 2151 .recalc_rate = swclk_recalc_rate, 2152 2153 }; 2154 2155 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd) 2156 { 2157 struct clk *parent = wcd->extclk; 2158 struct device *dev = wcd->dev; 2159 struct device_node *np = dev->parent->of_node; 2160 const char *parent_clk_name = NULL; 2161 const char *clk_name = "mclk"; 2162 struct clk_hw *hw; 2163 struct clk_init_data init; 2164 int ret; 2165 2166 if (of_property_read_u32(np, "clock-frequency", &wcd->rate)) 2167 return NULL; 2168 2169 parent_clk_name = __clk_get_name(parent); 2170 2171 of_property_read_string(np, "clock-output-names", &clk_name); 2172 2173 init.name = clk_name; 2174 init.ops = &swclk_gate_ops; 2175 init.flags = 0; 2176 init.parent_names = &parent_clk_name; 2177 init.num_parents = 1; 2178 wcd->hw.init = &init; 2179 2180 hw = &wcd->hw; 2181 ret = devm_clk_hw_register(wcd->dev->parent, hw); 2182 if (ret) 2183 return ERR_PTR(ret); 2184 2185 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2186 if (ret) 2187 return ERR_PTR(ret); 2188 2189 return NULL; 2190 } 2191 2192 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias, 2193 u32 *micb_mv) 2194 { 2195 int mv; 2196 2197 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) { 2198 dev_err(dev, "%s value not found, using default\n", micbias); 2199 mv = WCD934X_DEF_MICBIAS_MV; 2200 } else { 2201 /* convert it to milli volts */ 2202 mv = mv/1000; 2203 } 2204 2205 if (mv < 1000 || mv > 2850) { 2206 dev_err(dev, "%s value not in valid range, using default\n", 2207 micbias); 2208 mv = WCD934X_DEF_MICBIAS_MV; 2209 } 2210 2211 *micb_mv = mv; 2212 2213 return (mv - 1000) / 50; 2214 } 2215 2216 static int wcd934x_init_dmic(struct snd_soc_component *comp) 2217 { 2218 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4; 2219 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 2220 u32 def_dmic_rate, dmic_clk_drv; 2221 2222 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev, 2223 "qcom,micbias1-microvolt", 2224 &wcd->micb1_mv); 2225 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev, 2226 "qcom,micbias2-microvolt", 2227 &wcd->micb2_mv); 2228 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev, 2229 "qcom,micbias3-microvolt", 2230 &wcd->micb3_mv); 2231 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev, 2232 "qcom,micbias4-microvolt", 2233 &wcd->micb4_mv); 2234 2235 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1, 2236 WCD934X_MICB_VAL_MASK, vout_ctl_1); 2237 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2, 2238 WCD934X_MICB_VAL_MASK, vout_ctl_2); 2239 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3, 2240 WCD934X_MICB_VAL_MASK, vout_ctl_3); 2241 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4, 2242 WCD934X_MICB_VAL_MASK, vout_ctl_4); 2243 2244 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ) 2245 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 2246 else 2247 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ; 2248 2249 wcd->dmic_sample_rate = def_dmic_rate; 2250 2251 dmic_clk_drv = 0; 2252 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 2253 0x0C, dmic_clk_drv << 2); 2254 2255 return 0; 2256 } 2257 2258 static void wcd934x_hw_init(struct wcd934x_codec *wcd) 2259 { 2260 struct regmap *rm = wcd->regmap; 2261 2262 /* set SPKR rate to FS_2P4_3P072 */ 2263 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08); 2264 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08); 2265 2266 /* Take DMICs out of reset */ 2267 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00); 2268 } 2269 2270 static int wcd934x_comp_init(struct snd_soc_component *component) 2271 { 2272 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2273 2274 wcd934x_hw_init(wcd); 2275 wcd934x_enable_efuse_sensing(wcd); 2276 wcd934x_get_version(wcd); 2277 2278 return 0; 2279 } 2280 2281 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data) 2282 { 2283 struct wcd934x_codec *wcd = data; 2284 unsigned long status = 0; 2285 int i, j, port_id; 2286 unsigned int val, int_val = 0; 2287 irqreturn_t ret = IRQ_NONE; 2288 bool tx; 2289 unsigned short reg = 0; 2290 2291 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 2292 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 2293 regmap_read(wcd->if_regmap, i, &val); 2294 status |= ((u32)val << (8 * j)); 2295 } 2296 2297 for_each_set_bit(j, &status, 32) { 2298 tx = false; 2299 port_id = j; 2300 2301 if (j >= 16) { 2302 tx = true; 2303 port_id = j - 16; 2304 } 2305 2306 regmap_read(wcd->if_regmap, 2307 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 2308 if (val) { 2309 if (!tx) 2310 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2311 (port_id / 8); 2312 else 2313 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2314 (port_id / 8); 2315 regmap_read(wcd->if_regmap, reg, &int_val); 2316 } 2317 2318 if (val & WCD934X_SLIM_IRQ_OVERFLOW) 2319 dev_err_ratelimited(wcd->dev, 2320 "overflow error on %s port %d, value %x\n", 2321 (tx ? "TX" : "RX"), port_id, val); 2322 2323 if (val & WCD934X_SLIM_IRQ_UNDERFLOW) 2324 dev_err_ratelimited(wcd->dev, 2325 "underflow error on %s port %d, value %x\n", 2326 (tx ? "TX" : "RX"), port_id, val); 2327 2328 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) || 2329 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) { 2330 if (!tx) 2331 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + 2332 (port_id / 8); 2333 else 2334 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + 2335 (port_id / 8); 2336 regmap_read( 2337 wcd->if_regmap, reg, &int_val); 2338 if (int_val & (1 << (port_id % 8))) { 2339 int_val = int_val ^ (1 << (port_id % 8)); 2340 regmap_write(wcd->if_regmap, 2341 reg, int_val); 2342 } 2343 } 2344 2345 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED) 2346 dev_err_ratelimited(wcd->dev, 2347 "Port Closed %s port %d, value %x\n", 2348 (tx ? "TX" : "RX"), port_id, val); 2349 2350 regmap_write(wcd->if_regmap, 2351 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 2352 BIT(j % 8)); 2353 ret = IRQ_HANDLED; 2354 } 2355 2356 return ret; 2357 } 2358 2359 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component, 2360 bool enable) 2361 { 2362 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1, 2363 WCD934X_MBHC_CTL_RCO_EN_MASK, enable); 2364 } 2365 2366 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component, 2367 bool enable) 2368 { 2369 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT, 2370 WCD934X_ANA_MBHC_BIAS_EN, enable); 2371 } 2372 2373 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component, 2374 int *btn_low, int *btn_high, 2375 int num_btn, bool is_micbias) 2376 { 2377 int i, vth; 2378 2379 if (num_btn > WCD_MBHC_DEF_BUTTONS) { 2380 dev_err(component->dev, "%s: invalid number of buttons: %d\n", 2381 __func__, num_btn); 2382 return; 2383 } 2384 2385 for (i = 0; i < num_btn; i++) { 2386 vth = ((btn_high[i] * 2) / 25) & 0x3F; 2387 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i, 2388 WCD934X_MBHC_BTN_VTH_MASK, vth); 2389 } 2390 } 2391 2392 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num) 2393 { 2394 u8 val; 2395 2396 if (micb_num == MIC_BIAS_2) { 2397 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2, 2398 WCD934X_ANA_MICB2_ENABLE_MASK); 2399 if (val == WCD934X_MICB_ENABLE) 2400 return true; 2401 } 2402 return false; 2403 } 2404 2405 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component, 2406 enum mbhc_hs_pullup_iref pull_up_cur) 2407 { 2408 /* Default pull up current to 2uA */ 2409 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || 2410 pull_up_cur == I_DEFAULT) 2411 pull_up_cur = I_2P0_UA; 2412 2413 2414 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 2415 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur); 2416 } 2417 2418 static int wcd934x_micbias_control(struct snd_soc_component *component, 2419 int micb_num, int req, bool is_dapm) 2420 { 2421 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2422 int micb_index = micb_num - 1; 2423 u16 micb_reg; 2424 2425 switch (micb_num) { 2426 case MIC_BIAS_1: 2427 micb_reg = WCD934X_ANA_MICB1; 2428 break; 2429 case MIC_BIAS_2: 2430 micb_reg = WCD934X_ANA_MICB2; 2431 break; 2432 case MIC_BIAS_3: 2433 micb_reg = WCD934X_ANA_MICB3; 2434 break; 2435 case MIC_BIAS_4: 2436 micb_reg = WCD934X_ANA_MICB4; 2437 break; 2438 default: 2439 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2440 __func__, micb_num); 2441 return -EINVAL; 2442 } 2443 mutex_lock(&wcd934x->micb_lock); 2444 2445 switch (req) { 2446 case MICB_PULLUP_ENABLE: 2447 wcd934x->pullup_ref[micb_index]++; 2448 if ((wcd934x->pullup_ref[micb_index] == 1) && 2449 (wcd934x->micb_ref[micb_index] == 0)) 2450 snd_soc_component_write_field(component, micb_reg, 2451 WCD934X_ANA_MICB_EN_MASK, 2452 WCD934X_MICB_PULL_UP); 2453 break; 2454 case MICB_PULLUP_DISABLE: 2455 if (wcd934x->pullup_ref[micb_index] > 0) 2456 wcd934x->pullup_ref[micb_index]--; 2457 2458 if ((wcd934x->pullup_ref[micb_index] == 0) && 2459 (wcd934x->micb_ref[micb_index] == 0)) 2460 snd_soc_component_write_field(component, micb_reg, 2461 WCD934X_ANA_MICB_EN_MASK, 0); 2462 break; 2463 case MICB_ENABLE: 2464 wcd934x->micb_ref[micb_index]++; 2465 if (wcd934x->micb_ref[micb_index] == 1) { 2466 snd_soc_component_write_field(component, micb_reg, 2467 WCD934X_ANA_MICB_EN_MASK, 2468 WCD934X_MICB_ENABLE); 2469 if (micb_num == MIC_BIAS_2) 2470 wcd_mbhc_event_notify(wcd934x->mbhc, 2471 WCD_EVENT_POST_MICBIAS_2_ON); 2472 } 2473 2474 if (micb_num == MIC_BIAS_2 && is_dapm) 2475 wcd_mbhc_event_notify(wcd934x->mbhc, 2476 WCD_EVENT_POST_DAPM_MICBIAS_2_ON); 2477 break; 2478 case MICB_DISABLE: 2479 if (wcd934x->micb_ref[micb_index] > 0) 2480 wcd934x->micb_ref[micb_index]--; 2481 2482 if ((wcd934x->micb_ref[micb_index] == 0) && 2483 (wcd934x->pullup_ref[micb_index] > 0)) 2484 snd_soc_component_write_field(component, micb_reg, 2485 WCD934X_ANA_MICB_EN_MASK, 2486 WCD934X_MICB_PULL_UP); 2487 else if ((wcd934x->micb_ref[micb_index] == 0) && 2488 (wcd934x->pullup_ref[micb_index] == 0)) { 2489 if (micb_num == MIC_BIAS_2) 2490 wcd_mbhc_event_notify(wcd934x->mbhc, 2491 WCD_EVENT_PRE_MICBIAS_2_OFF); 2492 2493 snd_soc_component_write_field(component, micb_reg, 2494 WCD934X_ANA_MICB_EN_MASK, 0); 2495 if (micb_num == MIC_BIAS_2) 2496 wcd_mbhc_event_notify(wcd934x->mbhc, 2497 WCD_EVENT_POST_MICBIAS_2_OFF); 2498 } 2499 if (is_dapm && micb_num == MIC_BIAS_2) 2500 wcd_mbhc_event_notify(wcd934x->mbhc, 2501 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); 2502 break; 2503 } 2504 2505 mutex_unlock(&wcd934x->micb_lock); 2506 2507 return 0; 2508 } 2509 2510 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component, 2511 int micb_num, int req) 2512 { 2513 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 2514 int ret; 2515 2516 if (req == MICB_ENABLE) 2517 __wcd934x_cdc_mclk_enable(wcd, true); 2518 2519 ret = wcd934x_micbias_control(component, micb_num, req, false); 2520 2521 if (req == MICB_DISABLE) 2522 __wcd934x_cdc_mclk_enable(wcd, false); 2523 2524 return ret; 2525 } 2526 2527 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component, 2528 bool enable) 2529 { 2530 if (enable) { 2531 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2532 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3); 2533 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2534 WCD934X_RAMP_EN_MASK, 1); 2535 } else { 2536 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2537 WCD934X_RAMP_EN_MASK, 0); 2538 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP, 2539 WCD934X_RAMP_SHIFT_CTRL_MASK, 0); 2540 } 2541 } 2542 2543 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv) 2544 { 2545 /* min micbias voltage is 1V and maximum is 2.85V */ 2546 if (micb_mv < 1000 || micb_mv > 2850) 2547 return -EINVAL; 2548 2549 return (micb_mv - 1000) / 50; 2550 } 2551 2552 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component, 2553 int req_volt, int micb_num) 2554 { 2555 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2556 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0; 2557 2558 switch (micb_num) { 2559 case MIC_BIAS_1: 2560 micb_reg = WCD934X_ANA_MICB1; 2561 break; 2562 case MIC_BIAS_2: 2563 micb_reg = WCD934X_ANA_MICB2; 2564 break; 2565 case MIC_BIAS_3: 2566 micb_reg = WCD934X_ANA_MICB3; 2567 break; 2568 case MIC_BIAS_4: 2569 micb_reg = WCD934X_ANA_MICB4; 2570 break; 2571 default: 2572 return -EINVAL; 2573 } 2574 mutex_lock(&wcd934x->micb_lock); 2575 /* 2576 * If requested micbias voltage is same as current micbias 2577 * voltage, then just return. Otherwise, adjust voltage as 2578 * per requested value. If micbias is already enabled, then 2579 * to avoid slow micbias ramp-up or down enable pull-up 2580 * momentarily, change the micbias value and then re-enable 2581 * micbias. 2582 */ 2583 micb_en = snd_soc_component_read_field(component, micb_reg, 2584 WCD934X_ANA_MICB_EN_MASK); 2585 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg, 2586 WCD934X_MICB_VAL_MASK); 2587 2588 req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt); 2589 if (req_vout_ctl < 0) { 2590 ret = -EINVAL; 2591 goto exit; 2592 } 2593 2594 if (cur_vout_ctl == req_vout_ctl) { 2595 ret = 0; 2596 goto exit; 2597 } 2598 2599 if (micb_en == WCD934X_MICB_ENABLE) 2600 snd_soc_component_write_field(component, micb_reg, 2601 WCD934X_ANA_MICB_EN_MASK, 2602 WCD934X_MICB_PULL_UP); 2603 2604 snd_soc_component_write_field(component, micb_reg, 2605 WCD934X_MICB_VAL_MASK, 2606 req_vout_ctl); 2607 2608 if (micb_en == WCD934X_MICB_ENABLE) { 2609 snd_soc_component_write_field(component, micb_reg, 2610 WCD934X_ANA_MICB_EN_MASK, 2611 WCD934X_MICB_ENABLE); 2612 /* 2613 * Add 2ms delay as per HW requirement after enabling 2614 * micbias 2615 */ 2616 usleep_range(2000, 2100); 2617 } 2618 exit: 2619 mutex_unlock(&wcd934x->micb_lock); 2620 return ret; 2621 } 2622 2623 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component, 2624 int micb_num, bool req_en) 2625 { 2626 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component); 2627 int rc, micb_mv; 2628 2629 if (micb_num != MIC_BIAS_2) 2630 return -EINVAL; 2631 /* 2632 * If device tree micbias level is already above the minimum 2633 * voltage needed to detect threshold microphone, then do 2634 * not change the micbias, just return. 2635 */ 2636 if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV) 2637 return 0; 2638 2639 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv; 2640 2641 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2); 2642 2643 return rc; 2644 } 2645 2646 static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x, 2647 s16 *d1_a, u16 noff, 2648 int32_t *zdet) 2649 { 2650 int i; 2651 int val, val1; 2652 s16 c1; 2653 s32 x1, d1; 2654 int32_t denom; 2655 int minCode_param[] = { 2656 3277, 1639, 820, 410, 205, 103, 52, 26 2657 }; 2658 2659 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20); 2660 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) { 2661 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val); 2662 if (val & 0x80) 2663 break; 2664 } 2665 val = val << 0x8; 2666 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1); 2667 val |= val1; 2668 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00); 2669 x1 = WCD934X_MBHC_GET_X1(val); 2670 c1 = WCD934X_MBHC_GET_C1(val); 2671 /* If ramp is not complete, give additional 5ms */ 2672 if ((c1 < 2) && x1) 2673 usleep_range(5000, 5050); 2674 2675 if (!c1 || !x1) { 2676 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n", 2677 __func__, c1, x1); 2678 goto ramp_down; 2679 } 2680 d1 = d1_a[c1]; 2681 denom = (x1 * d1) - (1 << (14 - noff)); 2682 if (denom > 0) 2683 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom; 2684 else if (x1 < minCode_param[noff]) 2685 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE; 2686 2687 dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n", 2688 __func__, d1, c1, x1, *zdet); 2689 ramp_down: 2690 i = 0; 2691 2692 while (x1) { 2693 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val); 2694 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1); 2695 val = val << 0x08; 2696 val |= val1; 2697 x1 = WCD934X_MBHC_GET_X1(val); 2698 i++; 2699 if (i == WCD934X_ZDET_NUM_MEASUREMENTS) 2700 break; 2701 } 2702 } 2703 2704 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component, 2705 struct wcd934x_mbhc_zdet_param *zdet_param, 2706 int32_t *zl, int32_t *zr, s16 *d1_a) 2707 { 2708 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2709 int32_t zdet = 0; 2710 2711 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2712 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl); 2713 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5, 2714 WCD934X_VTH_MASK, zdet_param->btn5); 2715 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6, 2716 WCD934X_VTH_MASK, zdet_param->btn6); 2717 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7, 2718 WCD934X_VTH_MASK, zdet_param->btn7); 2719 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, 2720 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff); 2721 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 2722 0x0F, zdet_param->nshift); 2723 2724 if (!zl) 2725 goto z_right; 2726 /* Start impedance measurement for HPH_L */ 2727 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80); 2728 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2729 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00); 2730 2731 *zl = zdet; 2732 2733 z_right: 2734 if (!zr) 2735 return; 2736 /* Start impedance measurement for HPH_R */ 2737 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40); 2738 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet); 2739 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00); 2740 2741 *zr = zdet; 2742 } 2743 2744 static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component, 2745 int32_t *z_val, int flag_l_r) 2746 { 2747 s16 q1; 2748 int q1_cal; 2749 2750 if (*z_val < (WCD934X_ZDET_VAL_400/1000)) 2751 q1 = snd_soc_component_read(component, 2752 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r)); 2753 else 2754 q1 = snd_soc_component_read(component, 2755 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r)); 2756 if (q1 & 0x80) 2757 q1_cal = (10000 - ((q1 & 0x7F) * 25)); 2758 else 2759 q1_cal = (10000 + (q1 * 25)); 2760 if (q1_cal > 0) 2761 *z_val = ((*z_val) * 10000) / q1_cal; 2762 } 2763 2764 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component, 2765 uint32_t *zl, uint32_t *zr) 2766 { 2767 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev); 2768 s16 reg0, reg1, reg2, reg3, reg4; 2769 int32_t z1L, z1R, z1Ls; 2770 int zMono, z_diff1, z_diff2; 2771 bool is_fsm_disable = false; 2772 struct wcd934x_mbhc_zdet_param zdet_param[] = { 2773 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */ 2774 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */ 2775 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */ 2776 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */ 2777 }; 2778 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL; 2779 s16 d1_a[][4] = { 2780 {0, 30, 90, 30}, 2781 {0, 30, 30, 5}, 2782 {0, 30, 30, 5}, 2783 {0, 30, 30, 5}, 2784 }; 2785 s16 *d1 = NULL; 2786 2787 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5); 2788 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6); 2789 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7); 2790 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK); 2791 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL); 2792 2793 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) { 2794 is_fsm_disable = true; 2795 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); 2796 } 2797 2798 /* For NO-jack, disable L_DET_EN before Z-det measurements */ 2799 if (wcd934x->mbhc_cfg.hphl_swh) 2800 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00); 2801 2802 /* Turn off 100k pull down on HPHL */ 2803 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00); 2804 2805 /* First get impedance on Left */ 2806 d1 = d1_a[1]; 2807 zdet_param_ptr = &zdet_param[1]; 2808 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2809 2810 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L)) 2811 goto left_ch_impedance; 2812 2813 /* Second ramp for left ch */ 2814 if (z1L < WCD934X_ZDET_VAL_32) { 2815 zdet_param_ptr = &zdet_param[0]; 2816 d1 = d1_a[0]; 2817 } else if ((z1L > WCD934X_ZDET_VAL_400) && 2818 (z1L <= WCD934X_ZDET_VAL_1200)) { 2819 zdet_param_ptr = &zdet_param[2]; 2820 d1 = d1_a[2]; 2821 } else if (z1L > WCD934X_ZDET_VAL_1200) { 2822 zdet_param_ptr = &zdet_param[3]; 2823 d1 = d1_a[3]; 2824 } 2825 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1); 2826 2827 left_ch_impedance: 2828 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2829 (z1L > WCD934X_ZDET_VAL_100K)) { 2830 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE; 2831 zdet_param_ptr = &zdet_param[1]; 2832 d1 = d1_a[1]; 2833 } else { 2834 *zl = z1L/1000; 2835 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0); 2836 } 2837 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", 2838 __func__, *zl); 2839 2840 /* Start of right impedance ramp and calculation */ 2841 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2842 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) { 2843 if (((z1R > WCD934X_ZDET_VAL_1200) && 2844 (zdet_param_ptr->noff == 0x6)) || 2845 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE)) 2846 goto right_ch_impedance; 2847 /* Second ramp for right ch */ 2848 if (z1R < WCD934X_ZDET_VAL_32) { 2849 zdet_param_ptr = &zdet_param[0]; 2850 d1 = d1_a[0]; 2851 } else if ((z1R > WCD934X_ZDET_VAL_400) && 2852 (z1R <= WCD934X_ZDET_VAL_1200)) { 2853 zdet_param_ptr = &zdet_param[2]; 2854 d1 = d1_a[2]; 2855 } else if (z1R > WCD934X_ZDET_VAL_1200) { 2856 zdet_param_ptr = &zdet_param[3]; 2857 d1 = d1_a[3]; 2858 } 2859 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1); 2860 } 2861 right_ch_impedance: 2862 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2863 (z1R > WCD934X_ZDET_VAL_100K)) { 2864 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE; 2865 } else { 2866 *zr = z1R/1000; 2867 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1); 2868 } 2869 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", 2870 __func__, *zr); 2871 2872 /* Mono/stereo detection */ 2873 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) && 2874 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) { 2875 dev_dbg(component->dev, 2876 "%s: plug type is invalid or extension cable\n", 2877 __func__); 2878 goto zdet_complete; 2879 } 2880 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2881 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) || 2882 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) || 2883 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) { 2884 dev_dbg(component->dev, 2885 "%s: Mono plug type with one ch floating or shorted to GND\n", 2886 __func__); 2887 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2888 goto zdet_complete; 2889 } 2890 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2891 WCD934X_HPHPA_GND_OVR_MASK, 1); 2892 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2893 WCD934X_HPHPA_GND_R_MASK, 1); 2894 if (*zl < (WCD934X_ZDET_VAL_32/1000)) 2895 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1); 2896 else 2897 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1); 2898 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2899 WCD934X_HPHPA_GND_R_MASK, 0); 2900 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST, 2901 WCD934X_HPHPA_GND_OVR_MASK, 0); 2902 z1Ls /= 1000; 2903 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0); 2904 /* Parallel of left Z and 9 ohm pull down resistor */ 2905 zMono = ((*zl) * 9) / ((*zl) + 9); 2906 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls); 2907 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl)); 2908 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) { 2909 dev_err(component->dev, "%s: stereo plug type detected\n", 2910 __func__); 2911 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO); 2912 } else { 2913 dev_err(component->dev, "%s: MONO plug type detected\n", 2914 __func__); 2915 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO); 2916 } 2917 2918 zdet_complete: 2919 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0); 2920 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1); 2921 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2); 2922 /* Turn on 100k pull down on HPHL */ 2923 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01); 2924 2925 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */ 2926 if (wcd934x->mbhc_cfg.hphl_swh) 2927 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80); 2928 2929 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4); 2930 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3); 2931 if (is_fsm_disable) 2932 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80); 2933 } 2934 2935 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component, 2936 bool enable) 2937 { 2938 if (enable) { 2939 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2940 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1); 2941 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2942 WCD934X_MBHC_GND_DET_EN_MASK, 1); 2943 } else { 2944 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2945 WCD934X_MBHC_GND_DET_EN_MASK, 0); 2946 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH, 2947 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0); 2948 } 2949 } 2950 2951 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, 2952 bool enable) 2953 { 2954 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2955 WCD934X_HPHPA_GND_R_MASK, enable); 2956 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2, 2957 WCD934X_HPHPA_GND_L_MASK, enable); 2958 } 2959 2960 static const struct wcd_mbhc_cb mbhc_cb = { 2961 .clk_setup = wcd934x_mbhc_clk_setup, 2962 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control, 2963 .set_btn_thr = wcd934x_mbhc_program_btn_thr, 2964 .micbias_enable_status = wcd934x_mbhc_micb_en_status, 2965 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control, 2966 .mbhc_micbias_control = wcd934x_mbhc_request_micbias, 2967 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control, 2968 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic, 2969 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance, 2970 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl, 2971 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl, 2972 }; 2973 2974 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol, 2975 struct snd_ctl_elem_value *ucontrol) 2976 { 2977 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2978 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2979 2980 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc); 2981 2982 return 0; 2983 } 2984 2985 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol, 2986 struct snd_ctl_elem_value *ucontrol) 2987 { 2988 uint32_t zl, zr; 2989 bool hphr; 2990 struct soc_mixer_control *mc; 2991 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2992 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 2993 2994 mc = (struct soc_mixer_control *)(kcontrol->private_value); 2995 hphr = mc->shift; 2996 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr); 2997 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr); 2998 ucontrol->value.integer.value[0] = hphr ? zr : zl; 2999 3000 return 0; 3001 } 3002 static const struct snd_kcontrol_new hph_type_detect_controls[] = { 3003 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0, 3004 wcd934x_get_hph_type, NULL), 3005 }; 3006 3007 static const struct snd_kcontrol_new impedance_detect_controls[] = { 3008 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0, 3009 wcd934x_hph_impedance_get, NULL), 3010 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0, 3011 wcd934x_hph_impedance_get, NULL), 3012 }; 3013 3014 static int wcd934x_mbhc_init(struct snd_soc_component *component) 3015 { 3016 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent); 3017 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3018 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids; 3019 3020 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data, 3021 WCD934X_IRQ_MBHC_SW_DET); 3022 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data, 3023 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET); 3024 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data, 3025 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET); 3026 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data, 3027 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET); 3028 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data, 3029 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET); 3030 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data, 3031 WCD934X_IRQ_HPH_PA_OCPL_FAULT); 3032 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data, 3033 WCD934X_IRQ_HPH_PA_OCPR_FAULT); 3034 3035 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true); 3036 if (IS_ERR(wcd->mbhc)) { 3037 wcd->mbhc = NULL; 3038 return -EINVAL; 3039 } 3040 3041 snd_soc_add_component_controls(component, impedance_detect_controls, 3042 ARRAY_SIZE(impedance_detect_controls)); 3043 snd_soc_add_component_controls(component, hph_type_detect_controls, 3044 ARRAY_SIZE(hph_type_detect_controls)); 3045 3046 return 0; 3047 } 3048 3049 static void wcd934x_mbhc_deinit(struct snd_soc_component *component) 3050 { 3051 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component); 3052 3053 if (!wcd->mbhc) 3054 return; 3055 3056 wcd_mbhc_deinit(wcd->mbhc); 3057 } 3058 3059 static int wcd934x_comp_probe(struct snd_soc_component *component) 3060 { 3061 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3062 int i; 3063 3064 snd_soc_component_init_regmap(component, wcd->regmap); 3065 wcd->component = component; 3066 3067 /* Class-H Init*/ 3068 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 3069 if (IS_ERR(wcd->clsh_ctrl)) 3070 return PTR_ERR(wcd->clsh_ctrl); 3071 3072 /* Default HPH Mode to Class-H Low HiFi */ 3073 wcd->hph_mode = CLS_H_LOHIFI; 3074 3075 wcd934x_comp_init(component); 3076 3077 for (i = 0; i < NUM_CODEC_DAIS; i++) 3078 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 3079 3080 wcd934x_init_dmic(component); 3081 3082 if (wcd934x_mbhc_init(component)) 3083 dev_err(component->dev, "Failed to Initialize MBHC\n"); 3084 3085 return 0; 3086 } 3087 3088 static void wcd934x_comp_remove(struct snd_soc_component *comp) 3089 { 3090 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3091 3092 wcd934x_mbhc_deinit(comp); 3093 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 3094 } 3095 3096 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp, 3097 int clk_id, int source, 3098 unsigned int freq, int dir) 3099 { 3100 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 3101 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ; 3102 3103 wcd->rate = freq; 3104 3105 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ) 3106 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ; 3107 3108 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 3109 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 3110 val); 3111 3112 return clk_set_rate(wcd->extclk, freq); 3113 } 3114 3115 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 3116 int iir_idx, int band_idx, int coeff_idx) 3117 { 3118 u32 value = 0; 3119 int reg, b2_reg; 3120 3121 /* Address does not automatically update if reading */ 3122 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3123 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3124 3125 snd_soc_component_write(component, reg, 3126 ((band_idx * BAND_MAX + coeff_idx) * 3127 sizeof(uint32_t)) & 0x7F); 3128 3129 value |= snd_soc_component_read(component, b2_reg); 3130 snd_soc_component_write(component, reg, 3131 ((band_idx * BAND_MAX + coeff_idx) 3132 * sizeof(uint32_t) + 1) & 0x7F); 3133 3134 value |= (snd_soc_component_read(component, b2_reg) << 8); 3135 snd_soc_component_write(component, reg, 3136 ((band_idx * BAND_MAX + coeff_idx) 3137 * sizeof(uint32_t) + 2) & 0x7F); 3138 3139 value |= (snd_soc_component_read(component, b2_reg) << 16); 3140 snd_soc_component_write(component, reg, 3141 ((band_idx * BAND_MAX + coeff_idx) 3142 * sizeof(uint32_t) + 3) & 0x7F); 3143 3144 /* Mask bits top 2 bits since they are reserved */ 3145 value |= (snd_soc_component_read(component, b2_reg) << 24); 3146 return value; 3147 } 3148 3149 static void set_iir_band_coeff(struct snd_soc_component *component, 3150 int iir_idx, int band_idx, uint32_t value) 3151 { 3152 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx; 3153 3154 snd_soc_component_write(component, reg, (value & 0xFF)); 3155 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 3156 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 3157 /* Mask top 2 bits, 7-8 are reserved */ 3158 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 3159 } 3160 3161 static int wcd934x_put_iir_band_audio_mixer( 3162 struct snd_kcontrol *kcontrol, 3163 struct snd_ctl_elem_value *ucontrol) 3164 { 3165 struct snd_soc_component *component = 3166 snd_soc_kcontrol_component(kcontrol); 3167 struct wcd_iir_filter_ctl *ctl = 3168 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3169 struct soc_bytes_ext *params = &ctl->bytes_ext; 3170 int iir_idx = ctl->iir_idx; 3171 int band_idx = ctl->band_idx; 3172 u32 coeff[BAND_MAX]; 3173 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx; 3174 3175 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 3176 3177 /* Mask top bit it is reserved */ 3178 /* Updates addr automatically for each B2 write */ 3179 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 3180 sizeof(uint32_t)) & 0x7F); 3181 3182 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 3183 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 3184 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 3185 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 3186 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 3187 3188 return 0; 3189 } 3190 3191 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 3192 struct snd_ctl_elem_value *ucontrol) 3193 { 3194 struct snd_soc_component *component = 3195 snd_soc_kcontrol_component(kcontrol); 3196 struct wcd_iir_filter_ctl *ctl = 3197 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3198 struct soc_bytes_ext *params = &ctl->bytes_ext; 3199 int iir_idx = ctl->iir_idx; 3200 int band_idx = ctl->band_idx; 3201 u32 coeff[BAND_MAX]; 3202 3203 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 3204 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 3205 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 3206 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 3207 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 3208 3209 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 3210 3211 return 0; 3212 } 3213 3214 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol, 3215 struct snd_ctl_elem_info *ucontrol) 3216 { 3217 struct wcd_iir_filter_ctl *ctl = 3218 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 3219 struct soc_bytes_ext *params = &ctl->bytes_ext; 3220 3221 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 3222 ucontrol->count = params->max; 3223 3224 return 0; 3225 } 3226 3227 static int wcd934x_compander_get(struct snd_kcontrol *kc, 3228 struct snd_ctl_elem_value *ucontrol) 3229 { 3230 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3231 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3232 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3233 3234 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 3235 3236 return 0; 3237 } 3238 3239 static int wcd934x_compander_set(struct snd_kcontrol *kc, 3240 struct snd_ctl_elem_value *ucontrol) 3241 { 3242 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3243 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3244 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 3245 int value = ucontrol->value.integer.value[0]; 3246 int sel; 3247 3248 if (wcd->comp_enabled[comp] == value) 3249 return 0; 3250 3251 wcd->comp_enabled[comp] = value; 3252 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER : 3253 WCD934X_HPH_GAIN_SRC_SEL_REGISTER; 3254 3255 /* Any specific register configuration for compander */ 3256 switch (comp) { 3257 case COMPANDER_1: 3258 /* Set Gain Source Select based on compander enable/disable */ 3259 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN, 3260 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3261 sel); 3262 break; 3263 case COMPANDER_2: 3264 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN, 3265 WCD934X_HPH_GAIN_SRC_SEL_MASK, 3266 sel); 3267 break; 3268 case COMPANDER_3: 3269 case COMPANDER_4: 3270 case COMPANDER_7: 3271 case COMPANDER_8: 3272 break; 3273 default: 3274 return 0; 3275 } 3276 3277 return 1; 3278 } 3279 3280 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc, 3281 struct snd_ctl_elem_value *ucontrol) 3282 { 3283 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3284 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3285 3286 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 3287 3288 return 0; 3289 } 3290 3291 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc, 3292 struct snd_ctl_elem_value *ucontrol) 3293 { 3294 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 3295 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 3296 u32 mode_val; 3297 3298 mode_val = ucontrol->value.enumerated.item[0]; 3299 3300 if (mode_val == wcd->hph_mode) 3301 return 0; 3302 3303 if (mode_val == 0) { 3304 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 3305 mode_val = CLS_H_LOHIFI; 3306 } 3307 wcd->hph_mode = mode_val; 3308 3309 return 1; 3310 } 3311 3312 static int slim_rx_mux_get(struct snd_kcontrol *kc, 3313 struct snd_ctl_elem_value *ucontrol) 3314 { 3315 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3316 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3317 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3318 3319 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift]; 3320 3321 return 0; 3322 } 3323 3324 static int slim_rx_mux_to_dai_id(int mux) 3325 { 3326 int aif_id; 3327 3328 switch (mux) { 3329 case 1: 3330 aif_id = AIF1_PB; 3331 break; 3332 case 2: 3333 aif_id = AIF2_PB; 3334 break; 3335 case 3: 3336 aif_id = AIF3_PB; 3337 break; 3338 case 4: 3339 aif_id = AIF4_PB; 3340 break; 3341 default: 3342 aif_id = -1; 3343 break; 3344 } 3345 3346 return aif_id; 3347 } 3348 3349 static int slim_rx_mux_put(struct snd_kcontrol *kc, 3350 struct snd_ctl_elem_value *ucontrol) 3351 { 3352 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 3353 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev); 3354 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3355 struct snd_soc_dapm_update *update = NULL; 3356 struct wcd934x_slim_ch *ch, *c; 3357 u32 port_id = w->shift; 3358 bool found = false; 3359 int mux_idx; 3360 int prev_mux_idx = wcd->rx_port_value[port_id]; 3361 int aif_id; 3362 3363 mux_idx = ucontrol->value.enumerated.item[0]; 3364 3365 if (mux_idx == prev_mux_idx) 3366 return 0; 3367 3368 switch(mux_idx) { 3369 case 0: 3370 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx); 3371 if (aif_id < 0) 3372 return 0; 3373 3374 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) { 3375 if (ch->port == port_id + WCD934X_RX_START) { 3376 found = true; 3377 list_del_init(&ch->list); 3378 break; 3379 } 3380 } 3381 if (!found) 3382 return 0; 3383 3384 break; 3385 case 1 ... 4: 3386 aif_id = slim_rx_mux_to_dai_id(mux_idx); 3387 if (aif_id < 0) 3388 return 0; 3389 3390 if (list_empty(&wcd->rx_chs[port_id].list)) { 3391 list_add_tail(&wcd->rx_chs[port_id].list, 3392 &wcd->dai[aif_id].slim_ch_list); 3393 } else { 3394 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id); 3395 return 0; 3396 } 3397 break; 3398 3399 default: 3400 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx); 3401 goto err; 3402 } 3403 3404 wcd->rx_port_value[port_id] = mux_idx; 3405 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 3406 e, update); 3407 3408 return 1; 3409 err: 3410 return -EINVAL; 3411 } 3412 3413 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc, 3414 struct snd_ctl_elem_value *ucontrol) 3415 { 3416 struct soc_enum *e = (struct soc_enum *)kc->private_value; 3417 struct snd_soc_component *component; 3418 int reg, val; 3419 3420 component = snd_soc_dapm_kcontrol_component(kc); 3421 val = ucontrol->value.enumerated.item[0]; 3422 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0) 3423 reg = WCD934X_CDC_RX0_RX_PATH_CFG0; 3424 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0) 3425 reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 3426 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0) 3427 reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 3428 else 3429 return -EINVAL; 3430 3431 /* Set Look Ahead Delay */ 3432 if (val) 3433 snd_soc_component_update_bits(component, reg, 3434 WCD934X_RX_DLY_ZN_EN_MASK, 3435 WCD934X_RX_DLY_ZN_ENABLE); 3436 else 3437 snd_soc_component_update_bits(component, reg, 3438 WCD934X_RX_DLY_ZN_EN_MASK, 3439 WCD934X_RX_DLY_ZN_DISABLE); 3440 3441 return snd_soc_dapm_put_enum_double(kc, ucontrol); 3442 } 3443 3444 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol, 3445 struct snd_ctl_elem_value *ucontrol) 3446 { 3447 struct snd_soc_component *comp; 3448 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 3449 unsigned int val; 3450 u16 mic_sel_reg = 0; 3451 u8 mic_sel; 3452 3453 comp = snd_soc_dapm_kcontrol_component(kcontrol); 3454 3455 val = ucontrol->value.enumerated.item[0]; 3456 if (val > e->items - 1) 3457 return -EINVAL; 3458 3459 switch (e->reg) { 3460 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 3461 if (e->shift_l == 0) 3462 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0; 3463 else if (e->shift_l == 2) 3464 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0; 3465 else if (e->shift_l == 4) 3466 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0; 3467 break; 3468 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 3469 if (e->shift_l == 0) 3470 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0; 3471 else if (e->shift_l == 2) 3472 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0; 3473 break; 3474 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 3475 if (e->shift_l == 0) 3476 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0; 3477 else if (e->shift_l == 2) 3478 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0; 3479 break; 3480 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 3481 if (e->shift_l == 0) 3482 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0; 3483 else if (e->shift_l == 2) 3484 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0; 3485 break; 3486 default: 3487 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n", 3488 __func__, e->reg); 3489 return -EINVAL; 3490 } 3491 3492 /* ADC: 0, DMIC: 1 */ 3493 mic_sel = val ? 0x0 : 0x1; 3494 if (mic_sel_reg) 3495 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7), 3496 mic_sel << 7); 3497 3498 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 3499 } 3500 3501 static const struct snd_kcontrol_new rx_int0_2_mux = 3502 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 3503 3504 static const struct snd_kcontrol_new rx_int1_2_mux = 3505 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 3506 3507 static const struct snd_kcontrol_new rx_int2_2_mux = 3508 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 3509 3510 static const struct snd_kcontrol_new rx_int3_2_mux = 3511 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 3512 3513 static const struct snd_kcontrol_new rx_int4_2_mux = 3514 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 3515 3516 static const struct snd_kcontrol_new rx_int7_2_mux = 3517 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 3518 3519 static const struct snd_kcontrol_new rx_int8_2_mux = 3520 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 3521 3522 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 3523 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 3524 3525 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 3526 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 3527 3528 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 3529 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 3530 3531 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 3532 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 3533 3534 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 3535 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 3536 3537 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 3538 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 3539 3540 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 3541 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 3542 3543 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 3544 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 3545 3546 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 3547 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 3548 3549 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 3550 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 3551 3552 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 3553 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 3554 3555 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 3556 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 3557 3558 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 3559 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 3560 3561 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 3562 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 3563 3564 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 3565 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 3566 3567 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 3568 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 3569 3570 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 3571 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 3572 3573 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 3574 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 3575 3576 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 3577 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 3578 3579 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 3580 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 3581 3582 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 3583 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 3584 3585 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 3586 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum); 3587 3588 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 3589 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum); 3590 3591 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 3592 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum); 3593 3594 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux = 3595 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum); 3596 3597 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux = 3598 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum); 3599 3600 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux = 3601 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum); 3602 3603 static const struct snd_kcontrol_new iir0_inp0_mux = 3604 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum); 3605 static const struct snd_kcontrol_new iir0_inp1_mux = 3606 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum); 3607 static const struct snd_kcontrol_new iir0_inp2_mux = 3608 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum); 3609 static const struct snd_kcontrol_new iir0_inp3_mux = 3610 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum); 3611 3612 static const struct snd_kcontrol_new iir1_inp0_mux = 3613 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum); 3614 static const struct snd_kcontrol_new iir1_inp1_mux = 3615 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); 3616 static const struct snd_kcontrol_new iir1_inp2_mux = 3617 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum); 3618 static const struct snd_kcontrol_new iir1_inp3_mux = 3619 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum); 3620 3621 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = { 3622 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 3623 slim_rx_mux_get, slim_rx_mux_put), 3624 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 3625 slim_rx_mux_get, slim_rx_mux_put), 3626 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 3627 slim_rx_mux_get, slim_rx_mux_put), 3628 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 3629 slim_rx_mux_get, slim_rx_mux_put), 3630 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 3631 slim_rx_mux_get, slim_rx_mux_put), 3632 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 3633 slim_rx_mux_get, slim_rx_mux_put), 3634 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 3635 slim_rx_mux_get, slim_rx_mux_put), 3636 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 3637 slim_rx_mux_get, slim_rx_mux_put), 3638 }; 3639 3640 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = { 3641 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0), 3642 }; 3643 3644 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = { 3645 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0), 3646 }; 3647 3648 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = { 3649 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0), 3650 }; 3651 3652 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = { 3653 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0), 3654 }; 3655 3656 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 3657 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 3658 snd_soc_dapm_get_enum_double, 3659 wcd934x_int_dem_inp_mux_put); 3660 3661 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 3662 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 3663 snd_soc_dapm_get_enum_double, 3664 wcd934x_int_dem_inp_mux_put); 3665 3666 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 3667 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 3668 snd_soc_dapm_get_enum_double, 3669 wcd934x_int_dem_inp_mux_put); 3670 3671 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 3672 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum); 3673 3674 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 3675 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum); 3676 3677 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 3678 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum); 3679 3680 static const struct snd_kcontrol_new rx_int3_1_interp_mux = 3681 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum); 3682 3683 static const struct snd_kcontrol_new rx_int4_1_interp_mux = 3684 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum); 3685 3686 static const struct snd_kcontrol_new rx_int7_1_interp_mux = 3687 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum); 3688 3689 static const struct snd_kcontrol_new rx_int8_1_interp_mux = 3690 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum); 3691 3692 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 3693 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum); 3694 3695 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 3696 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum); 3697 3698 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 3699 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum); 3700 3701 static const struct snd_kcontrol_new rx_int3_2_interp_mux = 3702 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum); 3703 3704 static const struct snd_kcontrol_new rx_int4_2_interp_mux = 3705 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum); 3706 3707 static const struct snd_kcontrol_new rx_int7_2_interp_mux = 3708 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum); 3709 3710 static const struct snd_kcontrol_new rx_int8_2_interp_mux = 3711 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum); 3712 3713 static const struct snd_kcontrol_new tx_dmic_mux0 = 3714 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 3715 3716 static const struct snd_kcontrol_new tx_dmic_mux1 = 3717 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 3718 3719 static const struct snd_kcontrol_new tx_dmic_mux2 = 3720 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 3721 3722 static const struct snd_kcontrol_new tx_dmic_mux3 = 3723 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 3724 3725 static const struct snd_kcontrol_new tx_dmic_mux4 = 3726 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 3727 3728 static const struct snd_kcontrol_new tx_dmic_mux5 = 3729 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 3730 3731 static const struct snd_kcontrol_new tx_dmic_mux6 = 3732 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 3733 3734 static const struct snd_kcontrol_new tx_dmic_mux7 = 3735 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 3736 3737 static const struct snd_kcontrol_new tx_dmic_mux8 = 3738 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 3739 3740 static const struct snd_kcontrol_new tx_amic_mux0 = 3741 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 3742 3743 static const struct snd_kcontrol_new tx_amic_mux1 = 3744 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 3745 3746 static const struct snd_kcontrol_new tx_amic_mux2 = 3747 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 3748 3749 static const struct snd_kcontrol_new tx_amic_mux3 = 3750 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 3751 3752 static const struct snd_kcontrol_new tx_amic_mux4 = 3753 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 3754 3755 static const struct snd_kcontrol_new tx_amic_mux5 = 3756 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 3757 3758 static const struct snd_kcontrol_new tx_amic_mux6 = 3759 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 3760 3761 static const struct snd_kcontrol_new tx_amic_mux7 = 3762 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 3763 3764 static const struct snd_kcontrol_new tx_amic_mux8 = 3765 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 3766 3767 static const struct snd_kcontrol_new tx_amic4_5 = 3768 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum); 3769 3770 static const struct snd_kcontrol_new tx_adc_mux0_mux = 3771 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum, 3772 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3773 static const struct snd_kcontrol_new tx_adc_mux1_mux = 3774 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum, 3775 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3776 static const struct snd_kcontrol_new tx_adc_mux2_mux = 3777 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum, 3778 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3779 static const struct snd_kcontrol_new tx_adc_mux3_mux = 3780 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum, 3781 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3782 static const struct snd_kcontrol_new tx_adc_mux4_mux = 3783 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum, 3784 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3785 static const struct snd_kcontrol_new tx_adc_mux5_mux = 3786 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum, 3787 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3788 static const struct snd_kcontrol_new tx_adc_mux6_mux = 3789 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum, 3790 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3791 static const struct snd_kcontrol_new tx_adc_mux7_mux = 3792 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum, 3793 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3794 static const struct snd_kcontrol_new tx_adc_mux8_mux = 3795 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum, 3796 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put); 3797 3798 static const struct snd_kcontrol_new cdc_if_tx0_mux = 3799 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum); 3800 static const struct snd_kcontrol_new cdc_if_tx1_mux = 3801 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum); 3802 static const struct snd_kcontrol_new cdc_if_tx2_mux = 3803 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum); 3804 static const struct snd_kcontrol_new cdc_if_tx3_mux = 3805 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum); 3806 static const struct snd_kcontrol_new cdc_if_tx4_mux = 3807 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum); 3808 static const struct snd_kcontrol_new cdc_if_tx5_mux = 3809 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum); 3810 static const struct snd_kcontrol_new cdc_if_tx6_mux = 3811 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum); 3812 static const struct snd_kcontrol_new cdc_if_tx7_mux = 3813 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum); 3814 static const struct snd_kcontrol_new cdc_if_tx8_mux = 3815 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum); 3816 static const struct snd_kcontrol_new cdc_if_tx9_mux = 3817 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum); 3818 static const struct snd_kcontrol_new cdc_if_tx10_mux = 3819 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum); 3820 static const struct snd_kcontrol_new cdc_if_tx11_mux = 3821 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum); 3822 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux = 3823 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum); 3824 static const struct snd_kcontrol_new cdc_if_tx13_mux = 3825 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum); 3826 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux = 3827 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum); 3828 3829 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 3830 struct snd_ctl_elem_value *ucontrol) 3831 { 3832 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 3833 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev); 3834 struct soc_mixer_control *mixer = 3835 (struct soc_mixer_control *)kc->private_value; 3836 int port_id = mixer->shift; 3837 3838 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id]; 3839 3840 return 0; 3841 } 3842 3843 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 3844 struct snd_ctl_elem_value *ucontrol) 3845 { 3846 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 3847 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev); 3848 struct snd_soc_dapm_update *update = NULL; 3849 struct soc_mixer_control *mixer = 3850 (struct soc_mixer_control *)kc->private_value; 3851 int enable = ucontrol->value.integer.value[0]; 3852 struct wcd934x_slim_ch *ch, *c; 3853 int dai_id = widget->shift; 3854 int port_id = mixer->shift; 3855 3856 /* only add to the list if value not set */ 3857 if (enable == wcd->tx_port_value[port_id]) 3858 return 0; 3859 3860 if (enable) { 3861 if (list_empty(&wcd->tx_chs[port_id].list)) { 3862 list_add_tail(&wcd->tx_chs[port_id].list, 3863 &wcd->dai[dai_id].slim_ch_list); 3864 } else { 3865 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id); 3866 return 0; 3867 } 3868 } else { 3869 bool found = false; 3870 3871 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) { 3872 if (ch->port == port_id) { 3873 found = true; 3874 list_del_init(&wcd->tx_chs[port_id].list); 3875 break; 3876 } 3877 } 3878 if (!found) 3879 return 0; 3880 } 3881 3882 wcd->tx_port_value[port_id] = enable; 3883 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 3884 3885 return 1; 3886 } 3887 3888 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = { 3889 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3890 slim_tx_mixer_get, slim_tx_mixer_put), 3891 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3892 slim_tx_mixer_get, slim_tx_mixer_put), 3893 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3894 slim_tx_mixer_get, slim_tx_mixer_put), 3895 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3896 slim_tx_mixer_get, slim_tx_mixer_put), 3897 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3898 slim_tx_mixer_get, slim_tx_mixer_put), 3899 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3900 slim_tx_mixer_get, slim_tx_mixer_put), 3901 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3902 slim_tx_mixer_get, slim_tx_mixer_put), 3903 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3904 slim_tx_mixer_get, slim_tx_mixer_put), 3905 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3906 slim_tx_mixer_get, slim_tx_mixer_put), 3907 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3908 slim_tx_mixer_get, slim_tx_mixer_put), 3909 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3910 slim_tx_mixer_get, slim_tx_mixer_put), 3911 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3912 slim_tx_mixer_get, slim_tx_mixer_put), 3913 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3914 slim_tx_mixer_get, slim_tx_mixer_put), 3915 }; 3916 3917 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = { 3918 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3919 slim_tx_mixer_get, slim_tx_mixer_put), 3920 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3921 slim_tx_mixer_get, slim_tx_mixer_put), 3922 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3923 slim_tx_mixer_get, slim_tx_mixer_put), 3924 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3925 slim_tx_mixer_get, slim_tx_mixer_put), 3926 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3927 slim_tx_mixer_get, slim_tx_mixer_put), 3928 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3929 slim_tx_mixer_get, slim_tx_mixer_put), 3930 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3931 slim_tx_mixer_get, slim_tx_mixer_put), 3932 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3933 slim_tx_mixer_get, slim_tx_mixer_put), 3934 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3935 slim_tx_mixer_get, slim_tx_mixer_put), 3936 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3937 slim_tx_mixer_get, slim_tx_mixer_put), 3938 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3939 slim_tx_mixer_get, slim_tx_mixer_put), 3940 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3941 slim_tx_mixer_get, slim_tx_mixer_put), 3942 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3943 slim_tx_mixer_get, slim_tx_mixer_put), 3944 }; 3945 3946 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = { 3947 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0, 3948 slim_tx_mixer_get, slim_tx_mixer_put), 3949 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0, 3950 slim_tx_mixer_get, slim_tx_mixer_put), 3951 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0, 3952 slim_tx_mixer_get, slim_tx_mixer_put), 3953 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0, 3954 slim_tx_mixer_get, slim_tx_mixer_put), 3955 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0, 3956 slim_tx_mixer_get, slim_tx_mixer_put), 3957 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0, 3958 slim_tx_mixer_get, slim_tx_mixer_put), 3959 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0, 3960 slim_tx_mixer_get, slim_tx_mixer_put), 3961 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0, 3962 slim_tx_mixer_get, slim_tx_mixer_put), 3963 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0, 3964 slim_tx_mixer_get, slim_tx_mixer_put), 3965 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0, 3966 slim_tx_mixer_get, slim_tx_mixer_put), 3967 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0, 3968 slim_tx_mixer_get, slim_tx_mixer_put), 3969 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0, 3970 slim_tx_mixer_get, slim_tx_mixer_put), 3971 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0, 3972 slim_tx_mixer_get, slim_tx_mixer_put), 3973 }; 3974 3975 static const struct snd_kcontrol_new wcd934x_snd_controls[] = { 3976 /* Gain Controls */ 3977 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain), 3978 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), 3979 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), 3980 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3981 3, 16, 1, line_gain), 3982 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, 3983 3, 16, 1, line_gain), 3984 3985 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain), 3986 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain), 3987 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain), 3988 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain), 3989 3990 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 3991 -84, 40, digital_gain), /* -84dB min - 40dB max */ 3992 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 3993 -84, 40, digital_gain), 3994 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 3995 -84, 40, digital_gain), 3996 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 3997 -84, 40, digital_gain), 3998 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, 3999 -84, 40, digital_gain), 4000 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL, 4001 -84, 40, digital_gain), 4002 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL, 4003 -84, 40, digital_gain), 4004 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", 4005 WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 4006 -84, 40, digital_gain), 4007 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", 4008 WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 4009 -84, 40, digital_gain), 4010 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", 4011 WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 4012 -84, 40, digital_gain), 4013 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", 4014 WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 4015 -84, 40, digital_gain), 4016 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", 4017 WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 4018 -84, 40, digital_gain), 4019 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", 4020 WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 4021 -84, 40, digital_gain), 4022 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", 4023 WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 4024 -84, 40, digital_gain), 4025 4026 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL, 4027 -84, 40, digital_gain), 4028 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL, 4029 -84, 40, digital_gain), 4030 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL, 4031 -84, 40, digital_gain), 4032 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL, 4033 -84, 40, digital_gain), 4034 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 4035 -84, 40, digital_gain), 4036 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 4037 -84, 40, digital_gain), 4038 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 4039 -84, 40, digital_gain), 4040 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 4041 -84, 40, digital_gain), 4042 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 4043 -84, 40, digital_gain), 4044 4045 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 4046 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 4047 digital_gain), 4048 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 4049 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 4050 digital_gain), 4051 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 4052 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 4053 digital_gain), 4054 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 4055 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 4056 digital_gain), 4057 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 4058 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 4059 digital_gain), 4060 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 4061 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 4062 digital_gain), 4063 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 4064 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 4065 digital_gain), 4066 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 4067 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 4068 digital_gain), 4069 4070 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 4071 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 4072 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 4073 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 4074 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 4075 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 4076 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 4077 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 4078 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 4079 4080 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 4081 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 4082 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 4083 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 4084 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 4085 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 4086 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 4087 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 4088 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 4089 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 4090 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 4091 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 4092 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 4093 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 4094 4095 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 4096 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put), 4097 4098 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4099 0, 1, 0), 4100 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4101 1, 1, 0), 4102 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4103 2, 1, 0), 4104 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4105 3, 1, 0), 4106 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 4107 4, 1, 0), 4108 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4109 0, 1, 0), 4110 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4111 1, 1, 0), 4112 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4113 2, 1, 0), 4114 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4115 3, 1, 0), 4116 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 4117 4, 1, 0), 4118 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 4119 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 4120 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 4121 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 4122 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 4123 4124 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 4125 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 4126 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 4127 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 4128 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 4129 4130 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 4131 wcd934x_compander_get, wcd934x_compander_set), 4132 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 4133 wcd934x_compander_get, wcd934x_compander_set), 4134 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 4135 wcd934x_compander_get, wcd934x_compander_set), 4136 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 4137 wcd934x_compander_get, wcd934x_compander_set), 4138 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 4139 wcd934x_compander_get, wcd934x_compander_set), 4140 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 4141 wcd934x_compander_get, wcd934x_compander_set), 4142 }; 4143 4144 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 4145 struct snd_soc_component *component) 4146 { 4147 int port_num = 0; 4148 unsigned short reg = 0; 4149 unsigned int val = 0; 4150 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev); 4151 struct wcd934x_slim_ch *ch; 4152 4153 list_for_each_entry(ch, &dai->slim_ch_list, list) { 4154 if (ch->port >= WCD934X_RX_START) { 4155 port_num = ch->port - WCD934X_RX_START; 4156 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 4157 } else { 4158 port_num = ch->port; 4159 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 4160 } 4161 4162 regmap_read(wcd->if_regmap, reg, &val); 4163 if (!(val & BIT(port_num % 8))) 4164 regmap_write(wcd->if_regmap, reg, 4165 val | BIT(port_num % 8)); 4166 } 4167 } 4168 4169 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w, 4170 struct snd_kcontrol *kc, int event) 4171 { 4172 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4173 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4174 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 4175 4176 switch (event) { 4177 case SND_SOC_DAPM_POST_PMU: 4178 wcd934x_codec_enable_int_port(dai, comp); 4179 break; 4180 } 4181 4182 return 0; 4183 } 4184 4185 static void wcd934x_codec_hd2_control(struct snd_soc_component *component, 4186 u16 interp_idx, int event) 4187 { 4188 u16 hd2_scale_reg; 4189 u16 hd2_enable_reg = 0; 4190 4191 switch (interp_idx) { 4192 case INTERP_HPHL: 4193 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3; 4194 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0; 4195 break; 4196 case INTERP_HPHR: 4197 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3; 4198 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0; 4199 break; 4200 default: 4201 return; 4202 } 4203 4204 if (SND_SOC_DAPM_EVENT_ON(event)) { 4205 snd_soc_component_update_bits(component, hd2_scale_reg, 4206 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4207 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125); 4208 snd_soc_component_update_bits(component, hd2_enable_reg, 4209 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4210 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE); 4211 } 4212 4213 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4214 snd_soc_component_update_bits(component, hd2_enable_reg, 4215 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK, 4216 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE); 4217 snd_soc_component_update_bits(component, hd2_scale_reg, 4218 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 4219 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 4220 } 4221 } 4222 4223 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp, 4224 u16 interp_idx, int event) 4225 { 4226 u8 hph_dly_mask; 4227 u16 hph_lut_bypass_reg = 0; 4228 4229 switch (interp_idx) { 4230 case INTERP_HPHL: 4231 hph_dly_mask = 1; 4232 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT; 4233 break; 4234 case INTERP_HPHR: 4235 hph_dly_mask = 2; 4236 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT; 4237 break; 4238 default: 4239 return; 4240 } 4241 4242 if (SND_SOC_DAPM_EVENT_ON(event)) { 4243 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4244 hph_dly_mask, 0x0); 4245 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4246 WCD934X_HPH_LUT_BYPASS_MASK, 4247 WCD934X_HPH_LUT_BYPASS_ENABLE); 4248 } 4249 4250 if (SND_SOC_DAPM_EVENT_OFF(event)) { 4251 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0, 4252 hph_dly_mask, hph_dly_mask); 4253 snd_soc_component_update_bits(comp, hph_lut_bypass_reg, 4254 WCD934X_HPH_LUT_BYPASS_MASK, 4255 WCD934X_HPH_LUT_BYPASS_DISABLE); 4256 } 4257 } 4258 4259 static int wcd934x_config_compander(struct snd_soc_component *comp, 4260 int interp_n, int event) 4261 { 4262 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4263 int compander; 4264 u16 comp_ctl0_reg, rx_path_cfg0_reg; 4265 4266 /* EAR does not have compander */ 4267 if (!interp_n) 4268 return 0; 4269 4270 compander = interp_n - 1; 4271 if (!wcd->comp_enabled[compander]) 4272 return 0; 4273 4274 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8); 4275 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20); 4276 4277 switch (event) { 4278 case SND_SOC_DAPM_PRE_PMU: 4279 /* Enable Compander Clock */ 4280 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4281 WCD934X_COMP_CLK_EN_MASK, 4282 WCD934X_COMP_CLK_ENABLE); 4283 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4284 WCD934X_COMP_SOFT_RST_MASK, 4285 WCD934X_COMP_SOFT_RST_ENABLE); 4286 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4287 WCD934X_COMP_SOFT_RST_MASK, 4288 WCD934X_COMP_SOFT_RST_DISABLE); 4289 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4290 WCD934X_HPH_CMP_EN_MASK, 4291 WCD934X_HPH_CMP_ENABLE); 4292 break; 4293 case SND_SOC_DAPM_POST_PMD: 4294 snd_soc_component_update_bits(comp, rx_path_cfg0_reg, 4295 WCD934X_HPH_CMP_EN_MASK, 4296 WCD934X_HPH_CMP_DISABLE); 4297 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4298 WCD934X_COMP_HALT_MASK, 4299 WCD934X_COMP_HALT); 4300 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4301 WCD934X_COMP_SOFT_RST_MASK, 4302 WCD934X_COMP_SOFT_RST_ENABLE); 4303 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4304 WCD934X_COMP_SOFT_RST_MASK, 4305 WCD934X_COMP_SOFT_RST_DISABLE); 4306 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4307 WCD934X_COMP_CLK_EN_MASK, 0x0); 4308 snd_soc_component_update_bits(comp, comp_ctl0_reg, 4309 WCD934X_COMP_SOFT_RST_MASK, 0x0); 4310 break; 4311 } 4312 4313 return 0; 4314 } 4315 4316 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w, 4317 struct snd_kcontrol *kc, int event) 4318 { 4319 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4320 int interp_idx = w->shift; 4321 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20); 4322 4323 switch (event) { 4324 case SND_SOC_DAPM_PRE_PMU: 4325 /* Clk enable */ 4326 snd_soc_component_update_bits(comp, main_reg, 4327 WCD934X_RX_CLK_EN_MASK, 4328 WCD934X_RX_CLK_ENABLE); 4329 wcd934x_codec_hd2_control(comp, interp_idx, event); 4330 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4331 wcd934x_config_compander(comp, interp_idx, event); 4332 break; 4333 case SND_SOC_DAPM_POST_PMD: 4334 wcd934x_config_compander(comp, interp_idx, event); 4335 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event); 4336 wcd934x_codec_hd2_control(comp, interp_idx, event); 4337 /* Clk Disable */ 4338 snd_soc_component_update_bits(comp, main_reg, 4339 WCD934X_RX_CLK_EN_MASK, 0); 4340 /* Reset enable and disable */ 4341 snd_soc_component_update_bits(comp, main_reg, 4342 WCD934X_RX_RESET_MASK, 4343 WCD934X_RX_RESET_ENABLE); 4344 snd_soc_component_update_bits(comp, main_reg, 4345 WCD934X_RX_RESET_MASK, 4346 WCD934X_RX_RESET_DISABLE); 4347 /* Reset rate to 48K*/ 4348 snd_soc_component_update_bits(comp, main_reg, 4349 WCD934X_RX_PCM_RATE_MASK, 4350 WCD934X_RX_PCM_RATE_F_48K); 4351 break; 4352 } 4353 4354 return 0; 4355 } 4356 4357 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 4358 struct snd_kcontrol *kc, int event) 4359 { 4360 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4361 int offset_val = 0; 4362 u16 gain_reg, mix_reg; 4363 int val = 0; 4364 4365 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL + 4366 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4367 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL + 4368 (w->shift * WCD934X_RX_PATH_CTL_OFFSET); 4369 4370 switch (event) { 4371 case SND_SOC_DAPM_PRE_PMU: 4372 /* Clk enable */ 4373 snd_soc_component_update_bits(comp, mix_reg, 4374 WCD934X_CDC_RX_MIX_CLK_EN_MASK, 4375 WCD934X_CDC_RX_MIX_CLK_ENABLE); 4376 break; 4377 4378 case SND_SOC_DAPM_POST_PMU: 4379 val = snd_soc_component_read(comp, gain_reg); 4380 val += offset_val; 4381 snd_soc_component_write(comp, gain_reg, val); 4382 break; 4383 } 4384 4385 return 0; 4386 } 4387 4388 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w, 4389 struct snd_kcontrol *kcontrol, int event) 4390 { 4391 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4392 int reg = w->reg; 4393 4394 switch (event) { 4395 case SND_SOC_DAPM_POST_PMU: 4396 /* B1 GAIN */ 4397 snd_soc_component_write(comp, reg, 4398 snd_soc_component_read(comp, reg)); 4399 /* B2 GAIN */ 4400 reg++; 4401 snd_soc_component_write(comp, reg, 4402 snd_soc_component_read(comp, reg)); 4403 /* B3 GAIN */ 4404 reg++; 4405 snd_soc_component_write(comp, reg, 4406 snd_soc_component_read(comp, reg)); 4407 /* B4 GAIN */ 4408 reg++; 4409 snd_soc_component_write(comp, reg, 4410 snd_soc_component_read(comp, reg)); 4411 /* B5 GAIN */ 4412 reg++; 4413 snd_soc_component_write(comp, reg, 4414 snd_soc_component_read(comp, reg)); 4415 break; 4416 default: 4417 break; 4418 } 4419 return 0; 4420 } 4421 4422 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w, 4423 struct snd_kcontrol *kcontrol, 4424 int event) 4425 { 4426 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4427 u16 gain_reg; 4428 4429 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift * 4430 WCD934X_RX_PATH_CTL_OFFSET); 4431 4432 switch (event) { 4433 case SND_SOC_DAPM_POST_PMU: 4434 snd_soc_component_write(comp, gain_reg, 4435 snd_soc_component_read(comp, gain_reg)); 4436 break; 4437 } 4438 4439 return 0; 4440 } 4441 4442 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 4443 struct snd_kcontrol *kc, int event) 4444 { 4445 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4446 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4447 4448 switch (event) { 4449 case SND_SOC_DAPM_PRE_PMU: 4450 /* Disable AutoChop timer during power up */ 4451 snd_soc_component_update_bits(comp, 4452 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4453 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4454 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4455 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4456 4457 break; 4458 case SND_SOC_DAPM_POST_PMD: 4459 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4460 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 4461 break; 4462 } 4463 4464 return 0; 4465 } 4466 4467 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 4468 struct snd_kcontrol *kcontrol, 4469 int event) 4470 { 4471 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4472 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4473 int hph_mode = wcd->hph_mode; 4474 u8 dem_inp; 4475 4476 switch (event) { 4477 case SND_SOC_DAPM_PRE_PMU: 4478 /* Read DEM INP Select */ 4479 dem_inp = snd_soc_component_read(comp, 4480 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03; 4481 4482 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4483 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4484 return -EINVAL; 4485 } 4486 if (hph_mode != CLS_H_LP) 4487 /* Ripple freq control enable */ 4488 snd_soc_component_update_bits(comp, 4489 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4490 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4491 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4492 /* Disable AutoChop timer during power up */ 4493 snd_soc_component_update_bits(comp, 4494 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4495 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4496 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4497 WCD_CLSH_STATE_HPHL, hph_mode); 4498 4499 break; 4500 case SND_SOC_DAPM_POST_PMD: 4501 /* 1000us required as per HW requirement */ 4502 usleep_range(1000, 1100); 4503 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4504 WCD_CLSH_STATE_HPHL, hph_mode); 4505 if (hph_mode != CLS_H_LP) 4506 /* Ripple freq control disable */ 4507 snd_soc_component_update_bits(comp, 4508 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4509 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4510 4511 break; 4512 default: 4513 break; 4514 } 4515 4516 return 0; 4517 } 4518 4519 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 4520 struct snd_kcontrol *kcontrol, 4521 int event) 4522 { 4523 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4524 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4525 int hph_mode = wcd->hph_mode; 4526 u8 dem_inp; 4527 4528 switch (event) { 4529 case SND_SOC_DAPM_PRE_PMU: 4530 dem_inp = snd_soc_component_read(comp, 4531 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03; 4532 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 4533 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 4534 return -EINVAL; 4535 } 4536 if (hph_mode != CLS_H_LP) 4537 /* Ripple freq control enable */ 4538 snd_soc_component_update_bits(comp, 4539 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4540 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 4541 WCD934X_SIDO_RIPPLE_FREQ_ENABLE); 4542 /* Disable AutoChop timer during power up */ 4543 snd_soc_component_update_bits(comp, 4544 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4545 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0); 4546 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4547 WCD_CLSH_STATE_HPHR, 4548 hph_mode); 4549 break; 4550 case SND_SOC_DAPM_POST_PMD: 4551 /* 1000us required as per HW requirement */ 4552 usleep_range(1000, 1100); 4553 4554 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4555 WCD_CLSH_STATE_HPHR, hph_mode); 4556 if (hph_mode != CLS_H_LP) 4557 /* Ripple freq control disable */ 4558 snd_soc_component_update_bits(comp, 4559 WCD934X_SIDO_NEW_VOUT_D_FREQ2, 4560 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0); 4561 break; 4562 default: 4563 break; 4564 } 4565 4566 return 0; 4567 } 4568 4569 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 4570 struct snd_kcontrol *kc, int event) 4571 { 4572 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4573 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4574 4575 switch (event) { 4576 case SND_SOC_DAPM_PRE_PMU: 4577 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 4578 WCD_CLSH_STATE_LO, CLS_AB); 4579 break; 4580 case SND_SOC_DAPM_POST_PMD: 4581 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 4582 WCD_CLSH_STATE_LO, CLS_AB); 4583 break; 4584 } 4585 4586 return 0; 4587 } 4588 4589 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 4590 struct snd_kcontrol *kcontrol, 4591 int event) 4592 { 4593 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4594 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4595 4596 switch (event) { 4597 case SND_SOC_DAPM_POST_PMU: 4598 /* 4599 * 7ms sleep is required after PA is enabled as per 4600 * HW requirement. If compander is disabled, then 4601 * 20ms delay is needed. 4602 */ 4603 usleep_range(20000, 20100); 4604 4605 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4606 WCD934X_HPH_OCP_DET_MASK, 4607 WCD934X_HPH_OCP_DET_ENABLE); 4608 /* Remove Mute on primary path */ 4609 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4610 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4611 0); 4612 /* Enable GM3 boost */ 4613 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4614 WCD934X_HPH_GM3_BOOST_EN_MASK, 4615 WCD934X_HPH_GM3_BOOST_ENABLE); 4616 /* Enable AutoChop timer at the end of power up */ 4617 snd_soc_component_update_bits(comp, 4618 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4619 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4620 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4621 /* Remove mix path mute */ 4622 snd_soc_component_update_bits(comp, 4623 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4624 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00); 4625 break; 4626 case SND_SOC_DAPM_PRE_PMD: 4627 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4628 /* Enable DSD Mute before PA disable */ 4629 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST, 4630 WCD934X_HPH_OCP_DET_MASK, 4631 WCD934X_HPH_OCP_DET_DISABLE); 4632 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL, 4633 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4634 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4635 snd_soc_component_update_bits(comp, 4636 WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 4637 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4638 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4639 break; 4640 case SND_SOC_DAPM_POST_PMD: 4641 /* 4642 * 5ms sleep is required after PA disable. If compander is 4643 * disabled, then 20ms delay is needed after PA disable. 4644 */ 4645 usleep_range(20000, 20100); 4646 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF); 4647 break; 4648 } 4649 4650 return 0; 4651 } 4652 4653 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 4654 struct snd_kcontrol *kcontrol, 4655 int event) 4656 { 4657 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4658 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp); 4659 4660 switch (event) { 4661 case SND_SOC_DAPM_POST_PMU: 4662 /* 4663 * 7ms sleep is required after PA is enabled as per 4664 * HW requirement. If compander is disabled, then 4665 * 20ms delay is needed. 4666 */ 4667 usleep_range(20000, 20100); 4668 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4669 WCD934X_HPH_OCP_DET_MASK, 4670 WCD934X_HPH_OCP_DET_ENABLE); 4671 /* Remove mute */ 4672 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4673 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4674 0); 4675 /* Enable GM3 boost */ 4676 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL, 4677 WCD934X_HPH_GM3_BOOST_EN_MASK, 4678 WCD934X_HPH_GM3_BOOST_ENABLE); 4679 /* Enable AutoChop timer at the end of power up */ 4680 snd_soc_component_update_bits(comp, 4681 WCD934X_HPH_NEW_INT_HPH_TIMER1, 4682 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 4683 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE); 4684 /* Remove mix path mute if it is enabled */ 4685 if ((snd_soc_component_read(comp, 4686 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10) 4687 snd_soc_component_update_bits(comp, 4688 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4689 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4690 WCD934X_CDC_RX_PGA_MUTE_DISABLE); 4691 break; 4692 case SND_SOC_DAPM_PRE_PMD: 4693 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF); 4694 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST, 4695 WCD934X_HPH_OCP_DET_MASK, 4696 WCD934X_HPH_OCP_DET_DISABLE); 4697 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL, 4698 WCD934X_RX_PATH_PGA_MUTE_EN_MASK, 4699 WCD934X_RX_PATH_PGA_MUTE_ENABLE); 4700 snd_soc_component_update_bits(comp, 4701 WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 4702 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 4703 WCD934X_CDC_RX_PGA_MUTE_ENABLE); 4704 break; 4705 case SND_SOC_DAPM_POST_PMD: 4706 /* 4707 * 5ms sleep is required after PA disable. If compander is 4708 * disabled, then 20ms delay is needed after PA disable. 4709 */ 4710 usleep_range(20000, 20100); 4711 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF); 4712 break; 4713 } 4714 4715 return 0; 4716 } 4717 4718 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp, 4719 unsigned int dmic, 4720 struct wcd934x_codec *wcd) 4721 { 4722 u8 tx_stream_fs; 4723 u8 adc_mux_index = 0, adc_mux_sel = 0; 4724 bool dec_found = false; 4725 u16 adc_mux_ctl_reg, tx_fs_reg; 4726 u32 dmic_fs; 4727 4728 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) { 4729 if (adc_mux_index < 4) { 4730 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4731 (adc_mux_index * 2); 4732 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) { 4733 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4734 adc_mux_index - 4; 4735 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) { 4736 ++adc_mux_index; 4737 continue; 4738 } 4739 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg) 4740 & 0xF8) >> 3) - 1; 4741 4742 if (adc_mux_sel == dmic) { 4743 dec_found = true; 4744 break; 4745 } 4746 4747 ++adc_mux_index; 4748 } 4749 4750 if (dec_found && adc_mux_index <= 8) { 4751 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index); 4752 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F; 4753 if (tx_stream_fs <= 4) 4754 dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ); 4755 else 4756 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ; 4757 } else { 4758 dmic_fs = wcd->dmic_sample_rate; 4759 } 4760 4761 return dmic_fs; 4762 } 4763 4764 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp, 4765 u32 mclk_rate, u32 dmic_clk_rate) 4766 { 4767 u32 div_factor; 4768 u8 dmic_ctl_val; 4769 4770 /* Default value to return in case of error */ 4771 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ) 4772 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4773 else 4774 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4775 4776 if (dmic_clk_rate == 0) { 4777 dev_err(comp->dev, 4778 "%s: dmic_sample_rate cannot be 0\n", 4779 __func__); 4780 goto done; 4781 } 4782 4783 div_factor = mclk_rate / dmic_clk_rate; 4784 switch (div_factor) { 4785 case 2: 4786 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2; 4787 break; 4788 case 3: 4789 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3; 4790 break; 4791 case 4: 4792 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4; 4793 break; 4794 case 6: 4795 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6; 4796 break; 4797 case 8: 4798 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8; 4799 break; 4800 case 16: 4801 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16; 4802 break; 4803 default: 4804 dev_err(comp->dev, 4805 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 4806 __func__, div_factor, mclk_rate, dmic_clk_rate); 4807 break; 4808 } 4809 4810 done: 4811 return dmic_ctl_val; 4812 } 4813 4814 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w, 4815 struct snd_kcontrol *kcontrol, int event) 4816 { 4817 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4818 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 4819 u8 dmic_clk_en = 0x01; 4820 u16 dmic_clk_reg; 4821 s32 *dmic_clk_cnt; 4822 u8 dmic_rate_val, dmic_rate_shift = 1; 4823 unsigned int dmic; 4824 u32 dmic_sample_rate; 4825 int ret; 4826 char *wname; 4827 4828 wname = strpbrk(w->name, "012345"); 4829 if (!wname) { 4830 dev_err(comp->dev, "%s: widget not found\n", __func__); 4831 return -EINVAL; 4832 } 4833 4834 ret = kstrtouint(wname, 10, &dmic); 4835 if (ret < 0) { 4836 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 4837 __func__); 4838 return -EINVAL; 4839 } 4840 4841 switch (dmic) { 4842 case 0: 4843 case 1: 4844 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt; 4845 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL; 4846 break; 4847 case 2: 4848 case 3: 4849 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt; 4850 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL; 4851 break; 4852 case 4: 4853 case 5: 4854 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt; 4855 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL; 4856 break; 4857 default: 4858 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 4859 __func__); 4860 return -EINVAL; 4861 } 4862 4863 switch (event) { 4864 case SND_SOC_DAPM_PRE_PMU: 4865 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic, 4866 wcd); 4867 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate, 4868 dmic_sample_rate); 4869 (*dmic_clk_cnt)++; 4870 if (*dmic_clk_cnt == 1) { 4871 dmic_rate_val = dmic_rate_val << dmic_rate_shift; 4872 snd_soc_component_update_bits(comp, dmic_clk_reg, 4873 WCD934X_DMIC_RATE_MASK, 4874 dmic_rate_val); 4875 snd_soc_component_update_bits(comp, dmic_clk_reg, 4876 dmic_clk_en, dmic_clk_en); 4877 } 4878 4879 break; 4880 case SND_SOC_DAPM_POST_PMD: 4881 (*dmic_clk_cnt)--; 4882 if (*dmic_clk_cnt == 0) 4883 snd_soc_component_update_bits(comp, dmic_clk_reg, 4884 dmic_clk_en, 0); 4885 break; 4886 } 4887 4888 return 0; 4889 } 4890 4891 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp, 4892 int adc_mux_n) 4893 { 4894 u16 mask, shift, adc_mux_in_reg; 4895 u16 amic_mux_sel_reg; 4896 bool is_amic; 4897 4898 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX || 4899 adc_mux_n == WCD934X_INVALID_ADC_MUX) 4900 return 0; 4901 4902 if (adc_mux_n < 3) { 4903 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4904 adc_mux_n; 4905 mask = 0x03; 4906 shift = 0; 4907 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4908 2 * adc_mux_n; 4909 } else if (adc_mux_n < 4) { 4910 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4911 mask = 0x03; 4912 shift = 0; 4913 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 4914 2 * adc_mux_n; 4915 } else if (adc_mux_n < 7) { 4916 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4917 (adc_mux_n - 4); 4918 mask = 0x0C; 4919 shift = 2; 4920 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4921 adc_mux_n - 4; 4922 } else if (adc_mux_n < 8) { 4923 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4924 mask = 0x0C; 4925 shift = 2; 4926 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4927 adc_mux_n - 4; 4928 } else if (adc_mux_n < 12) { 4929 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 4930 ((adc_mux_n == 8) ? (adc_mux_n - 8) : 4931 (adc_mux_n - 9)); 4932 mask = 0x30; 4933 shift = 4; 4934 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4935 adc_mux_n - 4; 4936 } else if (adc_mux_n < 13) { 4937 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1; 4938 mask = 0x30; 4939 shift = 4; 4940 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4941 adc_mux_n - 4; 4942 } else { 4943 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1; 4944 mask = 0xC0; 4945 shift = 6; 4946 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + 4947 adc_mux_n - 4; 4948 } 4949 4950 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg) 4951 & mask) >> shift) == 1); 4952 if (!is_amic) 4953 return 0; 4954 4955 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07; 4956 } 4957 4958 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 4959 int amic) 4960 { 4961 u16 pwr_level_reg = 0; 4962 4963 switch (amic) { 4964 case 1: 4965 case 2: 4966 pwr_level_reg = WCD934X_ANA_AMIC1; 4967 break; 4968 4969 case 3: 4970 case 4: 4971 pwr_level_reg = WCD934X_ANA_AMIC3; 4972 break; 4973 default: 4974 break; 4975 } 4976 4977 return pwr_level_reg; 4978 } 4979 4980 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w, 4981 struct snd_kcontrol *kcontrol, int event) 4982 { 4983 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4984 unsigned int decimator; 4985 char *dec_adc_mux_name = NULL; 4986 char *widget_name = NULL; 4987 char *wname; 4988 int ret = 0, amic_n; 4989 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 4990 u16 tx_gain_ctl_reg; 4991 char *dec; 4992 u8 hpf_coff_freq; 4993 4994 widget_name = kstrndup(w->name, 15, GFP_KERNEL); 4995 if (!widget_name) 4996 return -ENOMEM; 4997 4998 wname = widget_name; 4999 dec_adc_mux_name = strsep(&widget_name, " "); 5000 if (!dec_adc_mux_name) { 5001 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 5002 __func__, w->name); 5003 ret = -EINVAL; 5004 goto out; 5005 } 5006 dec_adc_mux_name = widget_name; 5007 5008 dec = strpbrk(dec_adc_mux_name, "012345678"); 5009 if (!dec) { 5010 dev_err(comp->dev, "%s: decimator index not found\n", 5011 __func__); 5012 ret = -EINVAL; 5013 goto out; 5014 } 5015 5016 ret = kstrtouint(dec, 10, &decimator); 5017 if (ret < 0) { 5018 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 5019 __func__, wname); 5020 ret = -EINVAL; 5021 goto out; 5022 } 5023 5024 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator; 5025 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 5026 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 5027 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator; 5028 5029 switch (event) { 5030 case SND_SOC_DAPM_PRE_PMU: 5031 amic_n = wcd934x_codec_find_amic_input(comp, decimator); 5032 if (amic_n) 5033 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp, 5034 amic_n); 5035 5036 if (!pwr_level_reg) 5037 break; 5038 5039 switch ((snd_soc_component_read(comp, pwr_level_reg) & 5040 WCD934X_AMIC_PWR_LVL_MASK) >> 5041 WCD934X_AMIC_PWR_LVL_SHIFT) { 5042 case WCD934X_AMIC_PWR_LEVEL_LP: 5043 snd_soc_component_update_bits(comp, dec_cfg_reg, 5044 WCD934X_DEC_PWR_LVL_MASK, 5045 WCD934X_DEC_PWR_LVL_LP); 5046 break; 5047 case WCD934X_AMIC_PWR_LEVEL_HP: 5048 snd_soc_component_update_bits(comp, dec_cfg_reg, 5049 WCD934X_DEC_PWR_LVL_MASK, 5050 WCD934X_DEC_PWR_LVL_HP); 5051 break; 5052 case WCD934X_AMIC_PWR_LEVEL_DEFAULT: 5053 case WCD934X_AMIC_PWR_LEVEL_HYBRID: 5054 default: 5055 snd_soc_component_update_bits(comp, dec_cfg_reg, 5056 WCD934X_DEC_PWR_LVL_MASK, 5057 WCD934X_DEC_PWR_LVL_DF); 5058 break; 5059 } 5060 break; 5061 case SND_SOC_DAPM_POST_PMU: 5062 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5063 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5064 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5065 snd_soc_component_update_bits(comp, dec_cfg_reg, 5066 TX_HPF_CUT_OFF_FREQ_MASK, 5067 CF_MIN_3DB_150HZ << 5); 5068 snd_soc_component_update_bits(comp, hpf_gate_reg, 5069 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5070 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5071 /* 5072 * Minimum 1 clk cycle delay is required as per 5073 * HW spec. 5074 */ 5075 usleep_range(1000, 1010); 5076 snd_soc_component_update_bits(comp, hpf_gate_reg, 5077 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5078 0); 5079 } 5080 /* apply gain after decimator is enabled */ 5081 snd_soc_component_write(comp, tx_gain_ctl_reg, 5082 snd_soc_component_read(comp, 5083 tx_gain_ctl_reg)); 5084 break; 5085 case SND_SOC_DAPM_PRE_PMD: 5086 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 5087 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 5088 5089 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 5090 snd_soc_component_update_bits(comp, dec_cfg_reg, 5091 TX_HPF_CUT_OFF_FREQ_MASK, 5092 hpf_coff_freq << 5); 5093 snd_soc_component_update_bits(comp, hpf_gate_reg, 5094 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5095 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ); 5096 /* 5097 * Minimum 1 clk cycle delay is required as per 5098 * HW spec. 5099 */ 5100 usleep_range(1000, 1010); 5101 snd_soc_component_update_bits(comp, hpf_gate_reg, 5102 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK, 5103 0); 5104 } 5105 break; 5106 case SND_SOC_DAPM_POST_PMD: 5107 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 5108 0x10, 0x00); 5109 snd_soc_component_update_bits(comp, dec_cfg_reg, 5110 WCD934X_DEC_PWR_LVL_MASK, 5111 WCD934X_DEC_PWR_LVL_DF); 5112 break; 5113 } 5114 out: 5115 kfree(wname); 5116 return ret; 5117 } 5118 5119 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp, 5120 u16 amic_reg, bool set) 5121 { 5122 u8 mask = 0x20; 5123 u8 val; 5124 5125 if (amic_reg == WCD934X_ANA_AMIC1 || 5126 amic_reg == WCD934X_ANA_AMIC3) 5127 mask = 0x40; 5128 5129 val = set ? mask : 0x00; 5130 5131 switch (amic_reg) { 5132 case WCD934X_ANA_AMIC1: 5133 case WCD934X_ANA_AMIC2: 5134 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2, 5135 mask, val); 5136 break; 5137 case WCD934X_ANA_AMIC3: 5138 case WCD934X_ANA_AMIC4: 5139 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4, 5140 mask, val); 5141 break; 5142 default: 5143 break; 5144 } 5145 } 5146 5147 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w, 5148 struct snd_kcontrol *kcontrol, int event) 5149 { 5150 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 5151 5152 switch (event) { 5153 case SND_SOC_DAPM_PRE_PMU: 5154 wcd934x_codec_set_tx_hold(comp, w->reg, true); 5155 break; 5156 default: 5157 break; 5158 } 5159 5160 return 0; 5161 } 5162 5163 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w, 5164 struct snd_kcontrol *kcontrol, 5165 int event) 5166 { 5167 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5168 int micb_num = w->shift; 5169 5170 switch (event) { 5171 case SND_SOC_DAPM_PRE_PMU: 5172 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true); 5173 break; 5174 case SND_SOC_DAPM_POST_PMU: 5175 /* 1 msec delay as per HW requirement */ 5176 usleep_range(1000, 1100); 5177 break; 5178 case SND_SOC_DAPM_POST_PMD: 5179 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true); 5180 break; 5181 } 5182 5183 return 0; 5184 } 5185 5186 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = { 5187 /* Analog Outputs */ 5188 SND_SOC_DAPM_OUTPUT("EAR"), 5189 SND_SOC_DAPM_OUTPUT("HPHL"), 5190 SND_SOC_DAPM_OUTPUT("HPHR"), 5191 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 5192 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 5193 SND_SOC_DAPM_OUTPUT("SPK1 OUT"), 5194 SND_SOC_DAPM_OUTPUT("SPK2 OUT"), 5195 SND_SOC_DAPM_OUTPUT("ANC EAR"), 5196 SND_SOC_DAPM_OUTPUT("ANC HPHL"), 5197 SND_SOC_DAPM_OUTPUT("ANC HPHR"), 5198 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"), 5199 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"), 5200 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"), 5201 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 5202 AIF1_PB, 0, wcd934x_codec_enable_slim, 5203 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5204 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 5205 AIF2_PB, 0, wcd934x_codec_enable_slim, 5206 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5207 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 5208 AIF3_PB, 0, wcd934x_codec_enable_slim, 5209 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5210 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 5211 AIF4_PB, 0, wcd934x_codec_enable_slim, 5212 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5213 5214 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0, 5215 &slim_rx_mux[WCD934X_RX0]), 5216 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0, 5217 &slim_rx_mux[WCD934X_RX1]), 5218 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0, 5219 &slim_rx_mux[WCD934X_RX2]), 5220 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0, 5221 &slim_rx_mux[WCD934X_RX3]), 5222 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0, 5223 &slim_rx_mux[WCD934X_RX4]), 5224 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0, 5225 &slim_rx_mux[WCD934X_RX5]), 5226 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0, 5227 &slim_rx_mux[WCD934X_RX6]), 5228 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0, 5229 &slim_rx_mux[WCD934X_RX7]), 5230 5231 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5232 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5233 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5234 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5235 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5236 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5237 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5238 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5239 5240 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0, 5241 &rx_int0_2_mux, wcd934x_codec_enable_mix_path, 5242 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5243 SND_SOC_DAPM_POST_PMD), 5244 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 5245 &rx_int1_2_mux, wcd934x_codec_enable_mix_path, 5246 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5247 SND_SOC_DAPM_POST_PMD), 5248 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 5249 &rx_int2_2_mux, wcd934x_codec_enable_mix_path, 5250 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5251 SND_SOC_DAPM_POST_PMD), 5252 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0, 5253 &rx_int3_2_mux, wcd934x_codec_enable_mix_path, 5254 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5255 SND_SOC_DAPM_POST_PMD), 5256 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0, 5257 &rx_int4_2_mux, wcd934x_codec_enable_mix_path, 5258 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5259 SND_SOC_DAPM_POST_PMD), 5260 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0, 5261 &rx_int7_2_mux, wcd934x_codec_enable_mix_path, 5262 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5263 SND_SOC_DAPM_POST_PMD), 5264 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0, 5265 &rx_int8_2_mux, wcd934x_codec_enable_mix_path, 5266 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5267 SND_SOC_DAPM_POST_PMD), 5268 5269 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5270 &rx_int0_1_mix_inp0_mux), 5271 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5272 &rx_int0_1_mix_inp1_mux), 5273 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5274 &rx_int0_1_mix_inp2_mux), 5275 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5276 &rx_int1_1_mix_inp0_mux), 5277 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5278 &rx_int1_1_mix_inp1_mux), 5279 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5280 &rx_int1_1_mix_inp2_mux), 5281 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5282 &rx_int2_1_mix_inp0_mux), 5283 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5284 &rx_int2_1_mix_inp1_mux), 5285 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5286 &rx_int2_1_mix_inp2_mux), 5287 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5288 &rx_int3_1_mix_inp0_mux), 5289 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5290 &rx_int3_1_mix_inp1_mux), 5291 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5292 &rx_int3_1_mix_inp2_mux), 5293 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5294 &rx_int4_1_mix_inp0_mux), 5295 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5296 &rx_int4_1_mix_inp1_mux), 5297 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5298 &rx_int4_1_mix_inp2_mux), 5299 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5300 &rx_int7_1_mix_inp0_mux), 5301 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5302 &rx_int7_1_mix_inp1_mux), 5303 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5304 &rx_int7_1_mix_inp2_mux), 5305 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 5306 &rx_int8_1_mix_inp0_mux), 5307 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 5308 &rx_int8_1_mix_inp1_mux), 5309 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 5310 &rx_int8_1_mix_inp2_mux), 5311 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5312 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5313 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5314 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, 5315 rx_int1_asrc_switch, 5316 ARRAY_SIZE(rx_int1_asrc_switch)), 5317 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5318 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, 5319 rx_int2_asrc_switch, 5320 ARRAY_SIZE(rx_int2_asrc_switch)), 5321 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5322 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, 5323 rx_int3_asrc_switch, 5324 ARRAY_SIZE(rx_int3_asrc_switch)), 5325 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5326 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, 5327 rx_int4_asrc_switch, 5328 ARRAY_SIZE(rx_int4_asrc_switch)), 5329 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5330 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5331 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5332 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 5333 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5334 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5335 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5336 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5337 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5338 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5339 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5340 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5341 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5342 5343 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5344 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0, 5345 NULL, 0, NULL, 0), 5346 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0, 5347 NULL, 0, NULL, 0), 5348 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4, 5349 0, &rx_int0_mix2_inp_mux, NULL, 5350 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5351 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4, 5352 0, &rx_int1_mix2_inp_mux, NULL, 5353 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5354 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4, 5355 0, &rx_int2_mix2_inp_mux, NULL, 5356 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5357 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4, 5358 0, &rx_int3_mix2_inp_mux, NULL, 5359 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5360 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4, 5361 0, &rx_int4_mix2_inp_mux, NULL, 5362 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5363 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4, 5364 0, &rx_int7_mix2_inp_mux, NULL, 5365 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5366 5367 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 5368 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 5369 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 5370 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 5371 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 5372 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 5373 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 5374 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 5375 5376 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 5377 0, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5378 SND_SOC_DAPM_POST_PMU), 5379 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 5380 1, 0, NULL, 0, wcd934x_codec_set_iir_gain, 5381 SND_SOC_DAPM_POST_PMU), 5382 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 5383 4, 0, NULL, 0), 5384 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 5385 4, 0, NULL, 0), 5386 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 5387 &rx_int0_dem_inp_mux), 5388 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 5389 &rx_int1_dem_inp_mux), 5390 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 5391 &rx_int2_dem_inp_mux), 5392 5393 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0, 5394 &rx_int0_1_interp_mux, 5395 wcd934x_codec_enable_main_path, 5396 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5397 SND_SOC_DAPM_POST_PMD), 5398 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 5399 &rx_int1_1_interp_mux, 5400 wcd934x_codec_enable_main_path, 5401 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5402 SND_SOC_DAPM_POST_PMD), 5403 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 5404 &rx_int2_1_interp_mux, 5405 wcd934x_codec_enable_main_path, 5406 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5407 SND_SOC_DAPM_POST_PMD), 5408 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0, 5409 &rx_int3_1_interp_mux, 5410 wcd934x_codec_enable_main_path, 5411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5412 SND_SOC_DAPM_POST_PMD), 5413 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0, 5414 &rx_int4_1_interp_mux, 5415 wcd934x_codec_enable_main_path, 5416 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5417 SND_SOC_DAPM_POST_PMD), 5418 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0, 5419 &rx_int7_1_interp_mux, 5420 wcd934x_codec_enable_main_path, 5421 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5422 SND_SOC_DAPM_POST_PMD), 5423 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0, 5424 &rx_int8_1_interp_mux, 5425 wcd934x_codec_enable_main_path, 5426 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5427 SND_SOC_DAPM_POST_PMD), 5428 5429 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 5430 &rx_int0_2_interp_mux), 5431 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 5432 &rx_int1_2_interp_mux), 5433 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 5434 &rx_int2_2_interp_mux), 5435 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0, 5436 &rx_int3_2_interp_mux), 5437 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0, 5438 &rx_int4_2_interp_mux), 5439 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0, 5440 &rx_int7_2_interp_mux), 5441 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0, 5442 &rx_int8_2_interp_mux), 5443 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 5444 0, 0, wcd934x_codec_ear_dac_event, 5445 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5446 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5447 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH, 5448 5, 0, wcd934x_codec_hphl_dac_event, 5449 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5450 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5451 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH, 5452 4, 0, wcd934x_codec_hphr_dac_event, 5453 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5454 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5455 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 5456 0, 0, wcd934x_codec_lineout_dac_event, 5457 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5458 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 5459 0, 0, wcd934x_codec_lineout_dac_event, 5460 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5461 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0), 5462 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0, 5463 wcd934x_codec_enable_hphl_pa, 5464 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5465 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5466 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0, 5467 wcd934x_codec_enable_hphr_pa, 5468 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5469 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5470 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0, 5471 NULL, 0), 5472 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0, 5473 NULL, 0), 5474 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL, 5475 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5476 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1, 5477 0, 0, NULL, 0), 5478 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 5479 0, 0, NULL, 0), 5480 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1, 5481 0, 0, NULL, 0), 5482 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 5483 0, 0, NULL, 0), 5484 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0, 5485 wcd934x_codec_enable_interp_clk, 5486 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5487 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0, 5488 wcd934x_codec_enable_interp_clk, 5489 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5490 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0, 5491 wcd934x_codec_enable_interp_clk, 5492 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5493 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0, 5494 wcd934x_codec_enable_interp_clk, 5495 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5496 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0, 5497 wcd934x_codec_enable_interp_clk, 5498 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5499 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0, 5500 wcd934x_codec_enable_interp_clk, 5501 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5502 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0, 5503 wcd934x_codec_enable_interp_clk, 5504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5505 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 5506 0, 0, NULL, 0), 5507 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 5508 0, 0, NULL, 0), 5509 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 5510 0, 0, NULL, 0), 5511 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 5512 0, 0, NULL, 0), 5513 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 5514 0, 0, NULL, 0), 5515 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 5516 0, 0, NULL, 0), 5517 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 5518 0, 0, NULL, 0), 5519 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 5520 wcd934x_codec_enable_mclk, 5521 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5522 5523 /* TX */ 5524 SND_SOC_DAPM_INPUT("AMIC1"), 5525 SND_SOC_DAPM_INPUT("AMIC2"), 5526 SND_SOC_DAPM_INPUT("AMIC3"), 5527 SND_SOC_DAPM_INPUT("AMIC4"), 5528 SND_SOC_DAPM_INPUT("AMIC5"), 5529 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 5530 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 5531 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 5532 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 5533 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 5534 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 5535 5536 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 5537 AIF1_CAP, 0, wcd934x_codec_enable_slim, 5538 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5539 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 5540 AIF2_CAP, 0, wcd934x_codec_enable_slim, 5541 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5542 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 5543 AIF3_CAP, 0, wcd934x_codec_enable_slim, 5544 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5545 5546 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0), 5547 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0), 5548 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0), 5549 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0), 5550 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0), 5551 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0), 5552 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0), 5553 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0), 5554 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0), 5555 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0), 5556 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0), 5557 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0), 5558 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0), 5559 5560 /* Digital Mic Inputs */ 5561 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 5562 wcd934x_codec_enable_dmic, 5563 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5564 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 5565 wcd934x_codec_enable_dmic, 5566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5567 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 5568 wcd934x_codec_enable_dmic, 5569 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5570 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 5571 wcd934x_codec_enable_dmic, 5572 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5573 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 5574 wcd934x_codec_enable_dmic, 5575 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5576 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 5577 wcd934x_codec_enable_dmic, 5578 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 5579 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0), 5580 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1), 5581 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2), 5582 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3), 5583 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4), 5584 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5), 5585 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6), 5586 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7), 5587 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8), 5588 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0), 5589 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1), 5590 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2), 5591 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3), 5592 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4), 5593 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5), 5594 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6), 5595 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7), 5596 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8), 5597 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0, 5598 &tx_adc_mux0_mux, wcd934x_codec_enable_dec, 5599 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5600 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5601 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0, 5602 &tx_adc_mux1_mux, wcd934x_codec_enable_dec, 5603 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5604 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5605 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0, 5606 &tx_adc_mux2_mux, wcd934x_codec_enable_dec, 5607 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5608 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5609 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0, 5610 &tx_adc_mux3_mux, wcd934x_codec_enable_dec, 5611 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5612 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5613 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0, 5614 &tx_adc_mux4_mux, wcd934x_codec_enable_dec, 5615 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5616 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5617 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0, 5618 &tx_adc_mux5_mux, wcd934x_codec_enable_dec, 5619 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5620 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5621 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0, 5622 &tx_adc_mux6_mux, wcd934x_codec_enable_dec, 5623 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5624 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5625 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0, 5626 &tx_adc_mux7_mux, wcd934x_codec_enable_dec, 5627 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5628 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5629 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0, 5630 &tx_adc_mux8_mux, wcd934x_codec_enable_dec, 5631 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 5632 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 5633 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0, 5634 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5635 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0, 5636 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5637 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0, 5638 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5639 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0, 5640 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 5641 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0, 5642 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5643 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5644 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0, 5645 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5646 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5647 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0, 5648 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5649 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5650 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0, 5651 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | 5652 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 5653 5654 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5), 5655 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0, 5656 &cdc_if_tx0_mux), 5657 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0, 5658 &cdc_if_tx1_mux), 5659 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0, 5660 &cdc_if_tx2_mux), 5661 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0, 5662 &cdc_if_tx3_mux), 5663 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0, 5664 &cdc_if_tx4_mux), 5665 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0, 5666 &cdc_if_tx5_mux), 5667 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0, 5668 &cdc_if_tx6_mux), 5669 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0, 5670 &cdc_if_tx7_mux), 5671 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0, 5672 &cdc_if_tx8_mux), 5673 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0, 5674 &cdc_if_tx9_mux), 5675 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0, 5676 &cdc_if_tx10_mux), 5677 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5678 &cdc_if_tx11_mux), 5679 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0, 5680 &cdc_if_tx11_inp1_mux), 5681 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5682 &cdc_if_tx13_mux), 5683 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0, 5684 &cdc_if_tx13_inp1_mux), 5685 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 5686 aif1_slim_cap_mixer, 5687 ARRAY_SIZE(aif1_slim_cap_mixer)), 5688 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 5689 aif2_slim_cap_mixer, 5690 ARRAY_SIZE(aif2_slim_cap_mixer)), 5691 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 5692 aif3_slim_cap_mixer, 5693 ARRAY_SIZE(aif3_slim_cap_mixer)), 5694 }; 5695 5696 static const struct snd_soc_dapm_route wcd934x_audio_map[] = { 5697 /* RX0-RX7 */ 5698 WCD934X_SLIM_RX_AIF_PATH(0), 5699 WCD934X_SLIM_RX_AIF_PATH(1), 5700 WCD934X_SLIM_RX_AIF_PATH(2), 5701 WCD934X_SLIM_RX_AIF_PATH(3), 5702 WCD934X_SLIM_RX_AIF_PATH(4), 5703 WCD934X_SLIM_RX_AIF_PATH(5), 5704 WCD934X_SLIM_RX_AIF_PATH(6), 5705 WCD934X_SLIM_RX_AIF_PATH(7), 5706 5707 /* RX0 Ear out */ 5708 WCD934X_INTERPOLATOR_PATH(0), 5709 WCD934X_INTERPOLATOR_MIX2(0), 5710 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 5711 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 5712 {"RX INT0 DAC", NULL, "RX_BIAS"}, 5713 {"EAR PA", NULL, "RX INT0 DAC"}, 5714 {"EAR", NULL, "EAR PA"}, 5715 5716 /* RX1 Headphone left */ 5717 WCD934X_INTERPOLATOR_PATH(1), 5718 WCD934X_INTERPOLATOR_MIX2(1), 5719 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"}, 5720 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"}, 5721 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 5722 {"RX INT1 DAC", NULL, "RX_BIAS"}, 5723 {"HPHL PA", NULL, "RX INT1 DAC"}, 5724 {"HPHL", NULL, "HPHL PA"}, 5725 5726 /* RX2 Headphone right */ 5727 WCD934X_INTERPOLATOR_PATH(2), 5728 WCD934X_INTERPOLATOR_MIX2(2), 5729 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"}, 5730 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"}, 5731 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 5732 {"RX INT2 DAC", NULL, "RX_BIAS"}, 5733 {"HPHR PA", NULL, "RX INT2 DAC"}, 5734 {"HPHR", NULL, "HPHR PA"}, 5735 5736 /* RX3 HIFi LineOut1 */ 5737 WCD934X_INTERPOLATOR_PATH(3), 5738 WCD934X_INTERPOLATOR_MIX2(3), 5739 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"}, 5740 {"RX INT3 DAC", NULL, "RX INT3 MIX3"}, 5741 {"RX INT3 DAC", NULL, "RX_BIAS"}, 5742 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 5743 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 5744 5745 /* RX4 HIFi LineOut2 */ 5746 WCD934X_INTERPOLATOR_PATH(4), 5747 WCD934X_INTERPOLATOR_MIX2(4), 5748 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"}, 5749 {"RX INT4 DAC", NULL, "RX INT4 MIX3"}, 5750 {"RX INT4 DAC", NULL, "RX_BIAS"}, 5751 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 5752 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 5753 5754 /* RX7 Speaker Left Out PA */ 5755 WCD934X_INTERPOLATOR_PATH(7), 5756 WCD934X_INTERPOLATOR_MIX2(7), 5757 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"}, 5758 {"RX INT7 CHAIN", NULL, "RX_BIAS"}, 5759 {"RX INT7 CHAIN", NULL, "SBOOST0"}, 5760 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"}, 5761 {"SPK1 OUT", NULL, "RX INT7 CHAIN"}, 5762 5763 /* RX8 Speaker Right Out PA */ 5764 WCD934X_INTERPOLATOR_PATH(8), 5765 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"}, 5766 {"RX INT8 CHAIN", NULL, "RX_BIAS"}, 5767 {"RX INT8 CHAIN", NULL, "SBOOST1"}, 5768 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"}, 5769 {"SPK2 OUT", NULL, "RX INT8 CHAIN"}, 5770 5771 /* Tx */ 5772 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 5773 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 5774 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 5775 5776 WCD934X_SLIM_TX_AIF_PATH(0), 5777 WCD934X_SLIM_TX_AIF_PATH(1), 5778 WCD934X_SLIM_TX_AIF_PATH(2), 5779 WCD934X_SLIM_TX_AIF_PATH(3), 5780 WCD934X_SLIM_TX_AIF_PATH(4), 5781 WCD934X_SLIM_TX_AIF_PATH(5), 5782 WCD934X_SLIM_TX_AIF_PATH(6), 5783 WCD934X_SLIM_TX_AIF_PATH(7), 5784 WCD934X_SLIM_TX_AIF_PATH(8), 5785 5786 WCD934X_ADC_MUX(0), 5787 WCD934X_ADC_MUX(1), 5788 WCD934X_ADC_MUX(2), 5789 WCD934X_ADC_MUX(3), 5790 WCD934X_ADC_MUX(4), 5791 WCD934X_ADC_MUX(5), 5792 WCD934X_ADC_MUX(6), 5793 WCD934X_ADC_MUX(7), 5794 WCD934X_ADC_MUX(8), 5795 5796 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"}, 5797 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"}, 5798 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"}, 5799 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"}, 5800 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"}, 5801 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"}, 5802 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"}, 5803 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"}, 5804 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"}, 5805 5806 {"AMIC4_5 SEL", "AMIC4", "AMIC4"}, 5807 {"AMIC4_5 SEL", "AMIC5", "AMIC5"}, 5808 5809 { "DMIC0", NULL, "DMIC0 Pin" }, 5810 { "DMIC1", NULL, "DMIC1 Pin" }, 5811 { "DMIC2", NULL, "DMIC2 Pin" }, 5812 { "DMIC3", NULL, "DMIC3 Pin" }, 5813 { "DMIC4", NULL, "DMIC4 Pin" }, 5814 { "DMIC5", NULL, "DMIC5 Pin" }, 5815 5816 {"ADC1", NULL, "AMIC1"}, 5817 {"ADC2", NULL, "AMIC2"}, 5818 {"ADC3", NULL, "AMIC3"}, 5819 {"ADC4", NULL, "AMIC4_5 SEL"}, 5820 5821 WCD934X_IIR_INP_MUX(0), 5822 WCD934X_IIR_INP_MUX(1), 5823 5824 {"SRC0", NULL, "IIR0"}, 5825 {"SRC1", NULL, "IIR1"}, 5826 }; 5827 5828 static int wcd934x_codec_set_jack(struct snd_soc_component *comp, 5829 struct snd_soc_jack *jack, void *data) 5830 { 5831 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev); 5832 int ret = 0; 5833 5834 if (!wcd->mbhc) 5835 return -ENOTSUPP; 5836 5837 if (jack && !wcd->mbhc_started) { 5838 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack); 5839 wcd->mbhc_started = true; 5840 } else if (wcd->mbhc_started) { 5841 wcd_mbhc_stop(wcd->mbhc); 5842 wcd->mbhc_started = false; 5843 } 5844 5845 return ret; 5846 } 5847 5848 static const struct snd_soc_component_driver wcd934x_component_drv = { 5849 .probe = wcd934x_comp_probe, 5850 .remove = wcd934x_comp_remove, 5851 .set_sysclk = wcd934x_comp_set_sysclk, 5852 .controls = wcd934x_snd_controls, 5853 .num_controls = ARRAY_SIZE(wcd934x_snd_controls), 5854 .dapm_widgets = wcd934x_dapm_widgets, 5855 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets), 5856 .dapm_routes = wcd934x_audio_map, 5857 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map), 5858 .set_jack = wcd934x_codec_set_jack, 5859 .endianness = 1, 5860 }; 5861 5862 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd) 5863 { 5864 struct device *dev = &wcd->sdev->dev; 5865 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg; 5866 struct device_node *ifc_dev_np; 5867 5868 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5869 if (!ifc_dev_np) { 5870 dev_err(dev, "No Interface device found\n"); 5871 return -EINVAL; 5872 } 5873 5874 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np); 5875 of_node_put(ifc_dev_np); 5876 if (!wcd->sidev) { 5877 dev_err(dev, "Unable to get SLIM Interface device\n"); 5878 return -EINVAL; 5879 } 5880 5881 slim_get_logical_addr(wcd->sidev); 5882 wcd->if_regmap = regmap_init_slimbus(wcd->sidev, 5883 &wcd934x_ifc_regmap_config); 5884 if (IS_ERR(wcd->if_regmap)) 5885 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap), 5886 "Failed to allocate ifc register map\n"); 5887 5888 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate", 5889 &wcd->dmic_sample_rate); 5890 5891 cfg->mbhc_micbias = MIC_BIAS_2; 5892 cfg->anc_micbias = MIC_BIAS_2; 5893 cfg->v_hs_max = WCD_MBHC_HS_V_MAX; 5894 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS; 5895 cfg->micb_mv = wcd->micb2_mv; 5896 cfg->linein_th = 5000; 5897 cfg->hs_thr = 1700; 5898 cfg->hph_thr = 50; 5899 5900 wcd_dt_parse_mbhc_data(dev, cfg); 5901 5902 5903 return 0; 5904 } 5905 5906 static int wcd934x_codec_probe(struct platform_device *pdev) 5907 { 5908 struct device *dev = &pdev->dev; 5909 struct wcd934x_ddata *data = dev_get_drvdata(dev->parent); 5910 struct wcd934x_codec *wcd; 5911 int ret, irq; 5912 5913 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5914 if (!wcd) 5915 return -ENOMEM; 5916 5917 wcd->dev = dev; 5918 wcd->regmap = data->regmap; 5919 wcd->extclk = data->extclk; 5920 wcd->sdev = to_slim_device(data->dev); 5921 mutex_init(&wcd->sysclk_mutex); 5922 mutex_init(&wcd->micb_lock); 5923 5924 ret = wcd934x_codec_parse_data(wcd); 5925 if (ret) { 5926 dev_err(wcd->dev, "Failed to get SLIM IRQ\n"); 5927 return ret; 5928 } 5929 5930 /* set default rate 9P6MHz */ 5931 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG, 5932 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 5933 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 5934 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs)); 5935 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs)); 5936 5937 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS); 5938 if (irq < 0) 5939 return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n"); 5940 5941 ret = devm_request_threaded_irq(dev, irq, NULL, 5942 wcd934x_slim_irq_handler, 5943 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5944 "slim", wcd); 5945 if (ret) 5946 return dev_err_probe(dev, ret, "Failed to request slimbus irq\n"); 5947 5948 wcd934x_register_mclk_output(wcd); 5949 platform_set_drvdata(pdev, wcd); 5950 5951 return devm_snd_soc_register_component(dev, &wcd934x_component_drv, 5952 wcd934x_slim_dais, 5953 ARRAY_SIZE(wcd934x_slim_dais)); 5954 } 5955 5956 static const struct platform_device_id wcd934x_driver_id[] = { 5957 { 5958 .name = "wcd934x-codec", 5959 }, 5960 {}, 5961 }; 5962 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id); 5963 5964 static struct platform_driver wcd934x_codec_driver = { 5965 .probe = &wcd934x_codec_probe, 5966 .id_table = wcd934x_driver_id, 5967 .driver = { 5968 .name = "wcd934x-codec", 5969 } 5970 }; 5971 5972 module_platform_driver(wcd934x_codec_driver); 5973 MODULE_DESCRIPTION("WCD934x codec driver"); 5974 MODULE_LICENSE("GPL v2"); 5975