1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2017-2018, Linaro Limited 4 5 #include <linux/module.h> 6 #include <linux/init.h> 7 #include <linux/platform_device.h> 8 #include <linux/device.h> 9 #include <linux/wait.h> 10 #include <linux/bitops.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/slimbus.h> 16 #include <sound/soc.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <sound/tlv.h> 23 #include <sound/info.h> 24 #include "wcd9335.h" 25 #include "wcd-clsh-v2.h" 26 27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 28 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 29 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 30 /* Fractional Rates */ 31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE) 34 35 /* slave port water mark level 36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 37 */ 38 #define SLAVE_PORT_WATER_MARK_6BYTES 0 39 #define SLAVE_PORT_WATER_MARK_9BYTES 1 40 #define SLAVE_PORT_WATER_MARK_12BYTES 2 41 #define SLAVE_PORT_WATER_MARK_15BYTES 3 42 #define SLAVE_PORT_WATER_MARK_SHIFT 1 43 #define SLAVE_PORT_ENABLE 1 44 #define SLAVE_PORT_DISABLE 0 45 #define WCD9335_SLIM_WATER_MARK_VAL \ 46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 47 (SLAVE_PORT_ENABLE)) 48 49 #define WCD9335_SLIM_NUM_PORT_REG 3 50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 51 52 #define WCD9335_MCLK_CLK_12P288MHZ 12288000 53 #define WCD9335_MCLK_CLK_9P6MHZ 9600000 54 55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000 56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 59 60 #define WCD9335_NUM_INTERPOLATORS 9 61 #define WCD9335_RX_START 16 62 #define WCD9335_SLIM_CH_START 128 63 #define WCD9335_MAX_MICBIAS 4 64 #define WCD9335_MAX_VALID_ADC_MUX 13 65 #define WCD9335_INVALID_ADC_MUX 9 66 67 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 68 #define CF_MIN_3DB_4HZ 0x0 69 #define CF_MIN_3DB_75HZ 0x1 70 #define CF_MIN_3DB_150HZ 0x2 71 #define WCD9335_DMIC_CLK_DIV_2 0x0 72 #define WCD9335_DMIC_CLK_DIV_3 0x1 73 #define WCD9335_DMIC_CLK_DIV_4 0x2 74 #define WCD9335_DMIC_CLK_DIV_6 0x3 75 #define WCD9335_DMIC_CLK_DIV_8 0x4 76 #define WCD9335_DMIC_CLK_DIV_16 0x5 77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 78 #define WCD9335_AMIC_PWR_LEVEL_LP 0 79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 80 #define WCD9335_AMIC_PWR_LEVEL_HP 2 81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60 82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 83 84 #define WCD9335_DEC_PWR_LVL_MASK 0x06 85 #define WCD9335_DEC_PWR_LVL_LP 0x02 86 #define WCD9335_DEC_PWR_LVL_HP 0x04 87 #define WCD9335_DEC_PWR_LVL_DF 0x00 88 89 #define WCD9335_SLIM_RX_CH(p) \ 90 {.port = p + WCD9335_RX_START, .shift = p,} 91 92 #define WCD9335_SLIM_TX_CH(p) \ 93 {.port = p, .shift = p,} 94 95 /* vout step value */ 96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 97 98 #define WCD9335_INTERPOLATOR_PATH(id) \ 99 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 100 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 101 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 107 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 108 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 109 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 115 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 116 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 117 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 123 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 124 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 125 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 126 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 127 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 128 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 129 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 130 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 131 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 132 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 134 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 135 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 136 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 137 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 138 139 #define WCD9335_ADC_MUX_PATH(id) \ 140 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 141 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 142 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 143 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 144 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 145 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 146 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 147 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 148 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 149 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 150 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 151 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 152 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 153 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 154 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 155 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 156 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 157 {"AMIC MUX" #id, "ADC6", "ADC6"} 158 159 enum { 160 WCD9335_RX0 = 0, 161 WCD9335_RX1, 162 WCD9335_RX2, 163 WCD9335_RX3, 164 WCD9335_RX4, 165 WCD9335_RX5, 166 WCD9335_RX6, 167 WCD9335_RX7, 168 WCD9335_RX8, 169 WCD9335_RX9, 170 WCD9335_RX10, 171 WCD9335_RX11, 172 WCD9335_RX12, 173 WCD9335_RX_MAX, 174 }; 175 176 enum { 177 WCD9335_TX0 = 0, 178 WCD9335_TX1, 179 WCD9335_TX2, 180 WCD9335_TX3, 181 WCD9335_TX4, 182 WCD9335_TX5, 183 WCD9335_TX6, 184 WCD9335_TX7, 185 WCD9335_TX8, 186 WCD9335_TX9, 187 WCD9335_TX10, 188 WCD9335_TX11, 189 WCD9335_TX12, 190 WCD9335_TX13, 191 WCD9335_TX14, 192 WCD9335_TX15, 193 WCD9335_TX_MAX, 194 }; 195 196 enum { 197 SIDO_SOURCE_INTERNAL = 0, 198 SIDO_SOURCE_RCO_BG, 199 }; 200 201 enum wcd9335_sido_voltage { 202 SIDO_VOLTAGE_SVS_MV = 950, 203 SIDO_VOLTAGE_NOMINAL_MV = 1100, 204 }; 205 206 enum { 207 AIF1_PB = 0, 208 AIF1_CAP, 209 AIF2_PB, 210 AIF2_CAP, 211 AIF3_PB, 212 AIF3_CAP, 213 AIF4_PB, 214 NUM_CODEC_DAIS, 215 }; 216 217 enum { 218 COMPANDER_1, /* HPH_L */ 219 COMPANDER_2, /* HPH_R */ 220 COMPANDER_3, /* LO1_DIFF */ 221 COMPANDER_4, /* LO2_DIFF */ 222 COMPANDER_5, /* LO3_SE */ 223 COMPANDER_6, /* LO4_SE */ 224 COMPANDER_7, /* SWR SPK CH1 */ 225 COMPANDER_8, /* SWR SPK CH2 */ 226 COMPANDER_MAX, 227 }; 228 229 enum { 230 INTn_2_INP_SEL_ZERO = 0, 231 INTn_2_INP_SEL_RX0, 232 INTn_2_INP_SEL_RX1, 233 INTn_2_INP_SEL_RX2, 234 INTn_2_INP_SEL_RX3, 235 INTn_2_INP_SEL_RX4, 236 INTn_2_INP_SEL_RX5, 237 INTn_2_INP_SEL_RX6, 238 INTn_2_INP_SEL_RX7, 239 INTn_2_INP_SEL_PROXIMITY, 240 }; 241 242 enum { 243 INTn_1_MIX_INP_SEL_ZERO = 0, 244 INTn_1_MIX_INP_SEL_DEC0, 245 INTn_1_MIX_INP_SEL_DEC1, 246 INTn_1_MIX_INP_SEL_IIR0, 247 INTn_1_MIX_INP_SEL_IIR1, 248 INTn_1_MIX_INP_SEL_RX0, 249 INTn_1_MIX_INP_SEL_RX1, 250 INTn_1_MIX_INP_SEL_RX2, 251 INTn_1_MIX_INP_SEL_RX3, 252 INTn_1_MIX_INP_SEL_RX4, 253 INTn_1_MIX_INP_SEL_RX5, 254 INTn_1_MIX_INP_SEL_RX6, 255 INTn_1_MIX_INP_SEL_RX7, 256 257 }; 258 259 enum { 260 INTERP_EAR = 0, 261 INTERP_HPHL, 262 INTERP_HPHR, 263 INTERP_LO1, 264 INTERP_LO2, 265 INTERP_LO3, 266 INTERP_LO4, 267 INTERP_SPKR1, 268 INTERP_SPKR2, 269 }; 270 271 enum wcd_clock_type { 272 WCD_CLK_OFF, 273 WCD_CLK_RCO, 274 WCD_CLK_MCLK, 275 }; 276 277 enum { 278 MIC_BIAS_1 = 1, 279 MIC_BIAS_2, 280 MIC_BIAS_3, 281 MIC_BIAS_4 282 }; 283 284 enum { 285 MICB_PULLUP_ENABLE, 286 MICB_PULLUP_DISABLE, 287 MICB_ENABLE, 288 MICB_DISABLE, 289 }; 290 291 struct wcd9335_slim_ch { 292 u32 ch_num; 293 u16 port; 294 u16 shift; 295 struct list_head list; 296 }; 297 298 struct wcd_slim_codec_dai_data { 299 struct list_head slim_ch_list; 300 struct slim_stream_config sconfig; 301 struct slim_stream_runtime *sruntime; 302 }; 303 304 struct wcd9335_codec { 305 struct device *dev; 306 struct clk *mclk; 307 struct clk *native_clk; 308 u32 mclk_rate; 309 u8 version; 310 311 struct slim_device *slim; 312 struct slim_device *slim_ifc_dev; 313 struct regmap *regmap; 314 struct regmap *if_regmap; 315 struct regmap_irq_chip_data *irq_data; 316 317 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 318 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 319 u32 num_rx_port; 320 u32 num_tx_port; 321 322 int sido_input_src; 323 enum wcd9335_sido_voltage sido_voltage; 324 325 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 326 struct snd_soc_component *component; 327 328 int master_bias_users; 329 int clk_mclk_users; 330 int clk_rco_users; 331 int sido_ccl_cnt; 332 enum wcd_clock_type clk_type; 333 334 struct wcd_clsh_ctrl *clsh_ctrl; 335 u32 hph_mode; 336 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 337 338 int comp_enabled[COMPANDER_MAX]; 339 340 int intr1; 341 int reset_gpio; 342 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY]; 343 344 unsigned int rx_port_value[WCD9335_RX_MAX]; 345 unsigned int tx_port_value[WCD9335_TX_MAX]; 346 int hph_l_gain; 347 int hph_r_gain; 348 u32 rx_bias_count; 349 350 /*TX*/ 351 int micb_ref[WCD9335_MAX_MICBIAS]; 352 int pullup_ref[WCD9335_MAX_MICBIAS]; 353 354 int dmic_0_1_clk_cnt; 355 int dmic_2_3_clk_cnt; 356 int dmic_4_5_clk_cnt; 357 int dmic_sample_rate; 358 int mad_dmic_sample_rate; 359 360 int native_clk_users; 361 }; 362 363 struct wcd9335_irq { 364 int irq; 365 irqreturn_t (*handler)(int irq, void *data); 366 char *name; 367 }; 368 369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 370 WCD9335_SLIM_TX_CH(0), 371 WCD9335_SLIM_TX_CH(1), 372 WCD9335_SLIM_TX_CH(2), 373 WCD9335_SLIM_TX_CH(3), 374 WCD9335_SLIM_TX_CH(4), 375 WCD9335_SLIM_TX_CH(5), 376 WCD9335_SLIM_TX_CH(6), 377 WCD9335_SLIM_TX_CH(7), 378 WCD9335_SLIM_TX_CH(8), 379 WCD9335_SLIM_TX_CH(9), 380 WCD9335_SLIM_TX_CH(10), 381 WCD9335_SLIM_TX_CH(11), 382 WCD9335_SLIM_TX_CH(12), 383 WCD9335_SLIM_TX_CH(13), 384 WCD9335_SLIM_TX_CH(14), 385 WCD9335_SLIM_TX_CH(15), 386 }; 387 388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 389 WCD9335_SLIM_RX_CH(0), /* 16 */ 390 WCD9335_SLIM_RX_CH(1), /* 17 */ 391 WCD9335_SLIM_RX_CH(2), 392 WCD9335_SLIM_RX_CH(3), 393 WCD9335_SLIM_RX_CH(4), 394 WCD9335_SLIM_RX_CH(5), 395 WCD9335_SLIM_RX_CH(6), 396 WCD9335_SLIM_RX_CH(7), 397 WCD9335_SLIM_RX_CH(8), 398 WCD9335_SLIM_RX_CH(9), 399 WCD9335_SLIM_RX_CH(10), 400 WCD9335_SLIM_RX_CH(11), 401 WCD9335_SLIM_RX_CH(12), 402 }; 403 404 struct interp_sample_rate { 405 int rate; 406 int rate_val; 407 }; 408 409 static struct interp_sample_rate int_mix_rate_val[] = { 410 {48000, 0x4}, /* 48K */ 411 {96000, 0x5}, /* 96K */ 412 {192000, 0x6}, /* 192K */ 413 }; 414 415 static struct interp_sample_rate int_prim_rate_val[] = { 416 {8000, 0x0}, /* 8K */ 417 {16000, 0x1}, /* 16K */ 418 {24000, -EINVAL},/* 24K */ 419 {32000, 0x3}, /* 32K */ 420 {48000, 0x4}, /* 48K */ 421 {96000, 0x5}, /* 96K */ 422 {192000, 0x6}, /* 192K */ 423 {384000, 0x7}, /* 384K */ 424 {44100, 0x8}, /* 44.1K */ 425 }; 426 427 struct wcd9335_reg_mask_val { 428 u16 reg; 429 u8 mask; 430 u8 val; 431 }; 432 433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 434 /* Rbuckfly/R_EAR(32) */ 435 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 436 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 437 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 438 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 439 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 440 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 441 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 442 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 443 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 444 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 445 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 446 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 447 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 448 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 449 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 454 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 455 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 456 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 466 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 467 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 468 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 469 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 470 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 471 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 472 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 473 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 474 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 475 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 476 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 477 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 478 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 479 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 480 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 481 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 482 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 483 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 484 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 485 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 486 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 487 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 488 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 489 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 490 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 491 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 492 }; 493 494 /* Cutoff frequency for high pass filter */ 495 static const char * const cf_text[] = { 496 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 497 }; 498 499 static const char * const rx_cf_text[] = { 500 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 501 "CF_NEG_3DB_0P48HZ" 502 }; 503 504 static const char * const rx_int0_7_mix_mux_text[] = { 505 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 506 "RX6", "RX7", "PROXIMITY" 507 }; 508 509 static const char * const rx_int_mix_mux_text[] = { 510 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 511 "RX6", "RX7" 512 }; 513 514 static const char * const rx_prim_mix_text[] = { 515 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 516 "RX3", "RX4", "RX5", "RX6", "RX7" 517 }; 518 519 static const char * const rx_int_dem_inp_mux_text[] = { 520 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 521 }; 522 523 static const char * const rx_int0_interp_mux_text[] = { 524 "ZERO", "RX INT0 MIX2", 525 }; 526 527 static const char * const rx_int1_interp_mux_text[] = { 528 "ZERO", "RX INT1 MIX2", 529 }; 530 531 static const char * const rx_int2_interp_mux_text[] = { 532 "ZERO", "RX INT2 MIX2", 533 }; 534 535 static const char * const rx_int3_interp_mux_text[] = { 536 "ZERO", "RX INT3 MIX2", 537 }; 538 539 static const char * const rx_int4_interp_mux_text[] = { 540 "ZERO", "RX INT4 MIX2", 541 }; 542 543 static const char * const rx_int5_interp_mux_text[] = { 544 "ZERO", "RX INT5 MIX2", 545 }; 546 547 static const char * const rx_int6_interp_mux_text[] = { 548 "ZERO", "RX INT6 MIX2", 549 }; 550 551 static const char * const rx_int7_interp_mux_text[] = { 552 "ZERO", "RX INT7 MIX2", 553 }; 554 555 static const char * const rx_int8_interp_mux_text[] = { 556 "ZERO", "RX INT8 SEC MIX" 557 }; 558 559 static const char * const rx_hph_mode_mux_text[] = { 560 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 561 "Class-H Hi-Fi Low Power" 562 }; 563 564 static const char *const slim_rx_mux_text[] = { 565 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 566 }; 567 568 static const char * const adc_mux_text[] = { 569 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 570 }; 571 572 static const char * const dmic_mux_text[] = { 573 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 574 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 575 }; 576 577 static const char * const dmic_mux_alt_text[] = { 578 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 579 }; 580 581 static const char * const amic_mux_text[] = { 582 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 583 }; 584 585 static const char * const sb_tx0_mux_text[] = { 586 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 587 }; 588 589 static const char * const sb_tx1_mux_text[] = { 590 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 591 }; 592 593 static const char * const sb_tx2_mux_text[] = { 594 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 595 }; 596 597 static const char * const sb_tx3_mux_text[] = { 598 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 599 }; 600 601 static const char * const sb_tx4_mux_text[] = { 602 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 603 }; 604 605 static const char * const sb_tx5_mux_text[] = { 606 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 607 }; 608 609 static const char * const sb_tx6_mux_text[] = { 610 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 611 }; 612 613 static const char * const sb_tx7_mux_text[] = { 614 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 615 }; 616 617 static const char * const sb_tx8_mux_text[] = { 618 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 619 }; 620 621 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 625 626 static const struct soc_enum cf_dec0_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 628 629 static const struct soc_enum cf_dec1_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 631 632 static const struct soc_enum cf_dec2_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 634 635 static const struct soc_enum cf_dec3_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 637 638 static const struct soc_enum cf_dec4_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 640 641 static const struct soc_enum cf_dec5_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 643 644 static const struct soc_enum cf_dec6_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 646 647 static const struct soc_enum cf_dec7_enum = 648 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 649 650 static const struct soc_enum cf_dec8_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 652 653 static const struct soc_enum cf_int0_1_enum = 654 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 655 656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 657 rx_cf_text); 658 659 static const struct soc_enum cf_int1_1_enum = 660 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 661 662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 663 rx_cf_text); 664 665 static const struct soc_enum cf_int2_1_enum = 666 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 667 668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 669 rx_cf_text); 670 671 static const struct soc_enum cf_int3_1_enum = 672 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 673 674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 675 rx_cf_text); 676 677 static const struct soc_enum cf_int4_1_enum = 678 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 679 680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 681 rx_cf_text); 682 683 static const struct soc_enum cf_int5_1_enum = 684 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 685 686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 687 rx_cf_text); 688 689 static const struct soc_enum cf_int6_1_enum = 690 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 691 692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 693 rx_cf_text); 694 695 static const struct soc_enum cf_int7_1_enum = 696 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 697 698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 699 rx_cf_text); 700 701 static const struct soc_enum cf_int8_1_enum = 702 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 703 704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 705 rx_cf_text); 706 707 static const struct soc_enum rx_hph_mode_mux_enum = 708 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 709 rx_hph_mode_mux_text); 710 711 static const struct soc_enum slim_rx_mux_enum = 712 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 713 714 static const struct soc_enum rx_int0_2_mux_chain_enum = 715 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 716 rx_int0_7_mix_mux_text); 717 718 static const struct soc_enum rx_int1_2_mux_chain_enum = 719 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 720 rx_int_mix_mux_text); 721 722 static const struct soc_enum rx_int2_2_mux_chain_enum = 723 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 724 rx_int_mix_mux_text); 725 726 static const struct soc_enum rx_int3_2_mux_chain_enum = 727 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 728 rx_int_mix_mux_text); 729 730 static const struct soc_enum rx_int4_2_mux_chain_enum = 731 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 732 rx_int_mix_mux_text); 733 734 static const struct soc_enum rx_int5_2_mux_chain_enum = 735 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 736 rx_int_mix_mux_text); 737 738 static const struct soc_enum rx_int6_2_mux_chain_enum = 739 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 740 rx_int_mix_mux_text); 741 742 static const struct soc_enum rx_int7_2_mux_chain_enum = 743 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 744 rx_int0_7_mix_mux_text); 745 746 static const struct soc_enum rx_int8_2_mux_chain_enum = 747 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 748 rx_int_mix_mux_text); 749 750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 751 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 752 rx_prim_mix_text); 753 754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 755 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 756 rx_prim_mix_text); 757 758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 759 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 760 rx_prim_mix_text); 761 762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 763 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 764 rx_prim_mix_text); 765 766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 767 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 768 rx_prim_mix_text); 769 770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 771 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 772 rx_prim_mix_text); 773 774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 775 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 776 rx_prim_mix_text); 777 778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 779 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 780 rx_prim_mix_text); 781 782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 783 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 784 rx_prim_mix_text); 785 786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 787 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 788 rx_prim_mix_text); 789 790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 791 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 792 rx_prim_mix_text); 793 794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 795 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 796 rx_prim_mix_text); 797 798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 799 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 800 rx_prim_mix_text); 801 802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 803 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 804 rx_prim_mix_text); 805 806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 807 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 808 rx_prim_mix_text); 809 810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 811 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 812 rx_prim_mix_text); 813 814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 815 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 816 rx_prim_mix_text); 817 818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 819 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 820 rx_prim_mix_text); 821 822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 823 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 824 rx_prim_mix_text); 825 826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 827 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 828 rx_prim_mix_text); 829 830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 831 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 832 rx_prim_mix_text); 833 834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 835 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 836 rx_prim_mix_text); 837 838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 839 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 840 rx_prim_mix_text); 841 842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 843 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 844 rx_prim_mix_text); 845 846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 847 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 848 rx_prim_mix_text); 849 850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 851 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 852 rx_prim_mix_text); 853 854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 856 rx_prim_mix_text); 857 858 static const struct soc_enum rx_int0_dem_inp_mux_enum = 859 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 860 ARRAY_SIZE(rx_int_dem_inp_mux_text), 861 rx_int_dem_inp_mux_text); 862 863 static const struct soc_enum rx_int1_dem_inp_mux_enum = 864 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 865 ARRAY_SIZE(rx_int_dem_inp_mux_text), 866 rx_int_dem_inp_mux_text); 867 868 static const struct soc_enum rx_int2_dem_inp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 870 ARRAY_SIZE(rx_int_dem_inp_mux_text), 871 rx_int_dem_inp_mux_text); 872 873 static const struct soc_enum rx_int0_interp_mux_enum = 874 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 875 rx_int0_interp_mux_text); 876 877 static const struct soc_enum rx_int1_interp_mux_enum = 878 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 879 rx_int1_interp_mux_text); 880 881 static const struct soc_enum rx_int2_interp_mux_enum = 882 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 883 rx_int2_interp_mux_text); 884 885 static const struct soc_enum rx_int3_interp_mux_enum = 886 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 887 rx_int3_interp_mux_text); 888 889 static const struct soc_enum rx_int4_interp_mux_enum = 890 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 891 rx_int4_interp_mux_text); 892 893 static const struct soc_enum rx_int5_interp_mux_enum = 894 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 895 rx_int5_interp_mux_text); 896 897 static const struct soc_enum rx_int6_interp_mux_enum = 898 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 899 rx_int6_interp_mux_text); 900 901 static const struct soc_enum rx_int7_interp_mux_enum = 902 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 903 rx_int7_interp_mux_text); 904 905 static const struct soc_enum rx_int8_interp_mux_enum = 906 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 907 rx_int8_interp_mux_text); 908 909 static const struct soc_enum tx_adc_mux0_chain_enum = 910 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 911 adc_mux_text); 912 913 static const struct soc_enum tx_adc_mux1_chain_enum = 914 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 915 adc_mux_text); 916 917 static const struct soc_enum tx_adc_mux2_chain_enum = 918 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 919 adc_mux_text); 920 921 static const struct soc_enum tx_adc_mux3_chain_enum = 922 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 923 adc_mux_text); 924 925 static const struct soc_enum tx_adc_mux4_chain_enum = 926 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 927 adc_mux_text); 928 929 static const struct soc_enum tx_adc_mux5_chain_enum = 930 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 931 adc_mux_text); 932 933 static const struct soc_enum tx_adc_mux6_chain_enum = 934 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 935 adc_mux_text); 936 937 static const struct soc_enum tx_adc_mux7_chain_enum = 938 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 939 adc_mux_text); 940 941 static const struct soc_enum tx_adc_mux8_chain_enum = 942 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 943 adc_mux_text); 944 945 static const struct soc_enum tx_dmic_mux0_enum = 946 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 947 dmic_mux_text); 948 949 static const struct soc_enum tx_dmic_mux1_enum = 950 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 951 dmic_mux_text); 952 953 static const struct soc_enum tx_dmic_mux2_enum = 954 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 955 dmic_mux_text); 956 957 static const struct soc_enum tx_dmic_mux3_enum = 958 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 959 dmic_mux_text); 960 961 static const struct soc_enum tx_dmic_mux4_enum = 962 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 963 dmic_mux_alt_text); 964 965 static const struct soc_enum tx_dmic_mux5_enum = 966 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 967 dmic_mux_alt_text); 968 969 static const struct soc_enum tx_dmic_mux6_enum = 970 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 971 dmic_mux_alt_text); 972 973 static const struct soc_enum tx_dmic_mux7_enum = 974 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 975 dmic_mux_alt_text); 976 977 static const struct soc_enum tx_dmic_mux8_enum = 978 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 979 dmic_mux_alt_text); 980 981 static const struct soc_enum tx_amic_mux0_enum = 982 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 983 amic_mux_text); 984 985 static const struct soc_enum tx_amic_mux1_enum = 986 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 987 amic_mux_text); 988 989 static const struct soc_enum tx_amic_mux2_enum = 990 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 991 amic_mux_text); 992 993 static const struct soc_enum tx_amic_mux3_enum = 994 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 995 amic_mux_text); 996 997 static const struct soc_enum tx_amic_mux4_enum = 998 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 999 amic_mux_text); 1000 1001 static const struct soc_enum tx_amic_mux5_enum = 1002 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 1003 amic_mux_text); 1004 1005 static const struct soc_enum tx_amic_mux6_enum = 1006 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 1007 amic_mux_text); 1008 1009 static const struct soc_enum tx_amic_mux7_enum = 1010 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1011 amic_mux_text); 1012 1013 static const struct soc_enum tx_amic_mux8_enum = 1014 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1015 amic_mux_text); 1016 1017 static const struct soc_enum sb_tx0_mux_enum = 1018 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1019 sb_tx0_mux_text); 1020 1021 static const struct soc_enum sb_tx1_mux_enum = 1022 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1023 sb_tx1_mux_text); 1024 1025 static const struct soc_enum sb_tx2_mux_enum = 1026 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1027 sb_tx2_mux_text); 1028 1029 static const struct soc_enum sb_tx3_mux_enum = 1030 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1031 sb_tx3_mux_text); 1032 1033 static const struct soc_enum sb_tx4_mux_enum = 1034 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1035 sb_tx4_mux_text); 1036 1037 static const struct soc_enum sb_tx5_mux_enum = 1038 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1039 sb_tx5_mux_text); 1040 1041 static const struct soc_enum sb_tx6_mux_enum = 1042 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1043 sb_tx6_mux_text); 1044 1045 static const struct soc_enum sb_tx7_mux_enum = 1046 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1047 sb_tx7_mux_text); 1048 1049 static const struct soc_enum sb_tx8_mux_enum = 1050 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1051 sb_tx8_mux_text); 1052 1053 static const struct snd_kcontrol_new rx_int0_2_mux = 1054 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1055 1056 static const struct snd_kcontrol_new rx_int1_2_mux = 1057 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1058 1059 static const struct snd_kcontrol_new rx_int2_2_mux = 1060 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1061 1062 static const struct snd_kcontrol_new rx_int3_2_mux = 1063 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1064 1065 static const struct snd_kcontrol_new rx_int4_2_mux = 1066 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1067 1068 static const struct snd_kcontrol_new rx_int5_2_mux = 1069 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1070 1071 static const struct snd_kcontrol_new rx_int6_2_mux = 1072 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1073 1074 static const struct snd_kcontrol_new rx_int7_2_mux = 1075 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1076 1077 static const struct snd_kcontrol_new rx_int8_2_mux = 1078 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1079 1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1082 1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1085 1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1088 1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1091 1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1094 1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1097 1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1100 1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1103 1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1106 1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1109 1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1112 1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1115 1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1118 1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1121 1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1124 1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1127 1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1130 1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1133 1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1136 1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1139 1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1142 1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1145 1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1148 1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1151 1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1153 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1154 1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1156 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1157 1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1159 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1160 1161 static const struct snd_kcontrol_new rx_int0_interp_mux = 1162 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1163 1164 static const struct snd_kcontrol_new rx_int1_interp_mux = 1165 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1166 1167 static const struct snd_kcontrol_new rx_int2_interp_mux = 1168 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1169 1170 static const struct snd_kcontrol_new rx_int3_interp_mux = 1171 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1172 1173 static const struct snd_kcontrol_new rx_int4_interp_mux = 1174 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1175 1176 static const struct snd_kcontrol_new rx_int5_interp_mux = 1177 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1178 1179 static const struct snd_kcontrol_new rx_int6_interp_mux = 1180 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1181 1182 static const struct snd_kcontrol_new rx_int7_interp_mux = 1183 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1184 1185 static const struct snd_kcontrol_new rx_int8_interp_mux = 1186 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1187 1188 static const struct snd_kcontrol_new tx_dmic_mux0 = 1189 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1190 1191 static const struct snd_kcontrol_new tx_dmic_mux1 = 1192 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1193 1194 static const struct snd_kcontrol_new tx_dmic_mux2 = 1195 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1196 1197 static const struct snd_kcontrol_new tx_dmic_mux3 = 1198 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1199 1200 static const struct snd_kcontrol_new tx_dmic_mux4 = 1201 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1202 1203 static const struct snd_kcontrol_new tx_dmic_mux5 = 1204 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1205 1206 static const struct snd_kcontrol_new tx_dmic_mux6 = 1207 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1208 1209 static const struct snd_kcontrol_new tx_dmic_mux7 = 1210 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1211 1212 static const struct snd_kcontrol_new tx_dmic_mux8 = 1213 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1214 1215 static const struct snd_kcontrol_new tx_amic_mux0 = 1216 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1217 1218 static const struct snd_kcontrol_new tx_amic_mux1 = 1219 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1220 1221 static const struct snd_kcontrol_new tx_amic_mux2 = 1222 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1223 1224 static const struct snd_kcontrol_new tx_amic_mux3 = 1225 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1226 1227 static const struct snd_kcontrol_new tx_amic_mux4 = 1228 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1229 1230 static const struct snd_kcontrol_new tx_amic_mux5 = 1231 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1232 1233 static const struct snd_kcontrol_new tx_amic_mux6 = 1234 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1235 1236 static const struct snd_kcontrol_new tx_amic_mux7 = 1237 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1238 1239 static const struct snd_kcontrol_new tx_amic_mux8 = 1240 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1241 1242 static const struct snd_kcontrol_new sb_tx0_mux = 1243 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1244 1245 static const struct snd_kcontrol_new sb_tx1_mux = 1246 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1247 1248 static const struct snd_kcontrol_new sb_tx2_mux = 1249 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1250 1251 static const struct snd_kcontrol_new sb_tx3_mux = 1252 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1253 1254 static const struct snd_kcontrol_new sb_tx4_mux = 1255 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1256 1257 static const struct snd_kcontrol_new sb_tx5_mux = 1258 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1259 1260 static const struct snd_kcontrol_new sb_tx6_mux = 1261 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1262 1263 static const struct snd_kcontrol_new sb_tx7_mux = 1264 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1265 1266 static const struct snd_kcontrol_new sb_tx8_mux = 1267 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1268 1269 static int slim_rx_mux_get(struct snd_kcontrol *kc, 1270 struct snd_ctl_elem_value *ucontrol) 1271 { 1272 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1273 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1274 u32 port_id = w->shift; 1275 1276 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id]; 1277 1278 return 0; 1279 } 1280 1281 static int slim_rx_mux_put(struct snd_kcontrol *kc, 1282 struct snd_ctl_elem_value *ucontrol) 1283 { 1284 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1285 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1286 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1287 struct snd_soc_dapm_update *update = NULL; 1288 u32 port_id = w->shift; 1289 1290 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 1291 return 0; 1292 1293 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 1294 1295 /* Remove channel from any list it's in before adding it to a new one */ 1296 list_del_init(&wcd->rx_chs[port_id].list); 1297 1298 switch (wcd->rx_port_value[port_id]) { 1299 case 0: 1300 /* Channel already removed from lists. Nothing to do here */ 1301 break; 1302 case 1: 1303 list_add_tail(&wcd->rx_chs[port_id].list, 1304 &wcd->dai[AIF1_PB].slim_ch_list); 1305 break; 1306 case 2: 1307 list_add_tail(&wcd->rx_chs[port_id].list, 1308 &wcd->dai[AIF2_PB].slim_ch_list); 1309 break; 1310 case 3: 1311 list_add_tail(&wcd->rx_chs[port_id].list, 1312 &wcd->dai[AIF3_PB].slim_ch_list); 1313 break; 1314 case 4: 1315 list_add_tail(&wcd->rx_chs[port_id].list, 1316 &wcd->dai[AIF4_PB].slim_ch_list); 1317 break; 1318 default: 1319 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]); 1320 goto err; 1321 } 1322 1323 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 1324 e, update); 1325 1326 return 0; 1327 err: 1328 return -EINVAL; 1329 } 1330 1331 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1332 struct snd_ctl_elem_value *ucontrol) 1333 { 1334 1335 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1336 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1337 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1338 struct soc_mixer_control *mixer = 1339 (struct soc_mixer_control *)kc->private_value; 1340 int dai_id = widget->shift; 1341 int port_id = mixer->shift; 1342 1343 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id; 1344 1345 return 0; 1346 } 1347 1348 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1349 struct snd_ctl_elem_value *ucontrol) 1350 { 1351 1352 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1353 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev); 1354 struct snd_soc_dapm_update *update = NULL; 1355 struct soc_mixer_control *mixer = 1356 (struct soc_mixer_control *)kc->private_value; 1357 int enable = ucontrol->value.integer.value[0]; 1358 int dai_id = widget->shift; 1359 int port_id = mixer->shift; 1360 1361 switch (dai_id) { 1362 case AIF1_CAP: 1363 case AIF2_CAP: 1364 case AIF3_CAP: 1365 /* only add to the list if value not set */ 1366 if (enable && wcd->tx_port_value[port_id] != dai_id) { 1367 wcd->tx_port_value[port_id] = dai_id; 1368 list_add_tail(&wcd->tx_chs[port_id].list, 1369 &wcd->dai[dai_id].slim_ch_list); 1370 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) { 1371 wcd->tx_port_value[port_id] = -1; 1372 list_del_init(&wcd->tx_chs[port_id].list); 1373 } 1374 break; 1375 default: 1376 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1377 return -EINVAL; 1378 } 1379 1380 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1381 1382 return 0; 1383 } 1384 1385 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1386 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1387 slim_rx_mux_get, slim_rx_mux_put), 1388 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1389 slim_rx_mux_get, slim_rx_mux_put), 1390 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1391 slim_rx_mux_get, slim_rx_mux_put), 1392 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1393 slim_rx_mux_get, slim_rx_mux_put), 1394 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1395 slim_rx_mux_get, slim_rx_mux_put), 1396 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1397 slim_rx_mux_get, slim_rx_mux_put), 1398 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1399 slim_rx_mux_get, slim_rx_mux_put), 1400 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1401 slim_rx_mux_get, slim_rx_mux_put), 1402 }; 1403 1404 static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1405 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1406 slim_tx_mixer_get, slim_tx_mixer_put), 1407 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1408 slim_tx_mixer_get, slim_tx_mixer_put), 1409 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1410 slim_tx_mixer_get, slim_tx_mixer_put), 1411 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1412 slim_tx_mixer_get, slim_tx_mixer_put), 1413 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1414 slim_tx_mixer_get, slim_tx_mixer_put), 1415 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1416 slim_tx_mixer_get, slim_tx_mixer_put), 1417 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1418 slim_tx_mixer_get, slim_tx_mixer_put), 1419 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1420 slim_tx_mixer_get, slim_tx_mixer_put), 1421 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1422 slim_tx_mixer_get, slim_tx_mixer_put), 1423 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1424 slim_tx_mixer_get, slim_tx_mixer_put), 1425 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1426 slim_tx_mixer_get, slim_tx_mixer_put), 1427 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1428 slim_tx_mixer_get, slim_tx_mixer_put), 1429 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1430 slim_tx_mixer_get, slim_tx_mixer_put), 1431 }; 1432 1433 static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1434 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1435 slim_tx_mixer_get, slim_tx_mixer_put), 1436 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1437 slim_tx_mixer_get, slim_tx_mixer_put), 1438 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1439 slim_tx_mixer_get, slim_tx_mixer_put), 1440 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1441 slim_tx_mixer_get, slim_tx_mixer_put), 1442 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1443 slim_tx_mixer_get, slim_tx_mixer_put), 1444 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1445 slim_tx_mixer_get, slim_tx_mixer_put), 1446 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1447 slim_tx_mixer_get, slim_tx_mixer_put), 1448 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1449 slim_tx_mixer_get, slim_tx_mixer_put), 1450 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1451 slim_tx_mixer_get, slim_tx_mixer_put), 1452 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1453 slim_tx_mixer_get, slim_tx_mixer_put), 1454 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1455 slim_tx_mixer_get, slim_tx_mixer_put), 1456 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1457 slim_tx_mixer_get, slim_tx_mixer_put), 1458 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1459 slim_tx_mixer_get, slim_tx_mixer_put), 1460 }; 1461 1462 static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1463 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1464 slim_tx_mixer_get, slim_tx_mixer_put), 1465 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1466 slim_tx_mixer_get, slim_tx_mixer_put), 1467 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1468 slim_tx_mixer_get, slim_tx_mixer_put), 1469 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1470 slim_tx_mixer_get, slim_tx_mixer_put), 1471 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1472 slim_tx_mixer_get, slim_tx_mixer_put), 1473 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1474 slim_tx_mixer_get, slim_tx_mixer_put), 1475 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1476 slim_tx_mixer_get, slim_tx_mixer_put), 1477 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1478 slim_tx_mixer_get, slim_tx_mixer_put), 1479 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1480 slim_tx_mixer_get, slim_tx_mixer_put), 1481 }; 1482 1483 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1484 struct snd_ctl_elem_value *ucontrol) 1485 { 1486 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1487 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1488 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1489 unsigned int val, reg, sel; 1490 1491 val = ucontrol->value.enumerated.item[0]; 1492 1493 switch (e->reg) { 1494 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1495 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1496 break; 1497 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1498 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1499 break; 1500 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1501 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1502 break; 1503 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1504 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1505 break; 1506 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1507 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1508 break; 1509 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1510 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1511 break; 1512 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1513 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1514 break; 1515 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1516 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1517 break; 1518 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1519 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1520 break; 1521 default: 1522 return -EINVAL; 1523 } 1524 1525 /* AMIC: 0, DMIC: 1 */ 1526 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1527 snd_soc_component_update_bits(component, reg, 1528 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1529 sel); 1530 1531 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1532 } 1533 1534 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1535 struct snd_ctl_elem_value *ucontrol) 1536 { 1537 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1538 struct snd_soc_component *component; 1539 int reg, val; 1540 1541 component = snd_soc_dapm_kcontrol_component(kc); 1542 val = ucontrol->value.enumerated.item[0]; 1543 1544 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1545 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1546 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1547 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1548 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1549 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1550 else 1551 return -EINVAL; 1552 1553 /* Set Look Ahead Delay */ 1554 snd_soc_component_update_bits(component, reg, 1555 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1556 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1557 /* Set DEM INP Select */ 1558 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1559 } 1560 1561 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1562 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1563 snd_soc_dapm_get_enum_double, 1564 wcd9335_int_dem_inp_mux_put); 1565 1566 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1567 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1568 snd_soc_dapm_get_enum_double, 1569 wcd9335_int_dem_inp_mux_put); 1570 1571 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1572 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1573 snd_soc_dapm_get_enum_double, 1574 wcd9335_int_dem_inp_mux_put); 1575 1576 static const struct snd_kcontrol_new tx_adc_mux0 = 1577 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1578 snd_soc_dapm_get_enum_double, 1579 wcd9335_put_dec_enum); 1580 1581 static const struct snd_kcontrol_new tx_adc_mux1 = 1582 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1583 snd_soc_dapm_get_enum_double, 1584 wcd9335_put_dec_enum); 1585 1586 static const struct snd_kcontrol_new tx_adc_mux2 = 1587 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1588 snd_soc_dapm_get_enum_double, 1589 wcd9335_put_dec_enum); 1590 1591 static const struct snd_kcontrol_new tx_adc_mux3 = 1592 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1593 snd_soc_dapm_get_enum_double, 1594 wcd9335_put_dec_enum); 1595 1596 static const struct snd_kcontrol_new tx_adc_mux4 = 1597 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1598 snd_soc_dapm_get_enum_double, 1599 wcd9335_put_dec_enum); 1600 1601 static const struct snd_kcontrol_new tx_adc_mux5 = 1602 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1603 snd_soc_dapm_get_enum_double, 1604 wcd9335_put_dec_enum); 1605 1606 static const struct snd_kcontrol_new tx_adc_mux6 = 1607 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1608 snd_soc_dapm_get_enum_double, 1609 wcd9335_put_dec_enum); 1610 1611 static const struct snd_kcontrol_new tx_adc_mux7 = 1612 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1613 snd_soc_dapm_get_enum_double, 1614 wcd9335_put_dec_enum); 1615 1616 static const struct snd_kcontrol_new tx_adc_mux8 = 1617 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1618 snd_soc_dapm_get_enum_double, 1619 wcd9335_put_dec_enum); 1620 1621 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1622 int rate_val, 1623 u32 rate) 1624 { 1625 struct snd_soc_component *component = dai->component; 1626 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1627 struct wcd9335_slim_ch *ch; 1628 int val, j; 1629 1630 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1631 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1632 val = snd_soc_component_read(component, 1633 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1634 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1635 1636 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1637 snd_soc_component_update_bits(component, 1638 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1639 WCD9335_CDC_MIX_PCM_RATE_MASK, 1640 rate_val); 1641 } 1642 } 1643 1644 return 0; 1645 } 1646 1647 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1648 u8 rate_val, 1649 u32 rate) 1650 { 1651 struct snd_soc_component *comp = dai->component; 1652 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1653 struct wcd9335_slim_ch *ch; 1654 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1655 int inp, j; 1656 1657 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1658 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1659 /* 1660 * Loop through all interpolator MUX inputs and find out 1661 * to which interpolator input, the slim rx port 1662 * is connected 1663 */ 1664 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1665 cfg0 = snd_soc_component_read(comp, 1666 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1667 cfg1 = snd_soc_component_read(comp, 1668 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1669 1670 inp0_sel = cfg0 & 1671 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1672 inp1_sel = (cfg0 >> 4) & 1673 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1674 inp2_sel = (cfg1 >> 4) & 1675 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1676 1677 if ((inp0_sel == inp) || (inp1_sel == inp) || 1678 (inp2_sel == inp)) { 1679 /* rate is in Hz */ 1680 if ((j == 0) && (rate == 44100)) 1681 dev_info(wcd->dev, 1682 "Cannot set 44.1KHz on INT0\n"); 1683 else 1684 snd_soc_component_update_bits(comp, 1685 WCD9335_CDC_RX_PATH_CTL(j), 1686 WCD9335_CDC_MIX_PCM_RATE_MASK, 1687 rate_val); 1688 } 1689 } 1690 } 1691 1692 return 0; 1693 } 1694 1695 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1696 { 1697 int i; 1698 1699 /* set mixing path rate */ 1700 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1701 if (rate == int_mix_rate_val[i].rate) { 1702 wcd9335_set_mix_interpolator_rate(dai, 1703 int_mix_rate_val[i].rate_val, rate); 1704 break; 1705 } 1706 } 1707 1708 /* set primary path sample rate */ 1709 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1710 if (rate == int_prim_rate_val[i].rate) { 1711 wcd9335_set_prim_interpolator_rate(dai, 1712 int_prim_rate_val[i].rate_val, rate); 1713 break; 1714 } 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1721 struct wcd_slim_codec_dai_data *dai_data, 1722 int direction) 1723 { 1724 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1725 struct slim_stream_config *cfg = &dai_data->sconfig; 1726 struct wcd9335_slim_ch *ch; 1727 u16 payload = 0; 1728 int ret, i; 1729 1730 cfg->ch_count = 0; 1731 cfg->direction = direction; 1732 cfg->port_mask = 0; 1733 1734 /* Configure slave interface device */ 1735 list_for_each_entry(ch, slim_ch_list, list) { 1736 cfg->ch_count++; 1737 payload |= 1 << ch->shift; 1738 cfg->port_mask |= BIT(ch->port); 1739 } 1740 1741 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1742 if (!cfg->chs) 1743 return -ENOMEM; 1744 1745 i = 0; 1746 list_for_each_entry(ch, slim_ch_list, list) { 1747 cfg->chs[i++] = ch->ch_num; 1748 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1749 /* write to interface device */ 1750 ret = regmap_write(wcd->if_regmap, 1751 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1752 payload); 1753 1754 if (ret < 0) 1755 goto err; 1756 1757 /* configure the slave port for water mark and enable*/ 1758 ret = regmap_write(wcd->if_regmap, 1759 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1760 WCD9335_SLIM_WATER_MARK_VAL); 1761 if (ret < 0) 1762 goto err; 1763 } else { 1764 ret = regmap_write(wcd->if_regmap, 1765 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1766 payload & 0x00FF); 1767 if (ret < 0) 1768 goto err; 1769 1770 /* ports 8,9 */ 1771 ret = regmap_write(wcd->if_regmap, 1772 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1773 (payload & 0xFF00)>>8); 1774 if (ret < 0) 1775 goto err; 1776 1777 /* configure the slave port for water mark and enable*/ 1778 ret = regmap_write(wcd->if_regmap, 1779 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1780 WCD9335_SLIM_WATER_MARK_VAL); 1781 1782 if (ret < 0) 1783 goto err; 1784 } 1785 } 1786 1787 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1788 1789 return 0; 1790 1791 err: 1792 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1793 kfree(cfg->chs); 1794 cfg->chs = NULL; 1795 1796 return ret; 1797 } 1798 1799 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1800 u8 rate_val, u32 rate) 1801 { 1802 struct snd_soc_component *comp = dai->component; 1803 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1804 u8 shift = 0, shift_val = 0, tx_mux_sel; 1805 struct wcd9335_slim_ch *ch; 1806 int tx_port, tx_port_reg; 1807 int decimator = -1; 1808 1809 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1810 tx_port = ch->port; 1811 if ((tx_port == 12) || (tx_port >= 14)) { 1812 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1813 tx_port, dai->id); 1814 return -EINVAL; 1815 } 1816 /* Find the SB TX MUX input - which decimator is connected */ 1817 if (tx_port < 4) { 1818 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1819 shift = (tx_port << 1); 1820 shift_val = 0x03; 1821 } else if ((tx_port >= 4) && (tx_port < 8)) { 1822 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1823 shift = ((tx_port - 4) << 1); 1824 shift_val = 0x03; 1825 } else if ((tx_port >= 8) && (tx_port < 11)) { 1826 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1827 shift = ((tx_port - 8) << 1); 1828 shift_val = 0x03; 1829 } else if (tx_port == 11) { 1830 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1831 shift = 0; 1832 shift_val = 0x0F; 1833 } else if (tx_port == 13) { 1834 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1835 shift = 4; 1836 shift_val = 0x03; 1837 } else { 1838 return -EINVAL; 1839 } 1840 1841 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1842 (shift_val << shift); 1843 1844 tx_mux_sel = tx_mux_sel >> shift; 1845 if (tx_port <= 8) { 1846 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1847 decimator = tx_port; 1848 } else if (tx_port <= 10) { 1849 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1850 decimator = ((tx_port == 9) ? 7 : 6); 1851 } else if (tx_port == 11) { 1852 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1853 decimator = tx_mux_sel - 1; 1854 } else if (tx_port == 13) { 1855 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1856 decimator = 5; 1857 } 1858 1859 if (decimator >= 0) { 1860 snd_soc_component_update_bits(comp, 1861 WCD9335_CDC_TX_PATH_CTL(decimator), 1862 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1863 rate_val); 1864 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1865 /* Check if the TX Mux input is RX MIX TXn */ 1866 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1867 tx_port, tx_port); 1868 } else { 1869 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1870 decimator); 1871 return -EINVAL; 1872 } 1873 } 1874 1875 return 0; 1876 } 1877 1878 static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1879 struct snd_pcm_hw_params *params, 1880 struct snd_soc_dai *dai) 1881 { 1882 struct wcd9335_codec *wcd; 1883 int ret, tx_fs_rate = 0; 1884 1885 wcd = snd_soc_component_get_drvdata(dai->component); 1886 1887 switch (substream->stream) { 1888 case SNDRV_PCM_STREAM_PLAYBACK: 1889 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1890 if (ret) { 1891 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1892 params_rate(params)); 1893 return ret; 1894 } 1895 switch (params_width(params)) { 1896 case 16 ... 24: 1897 wcd->dai[dai->id].sconfig.bps = params_width(params); 1898 break; 1899 default: 1900 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1901 __func__, params_width(params)); 1902 return -EINVAL; 1903 } 1904 break; 1905 1906 case SNDRV_PCM_STREAM_CAPTURE: 1907 switch (params_rate(params)) { 1908 case 8000: 1909 tx_fs_rate = 0; 1910 break; 1911 case 16000: 1912 tx_fs_rate = 1; 1913 break; 1914 case 32000: 1915 tx_fs_rate = 3; 1916 break; 1917 case 48000: 1918 tx_fs_rate = 4; 1919 break; 1920 case 96000: 1921 tx_fs_rate = 5; 1922 break; 1923 case 192000: 1924 tx_fs_rate = 6; 1925 break; 1926 case 384000: 1927 tx_fs_rate = 7; 1928 break; 1929 default: 1930 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1931 __func__, params_rate(params)); 1932 return -EINVAL; 1933 1934 } 1935 1936 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1937 params_rate(params)); 1938 if (ret < 0) { 1939 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1940 return ret; 1941 } 1942 switch (params_width(params)) { 1943 case 16 ... 32: 1944 wcd->dai[dai->id].sconfig.bps = params_width(params); 1945 break; 1946 default: 1947 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1948 __func__, params_width(params)); 1949 return -EINVAL; 1950 } 1951 break; 1952 default: 1953 dev_err(wcd->dev, "Invalid stream type %d\n", 1954 substream->stream); 1955 return -EINVAL; 1956 } 1957 1958 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1959 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1960 1961 return 0; 1962 } 1963 1964 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1965 struct snd_soc_dai *dai) 1966 { 1967 struct wcd_slim_codec_dai_data *dai_data; 1968 struct wcd9335_codec *wcd; 1969 struct slim_stream_config *cfg; 1970 1971 wcd = snd_soc_component_get_drvdata(dai->component); 1972 1973 dai_data = &wcd->dai[dai->id]; 1974 1975 switch (cmd) { 1976 case SNDRV_PCM_TRIGGER_START: 1977 case SNDRV_PCM_TRIGGER_RESUME: 1978 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1979 cfg = &dai_data->sconfig; 1980 slim_stream_prepare(dai_data->sruntime, cfg); 1981 slim_stream_enable(dai_data->sruntime); 1982 break; 1983 case SNDRV_PCM_TRIGGER_STOP: 1984 case SNDRV_PCM_TRIGGER_SUSPEND: 1985 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1986 slim_stream_unprepare(dai_data->sruntime); 1987 slim_stream_disable(dai_data->sruntime); 1988 break; 1989 default: 1990 break; 1991 } 1992 1993 return 0; 1994 } 1995 1996 static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1997 unsigned int tx_num, unsigned int *tx_slot, 1998 unsigned int rx_num, unsigned int *rx_slot) 1999 { 2000 struct wcd9335_codec *wcd; 2001 int i; 2002 2003 wcd = snd_soc_component_get_drvdata(dai->component); 2004 2005 if (!tx_slot || !rx_slot) { 2006 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 2007 tx_slot, rx_slot); 2008 return -EINVAL; 2009 } 2010 2011 wcd->num_rx_port = rx_num; 2012 for (i = 0; i < rx_num; i++) { 2013 wcd->rx_chs[i].ch_num = rx_slot[i]; 2014 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2015 } 2016 2017 wcd->num_tx_port = tx_num; 2018 for (i = 0; i < tx_num; i++) { 2019 wcd->tx_chs[i].ch_num = tx_slot[i]; 2020 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2021 } 2022 2023 return 0; 2024 } 2025 2026 static int wcd9335_get_channel_map(struct snd_soc_dai *dai, 2027 unsigned int *tx_num, unsigned int *tx_slot, 2028 unsigned int *rx_num, unsigned int *rx_slot) 2029 { 2030 struct wcd9335_slim_ch *ch; 2031 struct wcd9335_codec *wcd; 2032 int i = 0; 2033 2034 wcd = snd_soc_component_get_drvdata(dai->component); 2035 2036 switch (dai->id) { 2037 case AIF1_PB: 2038 case AIF2_PB: 2039 case AIF3_PB: 2040 case AIF4_PB: 2041 if (!rx_slot || !rx_num) { 2042 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2043 rx_slot, rx_num); 2044 return -EINVAL; 2045 } 2046 2047 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2048 rx_slot[i++] = ch->ch_num; 2049 2050 *rx_num = i; 2051 break; 2052 case AIF1_CAP: 2053 case AIF2_CAP: 2054 case AIF3_CAP: 2055 if (!tx_slot || !tx_num) { 2056 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2057 tx_slot, tx_num); 2058 return -EINVAL; 2059 } 2060 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2061 tx_slot[i++] = ch->ch_num; 2062 2063 *tx_num = i; 2064 break; 2065 default: 2066 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2067 break; 2068 } 2069 2070 return 0; 2071 } 2072 2073 static const struct snd_soc_dai_ops wcd9335_dai_ops = { 2074 .hw_params = wcd9335_hw_params, 2075 .trigger = wcd9335_trigger, 2076 .set_channel_map = wcd9335_set_channel_map, 2077 .get_channel_map = wcd9335_get_channel_map, 2078 }; 2079 2080 static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2081 [0] = { 2082 .name = "wcd9335_rx1", 2083 .id = AIF1_PB, 2084 .playback = { 2085 .stream_name = "AIF1 Playback", 2086 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2087 SNDRV_PCM_RATE_384000, 2088 .formats = WCD9335_FORMATS_S16_S24_LE, 2089 .rate_max = 384000, 2090 .rate_min = 8000, 2091 .channels_min = 1, 2092 .channels_max = 2, 2093 }, 2094 .ops = &wcd9335_dai_ops, 2095 }, 2096 [1] = { 2097 .name = "wcd9335_tx1", 2098 .id = AIF1_CAP, 2099 .capture = { 2100 .stream_name = "AIF1 Capture", 2101 .rates = WCD9335_RATES_MASK, 2102 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2103 .rate_min = 8000, 2104 .rate_max = 192000, 2105 .channels_min = 1, 2106 .channels_max = 4, 2107 }, 2108 .ops = &wcd9335_dai_ops, 2109 }, 2110 [2] = { 2111 .name = "wcd9335_rx2", 2112 .id = AIF2_PB, 2113 .playback = { 2114 .stream_name = "AIF2 Playback", 2115 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2116 SNDRV_PCM_RATE_384000, 2117 .formats = WCD9335_FORMATS_S16_S24_LE, 2118 .rate_min = 8000, 2119 .rate_max = 384000, 2120 .channels_min = 1, 2121 .channels_max = 2, 2122 }, 2123 .ops = &wcd9335_dai_ops, 2124 }, 2125 [3] = { 2126 .name = "wcd9335_tx2", 2127 .id = AIF2_CAP, 2128 .capture = { 2129 .stream_name = "AIF2 Capture", 2130 .rates = WCD9335_RATES_MASK, 2131 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2132 .rate_min = 8000, 2133 .rate_max = 192000, 2134 .channels_min = 1, 2135 .channels_max = 4, 2136 }, 2137 .ops = &wcd9335_dai_ops, 2138 }, 2139 [4] = { 2140 .name = "wcd9335_rx3", 2141 .id = AIF3_PB, 2142 .playback = { 2143 .stream_name = "AIF3 Playback", 2144 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2145 SNDRV_PCM_RATE_384000, 2146 .formats = WCD9335_FORMATS_S16_S24_LE, 2147 .rate_min = 8000, 2148 .rate_max = 384000, 2149 .channels_min = 1, 2150 .channels_max = 2, 2151 }, 2152 .ops = &wcd9335_dai_ops, 2153 }, 2154 [5] = { 2155 .name = "wcd9335_tx3", 2156 .id = AIF3_CAP, 2157 .capture = { 2158 .stream_name = "AIF3 Capture", 2159 .rates = WCD9335_RATES_MASK, 2160 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2161 .rate_min = 8000, 2162 .rate_max = 192000, 2163 .channels_min = 1, 2164 .channels_max = 4, 2165 }, 2166 .ops = &wcd9335_dai_ops, 2167 }, 2168 [6] = { 2169 .name = "wcd9335_rx4", 2170 .id = AIF4_PB, 2171 .playback = { 2172 .stream_name = "AIF4 Playback", 2173 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2174 SNDRV_PCM_RATE_384000, 2175 .formats = WCD9335_FORMATS_S16_S24_LE, 2176 .rate_min = 8000, 2177 .rate_max = 384000, 2178 .channels_min = 1, 2179 .channels_max = 2, 2180 }, 2181 .ops = &wcd9335_dai_ops, 2182 }, 2183 }; 2184 2185 static int wcd9335_get_compander(struct snd_kcontrol *kc, 2186 struct snd_ctl_elem_value *ucontrol) 2187 { 2188 2189 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2190 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2191 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2192 2193 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2194 return 0; 2195 } 2196 2197 static int wcd9335_set_compander(struct snd_kcontrol *kc, 2198 struct snd_ctl_elem_value *ucontrol) 2199 { 2200 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2201 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2202 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2203 int value = ucontrol->value.integer.value[0]; 2204 int sel; 2205 2206 wcd->comp_enabled[comp] = value; 2207 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2208 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2209 2210 /* Any specific register configuration for compander */ 2211 switch (comp) { 2212 case COMPANDER_1: 2213 /* Set Gain Source Select based on compander enable/disable */ 2214 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2215 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2216 break; 2217 case COMPANDER_2: 2218 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2219 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2220 break; 2221 case COMPANDER_5: 2222 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2223 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2224 break; 2225 case COMPANDER_6: 2226 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2227 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2228 break; 2229 default: 2230 break; 2231 } 2232 2233 return 0; 2234 } 2235 2236 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2237 struct snd_ctl_elem_value *ucontrol) 2238 { 2239 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2240 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2241 2242 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2243 2244 return 0; 2245 } 2246 2247 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2248 struct snd_ctl_elem_value *ucontrol) 2249 { 2250 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2251 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2252 u32 mode_val; 2253 2254 mode_val = ucontrol->value.enumerated.item[0]; 2255 2256 if (mode_val == 0) { 2257 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2258 mode_val = CLS_H_HIFI; 2259 } 2260 wcd->hph_mode = mode_val; 2261 2262 return 0; 2263 } 2264 2265 static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2266 /* -84dB min - 40dB max */ 2267 SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2268 0, -84, 40, digital_gain), 2269 SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2270 0, -84, 40, digital_gain), 2271 SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2272 0, -84, 40, digital_gain), 2273 SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2274 0, -84, 40, digital_gain), 2275 SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2276 0, -84, 40, digital_gain), 2277 SOC_SINGLE_SX_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2278 0, -84, 40, digital_gain), 2279 SOC_SINGLE_SX_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2280 0, -84, 40, digital_gain), 2281 SOC_SINGLE_SX_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2282 0, -84, 40, digital_gain), 2283 SOC_SINGLE_SX_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2284 0, -84, 40, digital_gain), 2285 SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume", 2286 WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2287 0, -84, 40, digital_gain), 2288 SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume", 2289 WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2290 0, -84, 40, digital_gain), 2291 SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume", 2292 WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2293 0, -84, 40, digital_gain), 2294 SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume", 2295 WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2296 0, -84, 40, digital_gain), 2297 SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume", 2298 WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2299 0, -84, 40, digital_gain), 2300 SOC_SINGLE_SX_TLV("RX5 Mix Digital Volume", 2301 WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2302 0, -84, 40, digital_gain), 2303 SOC_SINGLE_SX_TLV("RX6 Mix Digital Volume", 2304 WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2305 0, -84, 40, digital_gain), 2306 SOC_SINGLE_SX_TLV("RX7 Mix Digital Volume", 2307 WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2308 0, -84, 40, digital_gain), 2309 SOC_SINGLE_SX_TLV("RX8 Mix Digital Volume", 2310 WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2311 0, -84, 40, digital_gain), 2312 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2313 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2314 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2315 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2316 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2317 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2318 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2319 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2320 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2321 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2322 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2323 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2324 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2325 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2326 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2327 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2328 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2329 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2330 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2331 wcd9335_get_compander, wcd9335_set_compander), 2332 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2333 wcd9335_get_compander, wcd9335_set_compander), 2334 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2335 wcd9335_get_compander, wcd9335_set_compander), 2336 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2337 wcd9335_get_compander, wcd9335_set_compander), 2338 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2339 wcd9335_get_compander, wcd9335_set_compander), 2340 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2341 wcd9335_get_compander, wcd9335_set_compander), 2342 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2343 wcd9335_get_compander, wcd9335_set_compander), 2344 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2345 wcd9335_get_compander, wcd9335_set_compander), 2346 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2347 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2348 2349 /* Gain Controls */ 2350 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2351 ear_pa_gain), 2352 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2353 line_gain), 2354 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2355 line_gain), 2356 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2357 3, 16, 1, line_gain), 2358 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2359 3, 16, 1, line_gain), 2360 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2361 line_gain), 2362 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2363 line_gain), 2364 2365 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2366 analog_gain), 2367 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2368 analog_gain), 2369 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2370 analog_gain), 2371 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2372 analog_gain), 2373 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2374 analog_gain), 2375 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2376 analog_gain), 2377 2378 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2379 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2380 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2381 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2382 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2383 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2384 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2385 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2386 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2387 }; 2388 2389 static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2390 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2391 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2392 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2393 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2394 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2395 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2396 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2397 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2398 2399 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2400 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2401 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2402 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2403 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2404 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2405 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2406 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2407 2408 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2409 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2410 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2411 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2412 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2413 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2414 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2415 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2416 2417 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2418 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2419 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2420 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2421 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2422 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2423 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2424 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2425 2426 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2427 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2428 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2429 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2430 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2431 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2432 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2433 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2434 2435 WCD9335_INTERPOLATOR_PATH(0), 2436 WCD9335_INTERPOLATOR_PATH(1), 2437 WCD9335_INTERPOLATOR_PATH(2), 2438 WCD9335_INTERPOLATOR_PATH(3), 2439 WCD9335_INTERPOLATOR_PATH(4), 2440 WCD9335_INTERPOLATOR_PATH(5), 2441 WCD9335_INTERPOLATOR_PATH(6), 2442 WCD9335_INTERPOLATOR_PATH(7), 2443 WCD9335_INTERPOLATOR_PATH(8), 2444 2445 /* EAR PA */ 2446 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2447 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2448 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2449 {"EAR PA", NULL, "RX INT0 DAC"}, 2450 {"EAR", NULL, "EAR PA"}, 2451 2452 /* HPHL */ 2453 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2454 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2455 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2456 {"HPHL PA", NULL, "RX INT1 DAC"}, 2457 {"HPHL", NULL, "HPHL PA"}, 2458 2459 /* HPHR */ 2460 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2461 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2462 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2463 {"HPHR PA", NULL, "RX INT2 DAC"}, 2464 {"HPHR", NULL, "HPHR PA"}, 2465 2466 /* LINEOUT1 */ 2467 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2468 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2469 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2470 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2471 2472 /* LINEOUT2 */ 2473 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2474 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2475 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2476 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2477 2478 /* LINEOUT3 */ 2479 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2480 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2481 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2482 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2483 2484 /* LINEOUT4 */ 2485 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2486 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2487 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2488 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2489 2490 /* SLIMBUS Connections */ 2491 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2492 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2493 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2494 2495 /* ADC Mux */ 2496 WCD9335_ADC_MUX_PATH(0), 2497 WCD9335_ADC_MUX_PATH(1), 2498 WCD9335_ADC_MUX_PATH(2), 2499 WCD9335_ADC_MUX_PATH(3), 2500 WCD9335_ADC_MUX_PATH(4), 2501 WCD9335_ADC_MUX_PATH(5), 2502 WCD9335_ADC_MUX_PATH(6), 2503 WCD9335_ADC_MUX_PATH(7), 2504 WCD9335_ADC_MUX_PATH(8), 2505 2506 /* ADC Connections */ 2507 {"ADC1", NULL, "AMIC1"}, 2508 {"ADC2", NULL, "AMIC2"}, 2509 {"ADC3", NULL, "AMIC3"}, 2510 {"ADC4", NULL, "AMIC4"}, 2511 {"ADC5", NULL, "AMIC5"}, 2512 {"ADC6", NULL, "AMIC6"}, 2513 }; 2514 2515 static int wcd9335_micbias_control(struct snd_soc_component *component, 2516 int micb_num, int req, bool is_dapm) 2517 { 2518 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2519 int micb_index = micb_num - 1; 2520 u16 micb_reg; 2521 2522 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2523 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2524 micb_index); 2525 return -EINVAL; 2526 } 2527 2528 switch (micb_num) { 2529 case MIC_BIAS_1: 2530 micb_reg = WCD9335_ANA_MICB1; 2531 break; 2532 case MIC_BIAS_2: 2533 micb_reg = WCD9335_ANA_MICB2; 2534 break; 2535 case MIC_BIAS_3: 2536 micb_reg = WCD9335_ANA_MICB3; 2537 break; 2538 case MIC_BIAS_4: 2539 micb_reg = WCD9335_ANA_MICB4; 2540 break; 2541 default: 2542 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2543 __func__, micb_num); 2544 return -EINVAL; 2545 } 2546 2547 switch (req) { 2548 case MICB_PULLUP_ENABLE: 2549 wcd->pullup_ref[micb_index]++; 2550 if ((wcd->pullup_ref[micb_index] == 1) && 2551 (wcd->micb_ref[micb_index] == 0)) 2552 snd_soc_component_update_bits(component, micb_reg, 2553 0xC0, 0x80); 2554 break; 2555 case MICB_PULLUP_DISABLE: 2556 wcd->pullup_ref[micb_index]--; 2557 if ((wcd->pullup_ref[micb_index] == 0) && 2558 (wcd->micb_ref[micb_index] == 0)) 2559 snd_soc_component_update_bits(component, micb_reg, 2560 0xC0, 0x00); 2561 break; 2562 case MICB_ENABLE: 2563 wcd->micb_ref[micb_index]++; 2564 if (wcd->micb_ref[micb_index] == 1) 2565 snd_soc_component_update_bits(component, micb_reg, 2566 0xC0, 0x40); 2567 break; 2568 case MICB_DISABLE: 2569 wcd->micb_ref[micb_index]--; 2570 if ((wcd->micb_ref[micb_index] == 0) && 2571 (wcd->pullup_ref[micb_index] > 0)) 2572 snd_soc_component_update_bits(component, micb_reg, 2573 0xC0, 0x80); 2574 else if ((wcd->micb_ref[micb_index] == 0) && 2575 (wcd->pullup_ref[micb_index] == 0)) { 2576 snd_soc_component_update_bits(component, micb_reg, 2577 0xC0, 0x00); 2578 } 2579 break; 2580 } 2581 2582 return 0; 2583 } 2584 2585 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2586 int event) 2587 { 2588 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2589 int micb_num; 2590 2591 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2592 micb_num = MIC_BIAS_1; 2593 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2594 micb_num = MIC_BIAS_2; 2595 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2596 micb_num = MIC_BIAS_3; 2597 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2598 micb_num = MIC_BIAS_4; 2599 else 2600 return -EINVAL; 2601 2602 switch (event) { 2603 case SND_SOC_DAPM_PRE_PMU: 2604 /* 2605 * MIC BIAS can also be requested by MBHC, 2606 * so use ref count to handle micbias pullup 2607 * and enable requests 2608 */ 2609 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2610 break; 2611 case SND_SOC_DAPM_POST_PMU: 2612 /* wait for cnp time */ 2613 usleep_range(1000, 1100); 2614 break; 2615 case SND_SOC_DAPM_POST_PMD: 2616 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2617 break; 2618 } 2619 2620 return 0; 2621 } 2622 2623 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2624 struct snd_kcontrol *kc, int event) 2625 { 2626 return __wcd9335_codec_enable_micbias(w, event); 2627 } 2628 2629 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2630 u16 amic_reg, bool set) 2631 { 2632 u8 mask = 0x20; 2633 u8 val; 2634 2635 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2636 amic_reg == WCD9335_ANA_AMIC5) 2637 mask = 0x40; 2638 2639 val = set ? mask : 0x00; 2640 2641 switch (amic_reg) { 2642 case WCD9335_ANA_AMIC1: 2643 case WCD9335_ANA_AMIC2: 2644 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2645 val); 2646 break; 2647 case WCD9335_ANA_AMIC3: 2648 case WCD9335_ANA_AMIC4: 2649 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2650 val); 2651 break; 2652 case WCD9335_ANA_AMIC5: 2653 case WCD9335_ANA_AMIC6: 2654 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2655 val); 2656 break; 2657 default: 2658 dev_err(comp->dev, "%s: invalid amic: %d\n", 2659 __func__, amic_reg); 2660 break; 2661 } 2662 } 2663 2664 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2665 struct snd_kcontrol *kc, int event) 2666 { 2667 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2668 2669 switch (event) { 2670 case SND_SOC_DAPM_PRE_PMU: 2671 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2672 break; 2673 default: 2674 break; 2675 } 2676 2677 return 0; 2678 } 2679 2680 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2681 int adc_mux_n) 2682 { 2683 int mux_sel, reg, mreg; 2684 2685 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2686 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2687 return 0; 2688 2689 /* Check whether adc mux input is AMIC or DMIC */ 2690 if (adc_mux_n < 4) { 2691 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2692 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2693 mux_sel = snd_soc_component_read(comp, reg) & 0x3; 2694 } else { 2695 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2696 mreg = reg; 2697 mux_sel = snd_soc_component_read(comp, reg) >> 6; 2698 } 2699 2700 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2701 return 0; 2702 2703 return snd_soc_component_read(comp, mreg) & 0x07; 2704 } 2705 2706 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2707 int amic) 2708 { 2709 u16 pwr_level_reg = 0; 2710 2711 switch (amic) { 2712 case 1: 2713 case 2: 2714 pwr_level_reg = WCD9335_ANA_AMIC1; 2715 break; 2716 2717 case 3: 2718 case 4: 2719 pwr_level_reg = WCD9335_ANA_AMIC3; 2720 break; 2721 2722 case 5: 2723 case 6: 2724 pwr_level_reg = WCD9335_ANA_AMIC5; 2725 break; 2726 default: 2727 dev_err(comp->dev, "invalid amic: %d\n", amic); 2728 break; 2729 } 2730 2731 return pwr_level_reg; 2732 } 2733 2734 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2735 struct snd_kcontrol *kc, int event) 2736 { 2737 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2738 unsigned int decimator; 2739 char *dec_adc_mux_name = NULL; 2740 char *widget_name = NULL; 2741 char *wname; 2742 int ret = 0, amic_n; 2743 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2744 u16 tx_gain_ctl_reg; 2745 char *dec; 2746 u8 hpf_coff_freq; 2747 2748 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); 2749 if (!widget_name) 2750 return -ENOMEM; 2751 2752 wname = widget_name; 2753 dec_adc_mux_name = strsep(&widget_name, " "); 2754 if (!dec_adc_mux_name) { 2755 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2756 __func__, w->name); 2757 ret = -EINVAL; 2758 goto out; 2759 } 2760 dec_adc_mux_name = widget_name; 2761 2762 dec = strpbrk(dec_adc_mux_name, "012345678"); 2763 if (!dec) { 2764 dev_err(comp->dev, "%s: decimator index not found\n", 2765 __func__); 2766 ret = -EINVAL; 2767 goto out; 2768 } 2769 2770 ret = kstrtouint(dec, 10, &decimator); 2771 if (ret < 0) { 2772 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2773 __func__, wname); 2774 ret = -EINVAL; 2775 goto out; 2776 } 2777 2778 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2779 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2780 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2781 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2782 2783 switch (event) { 2784 case SND_SOC_DAPM_PRE_PMU: 2785 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2786 if (amic_n) 2787 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2788 amic_n); 2789 2790 if (pwr_level_reg) { 2791 switch ((snd_soc_component_read(comp, pwr_level_reg) & 2792 WCD9335_AMIC_PWR_LVL_MASK) >> 2793 WCD9335_AMIC_PWR_LVL_SHIFT) { 2794 case WCD9335_AMIC_PWR_LEVEL_LP: 2795 snd_soc_component_update_bits(comp, dec_cfg_reg, 2796 WCD9335_DEC_PWR_LVL_MASK, 2797 WCD9335_DEC_PWR_LVL_LP); 2798 break; 2799 2800 case WCD9335_AMIC_PWR_LEVEL_HP: 2801 snd_soc_component_update_bits(comp, dec_cfg_reg, 2802 WCD9335_DEC_PWR_LVL_MASK, 2803 WCD9335_DEC_PWR_LVL_HP); 2804 break; 2805 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2806 default: 2807 snd_soc_component_update_bits(comp, dec_cfg_reg, 2808 WCD9335_DEC_PWR_LVL_MASK, 2809 WCD9335_DEC_PWR_LVL_DF); 2810 break; 2811 } 2812 } 2813 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2814 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2815 2816 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2817 snd_soc_component_update_bits(comp, dec_cfg_reg, 2818 TX_HPF_CUT_OFF_FREQ_MASK, 2819 CF_MIN_3DB_150HZ << 5); 2820 /* Enable TX PGA Mute */ 2821 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2822 0x10, 0x10); 2823 /* Enable APC */ 2824 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2825 break; 2826 case SND_SOC_DAPM_POST_PMU: 2827 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2828 2829 if (decimator == 0) { 2830 snd_soc_component_write(comp, 2831 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2832 snd_soc_component_write(comp, 2833 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2834 snd_soc_component_write(comp, 2835 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2836 snd_soc_component_write(comp, 2837 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2838 } 2839 2840 snd_soc_component_update_bits(comp, hpf_gate_reg, 2841 0x01, 0x01); 2842 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2843 0x10, 0x00); 2844 snd_soc_component_write(comp, tx_gain_ctl_reg, 2845 snd_soc_component_read(comp, tx_gain_ctl_reg)); 2846 break; 2847 case SND_SOC_DAPM_PRE_PMD: 2848 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2849 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2850 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2851 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2852 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2853 snd_soc_component_update_bits(comp, dec_cfg_reg, 2854 TX_HPF_CUT_OFF_FREQ_MASK, 2855 hpf_coff_freq << 5); 2856 } 2857 break; 2858 case SND_SOC_DAPM_POST_PMD: 2859 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2860 break; 2861 } 2862 out: 2863 kfree(wname); 2864 return ret; 2865 } 2866 2867 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2868 u32 mclk_rate, u32 dmic_clk_rate) 2869 { 2870 u32 div_factor; 2871 u8 dmic_ctl_val; 2872 2873 dev_err(component->dev, 2874 "%s: mclk_rate = %d, dmic_sample_rate = %d\n", 2875 __func__, mclk_rate, dmic_clk_rate); 2876 2877 /* Default value to return in case of error */ 2878 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2879 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2880 else 2881 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2882 2883 if (dmic_clk_rate == 0) { 2884 dev_err(component->dev, 2885 "%s: dmic_sample_rate cannot be 0\n", 2886 __func__); 2887 goto done; 2888 } 2889 2890 div_factor = mclk_rate / dmic_clk_rate; 2891 switch (div_factor) { 2892 case 2: 2893 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2894 break; 2895 case 3: 2896 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2897 break; 2898 case 4: 2899 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4; 2900 break; 2901 case 6: 2902 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6; 2903 break; 2904 case 8: 2905 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8; 2906 break; 2907 case 16: 2908 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16; 2909 break; 2910 default: 2911 dev_err(component->dev, 2912 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 2913 __func__, div_factor, mclk_rate, dmic_clk_rate); 2914 break; 2915 } 2916 2917 done: 2918 return dmic_ctl_val; 2919 } 2920 2921 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2922 struct snd_kcontrol *kc, int event) 2923 { 2924 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2925 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2926 u8 dmic_clk_en = 0x01; 2927 u16 dmic_clk_reg; 2928 s32 *dmic_clk_cnt; 2929 u8 dmic_rate_val, dmic_rate_shift = 1; 2930 unsigned int dmic; 2931 int ret; 2932 char *wname; 2933 2934 wname = strpbrk(w->name, "012345"); 2935 if (!wname) { 2936 dev_err(comp->dev, "%s: widget not found\n", __func__); 2937 return -EINVAL; 2938 } 2939 2940 ret = kstrtouint(wname, 10, &dmic); 2941 if (ret < 0) { 2942 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2943 __func__); 2944 return -EINVAL; 2945 } 2946 2947 switch (dmic) { 2948 case 0: 2949 case 1: 2950 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2951 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2952 break; 2953 case 2: 2954 case 3: 2955 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2956 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2957 break; 2958 case 4: 2959 case 5: 2960 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2961 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2962 break; 2963 default: 2964 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2965 __func__); 2966 return -EINVAL; 2967 } 2968 2969 switch (event) { 2970 case SND_SOC_DAPM_PRE_PMU: 2971 dmic_rate_val = 2972 wcd9335_get_dmic_clk_val(comp, 2973 wcd->mclk_rate, 2974 wcd->dmic_sample_rate); 2975 2976 (*dmic_clk_cnt)++; 2977 if (*dmic_clk_cnt == 1) { 2978 snd_soc_component_update_bits(comp, dmic_clk_reg, 2979 0x07 << dmic_rate_shift, 2980 dmic_rate_val << dmic_rate_shift); 2981 snd_soc_component_update_bits(comp, dmic_clk_reg, 2982 dmic_clk_en, dmic_clk_en); 2983 } 2984 2985 break; 2986 case SND_SOC_DAPM_POST_PMD: 2987 dmic_rate_val = 2988 wcd9335_get_dmic_clk_val(comp, 2989 wcd->mclk_rate, 2990 wcd->mad_dmic_sample_rate); 2991 (*dmic_clk_cnt)--; 2992 if (*dmic_clk_cnt == 0) { 2993 snd_soc_component_update_bits(comp, dmic_clk_reg, 2994 dmic_clk_en, 0); 2995 snd_soc_component_update_bits(comp, dmic_clk_reg, 2996 0x07 << dmic_rate_shift, 2997 dmic_rate_val << dmic_rate_shift); 2998 } 2999 break; 3000 } 3001 3002 return 0; 3003 } 3004 3005 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 3006 struct snd_soc_component *component) 3007 { 3008 int port_num = 0; 3009 unsigned short reg = 0; 3010 unsigned int val = 0; 3011 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3012 struct wcd9335_slim_ch *ch; 3013 3014 list_for_each_entry(ch, &dai->slim_ch_list, list) { 3015 if (ch->port >= WCD9335_RX_START) { 3016 port_num = ch->port - WCD9335_RX_START; 3017 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 3018 } else { 3019 port_num = ch->port; 3020 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 3021 } 3022 3023 regmap_read(wcd->if_regmap, reg, &val); 3024 if (!(val & BIT(port_num % 8))) 3025 regmap_write(wcd->if_regmap, reg, 3026 val | BIT(port_num % 8)); 3027 } 3028 } 3029 3030 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 3031 struct snd_kcontrol *kc, 3032 int event) 3033 { 3034 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3035 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 3036 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 3037 3038 switch (event) { 3039 case SND_SOC_DAPM_POST_PMU: 3040 wcd9335_codec_enable_int_port(dai, comp); 3041 break; 3042 case SND_SOC_DAPM_POST_PMD: 3043 kfree(dai->sconfig.chs); 3044 3045 break; 3046 } 3047 3048 return 0; 3049 } 3050 3051 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 3052 struct snd_kcontrol *kc, int event) 3053 { 3054 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3055 u16 gain_reg; 3056 int offset_val = 0; 3057 int val = 0; 3058 3059 switch (w->reg) { 3060 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3061 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 3062 break; 3063 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3064 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 3065 break; 3066 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3067 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3068 break; 3069 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3070 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3071 break; 3072 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3073 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3074 break; 3075 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3076 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3077 break; 3078 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3079 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3080 break; 3081 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3082 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3083 break; 3084 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3085 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3086 break; 3087 default: 3088 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3089 __func__, w->name); 3090 return 0; 3091 } 3092 3093 switch (event) { 3094 case SND_SOC_DAPM_POST_PMU: 3095 val = snd_soc_component_read(comp, gain_reg); 3096 val += offset_val; 3097 snd_soc_component_write(comp, gain_reg, val); 3098 break; 3099 case SND_SOC_DAPM_POST_PMD: 3100 break; 3101 } 3102 3103 return 0; 3104 } 3105 3106 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3107 { 3108 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3109 3110 switch (reg) { 3111 case WCD9335_CDC_RX0_RX_PATH_CTL: 3112 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3113 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3114 *ind = 0; 3115 break; 3116 case WCD9335_CDC_RX1_RX_PATH_CTL: 3117 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3118 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3119 *ind = 1; 3120 break; 3121 case WCD9335_CDC_RX2_RX_PATH_CTL: 3122 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3123 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3124 *ind = 2; 3125 break; 3126 case WCD9335_CDC_RX3_RX_PATH_CTL: 3127 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3128 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3129 *ind = 3; 3130 break; 3131 case WCD9335_CDC_RX4_RX_PATH_CTL: 3132 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3133 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3134 *ind = 4; 3135 break; 3136 case WCD9335_CDC_RX5_RX_PATH_CTL: 3137 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3138 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3139 *ind = 5; 3140 break; 3141 case WCD9335_CDC_RX6_RX_PATH_CTL: 3142 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3143 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3144 *ind = 6; 3145 break; 3146 case WCD9335_CDC_RX7_RX_PATH_CTL: 3147 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3148 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3149 *ind = 7; 3150 break; 3151 case WCD9335_CDC_RX8_RX_PATH_CTL: 3152 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3153 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3154 *ind = 8; 3155 break; 3156 } 3157 3158 return prim_int_reg; 3159 } 3160 3161 static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3162 u16 prim_int_reg, int event) 3163 { 3164 u16 hd2_scale_reg; 3165 u16 hd2_enable_reg = 0; 3166 3167 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3168 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3169 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3170 } 3171 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3172 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3173 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3174 } 3175 3176 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3177 snd_soc_component_update_bits(component, hd2_scale_reg, 3178 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3179 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3180 snd_soc_component_update_bits(component, hd2_scale_reg, 3181 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3182 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3183 snd_soc_component_update_bits(component, hd2_enable_reg, 3184 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3185 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3186 } 3187 3188 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3189 snd_soc_component_update_bits(component, hd2_enable_reg, 3190 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3191 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3192 snd_soc_component_update_bits(component, hd2_scale_reg, 3193 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3194 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3195 snd_soc_component_update_bits(component, hd2_scale_reg, 3196 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3197 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3198 } 3199 } 3200 3201 static int wcd9335_codec_enable_prim_interpolator( 3202 struct snd_soc_component *comp, 3203 u16 reg, int event) 3204 { 3205 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3206 u16 ind = 0; 3207 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3208 3209 switch (event) { 3210 case SND_SOC_DAPM_PRE_PMU: 3211 wcd->prim_int_users[ind]++; 3212 if (wcd->prim_int_users[ind] == 1) { 3213 snd_soc_component_update_bits(comp, prim_int_reg, 3214 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3215 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3216 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3217 snd_soc_component_update_bits(comp, prim_int_reg, 3218 WCD9335_CDC_RX_CLK_EN_MASK, 3219 WCD9335_CDC_RX_CLK_ENABLE); 3220 } 3221 3222 if ((reg != prim_int_reg) && 3223 ((snd_soc_component_read(comp, prim_int_reg)) & 3224 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3225 snd_soc_component_update_bits(comp, reg, 3226 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3227 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3228 break; 3229 case SND_SOC_DAPM_POST_PMD: 3230 wcd->prim_int_users[ind]--; 3231 if (wcd->prim_int_users[ind] == 0) { 3232 snd_soc_component_update_bits(comp, prim_int_reg, 3233 WCD9335_CDC_RX_CLK_EN_MASK, 3234 WCD9335_CDC_RX_CLK_DISABLE); 3235 snd_soc_component_update_bits(comp, prim_int_reg, 3236 WCD9335_CDC_RX_RESET_MASK, 3237 WCD9335_CDC_RX_RESET_ENABLE); 3238 snd_soc_component_update_bits(comp, prim_int_reg, 3239 WCD9335_CDC_RX_RESET_MASK, 3240 WCD9335_CDC_RX_RESET_DISABLE); 3241 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3242 } 3243 break; 3244 } 3245 3246 return 0; 3247 } 3248 3249 static int wcd9335_config_compander(struct snd_soc_component *component, 3250 int interp_n, int event) 3251 { 3252 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3253 int comp; 3254 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3255 3256 /* EAR does not have compander */ 3257 if (!interp_n) 3258 return 0; 3259 3260 comp = interp_n - 1; 3261 if (!wcd->comp_enabled[comp]) 3262 return 0; 3263 3264 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3265 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3266 3267 if (SND_SOC_DAPM_EVENT_ON(event)) { 3268 /* Enable Compander Clock */ 3269 snd_soc_component_update_bits(component, comp_ctl0_reg, 3270 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3271 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3272 /* Reset comander */ 3273 snd_soc_component_update_bits(component, comp_ctl0_reg, 3274 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3275 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3276 snd_soc_component_update_bits(component, comp_ctl0_reg, 3277 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3278 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3279 /* Enables DRE in this path */ 3280 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3281 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3282 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3283 } 3284 3285 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3286 snd_soc_component_update_bits(component, comp_ctl0_reg, 3287 WCD9335_CDC_COMPANDER_HALT_MASK, 3288 WCD9335_CDC_COMPANDER_HALT); 3289 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3290 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3291 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3292 3293 snd_soc_component_update_bits(component, comp_ctl0_reg, 3294 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3295 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3296 snd_soc_component_update_bits(component, comp_ctl0_reg, 3297 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3298 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3299 snd_soc_component_update_bits(component, comp_ctl0_reg, 3300 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3301 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3302 snd_soc_component_update_bits(component, comp_ctl0_reg, 3303 WCD9335_CDC_COMPANDER_HALT_MASK, 3304 WCD9335_CDC_COMPANDER_NOHALT); 3305 } 3306 3307 return 0; 3308 } 3309 3310 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3311 struct snd_kcontrol *kc, int event) 3312 { 3313 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3314 u16 gain_reg; 3315 u16 reg; 3316 int val; 3317 int offset_val = 0; 3318 3319 if (!(strcmp(w->name, "RX INT0 INTERP"))) { 3320 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3321 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3322 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) { 3323 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3324 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3325 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) { 3326 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3327 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3328 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) { 3329 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3330 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3331 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) { 3332 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3333 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3334 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) { 3335 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3336 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3337 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) { 3338 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3339 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3340 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) { 3341 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3342 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3343 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) { 3344 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3345 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3346 } else { 3347 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3348 __func__); 3349 return -EINVAL; 3350 } 3351 3352 switch (event) { 3353 case SND_SOC_DAPM_PRE_PMU: 3354 /* Reset if needed */ 3355 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3356 break; 3357 case SND_SOC_DAPM_POST_PMU: 3358 wcd9335_config_compander(comp, w->shift, event); 3359 val = snd_soc_component_read(comp, gain_reg); 3360 val += offset_val; 3361 snd_soc_component_write(comp, gain_reg, val); 3362 break; 3363 case SND_SOC_DAPM_POST_PMD: 3364 wcd9335_config_compander(comp, w->shift, event); 3365 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3366 break; 3367 } 3368 3369 return 0; 3370 } 3371 3372 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3373 u8 gain) 3374 { 3375 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3376 u8 hph_l_en, hph_r_en; 3377 u8 l_val, r_val; 3378 u8 hph_pa_status; 3379 bool is_hphl_pa, is_hphr_pa; 3380 3381 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH); 3382 is_hphl_pa = hph_pa_status >> 7; 3383 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3384 3385 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN); 3386 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN); 3387 3388 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3389 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3390 3391 /* 3392 * Set HPH_L & HPH_R gain source selection to REGISTER 3393 * for better click and pop only if corresponding PAs are 3394 * not enabled. Also cache the values of the HPHL/R 3395 * PA gains to be applied after PAs are enabled 3396 */ 3397 if ((l_val != hph_l_en) && !is_hphl_pa) { 3398 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3399 wcd->hph_l_gain = hph_l_en & 0x1F; 3400 } 3401 3402 if ((r_val != hph_r_en) && !is_hphr_pa) { 3403 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3404 wcd->hph_r_gain = hph_r_en & 0x1F; 3405 } 3406 } 3407 3408 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3409 int event) 3410 { 3411 if (SND_SOC_DAPM_EVENT_ON(event)) { 3412 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3413 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3414 0x06); 3415 snd_soc_component_update_bits(comp, 3416 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3417 0xF0, 0x40); 3418 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3419 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3420 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3421 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3422 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3423 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3424 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3425 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3426 0x0C); 3427 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3428 } 3429 3430 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3431 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3432 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3433 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3434 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3435 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3436 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3437 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3438 0x8A); 3439 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3440 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3441 0x0A); 3442 } 3443 } 3444 3445 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3446 int event) 3447 { 3448 if (SND_SOC_DAPM_EVENT_ON(event)) { 3449 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3450 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3451 0x0C); 3452 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3453 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3454 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3455 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3456 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3457 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3458 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3459 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3460 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3461 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3462 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3463 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3464 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3465 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3466 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3467 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3468 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3469 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3470 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3471 snd_soc_component_update_bits(comp, 3472 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3473 snd_soc_component_update_bits(comp, 3474 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3475 } 3476 3477 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3478 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3479 0x88); 3480 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3481 0x33); 3482 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3483 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3484 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3485 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3486 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3487 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3488 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3489 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3490 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3491 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3492 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3493 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3494 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3495 WCD9335_HPH_CONST_SEL_L_MASK, 3496 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3497 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3498 WCD9335_HPH_CONST_SEL_L_MASK, 3499 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3500 } 3501 } 3502 3503 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3504 int event) 3505 { 3506 if (SND_SOC_DAPM_EVENT_ON(event)) { 3507 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3508 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3509 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3510 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3511 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3512 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3513 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3514 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3515 0x0C); 3516 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3517 } 3518 3519 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3520 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3521 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3522 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3523 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3524 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3525 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3526 } 3527 } 3528 3529 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3530 int event, int mode) 3531 { 3532 switch (mode) { 3533 case CLS_H_LP: 3534 wcd9335_codec_hph_lp_config(component, event); 3535 break; 3536 case CLS_H_LOHIFI: 3537 wcd9335_codec_hph_lohifi_config(component, event); 3538 break; 3539 case CLS_H_HIFI: 3540 wcd9335_codec_hph_hifi_config(component, event); 3541 break; 3542 } 3543 } 3544 3545 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3546 struct snd_kcontrol *kc, 3547 int event) 3548 { 3549 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3550 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3551 int hph_mode = wcd->hph_mode; 3552 u8 dem_inp; 3553 3554 switch (event) { 3555 case SND_SOC_DAPM_PRE_PMU: 3556 /* Read DEM INP Select */ 3557 dem_inp = snd_soc_component_read(comp, 3558 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3559 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3560 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3561 dev_err(comp->dev, "Incorrect DEM Input\n"); 3562 return -EINVAL; 3563 } 3564 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3565 WCD_CLSH_STATE_HPHL, 3566 ((hph_mode == CLS_H_LOHIFI) ? 3567 CLS_H_HIFI : hph_mode)); 3568 3569 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3570 3571 break; 3572 case SND_SOC_DAPM_POST_PMU: 3573 usleep_range(1000, 1100); 3574 break; 3575 case SND_SOC_DAPM_PRE_PMD: 3576 break; 3577 case SND_SOC_DAPM_POST_PMD: 3578 /* 1000us required as per HW requirement */ 3579 usleep_range(1000, 1100); 3580 3581 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3582 WCD_CLSH_STATE_HPHR)) 3583 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3584 3585 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3586 WCD_CLSH_STATE_HPHL, 3587 ((hph_mode == CLS_H_LOHIFI) ? 3588 CLS_H_HIFI : hph_mode)); 3589 break; 3590 } 3591 3592 return 0; 3593 } 3594 3595 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3596 struct snd_kcontrol *kc, int event) 3597 { 3598 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3599 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3600 3601 switch (event) { 3602 case SND_SOC_DAPM_PRE_PMU: 3603 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3604 WCD_CLSH_STATE_LO, CLS_AB); 3605 break; 3606 case SND_SOC_DAPM_POST_PMD: 3607 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3608 WCD_CLSH_STATE_LO, CLS_AB); 3609 break; 3610 } 3611 3612 return 0; 3613 } 3614 3615 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3616 struct snd_kcontrol *kc, int event) 3617 { 3618 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3619 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3620 3621 switch (event) { 3622 case SND_SOC_DAPM_PRE_PMU: 3623 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3624 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3625 3626 break; 3627 case SND_SOC_DAPM_POST_PMD: 3628 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3629 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3630 break; 3631 } 3632 3633 return 0; 3634 } 3635 3636 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3637 int mode, int event) 3638 { 3639 u8 scale_val = 0; 3640 3641 switch (event) { 3642 case SND_SOC_DAPM_POST_PMU: 3643 switch (mode) { 3644 case CLS_H_HIFI: 3645 scale_val = 0x3; 3646 break; 3647 case CLS_H_LOHIFI: 3648 scale_val = 0x1; 3649 break; 3650 } 3651 break; 3652 case SND_SOC_DAPM_PRE_PMD: 3653 scale_val = 0x6; 3654 break; 3655 } 3656 3657 if (scale_val) 3658 snd_soc_component_update_bits(wcd->component, 3659 WCD9335_HPH_PA_CTL1, 3660 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3661 scale_val << 1); 3662 if (SND_SOC_DAPM_EVENT_ON(event)) { 3663 if (wcd->comp_enabled[COMPANDER_1] || 3664 wcd->comp_enabled[COMPANDER_2]) { 3665 /* GAIN Source Selection */ 3666 snd_soc_component_update_bits(wcd->component, 3667 WCD9335_HPH_L_EN, 3668 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3669 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3670 snd_soc_component_update_bits(wcd->component, 3671 WCD9335_HPH_R_EN, 3672 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3673 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3674 snd_soc_component_update_bits(wcd->component, 3675 WCD9335_HPH_AUTO_CHOP, 3676 WCD9335_HPH_AUTO_CHOP_MASK, 3677 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3678 } 3679 snd_soc_component_update_bits(wcd->component, 3680 WCD9335_HPH_L_EN, 3681 WCD9335_HPH_PA_GAIN_MASK, 3682 wcd->hph_l_gain); 3683 snd_soc_component_update_bits(wcd->component, 3684 WCD9335_HPH_R_EN, 3685 WCD9335_HPH_PA_GAIN_MASK, 3686 wcd->hph_r_gain); 3687 } 3688 3689 if (SND_SOC_DAPM_EVENT_OFF(event)) 3690 snd_soc_component_update_bits(wcd->component, 3691 WCD9335_HPH_AUTO_CHOP, 3692 WCD9335_HPH_AUTO_CHOP_MASK, 3693 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3694 } 3695 3696 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3697 struct snd_kcontrol *kc, 3698 int event) 3699 { 3700 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3701 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3702 int hph_mode = wcd->hph_mode; 3703 u8 dem_inp; 3704 3705 switch (event) { 3706 case SND_SOC_DAPM_PRE_PMU: 3707 3708 /* Read DEM INP Select */ 3709 dem_inp = snd_soc_component_read(comp, 3710 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3711 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3712 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3713 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3714 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3715 hph_mode); 3716 return -EINVAL; 3717 } 3718 3719 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3720 WCD_CLSH_EVENT_PRE_DAC, 3721 WCD_CLSH_STATE_HPHR, 3722 ((hph_mode == CLS_H_LOHIFI) ? 3723 CLS_H_HIFI : hph_mode)); 3724 3725 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3726 3727 break; 3728 case SND_SOC_DAPM_POST_PMD: 3729 /* 1000us required as per HW requirement */ 3730 usleep_range(1000, 1100); 3731 3732 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3733 WCD_CLSH_STATE_HPHL)) 3734 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3735 3736 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3737 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3738 CLS_H_HIFI : hph_mode)); 3739 break; 3740 } 3741 3742 return 0; 3743 } 3744 3745 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3746 struct snd_kcontrol *kc, 3747 int event) 3748 { 3749 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3750 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3751 int hph_mode = wcd->hph_mode; 3752 3753 switch (event) { 3754 case SND_SOC_DAPM_PRE_PMU: 3755 break; 3756 case SND_SOC_DAPM_POST_PMU: 3757 /* 3758 * 7ms sleep is required after PA is enabled as per 3759 * HW requirement 3760 */ 3761 usleep_range(7000, 7100); 3762 3763 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3764 snd_soc_component_update_bits(comp, 3765 WCD9335_CDC_RX1_RX_PATH_CTL, 3766 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3767 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3768 3769 /* Remove mix path mute if it is enabled */ 3770 if ((snd_soc_component_read(comp, 3771 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3772 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3773 snd_soc_component_update_bits(comp, 3774 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3775 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3776 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3777 3778 break; 3779 case SND_SOC_DAPM_PRE_PMD: 3780 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3781 break; 3782 case SND_SOC_DAPM_POST_PMD: 3783 /* 5ms sleep is required after PA is disabled as per 3784 * HW requirement 3785 */ 3786 usleep_range(5000, 5500); 3787 break; 3788 } 3789 3790 return 0; 3791 } 3792 3793 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3794 struct snd_kcontrol *kc, 3795 int event) 3796 { 3797 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3798 int vol_reg = 0, mix_vol_reg = 0; 3799 3800 if (w->reg == WCD9335_ANA_LO_1_2) { 3801 if (w->shift == 7) { 3802 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3803 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3804 } else if (w->shift == 6) { 3805 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3806 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3807 } 3808 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3809 if (w->shift == 7) { 3810 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3811 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3812 } else if (w->shift == 6) { 3813 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3814 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3815 } 3816 } else { 3817 dev_err(comp->dev, "Error enabling lineout PA\n"); 3818 return -EINVAL; 3819 } 3820 3821 switch (event) { 3822 case SND_SOC_DAPM_POST_PMU: 3823 /* 5ms sleep is required after PA is enabled as per 3824 * HW requirement 3825 */ 3826 usleep_range(5000, 5500); 3827 snd_soc_component_update_bits(comp, vol_reg, 3828 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3829 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3830 3831 /* Remove mix path mute if it is enabled */ 3832 if ((snd_soc_component_read(comp, mix_vol_reg)) & 3833 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3834 snd_soc_component_update_bits(comp, mix_vol_reg, 3835 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3836 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3837 break; 3838 case SND_SOC_DAPM_POST_PMD: 3839 /* 5ms sleep is required after PA is disabled as per 3840 * HW requirement 3841 */ 3842 usleep_range(5000, 5500); 3843 break; 3844 } 3845 3846 return 0; 3847 } 3848 3849 static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3850 { 3851 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3852 WCD9335_HPH_CONST_SEL_L_MASK, 3853 WCD9335_HPH_CONST_SEL_L_BYPASS); 3854 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3855 WCD9335_HPH_CONST_SEL_L_MASK, 3856 WCD9335_HPH_CONST_SEL_L_BYPASS); 3857 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3858 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3859 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3860 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3861 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3862 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3863 } 3864 3865 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3866 struct snd_kcontrol *kc, int event) 3867 { 3868 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3869 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3870 3871 switch (event) { 3872 case SND_SOC_DAPM_PRE_PMU: 3873 wcd->rx_bias_count++; 3874 if (wcd->rx_bias_count == 1) { 3875 wcd9335_codec_init_flyback(comp); 3876 snd_soc_component_update_bits(comp, 3877 WCD9335_ANA_RX_SUPPLIES, 3878 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3879 WCD9335_ANA_RX_BIAS_ENABLE); 3880 } 3881 break; 3882 case SND_SOC_DAPM_POST_PMD: 3883 wcd->rx_bias_count--; 3884 if (!wcd->rx_bias_count) 3885 snd_soc_component_update_bits(comp, 3886 WCD9335_ANA_RX_SUPPLIES, 3887 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3888 WCD9335_ANA_RX_BIAS_DISABLE); 3889 break; 3890 } 3891 3892 return 0; 3893 } 3894 3895 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3896 struct snd_kcontrol *kc, int event) 3897 { 3898 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3899 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3900 int hph_mode = wcd->hph_mode; 3901 3902 switch (event) { 3903 case SND_SOC_DAPM_PRE_PMU: 3904 break; 3905 case SND_SOC_DAPM_POST_PMU: 3906 /* 3907 * 7ms sleep is required after PA is enabled as per 3908 * HW requirement 3909 */ 3910 usleep_range(7000, 7100); 3911 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3912 snd_soc_component_update_bits(comp, 3913 WCD9335_CDC_RX2_RX_PATH_CTL, 3914 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3915 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3916 /* Remove mix path mute if it is enabled */ 3917 if ((snd_soc_component_read(comp, 3918 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3919 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3920 snd_soc_component_update_bits(comp, 3921 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3922 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3923 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3924 3925 break; 3926 3927 case SND_SOC_DAPM_PRE_PMD: 3928 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3929 break; 3930 case SND_SOC_DAPM_POST_PMD: 3931 /* 5ms sleep is required after PA is disabled as per 3932 * HW requirement 3933 */ 3934 usleep_range(5000, 5500); 3935 break; 3936 } 3937 3938 return 0; 3939 } 3940 3941 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3942 struct snd_kcontrol *kc, int event) 3943 { 3944 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3945 3946 switch (event) { 3947 case SND_SOC_DAPM_POST_PMU: 3948 /* 5ms sleep is required after PA is enabled as per 3949 * HW requirement 3950 */ 3951 usleep_range(5000, 5500); 3952 snd_soc_component_update_bits(comp, 3953 WCD9335_CDC_RX0_RX_PATH_CTL, 3954 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3955 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3956 /* Remove mix path mute if it is enabled */ 3957 if ((snd_soc_component_read(comp, 3958 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3959 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3960 snd_soc_component_update_bits(comp, 3961 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3962 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3963 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3964 break; 3965 case SND_SOC_DAPM_POST_PMD: 3966 /* 5ms sleep is required after PA is disabled as per 3967 * HW requirement 3968 */ 3969 usleep_range(5000, 5500); 3970 3971 break; 3972 } 3973 3974 return 0; 3975 } 3976 3977 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3978 { 3979 struct wcd9335_codec *wcd = data; 3980 unsigned long status = 0; 3981 int i, j, port_id; 3982 unsigned int val, int_val = 0; 3983 irqreturn_t ret = IRQ_NONE; 3984 bool tx; 3985 unsigned short reg = 0; 3986 3987 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3988 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3989 regmap_read(wcd->if_regmap, i, &val); 3990 status |= ((u32)val << (8 * j)); 3991 } 3992 3993 for_each_set_bit(j, &status, 32) { 3994 tx = (j >= 16); 3995 port_id = (tx ? j - 16 : j); 3996 regmap_read(wcd->if_regmap, 3997 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3998 if (val) { 3999 if (!tx) 4000 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4001 (port_id / 8); 4002 else 4003 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4004 (port_id / 8); 4005 regmap_read( 4006 wcd->if_regmap, reg, &int_val); 4007 /* 4008 * Ignore interrupts for ports for which the 4009 * interrupts are not specifically enabled. 4010 */ 4011 if (!(int_val & (1 << (port_id % 8)))) 4012 continue; 4013 } 4014 4015 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 4016 dev_err_ratelimited(wcd->dev, 4017 "%s: overflow error on %s port %d, value %x\n", 4018 __func__, (tx ? "TX" : "RX"), port_id, val); 4019 4020 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 4021 dev_err_ratelimited(wcd->dev, 4022 "%s: underflow error on %s port %d, value %x\n", 4023 __func__, (tx ? "TX" : "RX"), port_id, val); 4024 4025 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 4026 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 4027 if (!tx) 4028 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4029 (port_id / 8); 4030 else 4031 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4032 (port_id / 8); 4033 regmap_read( 4034 wcd->if_regmap, reg, &int_val); 4035 if (int_val & (1 << (port_id % 8))) { 4036 int_val = int_val ^ (1 << (port_id % 8)); 4037 regmap_write(wcd->if_regmap, 4038 reg, int_val); 4039 } 4040 } 4041 4042 regmap_write(wcd->if_regmap, 4043 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 4044 BIT(j % 8)); 4045 ret = IRQ_HANDLED; 4046 } 4047 4048 return ret; 4049 } 4050 4051 static struct wcd9335_irq wcd9335_irqs[] = { 4052 { 4053 .irq = WCD9335_IRQ_SLIMBUS, 4054 .handler = wcd9335_slimbus_irq, 4055 .name = "SLIM Slave", 4056 }, 4057 }; 4058 4059 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 4060 { 4061 int irq, ret, i; 4062 4063 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 4064 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 4065 if (irq < 0) { 4066 dev_err(wcd->dev, "Failed to get %s\n", 4067 wcd9335_irqs[i].name); 4068 return irq; 4069 } 4070 4071 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4072 wcd9335_irqs[i].handler, 4073 IRQF_TRIGGER_RISING | 4074 IRQF_ONESHOT, 4075 wcd9335_irqs[i].name, wcd); 4076 if (ret) { 4077 dev_err(wcd->dev, "Failed to request %s\n", 4078 wcd9335_irqs[i].name); 4079 return ret; 4080 } 4081 } 4082 4083 /* enable interrupts on all slave ports */ 4084 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4085 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4086 0xFF); 4087 4088 return ret; 4089 } 4090 4091 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd) 4092 { 4093 int i; 4094 4095 /* disable interrupts on all slave ports */ 4096 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4097 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4098 0x00); 4099 } 4100 4101 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4102 bool ccl_flag) 4103 { 4104 struct snd_soc_component *comp = wcd->component; 4105 4106 if (ccl_flag) { 4107 if (++wcd->sido_ccl_cnt == 1) 4108 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4109 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4110 } else { 4111 if (wcd->sido_ccl_cnt == 0) { 4112 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4113 return; 4114 } 4115 if (--wcd->sido_ccl_cnt == 0) 4116 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4117 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4118 } 4119 } 4120 4121 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4122 { 4123 wcd->master_bias_users++; 4124 if (wcd->master_bias_users == 1) { 4125 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4126 WCD9335_ANA_BIAS_EN_MASK, 4127 WCD9335_ANA_BIAS_ENABLE); 4128 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4129 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4130 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4131 /* 4132 * 1ms delay is required after pre-charge is enabled 4133 * as per HW requirement 4134 */ 4135 usleep_range(1000, 1100); 4136 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4137 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4138 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4139 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4140 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4141 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4142 } 4143 4144 return 0; 4145 } 4146 4147 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4148 { 4149 /* Enable mclk requires master bias to be enabled first */ 4150 if (wcd->master_bias_users <= 0) 4151 return -EINVAL; 4152 4153 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4154 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4155 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4156 wcd->clk_type); 4157 return -EINVAL; 4158 } 4159 4160 if (++wcd->clk_mclk_users == 1) { 4161 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4162 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4163 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4164 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4165 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4166 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4167 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4168 WCD9335_ANA_CLK_MCLK_EN_MASK, 4169 WCD9335_ANA_CLK_MCLK_ENABLE); 4170 regmap_update_bits(wcd->regmap, 4171 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4172 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4173 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4174 regmap_update_bits(wcd->regmap, 4175 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4176 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4177 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4178 /* 4179 * 10us sleep is required after clock is enabled 4180 * as per HW requirement 4181 */ 4182 usleep_range(10, 15); 4183 } 4184 4185 wcd->clk_type = WCD_CLK_MCLK; 4186 4187 return 0; 4188 } 4189 4190 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4191 { 4192 if (wcd->clk_mclk_users <= 0) 4193 return -EINVAL; 4194 4195 if (--wcd->clk_mclk_users == 0) { 4196 if (wcd->clk_rco_users > 0) { 4197 /* MCLK to RCO switch */ 4198 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4199 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4200 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4201 wcd->clk_type = WCD_CLK_RCO; 4202 } else { 4203 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4204 WCD9335_ANA_CLK_MCLK_EN_MASK, 4205 WCD9335_ANA_CLK_MCLK_DISABLE); 4206 wcd->clk_type = WCD_CLK_OFF; 4207 } 4208 4209 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4210 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4211 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4212 } 4213 4214 return 0; 4215 } 4216 4217 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4218 { 4219 if (wcd->master_bias_users <= 0) 4220 return -EINVAL; 4221 4222 wcd->master_bias_users--; 4223 if (wcd->master_bias_users == 0) { 4224 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4225 WCD9335_ANA_BIAS_EN_MASK, 4226 WCD9335_ANA_BIAS_DISABLE); 4227 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4228 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4229 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4230 } 4231 return 0; 4232 } 4233 4234 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4235 bool enable) 4236 { 4237 int ret = 0; 4238 4239 if (enable) { 4240 wcd9335_cdc_sido_ccl_enable(wcd, true); 4241 ret = clk_prepare_enable(wcd->mclk); 4242 if (ret) { 4243 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4244 __func__); 4245 goto err; 4246 } 4247 /* get BG */ 4248 wcd9335_enable_master_bias(wcd); 4249 /* get MCLK */ 4250 wcd9335_enable_mclk(wcd); 4251 4252 } else { 4253 /* put MCLK */ 4254 wcd9335_disable_mclk(wcd); 4255 /* put BG */ 4256 wcd9335_disable_master_bias(wcd); 4257 clk_disable_unprepare(wcd->mclk); 4258 wcd9335_cdc_sido_ccl_enable(wcd, false); 4259 } 4260 err: 4261 return ret; 4262 } 4263 4264 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4265 enum wcd9335_sido_voltage req_mv) 4266 { 4267 struct snd_soc_component *comp = wcd->component; 4268 int vout_d_val; 4269 4270 if (req_mv == wcd->sido_voltage) 4271 return; 4272 4273 /* compute the vout_d step value */ 4274 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4275 WCD9335_ANA_BUCK_VOUT_MASK; 4276 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4277 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4278 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4279 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4280 4281 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4282 usleep_range(1000, 1100); 4283 wcd->sido_voltage = req_mv; 4284 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4285 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4286 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4287 } 4288 4289 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4290 enum wcd9335_sido_voltage req_mv) 4291 { 4292 int ret = 0; 4293 4294 /* enable mclk before setting SIDO voltage */ 4295 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4296 if (ret) { 4297 dev_err(wcd->dev, "Ext clk enable failed\n"); 4298 goto err; 4299 } 4300 4301 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4302 wcd9335_cdc_req_mclk_enable(wcd, false); 4303 4304 err: 4305 return ret; 4306 } 4307 4308 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4309 int enable) 4310 { 4311 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4312 int ret; 4313 4314 if (enable) { 4315 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4316 if (ret) 4317 return ret; 4318 4319 wcd9335_codec_apply_sido_voltage(wcd, 4320 SIDO_VOLTAGE_NOMINAL_MV); 4321 } else { 4322 wcd9335_codec_update_sido_voltage(wcd, 4323 wcd->sido_voltage); 4324 wcd9335_cdc_req_mclk_enable(wcd, false); 4325 } 4326 4327 return 0; 4328 } 4329 4330 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4331 struct snd_kcontrol *kc, int event) 4332 { 4333 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4334 4335 switch (event) { 4336 case SND_SOC_DAPM_PRE_PMU: 4337 return _wcd9335_codec_enable_mclk(comp, true); 4338 case SND_SOC_DAPM_POST_PMD: 4339 return _wcd9335_codec_enable_mclk(comp, false); 4340 } 4341 4342 return 0; 4343 } 4344 4345 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4346 /* TODO SPK1 & SPK2 OUT*/ 4347 SND_SOC_DAPM_OUTPUT("EAR"), 4348 SND_SOC_DAPM_OUTPUT("HPHL"), 4349 SND_SOC_DAPM_OUTPUT("HPHR"), 4350 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4351 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4352 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4353 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4354 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4355 AIF1_PB, 0, wcd9335_codec_enable_slim, 4356 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4357 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4358 AIF2_PB, 0, wcd9335_codec_enable_slim, 4359 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4360 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4361 AIF3_PB, 0, wcd9335_codec_enable_slim, 4362 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4363 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4364 AIF4_PB, 0, wcd9335_codec_enable_slim, 4365 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4366 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4367 &slim_rx_mux[WCD9335_RX0]), 4368 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4369 &slim_rx_mux[WCD9335_RX1]), 4370 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4371 &slim_rx_mux[WCD9335_RX2]), 4372 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4373 &slim_rx_mux[WCD9335_RX3]), 4374 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4375 &slim_rx_mux[WCD9335_RX4]), 4376 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4377 &slim_rx_mux[WCD9335_RX5]), 4378 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4379 &slim_rx_mux[WCD9335_RX6]), 4380 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4381 &slim_rx_mux[WCD9335_RX7]), 4382 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4383 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4384 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4385 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4386 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4387 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4388 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4389 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4390 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4391 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4392 SND_SOC_DAPM_POST_PMU), 4393 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4394 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4395 SND_SOC_DAPM_POST_PMU), 4396 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4397 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4398 SND_SOC_DAPM_POST_PMU), 4399 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4400 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4401 SND_SOC_DAPM_POST_PMU), 4402 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4403 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4404 SND_SOC_DAPM_POST_PMU), 4405 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4406 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4407 SND_SOC_DAPM_POST_PMU), 4408 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4409 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4410 SND_SOC_DAPM_POST_PMU), 4411 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4412 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4413 SND_SOC_DAPM_POST_PMU), 4414 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4415 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4416 SND_SOC_DAPM_POST_PMU), 4417 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4418 &rx_int0_1_mix_inp0_mux), 4419 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4420 &rx_int0_1_mix_inp1_mux), 4421 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4422 &rx_int0_1_mix_inp2_mux), 4423 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4424 &rx_int1_1_mix_inp0_mux), 4425 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4426 &rx_int1_1_mix_inp1_mux), 4427 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4428 &rx_int1_1_mix_inp2_mux), 4429 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4430 &rx_int2_1_mix_inp0_mux), 4431 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4432 &rx_int2_1_mix_inp1_mux), 4433 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4434 &rx_int2_1_mix_inp2_mux), 4435 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4436 &rx_int3_1_mix_inp0_mux), 4437 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4438 &rx_int3_1_mix_inp1_mux), 4439 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4440 &rx_int3_1_mix_inp2_mux), 4441 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4442 &rx_int4_1_mix_inp0_mux), 4443 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4444 &rx_int4_1_mix_inp1_mux), 4445 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4446 &rx_int4_1_mix_inp2_mux), 4447 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4448 &rx_int5_1_mix_inp0_mux), 4449 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4450 &rx_int5_1_mix_inp1_mux), 4451 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4452 &rx_int5_1_mix_inp2_mux), 4453 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4454 &rx_int6_1_mix_inp0_mux), 4455 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4456 &rx_int6_1_mix_inp1_mux), 4457 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4458 &rx_int6_1_mix_inp2_mux), 4459 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4460 &rx_int7_1_mix_inp0_mux), 4461 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4462 &rx_int7_1_mix_inp1_mux), 4463 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4464 &rx_int7_1_mix_inp2_mux), 4465 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4466 &rx_int8_1_mix_inp0_mux), 4467 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4468 &rx_int8_1_mix_inp1_mux), 4469 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4470 &rx_int8_1_mix_inp2_mux), 4471 4472 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4473 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4474 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4475 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4476 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4477 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4478 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4479 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4480 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4481 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4482 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4483 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4484 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4485 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4486 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4487 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4488 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4489 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4490 4491 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4492 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4493 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4494 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4495 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4496 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4497 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4498 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4499 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4500 4501 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4502 &rx_int0_dem_inp_mux), 4503 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4504 &rx_int1_dem_inp_mux), 4505 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4506 &rx_int2_dem_inp_mux), 4507 4508 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4509 INTERP_EAR, 0, &rx_int0_interp_mux, 4510 wcd9335_codec_enable_interpolator, 4511 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4512 SND_SOC_DAPM_POST_PMD), 4513 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4514 INTERP_HPHL, 0, &rx_int1_interp_mux, 4515 wcd9335_codec_enable_interpolator, 4516 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4517 SND_SOC_DAPM_POST_PMD), 4518 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4519 INTERP_HPHR, 0, &rx_int2_interp_mux, 4520 wcd9335_codec_enable_interpolator, 4521 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4522 SND_SOC_DAPM_POST_PMD), 4523 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4524 INTERP_LO1, 0, &rx_int3_interp_mux, 4525 wcd9335_codec_enable_interpolator, 4526 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4527 SND_SOC_DAPM_POST_PMD), 4528 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4529 INTERP_LO2, 0, &rx_int4_interp_mux, 4530 wcd9335_codec_enable_interpolator, 4531 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4532 SND_SOC_DAPM_POST_PMD), 4533 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4534 INTERP_LO3, 0, &rx_int5_interp_mux, 4535 wcd9335_codec_enable_interpolator, 4536 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4537 SND_SOC_DAPM_POST_PMD), 4538 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4539 INTERP_LO4, 0, &rx_int6_interp_mux, 4540 wcd9335_codec_enable_interpolator, 4541 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4542 SND_SOC_DAPM_POST_PMD), 4543 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4544 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4545 wcd9335_codec_enable_interpolator, 4546 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4547 SND_SOC_DAPM_POST_PMD), 4548 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4549 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4550 wcd9335_codec_enable_interpolator, 4551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4552 SND_SOC_DAPM_POST_PMD), 4553 4554 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4555 0, 0, wcd9335_codec_ear_dac_event, 4556 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4557 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4558 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4559 5, 0, wcd9335_codec_hphl_dac_event, 4560 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4561 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4562 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4563 4, 0, wcd9335_codec_hphr_dac_event, 4564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4565 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4566 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4567 0, 0, wcd9335_codec_lineout_dac_event, 4568 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4569 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4570 0, 0, wcd9335_codec_lineout_dac_event, 4571 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4572 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4573 0, 0, wcd9335_codec_lineout_dac_event, 4574 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4575 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4576 0, 0, wcd9335_codec_lineout_dac_event, 4577 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4578 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4579 wcd9335_codec_enable_hphl_pa, 4580 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4581 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4582 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4583 wcd9335_codec_enable_hphr_pa, 4584 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4585 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4586 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4587 wcd9335_codec_enable_ear_pa, 4588 SND_SOC_DAPM_POST_PMU | 4589 SND_SOC_DAPM_POST_PMD), 4590 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4591 wcd9335_codec_enable_lineout_pa, 4592 SND_SOC_DAPM_POST_PMU | 4593 SND_SOC_DAPM_POST_PMD), 4594 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4595 wcd9335_codec_enable_lineout_pa, 4596 SND_SOC_DAPM_POST_PMU | 4597 SND_SOC_DAPM_POST_PMD), 4598 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4599 wcd9335_codec_enable_lineout_pa, 4600 SND_SOC_DAPM_POST_PMU | 4601 SND_SOC_DAPM_POST_PMD), 4602 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4603 wcd9335_codec_enable_lineout_pa, 4604 SND_SOC_DAPM_POST_PMU | 4605 SND_SOC_DAPM_POST_PMD), 4606 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4607 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4608 SND_SOC_DAPM_POST_PMD), 4609 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4610 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4611 SND_SOC_DAPM_POST_PMD), 4612 4613 /* TX */ 4614 SND_SOC_DAPM_INPUT("AMIC1"), 4615 SND_SOC_DAPM_INPUT("AMIC2"), 4616 SND_SOC_DAPM_INPUT("AMIC3"), 4617 SND_SOC_DAPM_INPUT("AMIC4"), 4618 SND_SOC_DAPM_INPUT("AMIC5"), 4619 SND_SOC_DAPM_INPUT("AMIC6"), 4620 4621 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4622 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4623 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4624 4625 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4626 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4627 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4628 4629 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4630 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4631 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4632 4633 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4634 wcd9335_codec_enable_micbias, 4635 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4636 SND_SOC_DAPM_POST_PMD), 4637 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4638 wcd9335_codec_enable_micbias, 4639 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4640 SND_SOC_DAPM_POST_PMD), 4641 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4642 wcd9335_codec_enable_micbias, 4643 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4644 SND_SOC_DAPM_POST_PMD), 4645 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4646 wcd9335_codec_enable_micbias, 4647 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4648 SND_SOC_DAPM_POST_PMD), 4649 4650 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4651 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4652 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4653 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4654 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4655 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4656 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4657 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4658 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4659 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4660 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4661 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4662 4663 /* Digital Mic Inputs */ 4664 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4665 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4666 SND_SOC_DAPM_POST_PMD), 4667 4668 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4669 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4670 SND_SOC_DAPM_POST_PMD), 4671 4672 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4673 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4674 SND_SOC_DAPM_POST_PMD), 4675 4676 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4677 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4678 SND_SOC_DAPM_POST_PMD), 4679 4680 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4681 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4682 SND_SOC_DAPM_POST_PMD), 4683 4684 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4685 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4686 SND_SOC_DAPM_POST_PMD), 4687 4688 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4689 &tx_dmic_mux0), 4690 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4691 &tx_dmic_mux1), 4692 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4693 &tx_dmic_mux2), 4694 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4695 &tx_dmic_mux3), 4696 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4697 &tx_dmic_mux4), 4698 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4699 &tx_dmic_mux5), 4700 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4701 &tx_dmic_mux6), 4702 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4703 &tx_dmic_mux7), 4704 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4705 &tx_dmic_mux8), 4706 4707 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4708 &tx_amic_mux0), 4709 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4710 &tx_amic_mux1), 4711 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4712 &tx_amic_mux2), 4713 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4714 &tx_amic_mux3), 4715 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4716 &tx_amic_mux4), 4717 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4718 &tx_amic_mux5), 4719 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4720 &tx_amic_mux6), 4721 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4722 &tx_amic_mux7), 4723 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4724 &tx_amic_mux8), 4725 4726 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4727 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4728 4729 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4730 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4731 4732 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4733 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4734 4735 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4736 &sb_tx0_mux), 4737 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4738 &sb_tx1_mux), 4739 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4740 &sb_tx2_mux), 4741 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4742 &sb_tx3_mux), 4743 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4744 &sb_tx4_mux), 4745 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4746 &sb_tx5_mux), 4747 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4748 &sb_tx6_mux), 4749 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4750 &sb_tx7_mux), 4751 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4752 &sb_tx8_mux), 4753 4754 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4755 &tx_adc_mux0, wcd9335_codec_enable_dec, 4756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4757 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4758 4759 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4760 &tx_adc_mux1, wcd9335_codec_enable_dec, 4761 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4762 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4763 4764 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4765 &tx_adc_mux2, wcd9335_codec_enable_dec, 4766 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4767 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4768 4769 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4770 &tx_adc_mux3, wcd9335_codec_enable_dec, 4771 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4772 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4773 4774 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4775 &tx_adc_mux4, wcd9335_codec_enable_dec, 4776 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4777 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4778 4779 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4780 &tx_adc_mux5, wcd9335_codec_enable_dec, 4781 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4782 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4783 4784 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4785 &tx_adc_mux6, wcd9335_codec_enable_dec, 4786 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4787 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4788 4789 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4790 &tx_adc_mux7, wcd9335_codec_enable_dec, 4791 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4792 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4793 4794 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4795 &tx_adc_mux8, wcd9335_codec_enable_dec, 4796 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4797 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4798 }; 4799 4800 static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4801 { 4802 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4803 4804 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4805 WCD9335_ANA_RCO_BG_EN_MASK, 4806 WCD9335_ANA_RCO_BG_ENABLE); 4807 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4808 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4809 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4810 /* 100us sleep needed after IREF settings */ 4811 usleep_range(100, 110); 4812 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4813 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4814 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4815 /* 100us sleep needed after VREF settings */ 4816 usleep_range(100, 110); 4817 wcd->sido_input_src = SIDO_SOURCE_RCO_BG; 4818 } 4819 4820 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4821 { 4822 _wcd9335_codec_enable_mclk(comp, true); 4823 snd_soc_component_update_bits(comp, 4824 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4825 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4826 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4827 /* 4828 * 5ms sleep required after enabling efuse control 4829 * before checking the status. 4830 */ 4831 usleep_range(5000, 5500); 4832 4833 if (!(snd_soc_component_read(comp, 4834 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4835 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4836 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4837 4838 wcd9335_enable_sido_buck(comp); 4839 _wcd9335_codec_enable_mclk(comp, false); 4840 4841 return 0; 4842 } 4843 4844 static void wcd9335_codec_init(struct snd_soc_component *component) 4845 { 4846 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4847 int i; 4848 4849 /* ungate MCLK and set clk rate */ 4850 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4851 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4852 4853 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4854 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4855 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4856 4857 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4858 snd_soc_component_update_bits(component, 4859 wcd9335_codec_reg_init[i].reg, 4860 wcd9335_codec_reg_init[i].mask, 4861 wcd9335_codec_reg_init[i].val); 4862 4863 wcd9335_enable_efuse_sensing(component); 4864 } 4865 4866 static int wcd9335_codec_probe(struct snd_soc_component *component) 4867 { 4868 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4869 int ret; 4870 int i; 4871 4872 snd_soc_component_init_regmap(component, wcd->regmap); 4873 /* Class-H Init*/ 4874 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335); 4875 if (IS_ERR(wcd->clsh_ctrl)) 4876 return PTR_ERR(wcd->clsh_ctrl); 4877 4878 /* Default HPH Mode to Class-H HiFi */ 4879 wcd->hph_mode = CLS_H_HIFI; 4880 wcd->component = component; 4881 4882 wcd9335_codec_init(component); 4883 4884 for (i = 0; i < NUM_CODEC_DAIS; i++) 4885 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4886 4887 ret = wcd9335_setup_irqs(wcd); 4888 if (ret) 4889 goto free_clsh_ctrl; 4890 4891 return 0; 4892 4893 free_clsh_ctrl: 4894 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4895 return ret; 4896 } 4897 4898 static void wcd9335_codec_remove(struct snd_soc_component *comp) 4899 { 4900 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4901 4902 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4903 wcd9335_teardown_irqs(wcd); 4904 } 4905 4906 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4907 int clk_id, int source, 4908 unsigned int freq, int dir) 4909 { 4910 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4911 4912 wcd->mclk_rate = freq; 4913 4914 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4915 snd_soc_component_update_bits(comp, 4916 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4917 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4918 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4919 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4920 snd_soc_component_update_bits(comp, 4921 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4922 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4923 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4924 4925 return clk_set_rate(wcd->mclk, freq); 4926 } 4927 4928 static const struct snd_soc_component_driver wcd9335_component_drv = { 4929 .probe = wcd9335_codec_probe, 4930 .remove = wcd9335_codec_remove, 4931 .set_sysclk = wcd9335_codec_set_sysclk, 4932 .controls = wcd9335_snd_controls, 4933 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4934 .dapm_widgets = wcd9335_dapm_widgets, 4935 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4936 .dapm_routes = wcd9335_audio_map, 4937 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4938 .endianness = 1, 4939 }; 4940 4941 static int wcd9335_probe(struct wcd9335_codec *wcd) 4942 { 4943 struct device *dev = wcd->dev; 4944 4945 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4946 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4947 4948 wcd->sido_input_src = SIDO_SOURCE_INTERNAL; 4949 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4950 4951 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4952 wcd9335_slim_dais, 4953 ARRAY_SIZE(wcd9335_slim_dais)); 4954 } 4955 4956 static const struct regmap_range_cfg wcd9335_ranges[] = { 4957 { 4958 .name = "WCD9335", 4959 .range_min = 0x0, 4960 .range_max = WCD9335_MAX_REGISTER, 4961 .selector_reg = WCD9335_SEL_REGISTER, 4962 .selector_mask = 0xff, 4963 .selector_shift = 0, 4964 .window_start = 0x800, 4965 .window_len = 0x100, 4966 }, 4967 }; 4968 4969 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4970 { 4971 switch (reg) { 4972 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4973 case WCD9335_ANA_MBHC_RESULT_3: 4974 case WCD9335_ANA_MBHC_RESULT_2: 4975 case WCD9335_ANA_MBHC_RESULT_1: 4976 case WCD9335_ANA_MBHC_MECH: 4977 case WCD9335_ANA_MBHC_ELECT: 4978 case WCD9335_ANA_MBHC_ZDET: 4979 case WCD9335_ANA_MICB2: 4980 case WCD9335_ANA_RCO: 4981 case WCD9335_ANA_BIAS: 4982 return true; 4983 default: 4984 return false; 4985 } 4986 } 4987 4988 static struct regmap_config wcd9335_regmap_config = { 4989 .reg_bits = 16, 4990 .val_bits = 8, 4991 .cache_type = REGCACHE_RBTREE, 4992 .max_register = WCD9335_MAX_REGISTER, 4993 .can_multi_write = true, 4994 .ranges = wcd9335_ranges, 4995 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4996 .volatile_reg = wcd9335_is_volatile_register, 4997 }; 4998 4999 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 5000 { 5001 .name = "WCD9335-IFC-DEV", 5002 .range_min = 0x0, 5003 .range_max = WCD9335_MAX_REGISTER, 5004 .selector_reg = WCD9335_SEL_REGISTER, 5005 .selector_mask = 0xfff, 5006 .selector_shift = 0, 5007 .window_start = 0x800, 5008 .window_len = 0x400, 5009 }, 5010 }; 5011 5012 static struct regmap_config wcd9335_ifc_regmap_config = { 5013 .reg_bits = 16, 5014 .val_bits = 8, 5015 .can_multi_write = true, 5016 .max_register = WCD9335_MAX_REGISTER, 5017 .ranges = wcd9335_ifc_ranges, 5018 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 5019 }; 5020 5021 static const struct regmap_irq wcd9335_codec_irqs[] = { 5022 /* INTR_REG 0 */ 5023 [WCD9335_IRQ_SLIMBUS] = { 5024 .reg_offset = 0, 5025 .mask = BIT(0), 5026 .type = { 5027 .type_reg_offset = 0, 5028 .types_supported = IRQ_TYPE_EDGE_BOTH, 5029 .type_reg_mask = BIT(0), 5030 }, 5031 }, 5032 }; 5033 5034 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 5035 .name = "wcd9335_pin1_irq", 5036 .status_base = WCD9335_INTR_PIN1_STATUS0, 5037 .mask_base = WCD9335_INTR_PIN1_MASK0, 5038 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 5039 .type_base = WCD9335_INTR_LEVEL0, 5040 .num_type_reg = 4, 5041 .num_regs = 4, 5042 .irqs = wcd9335_codec_irqs, 5043 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 5044 }; 5045 5046 static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 5047 { 5048 struct device *dev = wcd->dev; 5049 struct device_node *np = dev->of_node; 5050 int ret; 5051 5052 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 5053 if (wcd->reset_gpio < 0) { 5054 dev_err(dev, "Reset GPIO missing from DT\n"); 5055 return wcd->reset_gpio; 5056 } 5057 5058 wcd->mclk = devm_clk_get(dev, "mclk"); 5059 if (IS_ERR(wcd->mclk)) { 5060 dev_err(dev, "mclk not found\n"); 5061 return PTR_ERR(wcd->mclk); 5062 } 5063 5064 wcd->native_clk = devm_clk_get(dev, "slimbus"); 5065 if (IS_ERR(wcd->native_clk)) { 5066 dev_err(dev, "slimbus clock not found\n"); 5067 return PTR_ERR(wcd->native_clk); 5068 } 5069 5070 wcd->supplies[0].supply = "vdd-buck"; 5071 wcd->supplies[1].supply = "vdd-buck-sido"; 5072 wcd->supplies[2].supply = "vdd-tx"; 5073 wcd->supplies[3].supply = "vdd-rx"; 5074 wcd->supplies[4].supply = "vdd-io"; 5075 5076 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies); 5077 if (ret) { 5078 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5079 return ret; 5080 } 5081 5082 return 0; 5083 } 5084 5085 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5086 { 5087 struct device *dev = wcd->dev; 5088 int ret; 5089 5090 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies); 5091 if (ret) { 5092 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5093 return ret; 5094 } 5095 5096 /* 5097 * For WCD9335, it takes about 600us for the Vout_A and 5098 * Vout_D to be ready after BUCK_SIDO is powered up. 5099 * SYS_RST_N shouldn't be pulled high during this time 5100 * Toggle the reset line to make sure the reset pulse is 5101 * correctly applied 5102 */ 5103 usleep_range(600, 650); 5104 5105 gpio_direction_output(wcd->reset_gpio, 0); 5106 msleep(20); 5107 gpio_set_value(wcd->reset_gpio, 1); 5108 msleep(20); 5109 5110 return 0; 5111 } 5112 5113 static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5114 { 5115 struct regmap *rm = wcd->regmap; 5116 int val, byte0; 5117 5118 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5119 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5120 5121 if ((val < 0) || (byte0 < 0)) { 5122 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5123 return -EINVAL; 5124 } 5125 5126 if (byte0 == 0x1) { 5127 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5128 wcd->version = WCD9335_VERSION_2_0; 5129 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5130 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5131 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5132 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5133 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5134 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5135 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5136 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5137 } else { 5138 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5139 return -EINVAL; 5140 } 5141 5142 return 0; 5143 } 5144 5145 static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5146 { 5147 int ret; 5148 5149 /* 5150 * INTR1 consists of all possible interrupt sources Ear OCP, 5151 * HPH OCP, MBHC, MAD, VBAT, and SVA 5152 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5153 */ 5154 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5155 if (wcd->intr1 < 0) { 5156 if (wcd->intr1 != -EPROBE_DEFER) 5157 dev_err(wcd->dev, "Unable to configure IRQ\n"); 5158 5159 return wcd->intr1; 5160 } 5161 5162 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5163 IRQF_TRIGGER_HIGH, 0, 5164 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5165 if (ret) 5166 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret); 5167 5168 return ret; 5169 } 5170 5171 static int wcd9335_slim_probe(struct slim_device *slim) 5172 { 5173 struct device *dev = &slim->dev; 5174 struct wcd9335_codec *wcd; 5175 int ret; 5176 5177 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5178 if (!wcd) 5179 return -ENOMEM; 5180 5181 wcd->dev = dev; 5182 ret = wcd9335_parse_dt(wcd); 5183 if (ret) { 5184 dev_err(dev, "Error parsing DT: %d\n", ret); 5185 return ret; 5186 } 5187 5188 ret = wcd9335_power_on_reset(wcd); 5189 if (ret) 5190 return ret; 5191 5192 dev_set_drvdata(dev, wcd); 5193 5194 return 0; 5195 } 5196 5197 static int wcd9335_slim_status(struct slim_device *sdev, 5198 enum slim_device_status status) 5199 { 5200 struct device *dev = &sdev->dev; 5201 struct device_node *ifc_dev_np; 5202 struct wcd9335_codec *wcd; 5203 int ret; 5204 5205 wcd = dev_get_drvdata(dev); 5206 5207 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5208 if (!ifc_dev_np) { 5209 dev_err(dev, "No Interface device found\n"); 5210 return -EINVAL; 5211 } 5212 5213 wcd->slim = sdev; 5214 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5215 of_node_put(ifc_dev_np); 5216 if (!wcd->slim_ifc_dev) { 5217 dev_err(dev, "Unable to get SLIM Interface device\n"); 5218 return -EINVAL; 5219 } 5220 5221 slim_get_logical_addr(wcd->slim_ifc_dev); 5222 5223 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5224 if (IS_ERR(wcd->regmap)) { 5225 dev_err(dev, "Failed to allocate slim register map\n"); 5226 return PTR_ERR(wcd->regmap); 5227 } 5228 5229 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5230 &wcd9335_ifc_regmap_config); 5231 if (IS_ERR(wcd->if_regmap)) { 5232 dev_err(dev, "Failed to allocate ifc register map\n"); 5233 return PTR_ERR(wcd->if_regmap); 5234 } 5235 5236 ret = wcd9335_bring_up(wcd); 5237 if (ret) { 5238 dev_err(dev, "Failed to bringup WCD9335\n"); 5239 return ret; 5240 } 5241 5242 ret = wcd9335_irq_init(wcd); 5243 if (ret) 5244 return ret; 5245 5246 wcd9335_probe(wcd); 5247 5248 return 0; 5249 } 5250 5251 static const struct slim_device_id wcd9335_slim_id[] = { 5252 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5253 {} 5254 }; 5255 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5256 5257 static struct slim_driver wcd9335_slim_driver = { 5258 .driver = { 5259 .name = "wcd9335-slim", 5260 }, 5261 .probe = wcd9335_slim_probe, 5262 .device_status = wcd9335_slim_status, 5263 .id_table = wcd9335_slim_id, 5264 }; 5265 5266 module_slim_driver(wcd9335_slim_driver); 5267 MODULE_DESCRIPTION("WCD9335 slim driver"); 5268 MODULE_LICENSE("GPL v2"); 5269 MODULE_ALIAS("slim:217:1a0:*"); 5270