1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2017-2018, Linaro Limited 4 5 #include <linux/module.h> 6 #include <linux/init.h> 7 #include <linux/platform_device.h> 8 #include <linux/device.h> 9 #include <linux/wait.h> 10 #include <linux/bitops.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/slimbus.h> 16 #include <sound/soc.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <sound/tlv.h> 23 #include <sound/info.h> 24 #include "wcd9335.h" 25 #include "wcd-clsh-v2.h" 26 27 #include <dt-bindings/sound/qcom,wcd9335.h> 28 29 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 30 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 31 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 32 /* Fractional Rates */ 33 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 34 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 35 SNDRV_PCM_FMTBIT_S24_LE) 36 37 /* slave port water mark level 38 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 39 */ 40 #define SLAVE_PORT_WATER_MARK_6BYTES 0 41 #define SLAVE_PORT_WATER_MARK_9BYTES 1 42 #define SLAVE_PORT_WATER_MARK_12BYTES 2 43 #define SLAVE_PORT_WATER_MARK_15BYTES 3 44 #define SLAVE_PORT_WATER_MARK_SHIFT 1 45 #define SLAVE_PORT_ENABLE 1 46 #define SLAVE_PORT_DISABLE 0 47 #define WCD9335_SLIM_WATER_MARK_VAL \ 48 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 49 (SLAVE_PORT_ENABLE)) 50 51 #define WCD9335_SLIM_NUM_PORT_REG 3 52 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 53 54 #define WCD9335_MCLK_CLK_12P288MHZ 12288000 55 #define WCD9335_MCLK_CLK_9P6MHZ 9600000 56 57 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000 58 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 59 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 60 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 61 62 #define WCD9335_NUM_INTERPOLATORS 9 63 #define WCD9335_RX_START 16 64 #define WCD9335_SLIM_CH_START 128 65 #define WCD9335_MAX_MICBIAS 4 66 #define WCD9335_MAX_VALID_ADC_MUX 13 67 #define WCD9335_INVALID_ADC_MUX 9 68 69 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 70 #define CF_MIN_3DB_4HZ 0x0 71 #define CF_MIN_3DB_75HZ 0x1 72 #define CF_MIN_3DB_150HZ 0x2 73 #define WCD9335_DMIC_CLK_DIV_2 0x0 74 #define WCD9335_DMIC_CLK_DIV_3 0x1 75 #define WCD9335_DMIC_CLK_DIV_4 0x2 76 #define WCD9335_DMIC_CLK_DIV_6 0x3 77 #define WCD9335_DMIC_CLK_DIV_8 0x4 78 #define WCD9335_DMIC_CLK_DIV_16 0x5 79 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 80 #define WCD9335_AMIC_PWR_LEVEL_LP 0 81 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 82 #define WCD9335_AMIC_PWR_LEVEL_HP 2 83 #define WCD9335_AMIC_PWR_LVL_MASK 0x60 84 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 85 86 #define WCD9335_DEC_PWR_LVL_MASK 0x06 87 #define WCD9335_DEC_PWR_LVL_LP 0x02 88 #define WCD9335_DEC_PWR_LVL_HP 0x04 89 #define WCD9335_DEC_PWR_LVL_DF 0x00 90 91 #define WCD9335_SLIM_RX_CH(p) \ 92 {.port = p + WCD9335_RX_START, .shift = p,} 93 94 #define WCD9335_SLIM_TX_CH(p) \ 95 {.port = p, .shift = p,} 96 97 /* vout step value */ 98 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 99 100 #define WCD9335_INTERPOLATOR_PATH(id) \ 101 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 107 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 108 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 109 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 115 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 116 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 117 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 123 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 124 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 125 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 126 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 127 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 128 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 129 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 130 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 131 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 132 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 136 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 138 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 139 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 140 141 #define WCD9335_ADC_MUX_PATH(id) \ 142 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 143 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 144 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 145 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 146 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 147 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 148 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 149 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 150 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 151 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 152 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 153 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 154 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 155 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 156 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 157 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 158 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 159 {"AMIC MUX" #id, "ADC6", "ADC6"} 160 161 enum { 162 WCD9335_RX0 = 0, 163 WCD9335_RX1, 164 WCD9335_RX2, 165 WCD9335_RX3, 166 WCD9335_RX4, 167 WCD9335_RX5, 168 WCD9335_RX6, 169 WCD9335_RX7, 170 WCD9335_RX8, 171 WCD9335_RX9, 172 WCD9335_RX10, 173 WCD9335_RX11, 174 WCD9335_RX12, 175 WCD9335_RX_MAX, 176 }; 177 178 enum { 179 WCD9335_TX0 = 0, 180 WCD9335_TX1, 181 WCD9335_TX2, 182 WCD9335_TX3, 183 WCD9335_TX4, 184 WCD9335_TX5, 185 WCD9335_TX6, 186 WCD9335_TX7, 187 WCD9335_TX8, 188 WCD9335_TX9, 189 WCD9335_TX10, 190 WCD9335_TX11, 191 WCD9335_TX12, 192 WCD9335_TX13, 193 WCD9335_TX14, 194 WCD9335_TX15, 195 WCD9335_TX_MAX, 196 }; 197 198 enum { 199 SIDO_SOURCE_INTERNAL = 0, 200 SIDO_SOURCE_RCO_BG, 201 }; 202 203 enum wcd9335_sido_voltage { 204 SIDO_VOLTAGE_SVS_MV = 950, 205 SIDO_VOLTAGE_NOMINAL_MV = 1100, 206 }; 207 208 enum { 209 COMPANDER_1, /* HPH_L */ 210 COMPANDER_2, /* HPH_R */ 211 COMPANDER_3, /* LO1_DIFF */ 212 COMPANDER_4, /* LO2_DIFF */ 213 COMPANDER_5, /* LO3_SE */ 214 COMPANDER_6, /* LO4_SE */ 215 COMPANDER_7, /* SWR SPK CH1 */ 216 COMPANDER_8, /* SWR SPK CH2 */ 217 COMPANDER_MAX, 218 }; 219 220 enum { 221 INTn_2_INP_SEL_ZERO = 0, 222 INTn_2_INP_SEL_RX0, 223 INTn_2_INP_SEL_RX1, 224 INTn_2_INP_SEL_RX2, 225 INTn_2_INP_SEL_RX3, 226 INTn_2_INP_SEL_RX4, 227 INTn_2_INP_SEL_RX5, 228 INTn_2_INP_SEL_RX6, 229 INTn_2_INP_SEL_RX7, 230 INTn_2_INP_SEL_PROXIMITY, 231 }; 232 233 enum { 234 INTn_1_MIX_INP_SEL_ZERO = 0, 235 INTn_1_MIX_INP_SEL_DEC0, 236 INTn_1_MIX_INP_SEL_DEC1, 237 INTn_1_MIX_INP_SEL_IIR0, 238 INTn_1_MIX_INP_SEL_IIR1, 239 INTn_1_MIX_INP_SEL_RX0, 240 INTn_1_MIX_INP_SEL_RX1, 241 INTn_1_MIX_INP_SEL_RX2, 242 INTn_1_MIX_INP_SEL_RX3, 243 INTn_1_MIX_INP_SEL_RX4, 244 INTn_1_MIX_INP_SEL_RX5, 245 INTn_1_MIX_INP_SEL_RX6, 246 INTn_1_MIX_INP_SEL_RX7, 247 248 }; 249 250 enum { 251 INTERP_EAR = 0, 252 INTERP_HPHL, 253 INTERP_HPHR, 254 INTERP_LO1, 255 INTERP_LO2, 256 INTERP_LO3, 257 INTERP_LO4, 258 INTERP_SPKR1, 259 INTERP_SPKR2, 260 }; 261 262 enum wcd_clock_type { 263 WCD_CLK_OFF, 264 WCD_CLK_RCO, 265 WCD_CLK_MCLK, 266 }; 267 268 enum { 269 MIC_BIAS_1 = 1, 270 MIC_BIAS_2, 271 MIC_BIAS_3, 272 MIC_BIAS_4 273 }; 274 275 enum { 276 MICB_PULLUP_ENABLE, 277 MICB_PULLUP_DISABLE, 278 MICB_ENABLE, 279 MICB_DISABLE, 280 }; 281 282 struct wcd9335_slim_ch { 283 u32 ch_num; 284 u16 port; 285 u16 shift; 286 struct list_head list; 287 }; 288 289 struct wcd_slim_codec_dai_data { 290 struct list_head slim_ch_list; 291 struct slim_stream_config sconfig; 292 struct slim_stream_runtime *sruntime; 293 }; 294 295 struct wcd9335_codec { 296 struct device *dev; 297 struct clk *mclk; 298 struct clk *native_clk; 299 u32 mclk_rate; 300 u8 version; 301 302 struct slim_device *slim; 303 struct slim_device *slim_ifc_dev; 304 struct regmap *regmap; 305 struct regmap *if_regmap; 306 struct regmap_irq_chip_data *irq_data; 307 308 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 309 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 310 u32 num_rx_port; 311 u32 num_tx_port; 312 313 int sido_input_src; 314 enum wcd9335_sido_voltage sido_voltage; 315 316 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 317 struct snd_soc_component *component; 318 319 int master_bias_users; 320 int clk_mclk_users; 321 int clk_rco_users; 322 int sido_ccl_cnt; 323 enum wcd_clock_type clk_type; 324 325 struct wcd_clsh_ctrl *clsh_ctrl; 326 u32 hph_mode; 327 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 328 329 int comp_enabled[COMPANDER_MAX]; 330 331 int intr1; 332 int reset_gpio; 333 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY]; 334 335 unsigned int rx_port_value[WCD9335_RX_MAX]; 336 unsigned int tx_port_value; 337 int hph_l_gain; 338 int hph_r_gain; 339 u32 rx_bias_count; 340 341 /*TX*/ 342 int micb_ref[WCD9335_MAX_MICBIAS]; 343 int pullup_ref[WCD9335_MAX_MICBIAS]; 344 345 int dmic_0_1_clk_cnt; 346 int dmic_2_3_clk_cnt; 347 int dmic_4_5_clk_cnt; 348 int dmic_sample_rate; 349 int mad_dmic_sample_rate; 350 351 int native_clk_users; 352 }; 353 354 struct wcd9335_irq { 355 int irq; 356 irqreturn_t (*handler)(int irq, void *data); 357 char *name; 358 }; 359 360 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 361 WCD9335_SLIM_TX_CH(0), 362 WCD9335_SLIM_TX_CH(1), 363 WCD9335_SLIM_TX_CH(2), 364 WCD9335_SLIM_TX_CH(3), 365 WCD9335_SLIM_TX_CH(4), 366 WCD9335_SLIM_TX_CH(5), 367 WCD9335_SLIM_TX_CH(6), 368 WCD9335_SLIM_TX_CH(7), 369 WCD9335_SLIM_TX_CH(8), 370 WCD9335_SLIM_TX_CH(9), 371 WCD9335_SLIM_TX_CH(10), 372 WCD9335_SLIM_TX_CH(11), 373 WCD9335_SLIM_TX_CH(12), 374 WCD9335_SLIM_TX_CH(13), 375 WCD9335_SLIM_TX_CH(14), 376 WCD9335_SLIM_TX_CH(15), 377 }; 378 379 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 380 WCD9335_SLIM_RX_CH(0), /* 16 */ 381 WCD9335_SLIM_RX_CH(1), /* 17 */ 382 WCD9335_SLIM_RX_CH(2), 383 WCD9335_SLIM_RX_CH(3), 384 WCD9335_SLIM_RX_CH(4), 385 WCD9335_SLIM_RX_CH(5), 386 WCD9335_SLIM_RX_CH(6), 387 WCD9335_SLIM_RX_CH(7), 388 WCD9335_SLIM_RX_CH(8), 389 WCD9335_SLIM_RX_CH(9), 390 WCD9335_SLIM_RX_CH(10), 391 WCD9335_SLIM_RX_CH(11), 392 WCD9335_SLIM_RX_CH(12), 393 }; 394 395 struct interp_sample_rate { 396 int rate; 397 int rate_val; 398 }; 399 400 static struct interp_sample_rate int_mix_rate_val[] = { 401 {48000, 0x4}, /* 48K */ 402 {96000, 0x5}, /* 96K */ 403 {192000, 0x6}, /* 192K */ 404 }; 405 406 static struct interp_sample_rate int_prim_rate_val[] = { 407 {8000, 0x0}, /* 8K */ 408 {16000, 0x1}, /* 16K */ 409 {24000, -EINVAL},/* 24K */ 410 {32000, 0x3}, /* 32K */ 411 {48000, 0x4}, /* 48K */ 412 {96000, 0x5}, /* 96K */ 413 {192000, 0x6}, /* 192K */ 414 {384000, 0x7}, /* 384K */ 415 {44100, 0x8}, /* 44.1K */ 416 }; 417 418 struct wcd9335_reg_mask_val { 419 u16 reg; 420 u8 mask; 421 u8 val; 422 }; 423 424 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 425 /* Rbuckfly/R_EAR(32) */ 426 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 427 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 428 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 429 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 430 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 431 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 432 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 433 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 434 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 435 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 436 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 437 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 438 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 439 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 440 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 441 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 442 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 443 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 444 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 445 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 446 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 447 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 448 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 449 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 454 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 455 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 456 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 466 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 467 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 468 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 469 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 470 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 471 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 472 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 473 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 474 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 475 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 476 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 477 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 478 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 479 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 480 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 481 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 482 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 483 }; 484 485 /* Cutoff frequency for high pass filter */ 486 static const char * const cf_text[] = { 487 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 488 }; 489 490 static const char * const rx_cf_text[] = { 491 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 492 "CF_NEG_3DB_0P48HZ" 493 }; 494 495 static const char * const rx_int0_7_mix_mux_text[] = { 496 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 497 "RX6", "RX7", "PROXIMITY" 498 }; 499 500 static const char * const rx_int_mix_mux_text[] = { 501 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 502 "RX6", "RX7" 503 }; 504 505 static const char * const rx_prim_mix_text[] = { 506 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 507 "RX3", "RX4", "RX5", "RX6", "RX7" 508 }; 509 510 static const char * const rx_int_dem_inp_mux_text[] = { 511 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 512 }; 513 514 static const char * const rx_int0_interp_mux_text[] = { 515 "ZERO", "RX INT0 MIX2", 516 }; 517 518 static const char * const rx_int1_interp_mux_text[] = { 519 "ZERO", "RX INT1 MIX2", 520 }; 521 522 static const char * const rx_int2_interp_mux_text[] = { 523 "ZERO", "RX INT2 MIX2", 524 }; 525 526 static const char * const rx_int3_interp_mux_text[] = { 527 "ZERO", "RX INT3 MIX2", 528 }; 529 530 static const char * const rx_int4_interp_mux_text[] = { 531 "ZERO", "RX INT4 MIX2", 532 }; 533 534 static const char * const rx_int5_interp_mux_text[] = { 535 "ZERO", "RX INT5 MIX2", 536 }; 537 538 static const char * const rx_int6_interp_mux_text[] = { 539 "ZERO", "RX INT6 MIX2", 540 }; 541 542 static const char * const rx_int7_interp_mux_text[] = { 543 "ZERO", "RX INT7 MIX2", 544 }; 545 546 static const char * const rx_int8_interp_mux_text[] = { 547 "ZERO", "RX INT8 SEC MIX" 548 }; 549 550 static const char * const rx_hph_mode_mux_text[] = { 551 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 552 "Class-H Hi-Fi Low Power" 553 }; 554 555 static const char *const slim_rx_mux_text[] = { 556 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 557 }; 558 559 static const char * const adc_mux_text[] = { 560 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 561 }; 562 563 static const char * const dmic_mux_text[] = { 564 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 565 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 566 }; 567 568 static const char * const dmic_mux_alt_text[] = { 569 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 570 }; 571 572 static const char * const amic_mux_text[] = { 573 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 574 }; 575 576 static const char * const sb_tx0_mux_text[] = { 577 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 578 }; 579 580 static const char * const sb_tx1_mux_text[] = { 581 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 582 }; 583 584 static const char * const sb_tx2_mux_text[] = { 585 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 586 }; 587 588 static const char * const sb_tx3_mux_text[] = { 589 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 590 }; 591 592 static const char * const sb_tx4_mux_text[] = { 593 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 594 }; 595 596 static const char * const sb_tx5_mux_text[] = { 597 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 598 }; 599 600 static const char * const sb_tx6_mux_text[] = { 601 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 602 }; 603 604 static const char * const sb_tx7_mux_text[] = { 605 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 606 }; 607 608 static const char * const sb_tx8_mux_text[] = { 609 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 610 }; 611 612 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 613 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 614 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 615 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 616 617 static const struct soc_enum cf_dec0_enum = 618 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 619 620 static const struct soc_enum cf_dec1_enum = 621 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 622 623 static const struct soc_enum cf_dec2_enum = 624 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 625 626 static const struct soc_enum cf_dec3_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 628 629 static const struct soc_enum cf_dec4_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 631 632 static const struct soc_enum cf_dec5_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 634 635 static const struct soc_enum cf_dec6_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 637 638 static const struct soc_enum cf_dec7_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 640 641 static const struct soc_enum cf_dec8_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 643 644 static const struct soc_enum cf_int0_1_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 646 647 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 648 rx_cf_text); 649 650 static const struct soc_enum cf_int1_1_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 652 653 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 654 rx_cf_text); 655 656 static const struct soc_enum cf_int2_1_enum = 657 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 658 659 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 660 rx_cf_text); 661 662 static const struct soc_enum cf_int3_1_enum = 663 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 664 665 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 666 rx_cf_text); 667 668 static const struct soc_enum cf_int4_1_enum = 669 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 670 671 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 672 rx_cf_text); 673 674 static const struct soc_enum cf_int5_1_enum = 675 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 676 677 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 678 rx_cf_text); 679 680 static const struct soc_enum cf_int6_1_enum = 681 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 682 683 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 684 rx_cf_text); 685 686 static const struct soc_enum cf_int7_1_enum = 687 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 688 689 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 690 rx_cf_text); 691 692 static const struct soc_enum cf_int8_1_enum = 693 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 694 695 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 696 rx_cf_text); 697 698 static const struct soc_enum rx_hph_mode_mux_enum = 699 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 700 rx_hph_mode_mux_text); 701 702 static const struct soc_enum slim_rx_mux_enum = 703 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 704 705 static const struct soc_enum rx_int0_2_mux_chain_enum = 706 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 707 rx_int0_7_mix_mux_text); 708 709 static const struct soc_enum rx_int1_2_mux_chain_enum = 710 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 711 rx_int_mix_mux_text); 712 713 static const struct soc_enum rx_int2_2_mux_chain_enum = 714 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 715 rx_int_mix_mux_text); 716 717 static const struct soc_enum rx_int3_2_mux_chain_enum = 718 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 719 rx_int_mix_mux_text); 720 721 static const struct soc_enum rx_int4_2_mux_chain_enum = 722 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 723 rx_int_mix_mux_text); 724 725 static const struct soc_enum rx_int5_2_mux_chain_enum = 726 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 727 rx_int_mix_mux_text); 728 729 static const struct soc_enum rx_int6_2_mux_chain_enum = 730 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 731 rx_int_mix_mux_text); 732 733 static const struct soc_enum rx_int7_2_mux_chain_enum = 734 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 735 rx_int0_7_mix_mux_text); 736 737 static const struct soc_enum rx_int8_2_mux_chain_enum = 738 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 739 rx_int_mix_mux_text); 740 741 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 742 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 743 rx_prim_mix_text); 744 745 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 746 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 747 rx_prim_mix_text); 748 749 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 750 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 751 rx_prim_mix_text); 752 753 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 754 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 755 rx_prim_mix_text); 756 757 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 758 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 759 rx_prim_mix_text); 760 761 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 762 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 763 rx_prim_mix_text); 764 765 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 766 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 767 rx_prim_mix_text); 768 769 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 770 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 771 rx_prim_mix_text); 772 773 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 774 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 775 rx_prim_mix_text); 776 777 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 778 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 779 rx_prim_mix_text); 780 781 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 782 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 783 rx_prim_mix_text); 784 785 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 786 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 787 rx_prim_mix_text); 788 789 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 790 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 791 rx_prim_mix_text); 792 793 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 794 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 795 rx_prim_mix_text); 796 797 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 798 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 799 rx_prim_mix_text); 800 801 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 802 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 803 rx_prim_mix_text); 804 805 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 806 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 807 rx_prim_mix_text); 808 809 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 810 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 811 rx_prim_mix_text); 812 813 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 814 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 815 rx_prim_mix_text); 816 817 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 818 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 819 rx_prim_mix_text); 820 821 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 822 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 823 rx_prim_mix_text); 824 825 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 826 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 827 rx_prim_mix_text); 828 829 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 830 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 831 rx_prim_mix_text); 832 833 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 834 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 835 rx_prim_mix_text); 836 837 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 838 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 839 rx_prim_mix_text); 840 841 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 842 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 843 rx_prim_mix_text); 844 845 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 846 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 847 rx_prim_mix_text); 848 849 static const struct soc_enum rx_int0_dem_inp_mux_enum = 850 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 851 ARRAY_SIZE(rx_int_dem_inp_mux_text), 852 rx_int_dem_inp_mux_text); 853 854 static const struct soc_enum rx_int1_dem_inp_mux_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 856 ARRAY_SIZE(rx_int_dem_inp_mux_text), 857 rx_int_dem_inp_mux_text); 858 859 static const struct soc_enum rx_int2_dem_inp_mux_enum = 860 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 861 ARRAY_SIZE(rx_int_dem_inp_mux_text), 862 rx_int_dem_inp_mux_text); 863 864 static const struct soc_enum rx_int0_interp_mux_enum = 865 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 866 rx_int0_interp_mux_text); 867 868 static const struct soc_enum rx_int1_interp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 870 rx_int1_interp_mux_text); 871 872 static const struct soc_enum rx_int2_interp_mux_enum = 873 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 874 rx_int2_interp_mux_text); 875 876 static const struct soc_enum rx_int3_interp_mux_enum = 877 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 878 rx_int3_interp_mux_text); 879 880 static const struct soc_enum rx_int4_interp_mux_enum = 881 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 882 rx_int4_interp_mux_text); 883 884 static const struct soc_enum rx_int5_interp_mux_enum = 885 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 886 rx_int5_interp_mux_text); 887 888 static const struct soc_enum rx_int6_interp_mux_enum = 889 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 890 rx_int6_interp_mux_text); 891 892 static const struct soc_enum rx_int7_interp_mux_enum = 893 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 894 rx_int7_interp_mux_text); 895 896 static const struct soc_enum rx_int8_interp_mux_enum = 897 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 898 rx_int8_interp_mux_text); 899 900 static const struct soc_enum tx_adc_mux0_chain_enum = 901 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 902 adc_mux_text); 903 904 static const struct soc_enum tx_adc_mux1_chain_enum = 905 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 906 adc_mux_text); 907 908 static const struct soc_enum tx_adc_mux2_chain_enum = 909 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 910 adc_mux_text); 911 912 static const struct soc_enum tx_adc_mux3_chain_enum = 913 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 914 adc_mux_text); 915 916 static const struct soc_enum tx_adc_mux4_chain_enum = 917 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 918 adc_mux_text); 919 920 static const struct soc_enum tx_adc_mux5_chain_enum = 921 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 922 adc_mux_text); 923 924 static const struct soc_enum tx_adc_mux6_chain_enum = 925 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 926 adc_mux_text); 927 928 static const struct soc_enum tx_adc_mux7_chain_enum = 929 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 930 adc_mux_text); 931 932 static const struct soc_enum tx_adc_mux8_chain_enum = 933 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 934 adc_mux_text); 935 936 static const struct soc_enum tx_dmic_mux0_enum = 937 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 938 dmic_mux_text); 939 940 static const struct soc_enum tx_dmic_mux1_enum = 941 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 942 dmic_mux_text); 943 944 static const struct soc_enum tx_dmic_mux2_enum = 945 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 946 dmic_mux_text); 947 948 static const struct soc_enum tx_dmic_mux3_enum = 949 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 950 dmic_mux_text); 951 952 static const struct soc_enum tx_dmic_mux4_enum = 953 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 954 dmic_mux_alt_text); 955 956 static const struct soc_enum tx_dmic_mux5_enum = 957 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 958 dmic_mux_alt_text); 959 960 static const struct soc_enum tx_dmic_mux6_enum = 961 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 962 dmic_mux_alt_text); 963 964 static const struct soc_enum tx_dmic_mux7_enum = 965 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 966 dmic_mux_alt_text); 967 968 static const struct soc_enum tx_dmic_mux8_enum = 969 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 970 dmic_mux_alt_text); 971 972 static const struct soc_enum tx_amic_mux0_enum = 973 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 974 amic_mux_text); 975 976 static const struct soc_enum tx_amic_mux1_enum = 977 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 978 amic_mux_text); 979 980 static const struct soc_enum tx_amic_mux2_enum = 981 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 982 amic_mux_text); 983 984 static const struct soc_enum tx_amic_mux3_enum = 985 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 986 amic_mux_text); 987 988 static const struct soc_enum tx_amic_mux4_enum = 989 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 990 amic_mux_text); 991 992 static const struct soc_enum tx_amic_mux5_enum = 993 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 994 amic_mux_text); 995 996 static const struct soc_enum tx_amic_mux6_enum = 997 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 998 amic_mux_text); 999 1000 static const struct soc_enum tx_amic_mux7_enum = 1001 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1002 amic_mux_text); 1003 1004 static const struct soc_enum tx_amic_mux8_enum = 1005 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1006 amic_mux_text); 1007 1008 static const struct soc_enum sb_tx0_mux_enum = 1009 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1010 sb_tx0_mux_text); 1011 1012 static const struct soc_enum sb_tx1_mux_enum = 1013 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1014 sb_tx1_mux_text); 1015 1016 static const struct soc_enum sb_tx2_mux_enum = 1017 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1018 sb_tx2_mux_text); 1019 1020 static const struct soc_enum sb_tx3_mux_enum = 1021 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1022 sb_tx3_mux_text); 1023 1024 static const struct soc_enum sb_tx4_mux_enum = 1025 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1026 sb_tx4_mux_text); 1027 1028 static const struct soc_enum sb_tx5_mux_enum = 1029 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1030 sb_tx5_mux_text); 1031 1032 static const struct soc_enum sb_tx6_mux_enum = 1033 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1034 sb_tx6_mux_text); 1035 1036 static const struct soc_enum sb_tx7_mux_enum = 1037 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1038 sb_tx7_mux_text); 1039 1040 static const struct soc_enum sb_tx8_mux_enum = 1041 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1042 sb_tx8_mux_text); 1043 1044 static const struct snd_kcontrol_new rx_int0_2_mux = 1045 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1046 1047 static const struct snd_kcontrol_new rx_int1_2_mux = 1048 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1049 1050 static const struct snd_kcontrol_new rx_int2_2_mux = 1051 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1052 1053 static const struct snd_kcontrol_new rx_int3_2_mux = 1054 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1055 1056 static const struct snd_kcontrol_new rx_int4_2_mux = 1057 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1058 1059 static const struct snd_kcontrol_new rx_int5_2_mux = 1060 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1061 1062 static const struct snd_kcontrol_new rx_int6_2_mux = 1063 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1064 1065 static const struct snd_kcontrol_new rx_int7_2_mux = 1066 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1067 1068 static const struct snd_kcontrol_new rx_int8_2_mux = 1069 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1070 1071 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1072 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1073 1074 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1075 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1076 1077 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1078 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1079 1080 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1082 1083 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1085 1086 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1088 1089 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1091 1092 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1094 1095 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1097 1098 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1100 1101 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1103 1104 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1106 1107 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1109 1110 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1112 1113 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1115 1116 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1118 1119 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1121 1122 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1124 1125 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1127 1128 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1130 1131 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1133 1134 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1136 1137 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1139 1140 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1142 1143 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1145 1146 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1148 1149 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1151 1152 static const struct snd_kcontrol_new rx_int0_interp_mux = 1153 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1154 1155 static const struct snd_kcontrol_new rx_int1_interp_mux = 1156 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1157 1158 static const struct snd_kcontrol_new rx_int2_interp_mux = 1159 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1160 1161 static const struct snd_kcontrol_new rx_int3_interp_mux = 1162 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1163 1164 static const struct snd_kcontrol_new rx_int4_interp_mux = 1165 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1166 1167 static const struct snd_kcontrol_new rx_int5_interp_mux = 1168 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1169 1170 static const struct snd_kcontrol_new rx_int6_interp_mux = 1171 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1172 1173 static const struct snd_kcontrol_new rx_int7_interp_mux = 1174 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1175 1176 static const struct snd_kcontrol_new rx_int8_interp_mux = 1177 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1178 1179 static const struct snd_kcontrol_new tx_dmic_mux0 = 1180 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1181 1182 static const struct snd_kcontrol_new tx_dmic_mux1 = 1183 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1184 1185 static const struct snd_kcontrol_new tx_dmic_mux2 = 1186 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1187 1188 static const struct snd_kcontrol_new tx_dmic_mux3 = 1189 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1190 1191 static const struct snd_kcontrol_new tx_dmic_mux4 = 1192 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1193 1194 static const struct snd_kcontrol_new tx_dmic_mux5 = 1195 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1196 1197 static const struct snd_kcontrol_new tx_dmic_mux6 = 1198 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1199 1200 static const struct snd_kcontrol_new tx_dmic_mux7 = 1201 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1202 1203 static const struct snd_kcontrol_new tx_dmic_mux8 = 1204 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1205 1206 static const struct snd_kcontrol_new tx_amic_mux0 = 1207 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1208 1209 static const struct snd_kcontrol_new tx_amic_mux1 = 1210 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1211 1212 static const struct snd_kcontrol_new tx_amic_mux2 = 1213 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1214 1215 static const struct snd_kcontrol_new tx_amic_mux3 = 1216 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1217 1218 static const struct snd_kcontrol_new tx_amic_mux4 = 1219 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1220 1221 static const struct snd_kcontrol_new tx_amic_mux5 = 1222 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1223 1224 static const struct snd_kcontrol_new tx_amic_mux6 = 1225 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1226 1227 static const struct snd_kcontrol_new tx_amic_mux7 = 1228 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1229 1230 static const struct snd_kcontrol_new tx_amic_mux8 = 1231 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1232 1233 static const struct snd_kcontrol_new sb_tx0_mux = 1234 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1235 1236 static const struct snd_kcontrol_new sb_tx1_mux = 1237 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1238 1239 static const struct snd_kcontrol_new sb_tx2_mux = 1240 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1241 1242 static const struct snd_kcontrol_new sb_tx3_mux = 1243 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1244 1245 static const struct snd_kcontrol_new sb_tx4_mux = 1246 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1247 1248 static const struct snd_kcontrol_new sb_tx5_mux = 1249 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1250 1251 static const struct snd_kcontrol_new sb_tx6_mux = 1252 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1253 1254 static const struct snd_kcontrol_new sb_tx7_mux = 1255 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1256 1257 static const struct snd_kcontrol_new sb_tx8_mux = 1258 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1259 1260 static int slim_rx_mux_get(struct snd_kcontrol *kc, 1261 struct snd_ctl_elem_value *ucontrol) 1262 { 1263 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1264 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1265 u32 port_id = w->shift; 1266 1267 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id]; 1268 1269 return 0; 1270 } 1271 1272 static int slim_rx_mux_put(struct snd_kcontrol *kc, 1273 struct snd_ctl_elem_value *ucontrol) 1274 { 1275 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1276 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1277 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1278 struct snd_soc_dapm_update *update = NULL; 1279 u32 port_id = w->shift; 1280 1281 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0]) 1282 return 0; 1283 1284 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0]; 1285 1286 /* Remove channel from any list it's in before adding it to a new one */ 1287 list_del_init(&wcd->rx_chs[port_id].list); 1288 1289 switch (wcd->rx_port_value[port_id]) { 1290 case 0: 1291 /* Channel already removed from lists. Nothing to do here */ 1292 break; 1293 case 1: 1294 list_add_tail(&wcd->rx_chs[port_id].list, 1295 &wcd->dai[AIF1_PB].slim_ch_list); 1296 break; 1297 case 2: 1298 list_add_tail(&wcd->rx_chs[port_id].list, 1299 &wcd->dai[AIF2_PB].slim_ch_list); 1300 break; 1301 case 3: 1302 list_add_tail(&wcd->rx_chs[port_id].list, 1303 &wcd->dai[AIF3_PB].slim_ch_list); 1304 break; 1305 case 4: 1306 list_add_tail(&wcd->rx_chs[port_id].list, 1307 &wcd->dai[AIF4_PB].slim_ch_list); 1308 break; 1309 default: 1310 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]); 1311 goto err; 1312 } 1313 1314 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id], 1315 e, update); 1316 1317 return 0; 1318 err: 1319 return -EINVAL; 1320 } 1321 1322 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1323 struct snd_ctl_elem_value *ucontrol) 1324 { 1325 1326 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1327 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1328 1329 ucontrol->value.integer.value[0] = wcd->tx_port_value; 1330 1331 return 0; 1332 } 1333 1334 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1335 struct snd_ctl_elem_value *ucontrol) 1336 { 1337 1338 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1339 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev); 1340 struct snd_soc_dapm_update *update = NULL; 1341 struct soc_mixer_control *mixer = 1342 (struct soc_mixer_control *)kc->private_value; 1343 int enable = ucontrol->value.integer.value[0]; 1344 int dai_id = widget->shift; 1345 int port_id = mixer->shift; 1346 1347 switch (dai_id) { 1348 case AIF1_CAP: 1349 case AIF2_CAP: 1350 case AIF3_CAP: 1351 /* only add to the list if value not set */ 1352 if (enable && !(wcd->tx_port_value & BIT(port_id))) { 1353 wcd->tx_port_value |= BIT(port_id); 1354 list_add_tail(&wcd->tx_chs[port_id].list, 1355 &wcd->dai[dai_id].slim_ch_list); 1356 } else if (!enable && (wcd->tx_port_value & BIT(port_id))) { 1357 wcd->tx_port_value &= ~BIT(port_id); 1358 list_del_init(&wcd->tx_chs[port_id].list); 1359 } 1360 break; 1361 default: 1362 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1363 return -EINVAL; 1364 } 1365 1366 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1367 1368 return 0; 1369 } 1370 1371 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1372 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1373 slim_rx_mux_get, slim_rx_mux_put), 1374 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1375 slim_rx_mux_get, slim_rx_mux_put), 1376 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1377 slim_rx_mux_get, slim_rx_mux_put), 1378 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1379 slim_rx_mux_get, slim_rx_mux_put), 1380 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1381 slim_rx_mux_get, slim_rx_mux_put), 1382 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1383 slim_rx_mux_get, slim_rx_mux_put), 1384 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1385 slim_rx_mux_get, slim_rx_mux_put), 1386 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1387 slim_rx_mux_get, slim_rx_mux_put), 1388 }; 1389 1390 static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1391 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1392 slim_tx_mixer_get, slim_tx_mixer_put), 1393 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1394 slim_tx_mixer_get, slim_tx_mixer_put), 1395 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1396 slim_tx_mixer_get, slim_tx_mixer_put), 1397 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1398 slim_tx_mixer_get, slim_tx_mixer_put), 1399 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1400 slim_tx_mixer_get, slim_tx_mixer_put), 1401 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1402 slim_tx_mixer_get, slim_tx_mixer_put), 1403 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1404 slim_tx_mixer_get, slim_tx_mixer_put), 1405 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1406 slim_tx_mixer_get, slim_tx_mixer_put), 1407 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1408 slim_tx_mixer_get, slim_tx_mixer_put), 1409 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1410 slim_tx_mixer_get, slim_tx_mixer_put), 1411 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1412 slim_tx_mixer_get, slim_tx_mixer_put), 1413 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1414 slim_tx_mixer_get, slim_tx_mixer_put), 1415 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1416 slim_tx_mixer_get, slim_tx_mixer_put), 1417 }; 1418 1419 static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1420 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1421 slim_tx_mixer_get, slim_tx_mixer_put), 1422 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1423 slim_tx_mixer_get, slim_tx_mixer_put), 1424 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1425 slim_tx_mixer_get, slim_tx_mixer_put), 1426 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1427 slim_tx_mixer_get, slim_tx_mixer_put), 1428 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1429 slim_tx_mixer_get, slim_tx_mixer_put), 1430 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1431 slim_tx_mixer_get, slim_tx_mixer_put), 1432 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1433 slim_tx_mixer_get, slim_tx_mixer_put), 1434 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1435 slim_tx_mixer_get, slim_tx_mixer_put), 1436 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1437 slim_tx_mixer_get, slim_tx_mixer_put), 1438 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1439 slim_tx_mixer_get, slim_tx_mixer_put), 1440 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1441 slim_tx_mixer_get, slim_tx_mixer_put), 1442 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1443 slim_tx_mixer_get, slim_tx_mixer_put), 1444 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1445 slim_tx_mixer_get, slim_tx_mixer_put), 1446 }; 1447 1448 static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1449 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1450 slim_tx_mixer_get, slim_tx_mixer_put), 1451 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1452 slim_tx_mixer_get, slim_tx_mixer_put), 1453 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1454 slim_tx_mixer_get, slim_tx_mixer_put), 1455 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1456 slim_tx_mixer_get, slim_tx_mixer_put), 1457 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1458 slim_tx_mixer_get, slim_tx_mixer_put), 1459 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1460 slim_tx_mixer_get, slim_tx_mixer_put), 1461 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1462 slim_tx_mixer_get, slim_tx_mixer_put), 1463 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1464 slim_tx_mixer_get, slim_tx_mixer_put), 1465 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1466 slim_tx_mixer_get, slim_tx_mixer_put), 1467 }; 1468 1469 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1470 struct snd_ctl_elem_value *ucontrol) 1471 { 1472 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1473 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1474 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1475 unsigned int val, reg, sel; 1476 1477 val = ucontrol->value.enumerated.item[0]; 1478 1479 switch (e->reg) { 1480 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1481 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1482 break; 1483 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1484 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1485 break; 1486 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1487 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1488 break; 1489 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1490 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1491 break; 1492 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1493 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1494 break; 1495 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1496 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1497 break; 1498 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1499 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1500 break; 1501 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1502 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1503 break; 1504 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1505 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1506 break; 1507 default: 1508 return -EINVAL; 1509 } 1510 1511 /* AMIC: 0, DMIC: 1 */ 1512 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1513 snd_soc_component_update_bits(component, reg, 1514 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1515 sel); 1516 1517 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1518 } 1519 1520 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1521 struct snd_ctl_elem_value *ucontrol) 1522 { 1523 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1524 struct snd_soc_component *component; 1525 int reg, val; 1526 1527 component = snd_soc_dapm_kcontrol_component(kc); 1528 val = ucontrol->value.enumerated.item[0]; 1529 1530 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1531 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1532 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1533 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1534 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1535 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1536 else 1537 return -EINVAL; 1538 1539 /* Set Look Ahead Delay */ 1540 snd_soc_component_update_bits(component, reg, 1541 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1542 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1543 /* Set DEM INP Select */ 1544 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1545 } 1546 1547 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1548 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1549 snd_soc_dapm_get_enum_double, 1550 wcd9335_int_dem_inp_mux_put); 1551 1552 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1553 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1554 snd_soc_dapm_get_enum_double, 1555 wcd9335_int_dem_inp_mux_put); 1556 1557 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1558 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1559 snd_soc_dapm_get_enum_double, 1560 wcd9335_int_dem_inp_mux_put); 1561 1562 static const struct snd_kcontrol_new tx_adc_mux0 = 1563 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1564 snd_soc_dapm_get_enum_double, 1565 wcd9335_put_dec_enum); 1566 1567 static const struct snd_kcontrol_new tx_adc_mux1 = 1568 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1569 snd_soc_dapm_get_enum_double, 1570 wcd9335_put_dec_enum); 1571 1572 static const struct snd_kcontrol_new tx_adc_mux2 = 1573 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1574 snd_soc_dapm_get_enum_double, 1575 wcd9335_put_dec_enum); 1576 1577 static const struct snd_kcontrol_new tx_adc_mux3 = 1578 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1579 snd_soc_dapm_get_enum_double, 1580 wcd9335_put_dec_enum); 1581 1582 static const struct snd_kcontrol_new tx_adc_mux4 = 1583 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1584 snd_soc_dapm_get_enum_double, 1585 wcd9335_put_dec_enum); 1586 1587 static const struct snd_kcontrol_new tx_adc_mux5 = 1588 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1589 snd_soc_dapm_get_enum_double, 1590 wcd9335_put_dec_enum); 1591 1592 static const struct snd_kcontrol_new tx_adc_mux6 = 1593 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1594 snd_soc_dapm_get_enum_double, 1595 wcd9335_put_dec_enum); 1596 1597 static const struct snd_kcontrol_new tx_adc_mux7 = 1598 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1599 snd_soc_dapm_get_enum_double, 1600 wcd9335_put_dec_enum); 1601 1602 static const struct snd_kcontrol_new tx_adc_mux8 = 1603 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1604 snd_soc_dapm_get_enum_double, 1605 wcd9335_put_dec_enum); 1606 1607 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1608 int rate_val, 1609 u32 rate) 1610 { 1611 struct snd_soc_component *component = dai->component; 1612 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1613 struct wcd9335_slim_ch *ch; 1614 int val, j; 1615 1616 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1617 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1618 val = snd_soc_component_read(component, 1619 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1620 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1621 1622 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1623 snd_soc_component_update_bits(component, 1624 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1625 WCD9335_CDC_MIX_PCM_RATE_MASK, 1626 rate_val); 1627 } 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1634 u8 rate_val, 1635 u32 rate) 1636 { 1637 struct snd_soc_component *comp = dai->component; 1638 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1639 struct wcd9335_slim_ch *ch; 1640 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1641 int inp, j; 1642 1643 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1644 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1645 /* 1646 * Loop through all interpolator MUX inputs and find out 1647 * to which interpolator input, the slim rx port 1648 * is connected 1649 */ 1650 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1651 cfg0 = snd_soc_component_read(comp, 1652 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1653 cfg1 = snd_soc_component_read(comp, 1654 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1655 1656 inp0_sel = cfg0 & 1657 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1658 inp1_sel = (cfg0 >> 4) & 1659 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1660 inp2_sel = (cfg1 >> 4) & 1661 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1662 1663 if ((inp0_sel == inp) || (inp1_sel == inp) || 1664 (inp2_sel == inp)) { 1665 /* rate is in Hz */ 1666 if ((j == 0) && (rate == 44100)) 1667 dev_info(wcd->dev, 1668 "Cannot set 44.1KHz on INT0\n"); 1669 else 1670 snd_soc_component_update_bits(comp, 1671 WCD9335_CDC_RX_PATH_CTL(j), 1672 WCD9335_CDC_MIX_PCM_RATE_MASK, 1673 rate_val); 1674 } 1675 } 1676 } 1677 1678 return 0; 1679 } 1680 1681 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1682 { 1683 int i; 1684 1685 /* set mixing path rate */ 1686 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1687 if (rate == int_mix_rate_val[i].rate) { 1688 wcd9335_set_mix_interpolator_rate(dai, 1689 int_mix_rate_val[i].rate_val, rate); 1690 break; 1691 } 1692 } 1693 1694 /* set primary path sample rate */ 1695 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1696 if (rate == int_prim_rate_val[i].rate) { 1697 wcd9335_set_prim_interpolator_rate(dai, 1698 int_prim_rate_val[i].rate_val, rate); 1699 break; 1700 } 1701 } 1702 1703 return 0; 1704 } 1705 1706 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1707 struct wcd_slim_codec_dai_data *dai_data, 1708 int direction) 1709 { 1710 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1711 struct slim_stream_config *cfg = &dai_data->sconfig; 1712 struct wcd9335_slim_ch *ch; 1713 u16 payload = 0; 1714 int ret, i; 1715 1716 cfg->ch_count = 0; 1717 cfg->direction = direction; 1718 cfg->port_mask = 0; 1719 1720 /* Configure slave interface device */ 1721 list_for_each_entry(ch, slim_ch_list, list) { 1722 cfg->ch_count++; 1723 payload |= 1 << ch->shift; 1724 cfg->port_mask |= BIT(ch->port); 1725 } 1726 1727 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1728 if (!cfg->chs) 1729 return -ENOMEM; 1730 1731 i = 0; 1732 list_for_each_entry(ch, slim_ch_list, list) { 1733 cfg->chs[i++] = ch->ch_num; 1734 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1735 /* write to interface device */ 1736 ret = regmap_write(wcd->if_regmap, 1737 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1738 payload); 1739 1740 if (ret < 0) 1741 goto err; 1742 1743 /* configure the slave port for water mark and enable*/ 1744 ret = regmap_write(wcd->if_regmap, 1745 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1746 WCD9335_SLIM_WATER_MARK_VAL); 1747 if (ret < 0) 1748 goto err; 1749 } else { 1750 ret = regmap_write(wcd->if_regmap, 1751 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1752 payload & 0x00FF); 1753 if (ret < 0) 1754 goto err; 1755 1756 /* ports 8,9 */ 1757 ret = regmap_write(wcd->if_regmap, 1758 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1759 (payload & 0xFF00)>>8); 1760 if (ret < 0) 1761 goto err; 1762 1763 /* configure the slave port for water mark and enable*/ 1764 ret = regmap_write(wcd->if_regmap, 1765 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1766 WCD9335_SLIM_WATER_MARK_VAL); 1767 1768 if (ret < 0) 1769 goto err; 1770 } 1771 } 1772 1773 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1774 1775 return 0; 1776 1777 err: 1778 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1779 kfree(cfg->chs); 1780 cfg->chs = NULL; 1781 1782 return ret; 1783 } 1784 1785 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1786 u8 rate_val, u32 rate) 1787 { 1788 struct snd_soc_component *comp = dai->component; 1789 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1790 u8 shift = 0, shift_val = 0, tx_mux_sel; 1791 struct wcd9335_slim_ch *ch; 1792 int tx_port, tx_port_reg; 1793 int decimator = -1; 1794 1795 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1796 tx_port = ch->port; 1797 if ((tx_port == 12) || (tx_port >= 14)) { 1798 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1799 tx_port, dai->id); 1800 return -EINVAL; 1801 } 1802 /* Find the SB TX MUX input - which decimator is connected */ 1803 if (tx_port < 4) { 1804 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1805 shift = (tx_port << 1); 1806 shift_val = 0x03; 1807 } else if (tx_port < 8) { 1808 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1809 shift = ((tx_port - 4) << 1); 1810 shift_val = 0x03; 1811 } else if (tx_port < 11) { 1812 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1813 shift = ((tx_port - 8) << 1); 1814 shift_val = 0x03; 1815 } else if (tx_port == 11) { 1816 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1817 shift = 0; 1818 shift_val = 0x0F; 1819 } else if (tx_port == 13) { 1820 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1821 shift = 4; 1822 shift_val = 0x03; 1823 } else { 1824 return -EINVAL; 1825 } 1826 1827 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) & 1828 (shift_val << shift); 1829 1830 tx_mux_sel = tx_mux_sel >> shift; 1831 if (tx_port <= 8) { 1832 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1833 decimator = tx_port; 1834 } else if (tx_port <= 10) { 1835 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1836 decimator = ((tx_port == 9) ? 7 : 6); 1837 } else if (tx_port == 11) { 1838 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1839 decimator = tx_mux_sel - 1; 1840 } else if (tx_port == 13) { 1841 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1842 decimator = 5; 1843 } 1844 1845 if (decimator >= 0) { 1846 snd_soc_component_update_bits(comp, 1847 WCD9335_CDC_TX_PATH_CTL(decimator), 1848 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1849 rate_val); 1850 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1851 /* Check if the TX Mux input is RX MIX TXn */ 1852 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1853 tx_port, tx_port); 1854 } else { 1855 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1856 decimator); 1857 return -EINVAL; 1858 } 1859 } 1860 1861 return 0; 1862 } 1863 1864 static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1865 struct snd_pcm_hw_params *params, 1866 struct snd_soc_dai *dai) 1867 { 1868 struct wcd9335_codec *wcd; 1869 int ret, tx_fs_rate = 0; 1870 1871 wcd = snd_soc_component_get_drvdata(dai->component); 1872 1873 switch (substream->stream) { 1874 case SNDRV_PCM_STREAM_PLAYBACK: 1875 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1876 if (ret) { 1877 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1878 params_rate(params)); 1879 return ret; 1880 } 1881 switch (params_width(params)) { 1882 case 16 ... 24: 1883 wcd->dai[dai->id].sconfig.bps = params_width(params); 1884 break; 1885 default: 1886 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1887 __func__, params_width(params)); 1888 return -EINVAL; 1889 } 1890 break; 1891 1892 case SNDRV_PCM_STREAM_CAPTURE: 1893 switch (params_rate(params)) { 1894 case 8000: 1895 tx_fs_rate = 0; 1896 break; 1897 case 16000: 1898 tx_fs_rate = 1; 1899 break; 1900 case 32000: 1901 tx_fs_rate = 3; 1902 break; 1903 case 48000: 1904 tx_fs_rate = 4; 1905 break; 1906 case 96000: 1907 tx_fs_rate = 5; 1908 break; 1909 case 192000: 1910 tx_fs_rate = 6; 1911 break; 1912 case 384000: 1913 tx_fs_rate = 7; 1914 break; 1915 default: 1916 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1917 __func__, params_rate(params)); 1918 return -EINVAL; 1919 1920 } 1921 1922 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1923 params_rate(params)); 1924 if (ret < 0) { 1925 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1926 return ret; 1927 } 1928 switch (params_width(params)) { 1929 case 16 ... 32: 1930 wcd->dai[dai->id].sconfig.bps = params_width(params); 1931 break; 1932 default: 1933 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1934 __func__, params_width(params)); 1935 return -EINVAL; 1936 } 1937 break; 1938 default: 1939 dev_err(wcd->dev, "Invalid stream type %d\n", 1940 substream->stream); 1941 return -EINVAL; 1942 } 1943 1944 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1945 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1946 1947 return 0; 1948 } 1949 1950 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1951 struct snd_soc_dai *dai) 1952 { 1953 struct wcd_slim_codec_dai_data *dai_data; 1954 struct wcd9335_codec *wcd; 1955 struct slim_stream_config *cfg; 1956 1957 wcd = snd_soc_component_get_drvdata(dai->component); 1958 1959 dai_data = &wcd->dai[dai->id]; 1960 1961 switch (cmd) { 1962 case SNDRV_PCM_TRIGGER_START: 1963 case SNDRV_PCM_TRIGGER_RESUME: 1964 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1965 cfg = &dai_data->sconfig; 1966 slim_stream_prepare(dai_data->sruntime, cfg); 1967 slim_stream_enable(dai_data->sruntime); 1968 break; 1969 case SNDRV_PCM_TRIGGER_STOP: 1970 case SNDRV_PCM_TRIGGER_SUSPEND: 1971 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1972 slim_stream_unprepare(dai_data->sruntime); 1973 slim_stream_disable(dai_data->sruntime); 1974 break; 1975 default: 1976 break; 1977 } 1978 1979 return 0; 1980 } 1981 1982 static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1983 unsigned int tx_num, unsigned int *tx_slot, 1984 unsigned int rx_num, unsigned int *rx_slot) 1985 { 1986 struct wcd9335_codec *wcd; 1987 int i; 1988 1989 wcd = snd_soc_component_get_drvdata(dai->component); 1990 1991 if (!tx_slot || !rx_slot) { 1992 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1993 tx_slot, rx_slot); 1994 return -EINVAL; 1995 } 1996 1997 wcd->num_rx_port = rx_num; 1998 for (i = 0; i < rx_num; i++) { 1999 wcd->rx_chs[i].ch_num = rx_slot[i]; 2000 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2001 } 2002 2003 wcd->num_tx_port = tx_num; 2004 for (i = 0; i < tx_num; i++) { 2005 wcd->tx_chs[i].ch_num = tx_slot[i]; 2006 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int wcd9335_get_channel_map(struct snd_soc_dai *dai, 2013 unsigned int *tx_num, unsigned int *tx_slot, 2014 unsigned int *rx_num, unsigned int *rx_slot) 2015 { 2016 struct wcd9335_slim_ch *ch; 2017 struct wcd9335_codec *wcd; 2018 int i = 0; 2019 2020 wcd = snd_soc_component_get_drvdata(dai->component); 2021 2022 switch (dai->id) { 2023 case AIF1_PB: 2024 case AIF2_PB: 2025 case AIF3_PB: 2026 case AIF4_PB: 2027 if (!rx_slot || !rx_num) { 2028 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2029 rx_slot, rx_num); 2030 return -EINVAL; 2031 } 2032 2033 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2034 rx_slot[i++] = ch->ch_num; 2035 2036 *rx_num = i; 2037 break; 2038 case AIF1_CAP: 2039 case AIF2_CAP: 2040 case AIF3_CAP: 2041 if (!tx_slot || !tx_num) { 2042 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2043 tx_slot, tx_num); 2044 return -EINVAL; 2045 } 2046 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2047 tx_slot[i++] = ch->ch_num; 2048 2049 *tx_num = i; 2050 break; 2051 default: 2052 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2053 break; 2054 } 2055 2056 return 0; 2057 } 2058 2059 static const struct snd_soc_dai_ops wcd9335_dai_ops = { 2060 .hw_params = wcd9335_hw_params, 2061 .trigger = wcd9335_trigger, 2062 .set_channel_map = wcd9335_set_channel_map, 2063 .get_channel_map = wcd9335_get_channel_map, 2064 }; 2065 2066 static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2067 [0] = { 2068 .name = "wcd9335_rx1", 2069 .id = AIF1_PB, 2070 .playback = { 2071 .stream_name = "AIF1 Playback", 2072 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2073 SNDRV_PCM_RATE_384000, 2074 .formats = WCD9335_FORMATS_S16_S24_LE, 2075 .rate_max = 384000, 2076 .rate_min = 8000, 2077 .channels_min = 1, 2078 .channels_max = 2, 2079 }, 2080 .ops = &wcd9335_dai_ops, 2081 }, 2082 [1] = { 2083 .name = "wcd9335_tx1", 2084 .id = AIF1_CAP, 2085 .capture = { 2086 .stream_name = "AIF1 Capture", 2087 .rates = WCD9335_RATES_MASK, 2088 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2089 .rate_min = 8000, 2090 .rate_max = 192000, 2091 .channels_min = 1, 2092 .channels_max = 4, 2093 }, 2094 .ops = &wcd9335_dai_ops, 2095 }, 2096 [2] = { 2097 .name = "wcd9335_rx2", 2098 .id = AIF2_PB, 2099 .playback = { 2100 .stream_name = "AIF2 Playback", 2101 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2102 SNDRV_PCM_RATE_384000, 2103 .formats = WCD9335_FORMATS_S16_S24_LE, 2104 .rate_min = 8000, 2105 .rate_max = 384000, 2106 .channels_min = 1, 2107 .channels_max = 2, 2108 }, 2109 .ops = &wcd9335_dai_ops, 2110 }, 2111 [3] = { 2112 .name = "wcd9335_tx2", 2113 .id = AIF2_CAP, 2114 .capture = { 2115 .stream_name = "AIF2 Capture", 2116 .rates = WCD9335_RATES_MASK, 2117 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2118 .rate_min = 8000, 2119 .rate_max = 192000, 2120 .channels_min = 1, 2121 .channels_max = 4, 2122 }, 2123 .ops = &wcd9335_dai_ops, 2124 }, 2125 [4] = { 2126 .name = "wcd9335_rx3", 2127 .id = AIF3_PB, 2128 .playback = { 2129 .stream_name = "AIF3 Playback", 2130 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2131 SNDRV_PCM_RATE_384000, 2132 .formats = WCD9335_FORMATS_S16_S24_LE, 2133 .rate_min = 8000, 2134 .rate_max = 384000, 2135 .channels_min = 1, 2136 .channels_max = 2, 2137 }, 2138 .ops = &wcd9335_dai_ops, 2139 }, 2140 [5] = { 2141 .name = "wcd9335_tx3", 2142 .id = AIF3_CAP, 2143 .capture = { 2144 .stream_name = "AIF3 Capture", 2145 .rates = WCD9335_RATES_MASK, 2146 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2147 .rate_min = 8000, 2148 .rate_max = 192000, 2149 .channels_min = 1, 2150 .channels_max = 4, 2151 }, 2152 .ops = &wcd9335_dai_ops, 2153 }, 2154 [6] = { 2155 .name = "wcd9335_rx4", 2156 .id = AIF4_PB, 2157 .playback = { 2158 .stream_name = "AIF4 Playback", 2159 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2160 SNDRV_PCM_RATE_384000, 2161 .formats = WCD9335_FORMATS_S16_S24_LE, 2162 .rate_min = 8000, 2163 .rate_max = 384000, 2164 .channels_min = 1, 2165 .channels_max = 2, 2166 }, 2167 .ops = &wcd9335_dai_ops, 2168 }, 2169 }; 2170 2171 static int wcd9335_get_compander(struct snd_kcontrol *kc, 2172 struct snd_ctl_elem_value *ucontrol) 2173 { 2174 2175 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2176 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2177 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2178 2179 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2180 return 0; 2181 } 2182 2183 static int wcd9335_set_compander(struct snd_kcontrol *kc, 2184 struct snd_ctl_elem_value *ucontrol) 2185 { 2186 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2187 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2188 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2189 int value = ucontrol->value.integer.value[0]; 2190 int sel; 2191 2192 wcd->comp_enabled[comp] = value; 2193 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2194 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2195 2196 /* Any specific register configuration for compander */ 2197 switch (comp) { 2198 case COMPANDER_1: 2199 /* Set Gain Source Select based on compander enable/disable */ 2200 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2201 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2202 break; 2203 case COMPANDER_2: 2204 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2205 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2206 break; 2207 case COMPANDER_5: 2208 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2209 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2210 break; 2211 case COMPANDER_6: 2212 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2213 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2214 break; 2215 default: 2216 break; 2217 } 2218 2219 return 0; 2220 } 2221 2222 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2223 struct snd_ctl_elem_value *ucontrol) 2224 { 2225 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2226 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2227 2228 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2229 2230 return 0; 2231 } 2232 2233 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2234 struct snd_ctl_elem_value *ucontrol) 2235 { 2236 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2237 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2238 u32 mode_val; 2239 2240 mode_val = ucontrol->value.enumerated.item[0]; 2241 2242 if (mode_val == 0) { 2243 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2244 mode_val = CLS_H_HIFI; 2245 } 2246 wcd->hph_mode = mode_val; 2247 2248 return 0; 2249 } 2250 2251 static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2252 /* -84dB min - 40dB max */ 2253 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2254 -84, 40, digital_gain), 2255 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2256 -84, 40, digital_gain), 2257 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2258 -84, 40, digital_gain), 2259 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2260 -84, 40, digital_gain), 2261 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2262 -84, 40, digital_gain), 2263 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2264 -84, 40, digital_gain), 2265 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2266 -84, 40, digital_gain), 2267 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2268 -84, 40, digital_gain), 2269 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2270 -84, 40, digital_gain), 2271 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2272 -84, 40, digital_gain), 2273 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2274 -84, 40, digital_gain), 2275 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2276 -84, 40, digital_gain), 2277 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2278 -84, 40, digital_gain), 2279 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2280 -84, 40, digital_gain), 2281 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2282 -84, 40, digital_gain), 2283 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2284 -84, 40, digital_gain), 2285 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2286 -84, 40, digital_gain), 2287 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2288 -84, 40, digital_gain), 2289 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2290 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2291 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2292 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2293 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2294 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2295 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2296 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2297 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2298 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2299 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2300 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2301 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2302 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2303 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2304 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2305 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2306 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2307 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2308 wcd9335_get_compander, wcd9335_set_compander), 2309 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2310 wcd9335_get_compander, wcd9335_set_compander), 2311 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2312 wcd9335_get_compander, wcd9335_set_compander), 2313 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2314 wcd9335_get_compander, wcd9335_set_compander), 2315 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2316 wcd9335_get_compander, wcd9335_set_compander), 2317 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2318 wcd9335_get_compander, wcd9335_set_compander), 2319 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2320 wcd9335_get_compander, wcd9335_set_compander), 2321 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2322 wcd9335_get_compander, wcd9335_set_compander), 2323 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2324 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2325 2326 /* Gain Controls */ 2327 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2328 ear_pa_gain), 2329 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2330 line_gain), 2331 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2332 line_gain), 2333 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2334 3, 16, 1, line_gain), 2335 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2336 3, 16, 1, line_gain), 2337 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2338 line_gain), 2339 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2340 line_gain), 2341 2342 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2343 analog_gain), 2344 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2345 analog_gain), 2346 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2347 analog_gain), 2348 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2349 analog_gain), 2350 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2351 analog_gain), 2352 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2353 analog_gain), 2354 2355 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2356 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2357 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2358 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2359 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2360 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2361 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2362 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2363 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2364 }; 2365 2366 static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2367 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2368 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2369 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2370 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2371 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2372 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2373 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2374 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2375 2376 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2377 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2378 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2379 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2380 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2381 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2382 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2383 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2384 2385 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2386 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2387 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2388 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2389 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2390 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2391 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2392 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2393 2394 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2395 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2396 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2397 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2398 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2399 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2400 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2401 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2402 2403 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2404 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2405 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2406 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2407 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2408 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2409 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2410 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2411 2412 WCD9335_INTERPOLATOR_PATH(0), 2413 WCD9335_INTERPOLATOR_PATH(1), 2414 WCD9335_INTERPOLATOR_PATH(2), 2415 WCD9335_INTERPOLATOR_PATH(3), 2416 WCD9335_INTERPOLATOR_PATH(4), 2417 WCD9335_INTERPOLATOR_PATH(5), 2418 WCD9335_INTERPOLATOR_PATH(6), 2419 WCD9335_INTERPOLATOR_PATH(7), 2420 WCD9335_INTERPOLATOR_PATH(8), 2421 2422 /* EAR PA */ 2423 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2424 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2425 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2426 {"EAR PA", NULL, "RX INT0 DAC"}, 2427 {"EAR", NULL, "EAR PA"}, 2428 2429 /* HPHL */ 2430 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2431 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2432 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2433 {"HPHL PA", NULL, "RX INT1 DAC"}, 2434 {"HPHL", NULL, "HPHL PA"}, 2435 2436 /* HPHR */ 2437 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2438 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2439 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2440 {"HPHR PA", NULL, "RX INT2 DAC"}, 2441 {"HPHR", NULL, "HPHR PA"}, 2442 2443 /* LINEOUT1 */ 2444 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2445 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2446 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2447 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2448 2449 /* LINEOUT2 */ 2450 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2451 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2452 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2453 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2454 2455 /* LINEOUT3 */ 2456 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2457 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2458 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2459 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2460 2461 /* LINEOUT4 */ 2462 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2463 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2464 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2465 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2466 2467 /* SLIMBUS Connections */ 2468 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2469 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2470 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2471 2472 /* ADC Mux */ 2473 WCD9335_ADC_MUX_PATH(0), 2474 WCD9335_ADC_MUX_PATH(1), 2475 WCD9335_ADC_MUX_PATH(2), 2476 WCD9335_ADC_MUX_PATH(3), 2477 WCD9335_ADC_MUX_PATH(4), 2478 WCD9335_ADC_MUX_PATH(5), 2479 WCD9335_ADC_MUX_PATH(6), 2480 WCD9335_ADC_MUX_PATH(7), 2481 WCD9335_ADC_MUX_PATH(8), 2482 2483 /* ADC Connections */ 2484 {"ADC1", NULL, "AMIC1"}, 2485 {"ADC2", NULL, "AMIC2"}, 2486 {"ADC3", NULL, "AMIC3"}, 2487 {"ADC4", NULL, "AMIC4"}, 2488 {"ADC5", NULL, "AMIC5"}, 2489 {"ADC6", NULL, "AMIC6"}, 2490 }; 2491 2492 static int wcd9335_micbias_control(struct snd_soc_component *component, 2493 int micb_num, int req, bool is_dapm) 2494 { 2495 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2496 int micb_index = micb_num - 1; 2497 u16 micb_reg; 2498 2499 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2500 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2501 micb_index); 2502 return -EINVAL; 2503 } 2504 2505 switch (micb_num) { 2506 case MIC_BIAS_1: 2507 micb_reg = WCD9335_ANA_MICB1; 2508 break; 2509 case MIC_BIAS_2: 2510 micb_reg = WCD9335_ANA_MICB2; 2511 break; 2512 case MIC_BIAS_3: 2513 micb_reg = WCD9335_ANA_MICB3; 2514 break; 2515 case MIC_BIAS_4: 2516 micb_reg = WCD9335_ANA_MICB4; 2517 break; 2518 default: 2519 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2520 __func__, micb_num); 2521 return -EINVAL; 2522 } 2523 2524 switch (req) { 2525 case MICB_PULLUP_ENABLE: 2526 wcd->pullup_ref[micb_index]++; 2527 if ((wcd->pullup_ref[micb_index] == 1) && 2528 (wcd->micb_ref[micb_index] == 0)) 2529 snd_soc_component_update_bits(component, micb_reg, 2530 0xC0, 0x80); 2531 break; 2532 case MICB_PULLUP_DISABLE: 2533 wcd->pullup_ref[micb_index]--; 2534 if ((wcd->pullup_ref[micb_index] == 0) && 2535 (wcd->micb_ref[micb_index] == 0)) 2536 snd_soc_component_update_bits(component, micb_reg, 2537 0xC0, 0x00); 2538 break; 2539 case MICB_ENABLE: 2540 wcd->micb_ref[micb_index]++; 2541 if (wcd->micb_ref[micb_index] == 1) 2542 snd_soc_component_update_bits(component, micb_reg, 2543 0xC0, 0x40); 2544 break; 2545 case MICB_DISABLE: 2546 wcd->micb_ref[micb_index]--; 2547 if ((wcd->micb_ref[micb_index] == 0) && 2548 (wcd->pullup_ref[micb_index] > 0)) 2549 snd_soc_component_update_bits(component, micb_reg, 2550 0xC0, 0x80); 2551 else if ((wcd->micb_ref[micb_index] == 0) && 2552 (wcd->pullup_ref[micb_index] == 0)) { 2553 snd_soc_component_update_bits(component, micb_reg, 2554 0xC0, 0x00); 2555 } 2556 break; 2557 } 2558 2559 return 0; 2560 } 2561 2562 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2563 int event) 2564 { 2565 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2566 int micb_num; 2567 2568 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2569 micb_num = MIC_BIAS_1; 2570 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2571 micb_num = MIC_BIAS_2; 2572 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2573 micb_num = MIC_BIAS_3; 2574 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2575 micb_num = MIC_BIAS_4; 2576 else 2577 return -EINVAL; 2578 2579 switch (event) { 2580 case SND_SOC_DAPM_PRE_PMU: 2581 /* 2582 * MIC BIAS can also be requested by MBHC, 2583 * so use ref count to handle micbias pullup 2584 * and enable requests 2585 */ 2586 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2587 break; 2588 case SND_SOC_DAPM_POST_PMU: 2589 /* wait for cnp time */ 2590 usleep_range(1000, 1100); 2591 break; 2592 case SND_SOC_DAPM_POST_PMD: 2593 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2594 break; 2595 } 2596 2597 return 0; 2598 } 2599 2600 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2601 struct snd_kcontrol *kc, int event) 2602 { 2603 return __wcd9335_codec_enable_micbias(w, event); 2604 } 2605 2606 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2607 u16 amic_reg, bool set) 2608 { 2609 u8 mask = 0x20; 2610 u8 val; 2611 2612 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2613 amic_reg == WCD9335_ANA_AMIC5) 2614 mask = 0x40; 2615 2616 val = set ? mask : 0x00; 2617 2618 switch (amic_reg) { 2619 case WCD9335_ANA_AMIC1: 2620 case WCD9335_ANA_AMIC2: 2621 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2622 val); 2623 break; 2624 case WCD9335_ANA_AMIC3: 2625 case WCD9335_ANA_AMIC4: 2626 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2627 val); 2628 break; 2629 case WCD9335_ANA_AMIC5: 2630 case WCD9335_ANA_AMIC6: 2631 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2632 val); 2633 break; 2634 default: 2635 dev_err(comp->dev, "%s: invalid amic: %d\n", 2636 __func__, amic_reg); 2637 break; 2638 } 2639 } 2640 2641 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2642 struct snd_kcontrol *kc, int event) 2643 { 2644 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2645 2646 switch (event) { 2647 case SND_SOC_DAPM_PRE_PMU: 2648 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2649 break; 2650 default: 2651 break; 2652 } 2653 2654 return 0; 2655 } 2656 2657 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2658 int adc_mux_n) 2659 { 2660 int mux_sel, reg, mreg; 2661 2662 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2663 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2664 return 0; 2665 2666 /* Check whether adc mux input is AMIC or DMIC */ 2667 if (adc_mux_n < 4) { 2668 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2669 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2670 mux_sel = snd_soc_component_read(comp, reg) & 0x3; 2671 } else { 2672 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2673 mreg = reg; 2674 mux_sel = snd_soc_component_read(comp, reg) >> 6; 2675 } 2676 2677 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2678 return 0; 2679 2680 return snd_soc_component_read(comp, mreg) & 0x07; 2681 } 2682 2683 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2684 int amic) 2685 { 2686 u16 pwr_level_reg = 0; 2687 2688 switch (amic) { 2689 case 1: 2690 case 2: 2691 pwr_level_reg = WCD9335_ANA_AMIC1; 2692 break; 2693 2694 case 3: 2695 case 4: 2696 pwr_level_reg = WCD9335_ANA_AMIC3; 2697 break; 2698 2699 case 5: 2700 case 6: 2701 pwr_level_reg = WCD9335_ANA_AMIC5; 2702 break; 2703 default: 2704 dev_err(comp->dev, "invalid amic: %d\n", amic); 2705 break; 2706 } 2707 2708 return pwr_level_reg; 2709 } 2710 2711 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2712 struct snd_kcontrol *kc, int event) 2713 { 2714 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2715 unsigned int decimator; 2716 char *dec_adc_mux_name = NULL; 2717 char *widget_name = NULL; 2718 char *wname; 2719 int ret = 0, amic_n; 2720 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2721 u16 tx_gain_ctl_reg; 2722 char *dec; 2723 u8 hpf_coff_freq; 2724 2725 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); 2726 if (!widget_name) 2727 return -ENOMEM; 2728 2729 wname = widget_name; 2730 dec_adc_mux_name = strsep(&widget_name, " "); 2731 if (!dec_adc_mux_name) { 2732 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2733 __func__, w->name); 2734 ret = -EINVAL; 2735 goto out; 2736 } 2737 dec_adc_mux_name = widget_name; 2738 2739 dec = strpbrk(dec_adc_mux_name, "012345678"); 2740 if (!dec) { 2741 dev_err(comp->dev, "%s: decimator index not found\n", 2742 __func__); 2743 ret = -EINVAL; 2744 goto out; 2745 } 2746 2747 ret = kstrtouint(dec, 10, &decimator); 2748 if (ret < 0) { 2749 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2750 __func__, wname); 2751 ret = -EINVAL; 2752 goto out; 2753 } 2754 2755 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2756 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2757 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2758 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2759 2760 switch (event) { 2761 case SND_SOC_DAPM_PRE_PMU: 2762 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2763 if (amic_n) 2764 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2765 amic_n); 2766 2767 if (pwr_level_reg) { 2768 switch ((snd_soc_component_read(comp, pwr_level_reg) & 2769 WCD9335_AMIC_PWR_LVL_MASK) >> 2770 WCD9335_AMIC_PWR_LVL_SHIFT) { 2771 case WCD9335_AMIC_PWR_LEVEL_LP: 2772 snd_soc_component_update_bits(comp, dec_cfg_reg, 2773 WCD9335_DEC_PWR_LVL_MASK, 2774 WCD9335_DEC_PWR_LVL_LP); 2775 break; 2776 2777 case WCD9335_AMIC_PWR_LEVEL_HP: 2778 snd_soc_component_update_bits(comp, dec_cfg_reg, 2779 WCD9335_DEC_PWR_LVL_MASK, 2780 WCD9335_DEC_PWR_LVL_HP); 2781 break; 2782 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2783 default: 2784 snd_soc_component_update_bits(comp, dec_cfg_reg, 2785 WCD9335_DEC_PWR_LVL_MASK, 2786 WCD9335_DEC_PWR_LVL_DF); 2787 break; 2788 } 2789 } 2790 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2791 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2792 2793 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2794 snd_soc_component_update_bits(comp, dec_cfg_reg, 2795 TX_HPF_CUT_OFF_FREQ_MASK, 2796 CF_MIN_3DB_150HZ << 5); 2797 /* Enable TX PGA Mute */ 2798 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2799 0x10, 0x10); 2800 /* Enable APC */ 2801 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2802 break; 2803 case SND_SOC_DAPM_POST_PMU: 2804 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2805 2806 if (decimator == 0) { 2807 snd_soc_component_write(comp, 2808 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2809 snd_soc_component_write(comp, 2810 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2811 snd_soc_component_write(comp, 2812 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2813 snd_soc_component_write(comp, 2814 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2815 } 2816 2817 snd_soc_component_update_bits(comp, hpf_gate_reg, 2818 0x01, 0x01); 2819 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2820 0x10, 0x00); 2821 snd_soc_component_write(comp, tx_gain_ctl_reg, 2822 snd_soc_component_read(comp, tx_gain_ctl_reg)); 2823 break; 2824 case SND_SOC_DAPM_PRE_PMD: 2825 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 2826 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2827 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2828 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2829 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2830 snd_soc_component_update_bits(comp, dec_cfg_reg, 2831 TX_HPF_CUT_OFF_FREQ_MASK, 2832 hpf_coff_freq << 5); 2833 } 2834 break; 2835 case SND_SOC_DAPM_POST_PMD: 2836 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2837 break; 2838 } 2839 out: 2840 kfree(wname); 2841 return ret; 2842 } 2843 2844 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2845 u32 mclk_rate, u32 dmic_clk_rate) 2846 { 2847 u32 div_factor; 2848 u8 dmic_ctl_val; 2849 2850 dev_err(component->dev, 2851 "%s: mclk_rate = %d, dmic_sample_rate = %d\n", 2852 __func__, mclk_rate, dmic_clk_rate); 2853 2854 /* Default value to return in case of error */ 2855 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2856 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2857 else 2858 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2859 2860 if (dmic_clk_rate == 0) { 2861 dev_err(component->dev, 2862 "%s: dmic_sample_rate cannot be 0\n", 2863 __func__); 2864 goto done; 2865 } 2866 2867 div_factor = mclk_rate / dmic_clk_rate; 2868 switch (div_factor) { 2869 case 2: 2870 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2871 break; 2872 case 3: 2873 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2874 break; 2875 case 4: 2876 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4; 2877 break; 2878 case 6: 2879 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6; 2880 break; 2881 case 8: 2882 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8; 2883 break; 2884 case 16: 2885 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16; 2886 break; 2887 default: 2888 dev_err(component->dev, 2889 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 2890 __func__, div_factor, mclk_rate, dmic_clk_rate); 2891 break; 2892 } 2893 2894 done: 2895 return dmic_ctl_val; 2896 } 2897 2898 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2899 struct snd_kcontrol *kc, int event) 2900 { 2901 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2902 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2903 u8 dmic_clk_en = 0x01; 2904 u16 dmic_clk_reg; 2905 s32 *dmic_clk_cnt; 2906 u8 dmic_rate_val, dmic_rate_shift = 1; 2907 unsigned int dmic; 2908 int ret; 2909 char *wname; 2910 2911 wname = strpbrk(w->name, "012345"); 2912 if (!wname) { 2913 dev_err(comp->dev, "%s: widget not found\n", __func__); 2914 return -EINVAL; 2915 } 2916 2917 ret = kstrtouint(wname, 10, &dmic); 2918 if (ret < 0) { 2919 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2920 __func__); 2921 return -EINVAL; 2922 } 2923 2924 switch (dmic) { 2925 case 0: 2926 case 1: 2927 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2928 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2929 break; 2930 case 2: 2931 case 3: 2932 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2933 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2934 break; 2935 case 4: 2936 case 5: 2937 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2938 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2939 break; 2940 default: 2941 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2942 __func__); 2943 return -EINVAL; 2944 } 2945 2946 switch (event) { 2947 case SND_SOC_DAPM_PRE_PMU: 2948 dmic_rate_val = 2949 wcd9335_get_dmic_clk_val(comp, 2950 wcd->mclk_rate, 2951 wcd->dmic_sample_rate); 2952 2953 (*dmic_clk_cnt)++; 2954 if (*dmic_clk_cnt == 1) { 2955 snd_soc_component_update_bits(comp, dmic_clk_reg, 2956 0x07 << dmic_rate_shift, 2957 dmic_rate_val << dmic_rate_shift); 2958 snd_soc_component_update_bits(comp, dmic_clk_reg, 2959 dmic_clk_en, dmic_clk_en); 2960 } 2961 2962 break; 2963 case SND_SOC_DAPM_POST_PMD: 2964 dmic_rate_val = 2965 wcd9335_get_dmic_clk_val(comp, 2966 wcd->mclk_rate, 2967 wcd->mad_dmic_sample_rate); 2968 (*dmic_clk_cnt)--; 2969 if (*dmic_clk_cnt == 0) { 2970 snd_soc_component_update_bits(comp, dmic_clk_reg, 2971 dmic_clk_en, 0); 2972 snd_soc_component_update_bits(comp, dmic_clk_reg, 2973 0x07 << dmic_rate_shift, 2974 dmic_rate_val << dmic_rate_shift); 2975 } 2976 break; 2977 } 2978 2979 return 0; 2980 } 2981 2982 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 2983 struct snd_soc_component *component) 2984 { 2985 int port_num = 0; 2986 unsigned short reg = 0; 2987 unsigned int val = 0; 2988 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2989 struct wcd9335_slim_ch *ch; 2990 2991 list_for_each_entry(ch, &dai->slim_ch_list, list) { 2992 if (ch->port >= WCD9335_RX_START) { 2993 port_num = ch->port - WCD9335_RX_START; 2994 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 2995 } else { 2996 port_num = ch->port; 2997 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 2998 } 2999 3000 regmap_read(wcd->if_regmap, reg, &val); 3001 if (!(val & BIT(port_num % 8))) 3002 regmap_write(wcd->if_regmap, reg, 3003 val | BIT(port_num % 8)); 3004 } 3005 } 3006 3007 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 3008 struct snd_kcontrol *kc, 3009 int event) 3010 { 3011 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3012 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 3013 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 3014 3015 switch (event) { 3016 case SND_SOC_DAPM_POST_PMU: 3017 wcd9335_codec_enable_int_port(dai, comp); 3018 break; 3019 case SND_SOC_DAPM_POST_PMD: 3020 kfree(dai->sconfig.chs); 3021 3022 break; 3023 } 3024 3025 return 0; 3026 } 3027 3028 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 3029 struct snd_kcontrol *kc, int event) 3030 { 3031 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3032 u16 gain_reg; 3033 int offset_val = 0; 3034 int val = 0; 3035 3036 switch (w->reg) { 3037 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3038 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 3039 break; 3040 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3041 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 3042 break; 3043 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3044 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3045 break; 3046 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3047 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3048 break; 3049 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3050 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3051 break; 3052 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3053 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3054 break; 3055 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3056 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3057 break; 3058 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3059 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3060 break; 3061 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3062 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3063 break; 3064 default: 3065 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3066 __func__, w->name); 3067 return 0; 3068 } 3069 3070 switch (event) { 3071 case SND_SOC_DAPM_POST_PMU: 3072 val = snd_soc_component_read(comp, gain_reg); 3073 val += offset_val; 3074 snd_soc_component_write(comp, gain_reg, val); 3075 break; 3076 case SND_SOC_DAPM_POST_PMD: 3077 break; 3078 } 3079 3080 return 0; 3081 } 3082 3083 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3084 { 3085 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3086 3087 switch (reg) { 3088 case WCD9335_CDC_RX0_RX_PATH_CTL: 3089 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3090 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3091 *ind = 0; 3092 break; 3093 case WCD9335_CDC_RX1_RX_PATH_CTL: 3094 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3095 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3096 *ind = 1; 3097 break; 3098 case WCD9335_CDC_RX2_RX_PATH_CTL: 3099 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3100 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3101 *ind = 2; 3102 break; 3103 case WCD9335_CDC_RX3_RX_PATH_CTL: 3104 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3105 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3106 *ind = 3; 3107 break; 3108 case WCD9335_CDC_RX4_RX_PATH_CTL: 3109 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3110 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3111 *ind = 4; 3112 break; 3113 case WCD9335_CDC_RX5_RX_PATH_CTL: 3114 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3115 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3116 *ind = 5; 3117 break; 3118 case WCD9335_CDC_RX6_RX_PATH_CTL: 3119 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3120 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3121 *ind = 6; 3122 break; 3123 case WCD9335_CDC_RX7_RX_PATH_CTL: 3124 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3125 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3126 *ind = 7; 3127 break; 3128 case WCD9335_CDC_RX8_RX_PATH_CTL: 3129 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3130 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3131 *ind = 8; 3132 break; 3133 } 3134 3135 return prim_int_reg; 3136 } 3137 3138 static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3139 u16 prim_int_reg, int event) 3140 { 3141 u16 hd2_scale_reg; 3142 u16 hd2_enable_reg = 0; 3143 3144 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3145 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3146 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3147 } 3148 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3149 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3150 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3151 } 3152 3153 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3154 snd_soc_component_update_bits(component, hd2_scale_reg, 3155 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3156 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3157 snd_soc_component_update_bits(component, hd2_scale_reg, 3158 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3159 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3160 snd_soc_component_update_bits(component, hd2_enable_reg, 3161 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3162 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3163 } 3164 3165 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3166 snd_soc_component_update_bits(component, hd2_enable_reg, 3167 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3168 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3169 snd_soc_component_update_bits(component, hd2_scale_reg, 3170 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3171 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3172 snd_soc_component_update_bits(component, hd2_scale_reg, 3173 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3174 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3175 } 3176 } 3177 3178 static int wcd9335_codec_enable_prim_interpolator( 3179 struct snd_soc_component *comp, 3180 u16 reg, int event) 3181 { 3182 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3183 u16 ind = 0; 3184 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3185 3186 switch (event) { 3187 case SND_SOC_DAPM_PRE_PMU: 3188 wcd->prim_int_users[ind]++; 3189 if (wcd->prim_int_users[ind] == 1) { 3190 snd_soc_component_update_bits(comp, prim_int_reg, 3191 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3192 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3193 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3194 snd_soc_component_update_bits(comp, prim_int_reg, 3195 WCD9335_CDC_RX_CLK_EN_MASK, 3196 WCD9335_CDC_RX_CLK_ENABLE); 3197 } 3198 3199 if ((reg != prim_int_reg) && 3200 ((snd_soc_component_read(comp, prim_int_reg)) & 3201 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3202 snd_soc_component_update_bits(comp, reg, 3203 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3204 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3205 break; 3206 case SND_SOC_DAPM_POST_PMD: 3207 wcd->prim_int_users[ind]--; 3208 if (wcd->prim_int_users[ind] == 0) { 3209 snd_soc_component_update_bits(comp, prim_int_reg, 3210 WCD9335_CDC_RX_CLK_EN_MASK, 3211 WCD9335_CDC_RX_CLK_DISABLE); 3212 snd_soc_component_update_bits(comp, prim_int_reg, 3213 WCD9335_CDC_RX_RESET_MASK, 3214 WCD9335_CDC_RX_RESET_ENABLE); 3215 snd_soc_component_update_bits(comp, prim_int_reg, 3216 WCD9335_CDC_RX_RESET_MASK, 3217 WCD9335_CDC_RX_RESET_DISABLE); 3218 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3219 } 3220 break; 3221 } 3222 3223 return 0; 3224 } 3225 3226 static int wcd9335_config_compander(struct snd_soc_component *component, 3227 int interp_n, int event) 3228 { 3229 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3230 int comp; 3231 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3232 3233 /* EAR does not have compander */ 3234 if (!interp_n) 3235 return 0; 3236 3237 comp = interp_n - 1; 3238 if (!wcd->comp_enabled[comp]) 3239 return 0; 3240 3241 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3242 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3243 3244 if (SND_SOC_DAPM_EVENT_ON(event)) { 3245 /* Enable Compander Clock */ 3246 snd_soc_component_update_bits(component, comp_ctl0_reg, 3247 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3248 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3249 /* Reset comander */ 3250 snd_soc_component_update_bits(component, comp_ctl0_reg, 3251 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3252 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3253 snd_soc_component_update_bits(component, comp_ctl0_reg, 3254 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3255 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3256 /* Enables DRE in this path */ 3257 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3258 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3259 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3260 } 3261 3262 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3263 snd_soc_component_update_bits(component, comp_ctl0_reg, 3264 WCD9335_CDC_COMPANDER_HALT_MASK, 3265 WCD9335_CDC_COMPANDER_HALT); 3266 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3267 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3268 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3269 3270 snd_soc_component_update_bits(component, comp_ctl0_reg, 3271 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3272 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3273 snd_soc_component_update_bits(component, comp_ctl0_reg, 3274 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3275 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3276 snd_soc_component_update_bits(component, comp_ctl0_reg, 3277 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3278 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3279 snd_soc_component_update_bits(component, comp_ctl0_reg, 3280 WCD9335_CDC_COMPANDER_HALT_MASK, 3281 WCD9335_CDC_COMPANDER_NOHALT); 3282 } 3283 3284 return 0; 3285 } 3286 3287 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3288 struct snd_kcontrol *kc, int event) 3289 { 3290 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3291 u16 gain_reg; 3292 u16 reg; 3293 int val; 3294 int offset_val = 0; 3295 3296 if (!(strcmp(w->name, "RX INT0 INTERP"))) { 3297 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3298 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3299 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) { 3300 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3301 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3302 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) { 3303 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3304 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3305 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) { 3306 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3307 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3308 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) { 3309 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3310 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3311 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) { 3312 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3313 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3314 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) { 3315 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3316 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3317 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) { 3318 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3319 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3320 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) { 3321 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3322 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3323 } else { 3324 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3325 __func__); 3326 return -EINVAL; 3327 } 3328 3329 switch (event) { 3330 case SND_SOC_DAPM_PRE_PMU: 3331 /* Reset if needed */ 3332 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3333 break; 3334 case SND_SOC_DAPM_POST_PMU: 3335 wcd9335_config_compander(comp, w->shift, event); 3336 val = snd_soc_component_read(comp, gain_reg); 3337 val += offset_val; 3338 snd_soc_component_write(comp, gain_reg, val); 3339 break; 3340 case SND_SOC_DAPM_POST_PMD: 3341 wcd9335_config_compander(comp, w->shift, event); 3342 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3343 break; 3344 } 3345 3346 return 0; 3347 } 3348 3349 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3350 u8 gain) 3351 { 3352 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3353 u8 hph_l_en, hph_r_en; 3354 u8 l_val, r_val; 3355 u8 hph_pa_status; 3356 bool is_hphl_pa, is_hphr_pa; 3357 3358 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH); 3359 is_hphl_pa = hph_pa_status >> 7; 3360 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3361 3362 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN); 3363 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN); 3364 3365 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3366 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3367 3368 /* 3369 * Set HPH_L & HPH_R gain source selection to REGISTER 3370 * for better click and pop only if corresponding PAs are 3371 * not enabled. Also cache the values of the HPHL/R 3372 * PA gains to be applied after PAs are enabled 3373 */ 3374 if ((l_val != hph_l_en) && !is_hphl_pa) { 3375 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3376 wcd->hph_l_gain = hph_l_en & 0x1F; 3377 } 3378 3379 if ((r_val != hph_r_en) && !is_hphr_pa) { 3380 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3381 wcd->hph_r_gain = hph_r_en & 0x1F; 3382 } 3383 } 3384 3385 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3386 int event) 3387 { 3388 if (SND_SOC_DAPM_EVENT_ON(event)) { 3389 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3390 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3391 0x06); 3392 snd_soc_component_update_bits(comp, 3393 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3394 0xF0, 0x40); 3395 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3396 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3397 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3398 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3399 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3400 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3401 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3402 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3403 0x0C); 3404 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3405 } 3406 3407 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3408 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3409 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3410 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3411 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3412 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3413 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3414 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3415 0x8A); 3416 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3417 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3418 0x0A); 3419 } 3420 } 3421 3422 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3423 int event) 3424 { 3425 if (SND_SOC_DAPM_EVENT_ON(event)) { 3426 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3427 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3428 0x0C); 3429 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3430 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3431 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3432 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3433 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3434 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3435 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3436 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3437 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3438 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3439 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3440 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3441 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3442 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3443 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3444 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3445 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3446 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3447 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3448 snd_soc_component_update_bits(comp, 3449 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3450 snd_soc_component_update_bits(comp, 3451 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3452 } 3453 3454 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3455 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3456 0x88); 3457 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3458 0x33); 3459 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3460 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3461 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3462 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3463 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3464 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3465 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3466 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3467 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3468 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3469 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3470 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3471 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3472 WCD9335_HPH_CONST_SEL_L_MASK, 3473 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3474 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3475 WCD9335_HPH_CONST_SEL_L_MASK, 3476 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3477 } 3478 } 3479 3480 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3481 int event) 3482 { 3483 if (SND_SOC_DAPM_EVENT_ON(event)) { 3484 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3485 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3486 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3487 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3488 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3489 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3490 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3491 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3492 0x0C); 3493 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3494 } 3495 3496 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3497 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3498 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3499 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3500 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3501 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3502 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3503 } 3504 } 3505 3506 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3507 int event, int mode) 3508 { 3509 switch (mode) { 3510 case CLS_H_LP: 3511 wcd9335_codec_hph_lp_config(component, event); 3512 break; 3513 case CLS_H_LOHIFI: 3514 wcd9335_codec_hph_lohifi_config(component, event); 3515 break; 3516 case CLS_H_HIFI: 3517 wcd9335_codec_hph_hifi_config(component, event); 3518 break; 3519 } 3520 } 3521 3522 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3523 struct snd_kcontrol *kc, 3524 int event) 3525 { 3526 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3527 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3528 int hph_mode = wcd->hph_mode; 3529 u8 dem_inp; 3530 3531 switch (event) { 3532 case SND_SOC_DAPM_PRE_PMU: 3533 /* Read DEM INP Select */ 3534 dem_inp = snd_soc_component_read(comp, 3535 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3536 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3537 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3538 dev_err(comp->dev, "Incorrect DEM Input\n"); 3539 return -EINVAL; 3540 } 3541 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3542 WCD_CLSH_STATE_HPHL, 3543 ((hph_mode == CLS_H_LOHIFI) ? 3544 CLS_H_HIFI : hph_mode)); 3545 3546 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3547 3548 break; 3549 case SND_SOC_DAPM_POST_PMU: 3550 usleep_range(1000, 1100); 3551 break; 3552 case SND_SOC_DAPM_PRE_PMD: 3553 break; 3554 case SND_SOC_DAPM_POST_PMD: 3555 /* 1000us required as per HW requirement */ 3556 usleep_range(1000, 1100); 3557 3558 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3559 WCD_CLSH_STATE_HPHR)) 3560 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3561 3562 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3563 WCD_CLSH_STATE_HPHL, 3564 ((hph_mode == CLS_H_LOHIFI) ? 3565 CLS_H_HIFI : hph_mode)); 3566 break; 3567 } 3568 3569 return 0; 3570 } 3571 3572 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3573 struct snd_kcontrol *kc, int event) 3574 { 3575 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3576 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3577 3578 switch (event) { 3579 case SND_SOC_DAPM_PRE_PMU: 3580 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3581 WCD_CLSH_STATE_LO, CLS_AB); 3582 break; 3583 case SND_SOC_DAPM_POST_PMD: 3584 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3585 WCD_CLSH_STATE_LO, CLS_AB); 3586 break; 3587 } 3588 3589 return 0; 3590 } 3591 3592 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3593 struct snd_kcontrol *kc, int event) 3594 { 3595 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3596 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3597 3598 switch (event) { 3599 case SND_SOC_DAPM_PRE_PMU: 3600 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3601 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3602 3603 break; 3604 case SND_SOC_DAPM_POST_PMD: 3605 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3606 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3607 break; 3608 } 3609 3610 return 0; 3611 } 3612 3613 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3614 int mode, int event) 3615 { 3616 u8 scale_val = 0; 3617 3618 switch (event) { 3619 case SND_SOC_DAPM_POST_PMU: 3620 switch (mode) { 3621 case CLS_H_HIFI: 3622 scale_val = 0x3; 3623 break; 3624 case CLS_H_LOHIFI: 3625 scale_val = 0x1; 3626 break; 3627 } 3628 break; 3629 case SND_SOC_DAPM_PRE_PMD: 3630 scale_val = 0x6; 3631 break; 3632 } 3633 3634 if (scale_val) 3635 snd_soc_component_update_bits(wcd->component, 3636 WCD9335_HPH_PA_CTL1, 3637 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3638 scale_val << 1); 3639 if (SND_SOC_DAPM_EVENT_ON(event)) { 3640 if (wcd->comp_enabled[COMPANDER_1] || 3641 wcd->comp_enabled[COMPANDER_2]) { 3642 /* GAIN Source Selection */ 3643 snd_soc_component_update_bits(wcd->component, 3644 WCD9335_HPH_L_EN, 3645 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3646 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3647 snd_soc_component_update_bits(wcd->component, 3648 WCD9335_HPH_R_EN, 3649 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3650 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3651 snd_soc_component_update_bits(wcd->component, 3652 WCD9335_HPH_AUTO_CHOP, 3653 WCD9335_HPH_AUTO_CHOP_MASK, 3654 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3655 } 3656 snd_soc_component_update_bits(wcd->component, 3657 WCD9335_HPH_L_EN, 3658 WCD9335_HPH_PA_GAIN_MASK, 3659 wcd->hph_l_gain); 3660 snd_soc_component_update_bits(wcd->component, 3661 WCD9335_HPH_R_EN, 3662 WCD9335_HPH_PA_GAIN_MASK, 3663 wcd->hph_r_gain); 3664 } 3665 3666 if (SND_SOC_DAPM_EVENT_OFF(event)) 3667 snd_soc_component_update_bits(wcd->component, 3668 WCD9335_HPH_AUTO_CHOP, 3669 WCD9335_HPH_AUTO_CHOP_MASK, 3670 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3671 } 3672 3673 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3674 struct snd_kcontrol *kc, 3675 int event) 3676 { 3677 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3678 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3679 int hph_mode = wcd->hph_mode; 3680 u8 dem_inp; 3681 3682 switch (event) { 3683 case SND_SOC_DAPM_PRE_PMU: 3684 3685 /* Read DEM INP Select */ 3686 dem_inp = snd_soc_component_read(comp, 3687 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3688 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3689 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3690 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3691 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3692 hph_mode); 3693 return -EINVAL; 3694 } 3695 3696 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3697 WCD_CLSH_EVENT_PRE_DAC, 3698 WCD_CLSH_STATE_HPHR, 3699 ((hph_mode == CLS_H_LOHIFI) ? 3700 CLS_H_HIFI : hph_mode)); 3701 3702 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3703 3704 break; 3705 case SND_SOC_DAPM_POST_PMD: 3706 /* 1000us required as per HW requirement */ 3707 usleep_range(1000, 1100); 3708 3709 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3710 WCD_CLSH_STATE_HPHL)) 3711 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3712 3713 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3714 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3715 CLS_H_HIFI : hph_mode)); 3716 break; 3717 } 3718 3719 return 0; 3720 } 3721 3722 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3723 struct snd_kcontrol *kc, 3724 int event) 3725 { 3726 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3727 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3728 int hph_mode = wcd->hph_mode; 3729 3730 switch (event) { 3731 case SND_SOC_DAPM_PRE_PMU: 3732 break; 3733 case SND_SOC_DAPM_POST_PMU: 3734 /* 3735 * 7ms sleep is required after PA is enabled as per 3736 * HW requirement 3737 */ 3738 usleep_range(7000, 7100); 3739 3740 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3741 snd_soc_component_update_bits(comp, 3742 WCD9335_CDC_RX1_RX_PATH_CTL, 3743 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3744 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3745 3746 /* Remove mix path mute if it is enabled */ 3747 if ((snd_soc_component_read(comp, 3748 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3749 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3750 snd_soc_component_update_bits(comp, 3751 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3752 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3753 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3754 3755 break; 3756 case SND_SOC_DAPM_PRE_PMD: 3757 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3758 break; 3759 case SND_SOC_DAPM_POST_PMD: 3760 /* 5ms sleep is required after PA is disabled as per 3761 * HW requirement 3762 */ 3763 usleep_range(5000, 5500); 3764 break; 3765 } 3766 3767 return 0; 3768 } 3769 3770 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3771 struct snd_kcontrol *kc, 3772 int event) 3773 { 3774 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3775 int vol_reg = 0, mix_vol_reg = 0; 3776 3777 if (w->reg == WCD9335_ANA_LO_1_2) { 3778 if (w->shift == 7) { 3779 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3780 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3781 } else if (w->shift == 6) { 3782 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3783 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3784 } 3785 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3786 if (w->shift == 7) { 3787 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3788 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3789 } else if (w->shift == 6) { 3790 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3791 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3792 } 3793 } else { 3794 dev_err(comp->dev, "Error enabling lineout PA\n"); 3795 return -EINVAL; 3796 } 3797 3798 switch (event) { 3799 case SND_SOC_DAPM_POST_PMU: 3800 /* 5ms sleep is required after PA is enabled as per 3801 * HW requirement 3802 */ 3803 usleep_range(5000, 5500); 3804 snd_soc_component_update_bits(comp, vol_reg, 3805 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3806 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3807 3808 /* Remove mix path mute if it is enabled */ 3809 if ((snd_soc_component_read(comp, mix_vol_reg)) & 3810 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3811 snd_soc_component_update_bits(comp, mix_vol_reg, 3812 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3813 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3814 break; 3815 case SND_SOC_DAPM_POST_PMD: 3816 /* 5ms sleep is required after PA is disabled as per 3817 * HW requirement 3818 */ 3819 usleep_range(5000, 5500); 3820 break; 3821 } 3822 3823 return 0; 3824 } 3825 3826 static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3827 { 3828 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3829 WCD9335_HPH_CONST_SEL_L_MASK, 3830 WCD9335_HPH_CONST_SEL_L_BYPASS); 3831 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3832 WCD9335_HPH_CONST_SEL_L_MASK, 3833 WCD9335_HPH_CONST_SEL_L_BYPASS); 3834 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3835 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3836 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3837 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3838 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3839 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3840 } 3841 3842 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3843 struct snd_kcontrol *kc, int event) 3844 { 3845 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3846 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3847 3848 switch (event) { 3849 case SND_SOC_DAPM_PRE_PMU: 3850 wcd->rx_bias_count++; 3851 if (wcd->rx_bias_count == 1) { 3852 wcd9335_codec_init_flyback(comp); 3853 snd_soc_component_update_bits(comp, 3854 WCD9335_ANA_RX_SUPPLIES, 3855 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3856 WCD9335_ANA_RX_BIAS_ENABLE); 3857 } 3858 break; 3859 case SND_SOC_DAPM_POST_PMD: 3860 wcd->rx_bias_count--; 3861 if (!wcd->rx_bias_count) 3862 snd_soc_component_update_bits(comp, 3863 WCD9335_ANA_RX_SUPPLIES, 3864 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3865 WCD9335_ANA_RX_BIAS_DISABLE); 3866 break; 3867 } 3868 3869 return 0; 3870 } 3871 3872 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3873 struct snd_kcontrol *kc, int event) 3874 { 3875 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3876 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3877 int hph_mode = wcd->hph_mode; 3878 3879 switch (event) { 3880 case SND_SOC_DAPM_PRE_PMU: 3881 break; 3882 case SND_SOC_DAPM_POST_PMU: 3883 /* 3884 * 7ms sleep is required after PA is enabled as per 3885 * HW requirement 3886 */ 3887 usleep_range(7000, 7100); 3888 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3889 snd_soc_component_update_bits(comp, 3890 WCD9335_CDC_RX2_RX_PATH_CTL, 3891 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3892 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3893 /* Remove mix path mute if it is enabled */ 3894 if ((snd_soc_component_read(comp, 3895 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3896 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3897 snd_soc_component_update_bits(comp, 3898 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3899 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3900 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3901 3902 break; 3903 3904 case SND_SOC_DAPM_PRE_PMD: 3905 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3906 break; 3907 case SND_SOC_DAPM_POST_PMD: 3908 /* 5ms sleep is required after PA is disabled as per 3909 * HW requirement 3910 */ 3911 usleep_range(5000, 5500); 3912 break; 3913 } 3914 3915 return 0; 3916 } 3917 3918 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3919 struct snd_kcontrol *kc, int event) 3920 { 3921 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3922 3923 switch (event) { 3924 case SND_SOC_DAPM_POST_PMU: 3925 /* 5ms sleep is required after PA is enabled as per 3926 * HW requirement 3927 */ 3928 usleep_range(5000, 5500); 3929 snd_soc_component_update_bits(comp, 3930 WCD9335_CDC_RX0_RX_PATH_CTL, 3931 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3932 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3933 /* Remove mix path mute if it is enabled */ 3934 if ((snd_soc_component_read(comp, 3935 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3936 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3937 snd_soc_component_update_bits(comp, 3938 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3939 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3940 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3941 break; 3942 case SND_SOC_DAPM_POST_PMD: 3943 /* 5ms sleep is required after PA is disabled as per 3944 * HW requirement 3945 */ 3946 usleep_range(5000, 5500); 3947 3948 break; 3949 } 3950 3951 return 0; 3952 } 3953 3954 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3955 { 3956 struct wcd9335_codec *wcd = data; 3957 unsigned long status = 0; 3958 int i, j, port_id; 3959 unsigned int val, int_val = 0; 3960 irqreturn_t ret = IRQ_NONE; 3961 bool tx; 3962 unsigned short reg = 0; 3963 3964 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3965 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3966 regmap_read(wcd->if_regmap, i, &val); 3967 status |= ((u32)val << (8 * j)); 3968 } 3969 3970 for_each_set_bit(j, &status, 32) { 3971 tx = (j >= 16); 3972 port_id = (tx ? j - 16 : j); 3973 regmap_read(wcd->if_regmap, 3974 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3975 if (val) { 3976 if (!tx) 3977 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3978 (port_id / 8); 3979 else 3980 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3981 (port_id / 8); 3982 regmap_read( 3983 wcd->if_regmap, reg, &int_val); 3984 /* 3985 * Ignore interrupts for ports for which the 3986 * interrupts are not specifically enabled. 3987 */ 3988 if (!(int_val & (1 << (port_id % 8)))) 3989 continue; 3990 } 3991 3992 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 3993 dev_err_ratelimited(wcd->dev, 3994 "%s: overflow error on %s port %d, value %x\n", 3995 __func__, (tx ? "TX" : "RX"), port_id, val); 3996 3997 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 3998 dev_err_ratelimited(wcd->dev, 3999 "%s: underflow error on %s port %d, value %x\n", 4000 __func__, (tx ? "TX" : "RX"), port_id, val); 4001 4002 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 4003 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 4004 if (!tx) 4005 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4006 (port_id / 8); 4007 else 4008 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4009 (port_id / 8); 4010 regmap_read( 4011 wcd->if_regmap, reg, &int_val); 4012 if (int_val & (1 << (port_id % 8))) { 4013 int_val = int_val ^ (1 << (port_id % 8)); 4014 regmap_write(wcd->if_regmap, 4015 reg, int_val); 4016 } 4017 } 4018 4019 regmap_write(wcd->if_regmap, 4020 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 4021 BIT(j % 8)); 4022 ret = IRQ_HANDLED; 4023 } 4024 4025 return ret; 4026 } 4027 4028 static struct wcd9335_irq wcd9335_irqs[] = { 4029 { 4030 .irq = WCD9335_IRQ_SLIMBUS, 4031 .handler = wcd9335_slimbus_irq, 4032 .name = "SLIM Slave", 4033 }, 4034 }; 4035 4036 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 4037 { 4038 int irq, ret, i; 4039 4040 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 4041 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 4042 if (irq < 0) { 4043 dev_err(wcd->dev, "Failed to get %s\n", 4044 wcd9335_irqs[i].name); 4045 return irq; 4046 } 4047 4048 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4049 wcd9335_irqs[i].handler, 4050 IRQF_TRIGGER_RISING | 4051 IRQF_ONESHOT, 4052 wcd9335_irqs[i].name, wcd); 4053 if (ret) { 4054 dev_err(wcd->dev, "Failed to request %s\n", 4055 wcd9335_irqs[i].name); 4056 return ret; 4057 } 4058 } 4059 4060 /* enable interrupts on all slave ports */ 4061 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4062 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4063 0xFF); 4064 4065 return ret; 4066 } 4067 4068 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd) 4069 { 4070 int i; 4071 4072 /* disable interrupts on all slave ports */ 4073 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4074 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4075 0x00); 4076 } 4077 4078 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4079 bool ccl_flag) 4080 { 4081 struct snd_soc_component *comp = wcd->component; 4082 4083 if (ccl_flag) { 4084 if (++wcd->sido_ccl_cnt == 1) 4085 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4086 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4087 } else { 4088 if (wcd->sido_ccl_cnt == 0) { 4089 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4090 return; 4091 } 4092 if (--wcd->sido_ccl_cnt == 0) 4093 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4094 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4095 } 4096 } 4097 4098 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4099 { 4100 wcd->master_bias_users++; 4101 if (wcd->master_bias_users == 1) { 4102 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4103 WCD9335_ANA_BIAS_EN_MASK, 4104 WCD9335_ANA_BIAS_ENABLE); 4105 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4106 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4107 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4108 /* 4109 * 1ms delay is required after pre-charge is enabled 4110 * as per HW requirement 4111 */ 4112 usleep_range(1000, 1100); 4113 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4114 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4115 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4116 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4117 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4118 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4119 } 4120 4121 return 0; 4122 } 4123 4124 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4125 { 4126 /* Enable mclk requires master bias to be enabled first */ 4127 if (wcd->master_bias_users <= 0) 4128 return -EINVAL; 4129 4130 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4131 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4132 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4133 wcd->clk_type); 4134 return -EINVAL; 4135 } 4136 4137 if (++wcd->clk_mclk_users == 1) { 4138 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4139 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4140 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4141 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4142 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4143 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4144 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4145 WCD9335_ANA_CLK_MCLK_EN_MASK, 4146 WCD9335_ANA_CLK_MCLK_ENABLE); 4147 regmap_update_bits(wcd->regmap, 4148 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4149 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4150 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4151 regmap_update_bits(wcd->regmap, 4152 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4153 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4154 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4155 /* 4156 * 10us sleep is required after clock is enabled 4157 * as per HW requirement 4158 */ 4159 usleep_range(10, 15); 4160 } 4161 4162 wcd->clk_type = WCD_CLK_MCLK; 4163 4164 return 0; 4165 } 4166 4167 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4168 { 4169 if (wcd->clk_mclk_users <= 0) 4170 return -EINVAL; 4171 4172 if (--wcd->clk_mclk_users == 0) { 4173 if (wcd->clk_rco_users > 0) { 4174 /* MCLK to RCO switch */ 4175 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4176 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4177 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4178 wcd->clk_type = WCD_CLK_RCO; 4179 } else { 4180 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4181 WCD9335_ANA_CLK_MCLK_EN_MASK, 4182 WCD9335_ANA_CLK_MCLK_DISABLE); 4183 wcd->clk_type = WCD_CLK_OFF; 4184 } 4185 4186 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4187 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4188 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4189 } 4190 4191 return 0; 4192 } 4193 4194 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4195 { 4196 if (wcd->master_bias_users <= 0) 4197 return -EINVAL; 4198 4199 wcd->master_bias_users--; 4200 if (wcd->master_bias_users == 0) { 4201 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4202 WCD9335_ANA_BIAS_EN_MASK, 4203 WCD9335_ANA_BIAS_DISABLE); 4204 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4205 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4206 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4207 } 4208 return 0; 4209 } 4210 4211 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4212 bool enable) 4213 { 4214 int ret = 0; 4215 4216 if (enable) { 4217 wcd9335_cdc_sido_ccl_enable(wcd, true); 4218 ret = clk_prepare_enable(wcd->mclk); 4219 if (ret) { 4220 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4221 __func__); 4222 goto err; 4223 } 4224 /* get BG */ 4225 wcd9335_enable_master_bias(wcd); 4226 /* get MCLK */ 4227 wcd9335_enable_mclk(wcd); 4228 4229 } else { 4230 /* put MCLK */ 4231 wcd9335_disable_mclk(wcd); 4232 /* put BG */ 4233 wcd9335_disable_master_bias(wcd); 4234 clk_disable_unprepare(wcd->mclk); 4235 wcd9335_cdc_sido_ccl_enable(wcd, false); 4236 } 4237 err: 4238 return ret; 4239 } 4240 4241 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4242 enum wcd9335_sido_voltage req_mv) 4243 { 4244 struct snd_soc_component *comp = wcd->component; 4245 int vout_d_val; 4246 4247 if (req_mv == wcd->sido_voltage) 4248 return; 4249 4250 /* compute the vout_d step value */ 4251 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4252 WCD9335_ANA_BUCK_VOUT_MASK; 4253 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4254 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4255 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4256 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4257 4258 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4259 usleep_range(1000, 1100); 4260 wcd->sido_voltage = req_mv; 4261 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4262 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4263 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4264 } 4265 4266 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4267 enum wcd9335_sido_voltage req_mv) 4268 { 4269 int ret = 0; 4270 4271 /* enable mclk before setting SIDO voltage */ 4272 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4273 if (ret) { 4274 dev_err(wcd->dev, "Ext clk enable failed\n"); 4275 goto err; 4276 } 4277 4278 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4279 wcd9335_cdc_req_mclk_enable(wcd, false); 4280 4281 err: 4282 return ret; 4283 } 4284 4285 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4286 int enable) 4287 { 4288 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4289 int ret; 4290 4291 if (enable) { 4292 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4293 if (ret) 4294 return ret; 4295 4296 wcd9335_codec_apply_sido_voltage(wcd, 4297 SIDO_VOLTAGE_NOMINAL_MV); 4298 } else { 4299 wcd9335_codec_update_sido_voltage(wcd, 4300 wcd->sido_voltage); 4301 wcd9335_cdc_req_mclk_enable(wcd, false); 4302 } 4303 4304 return 0; 4305 } 4306 4307 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4308 struct snd_kcontrol *kc, int event) 4309 { 4310 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4311 4312 switch (event) { 4313 case SND_SOC_DAPM_PRE_PMU: 4314 return _wcd9335_codec_enable_mclk(comp, true); 4315 case SND_SOC_DAPM_POST_PMD: 4316 return _wcd9335_codec_enable_mclk(comp, false); 4317 } 4318 4319 return 0; 4320 } 4321 4322 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4323 /* TODO SPK1 & SPK2 OUT*/ 4324 SND_SOC_DAPM_OUTPUT("EAR"), 4325 SND_SOC_DAPM_OUTPUT("HPHL"), 4326 SND_SOC_DAPM_OUTPUT("HPHR"), 4327 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4328 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4329 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4330 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4331 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4332 AIF1_PB, 0, wcd9335_codec_enable_slim, 4333 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4334 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4335 AIF2_PB, 0, wcd9335_codec_enable_slim, 4336 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4337 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4338 AIF3_PB, 0, wcd9335_codec_enable_slim, 4339 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4340 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4341 AIF4_PB, 0, wcd9335_codec_enable_slim, 4342 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4343 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4344 &slim_rx_mux[WCD9335_RX0]), 4345 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4346 &slim_rx_mux[WCD9335_RX1]), 4347 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4348 &slim_rx_mux[WCD9335_RX2]), 4349 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4350 &slim_rx_mux[WCD9335_RX3]), 4351 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4352 &slim_rx_mux[WCD9335_RX4]), 4353 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4354 &slim_rx_mux[WCD9335_RX5]), 4355 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4356 &slim_rx_mux[WCD9335_RX6]), 4357 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4358 &slim_rx_mux[WCD9335_RX7]), 4359 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4360 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4361 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4362 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4363 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4364 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4365 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4366 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4367 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4368 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4369 SND_SOC_DAPM_POST_PMU), 4370 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4371 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4372 SND_SOC_DAPM_POST_PMU), 4373 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4374 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4375 SND_SOC_DAPM_POST_PMU), 4376 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4377 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4378 SND_SOC_DAPM_POST_PMU), 4379 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4380 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4381 SND_SOC_DAPM_POST_PMU), 4382 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4383 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4384 SND_SOC_DAPM_POST_PMU), 4385 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4386 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4387 SND_SOC_DAPM_POST_PMU), 4388 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4389 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4390 SND_SOC_DAPM_POST_PMU), 4391 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4392 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4393 SND_SOC_DAPM_POST_PMU), 4394 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4395 &rx_int0_1_mix_inp0_mux), 4396 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4397 &rx_int0_1_mix_inp1_mux), 4398 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4399 &rx_int0_1_mix_inp2_mux), 4400 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4401 &rx_int1_1_mix_inp0_mux), 4402 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4403 &rx_int1_1_mix_inp1_mux), 4404 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4405 &rx_int1_1_mix_inp2_mux), 4406 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4407 &rx_int2_1_mix_inp0_mux), 4408 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4409 &rx_int2_1_mix_inp1_mux), 4410 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4411 &rx_int2_1_mix_inp2_mux), 4412 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4413 &rx_int3_1_mix_inp0_mux), 4414 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4415 &rx_int3_1_mix_inp1_mux), 4416 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4417 &rx_int3_1_mix_inp2_mux), 4418 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4419 &rx_int4_1_mix_inp0_mux), 4420 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4421 &rx_int4_1_mix_inp1_mux), 4422 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4423 &rx_int4_1_mix_inp2_mux), 4424 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4425 &rx_int5_1_mix_inp0_mux), 4426 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4427 &rx_int5_1_mix_inp1_mux), 4428 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4429 &rx_int5_1_mix_inp2_mux), 4430 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4431 &rx_int6_1_mix_inp0_mux), 4432 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4433 &rx_int6_1_mix_inp1_mux), 4434 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4435 &rx_int6_1_mix_inp2_mux), 4436 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4437 &rx_int7_1_mix_inp0_mux), 4438 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4439 &rx_int7_1_mix_inp1_mux), 4440 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4441 &rx_int7_1_mix_inp2_mux), 4442 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4443 &rx_int8_1_mix_inp0_mux), 4444 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4445 &rx_int8_1_mix_inp1_mux), 4446 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4447 &rx_int8_1_mix_inp2_mux), 4448 4449 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4450 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4451 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4452 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4453 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4454 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4455 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4456 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4457 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4458 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4459 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4460 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4461 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4462 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4463 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4464 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4465 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4466 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4467 4468 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4469 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4470 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4471 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4472 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4473 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4474 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4475 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4476 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4477 4478 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4479 &rx_int0_dem_inp_mux), 4480 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4481 &rx_int1_dem_inp_mux), 4482 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4483 &rx_int2_dem_inp_mux), 4484 4485 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4486 INTERP_EAR, 0, &rx_int0_interp_mux, 4487 wcd9335_codec_enable_interpolator, 4488 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4489 SND_SOC_DAPM_POST_PMD), 4490 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4491 INTERP_HPHL, 0, &rx_int1_interp_mux, 4492 wcd9335_codec_enable_interpolator, 4493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4494 SND_SOC_DAPM_POST_PMD), 4495 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4496 INTERP_HPHR, 0, &rx_int2_interp_mux, 4497 wcd9335_codec_enable_interpolator, 4498 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4499 SND_SOC_DAPM_POST_PMD), 4500 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4501 INTERP_LO1, 0, &rx_int3_interp_mux, 4502 wcd9335_codec_enable_interpolator, 4503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4504 SND_SOC_DAPM_POST_PMD), 4505 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4506 INTERP_LO2, 0, &rx_int4_interp_mux, 4507 wcd9335_codec_enable_interpolator, 4508 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4509 SND_SOC_DAPM_POST_PMD), 4510 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4511 INTERP_LO3, 0, &rx_int5_interp_mux, 4512 wcd9335_codec_enable_interpolator, 4513 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4514 SND_SOC_DAPM_POST_PMD), 4515 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4516 INTERP_LO4, 0, &rx_int6_interp_mux, 4517 wcd9335_codec_enable_interpolator, 4518 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4519 SND_SOC_DAPM_POST_PMD), 4520 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4521 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4522 wcd9335_codec_enable_interpolator, 4523 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4524 SND_SOC_DAPM_POST_PMD), 4525 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4526 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4527 wcd9335_codec_enable_interpolator, 4528 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4529 SND_SOC_DAPM_POST_PMD), 4530 4531 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4532 0, 0, wcd9335_codec_ear_dac_event, 4533 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4534 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4535 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4536 5, 0, wcd9335_codec_hphl_dac_event, 4537 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4538 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4539 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4540 4, 0, wcd9335_codec_hphr_dac_event, 4541 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4542 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4543 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4544 0, 0, wcd9335_codec_lineout_dac_event, 4545 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4546 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4547 0, 0, wcd9335_codec_lineout_dac_event, 4548 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4549 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4550 0, 0, wcd9335_codec_lineout_dac_event, 4551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4552 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4553 0, 0, wcd9335_codec_lineout_dac_event, 4554 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4555 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4556 wcd9335_codec_enable_hphl_pa, 4557 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4558 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4559 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4560 wcd9335_codec_enable_hphr_pa, 4561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4562 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4563 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4564 wcd9335_codec_enable_ear_pa, 4565 SND_SOC_DAPM_POST_PMU | 4566 SND_SOC_DAPM_POST_PMD), 4567 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4568 wcd9335_codec_enable_lineout_pa, 4569 SND_SOC_DAPM_POST_PMU | 4570 SND_SOC_DAPM_POST_PMD), 4571 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4572 wcd9335_codec_enable_lineout_pa, 4573 SND_SOC_DAPM_POST_PMU | 4574 SND_SOC_DAPM_POST_PMD), 4575 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4576 wcd9335_codec_enable_lineout_pa, 4577 SND_SOC_DAPM_POST_PMU | 4578 SND_SOC_DAPM_POST_PMD), 4579 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4580 wcd9335_codec_enable_lineout_pa, 4581 SND_SOC_DAPM_POST_PMU | 4582 SND_SOC_DAPM_POST_PMD), 4583 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4584 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4585 SND_SOC_DAPM_POST_PMD), 4586 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4587 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4588 SND_SOC_DAPM_POST_PMD), 4589 4590 /* TX */ 4591 SND_SOC_DAPM_INPUT("AMIC1"), 4592 SND_SOC_DAPM_INPUT("AMIC2"), 4593 SND_SOC_DAPM_INPUT("AMIC3"), 4594 SND_SOC_DAPM_INPUT("AMIC4"), 4595 SND_SOC_DAPM_INPUT("AMIC5"), 4596 SND_SOC_DAPM_INPUT("AMIC6"), 4597 4598 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4599 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4600 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4601 4602 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4603 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4604 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4605 4606 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4607 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4608 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4609 4610 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4611 wcd9335_codec_enable_micbias, 4612 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4613 SND_SOC_DAPM_POST_PMD), 4614 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4615 wcd9335_codec_enable_micbias, 4616 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4617 SND_SOC_DAPM_POST_PMD), 4618 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4619 wcd9335_codec_enable_micbias, 4620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4621 SND_SOC_DAPM_POST_PMD), 4622 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4623 wcd9335_codec_enable_micbias, 4624 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4625 SND_SOC_DAPM_POST_PMD), 4626 4627 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4628 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4629 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4630 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4631 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4632 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4633 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4634 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4635 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4636 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4637 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4638 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4639 4640 /* Digital Mic Inputs */ 4641 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4642 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4643 SND_SOC_DAPM_POST_PMD), 4644 4645 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4646 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4647 SND_SOC_DAPM_POST_PMD), 4648 4649 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4650 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4651 SND_SOC_DAPM_POST_PMD), 4652 4653 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4654 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4655 SND_SOC_DAPM_POST_PMD), 4656 4657 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4658 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4659 SND_SOC_DAPM_POST_PMD), 4660 4661 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4662 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4663 SND_SOC_DAPM_POST_PMD), 4664 4665 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4666 &tx_dmic_mux0), 4667 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4668 &tx_dmic_mux1), 4669 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4670 &tx_dmic_mux2), 4671 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4672 &tx_dmic_mux3), 4673 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4674 &tx_dmic_mux4), 4675 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4676 &tx_dmic_mux5), 4677 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4678 &tx_dmic_mux6), 4679 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4680 &tx_dmic_mux7), 4681 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4682 &tx_dmic_mux8), 4683 4684 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4685 &tx_amic_mux0), 4686 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4687 &tx_amic_mux1), 4688 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4689 &tx_amic_mux2), 4690 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4691 &tx_amic_mux3), 4692 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4693 &tx_amic_mux4), 4694 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4695 &tx_amic_mux5), 4696 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4697 &tx_amic_mux6), 4698 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4699 &tx_amic_mux7), 4700 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4701 &tx_amic_mux8), 4702 4703 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4704 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4705 4706 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4707 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4708 4709 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4710 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4711 4712 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4713 &sb_tx0_mux), 4714 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4715 &sb_tx1_mux), 4716 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4717 &sb_tx2_mux), 4718 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4719 &sb_tx3_mux), 4720 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4721 &sb_tx4_mux), 4722 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4723 &sb_tx5_mux), 4724 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4725 &sb_tx6_mux), 4726 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4727 &sb_tx7_mux), 4728 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4729 &sb_tx8_mux), 4730 4731 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4732 &tx_adc_mux0, wcd9335_codec_enable_dec, 4733 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4734 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4735 4736 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4737 &tx_adc_mux1, wcd9335_codec_enable_dec, 4738 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4739 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4740 4741 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4742 &tx_adc_mux2, wcd9335_codec_enable_dec, 4743 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4744 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4745 4746 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4747 &tx_adc_mux3, wcd9335_codec_enable_dec, 4748 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4749 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4750 4751 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4752 &tx_adc_mux4, wcd9335_codec_enable_dec, 4753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4754 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4755 4756 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4757 &tx_adc_mux5, wcd9335_codec_enable_dec, 4758 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4759 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4760 4761 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4762 &tx_adc_mux6, wcd9335_codec_enable_dec, 4763 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4764 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4765 4766 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4767 &tx_adc_mux7, wcd9335_codec_enable_dec, 4768 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4769 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4770 4771 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4772 &tx_adc_mux8, wcd9335_codec_enable_dec, 4773 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4774 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4775 }; 4776 4777 static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4778 { 4779 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4780 4781 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4782 WCD9335_ANA_RCO_BG_EN_MASK, 4783 WCD9335_ANA_RCO_BG_ENABLE); 4784 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4785 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4786 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4787 /* 100us sleep needed after IREF settings */ 4788 usleep_range(100, 110); 4789 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4790 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4791 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4792 /* 100us sleep needed after VREF settings */ 4793 usleep_range(100, 110); 4794 wcd->sido_input_src = SIDO_SOURCE_RCO_BG; 4795 } 4796 4797 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4798 { 4799 _wcd9335_codec_enable_mclk(comp, true); 4800 snd_soc_component_update_bits(comp, 4801 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4802 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4803 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4804 /* 4805 * 5ms sleep required after enabling efuse control 4806 * before checking the status. 4807 */ 4808 usleep_range(5000, 5500); 4809 4810 if (!(snd_soc_component_read(comp, 4811 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4812 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4813 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4814 4815 wcd9335_enable_sido_buck(comp); 4816 _wcd9335_codec_enable_mclk(comp, false); 4817 4818 return 0; 4819 } 4820 4821 static void wcd9335_codec_init(struct snd_soc_component *component) 4822 { 4823 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4824 int i; 4825 4826 /* ungate MCLK and set clk rate */ 4827 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4828 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4829 4830 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4831 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4832 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4833 4834 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4835 snd_soc_component_update_bits(component, 4836 wcd9335_codec_reg_init[i].reg, 4837 wcd9335_codec_reg_init[i].mask, 4838 wcd9335_codec_reg_init[i].val); 4839 4840 wcd9335_enable_efuse_sensing(component); 4841 } 4842 4843 static int wcd9335_codec_probe(struct snd_soc_component *component) 4844 { 4845 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4846 int ret; 4847 int i; 4848 4849 snd_soc_component_init_regmap(component, wcd->regmap); 4850 /* Class-H Init*/ 4851 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335); 4852 if (IS_ERR(wcd->clsh_ctrl)) 4853 return PTR_ERR(wcd->clsh_ctrl); 4854 4855 /* Default HPH Mode to Class-H HiFi */ 4856 wcd->hph_mode = CLS_H_HIFI; 4857 wcd->component = component; 4858 4859 wcd9335_codec_init(component); 4860 4861 for (i = 0; i < NUM_CODEC_DAIS; i++) 4862 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4863 4864 ret = wcd9335_setup_irqs(wcd); 4865 if (ret) 4866 goto free_clsh_ctrl; 4867 4868 return 0; 4869 4870 free_clsh_ctrl: 4871 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4872 return ret; 4873 } 4874 4875 static void wcd9335_codec_remove(struct snd_soc_component *comp) 4876 { 4877 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4878 4879 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4880 wcd9335_teardown_irqs(wcd); 4881 } 4882 4883 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4884 int clk_id, int source, 4885 unsigned int freq, int dir) 4886 { 4887 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4888 4889 wcd->mclk_rate = freq; 4890 4891 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4892 snd_soc_component_update_bits(comp, 4893 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4894 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4895 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4896 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4897 snd_soc_component_update_bits(comp, 4898 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4899 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4900 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4901 4902 return clk_set_rate(wcd->mclk, freq); 4903 } 4904 4905 static const struct snd_soc_component_driver wcd9335_component_drv = { 4906 .probe = wcd9335_codec_probe, 4907 .remove = wcd9335_codec_remove, 4908 .set_sysclk = wcd9335_codec_set_sysclk, 4909 .controls = wcd9335_snd_controls, 4910 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4911 .dapm_widgets = wcd9335_dapm_widgets, 4912 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4913 .dapm_routes = wcd9335_audio_map, 4914 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4915 .endianness = 1, 4916 }; 4917 4918 static int wcd9335_probe(struct wcd9335_codec *wcd) 4919 { 4920 struct device *dev = wcd->dev; 4921 4922 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4923 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4924 4925 wcd->sido_input_src = SIDO_SOURCE_INTERNAL; 4926 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4927 4928 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4929 wcd9335_slim_dais, 4930 ARRAY_SIZE(wcd9335_slim_dais)); 4931 } 4932 4933 static const struct regmap_range_cfg wcd9335_ranges[] = { 4934 { 4935 .name = "WCD9335", 4936 .range_min = 0x0, 4937 .range_max = WCD9335_MAX_REGISTER, 4938 .selector_reg = WCD9335_SEL_REGISTER, 4939 .selector_mask = 0xff, 4940 .selector_shift = 0, 4941 .window_start = 0x800, 4942 .window_len = 0x100, 4943 }, 4944 }; 4945 4946 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4947 { 4948 switch (reg) { 4949 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4950 case WCD9335_ANA_MBHC_RESULT_3: 4951 case WCD9335_ANA_MBHC_RESULT_2: 4952 case WCD9335_ANA_MBHC_RESULT_1: 4953 case WCD9335_ANA_MBHC_MECH: 4954 case WCD9335_ANA_MBHC_ELECT: 4955 case WCD9335_ANA_MBHC_ZDET: 4956 case WCD9335_ANA_MICB2: 4957 case WCD9335_ANA_RCO: 4958 case WCD9335_ANA_BIAS: 4959 return true; 4960 default: 4961 return false; 4962 } 4963 } 4964 4965 static struct regmap_config wcd9335_regmap_config = { 4966 .reg_bits = 16, 4967 .val_bits = 8, 4968 .cache_type = REGCACHE_RBTREE, 4969 .max_register = WCD9335_MAX_REGISTER, 4970 .can_multi_write = true, 4971 .ranges = wcd9335_ranges, 4972 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4973 .volatile_reg = wcd9335_is_volatile_register, 4974 }; 4975 4976 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 4977 { 4978 .name = "WCD9335-IFC-DEV", 4979 .range_min = 0x0, 4980 .range_max = WCD9335_MAX_REGISTER, 4981 .selector_reg = WCD9335_SEL_REGISTER, 4982 .selector_mask = 0xfff, 4983 .selector_shift = 0, 4984 .window_start = 0x800, 4985 .window_len = 0x400, 4986 }, 4987 }; 4988 4989 static struct regmap_config wcd9335_ifc_regmap_config = { 4990 .reg_bits = 16, 4991 .val_bits = 8, 4992 .can_multi_write = true, 4993 .max_register = WCD9335_MAX_REGISTER, 4994 .ranges = wcd9335_ifc_ranges, 4995 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 4996 }; 4997 4998 static const struct regmap_irq wcd9335_codec_irqs[] = { 4999 /* INTR_REG 0 */ 5000 [WCD9335_IRQ_SLIMBUS] = { 5001 .reg_offset = 0, 5002 .mask = BIT(0), 5003 .type = { 5004 .type_reg_offset = 0, 5005 .types_supported = IRQ_TYPE_EDGE_BOTH, 5006 .type_reg_mask = BIT(0), 5007 }, 5008 }, 5009 }; 5010 5011 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 5012 .name = "wcd9335_pin1_irq", 5013 .status_base = WCD9335_INTR_PIN1_STATUS0, 5014 .mask_base = WCD9335_INTR_PIN1_MASK0, 5015 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 5016 .type_base = WCD9335_INTR_LEVEL0, 5017 .num_type_reg = 4, 5018 .num_regs = 4, 5019 .irqs = wcd9335_codec_irqs, 5020 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 5021 }; 5022 5023 static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 5024 { 5025 struct device *dev = wcd->dev; 5026 struct device_node *np = dev->of_node; 5027 int ret; 5028 5029 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 5030 if (wcd->reset_gpio < 0) { 5031 dev_err(dev, "Reset GPIO missing from DT\n"); 5032 return wcd->reset_gpio; 5033 } 5034 5035 wcd->mclk = devm_clk_get(dev, "mclk"); 5036 if (IS_ERR(wcd->mclk)) { 5037 dev_err(dev, "mclk not found\n"); 5038 return PTR_ERR(wcd->mclk); 5039 } 5040 5041 wcd->native_clk = devm_clk_get(dev, "slimbus"); 5042 if (IS_ERR(wcd->native_clk)) { 5043 dev_err(dev, "slimbus clock not found\n"); 5044 return PTR_ERR(wcd->native_clk); 5045 } 5046 5047 wcd->supplies[0].supply = "vdd-buck"; 5048 wcd->supplies[1].supply = "vdd-buck-sido"; 5049 wcd->supplies[2].supply = "vdd-tx"; 5050 wcd->supplies[3].supply = "vdd-rx"; 5051 wcd->supplies[4].supply = "vdd-io"; 5052 5053 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies); 5054 if (ret) { 5055 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5056 return ret; 5057 } 5058 5059 return 0; 5060 } 5061 5062 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5063 { 5064 struct device *dev = wcd->dev; 5065 int ret; 5066 5067 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies); 5068 if (ret) { 5069 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5070 return ret; 5071 } 5072 5073 /* 5074 * For WCD9335, it takes about 600us for the Vout_A and 5075 * Vout_D to be ready after BUCK_SIDO is powered up. 5076 * SYS_RST_N shouldn't be pulled high during this time 5077 * Toggle the reset line to make sure the reset pulse is 5078 * correctly applied 5079 */ 5080 usleep_range(600, 650); 5081 5082 gpio_direction_output(wcd->reset_gpio, 0); 5083 msleep(20); 5084 gpio_set_value(wcd->reset_gpio, 1); 5085 msleep(20); 5086 5087 return 0; 5088 } 5089 5090 static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5091 { 5092 struct regmap *rm = wcd->regmap; 5093 int val, byte0; 5094 5095 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5096 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5097 5098 if ((val < 0) || (byte0 < 0)) { 5099 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5100 return -EINVAL; 5101 } 5102 5103 if (byte0 == 0x1) { 5104 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5105 wcd->version = WCD9335_VERSION_2_0; 5106 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5107 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5108 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5109 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5110 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5111 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5112 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5113 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5114 } else { 5115 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5116 return -EINVAL; 5117 } 5118 5119 return 0; 5120 } 5121 5122 static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5123 { 5124 int ret; 5125 5126 /* 5127 * INTR1 consists of all possible interrupt sources Ear OCP, 5128 * HPH OCP, MBHC, MAD, VBAT, and SVA 5129 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5130 */ 5131 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5132 if (wcd->intr1 < 0) { 5133 if (wcd->intr1 != -EPROBE_DEFER) 5134 dev_err(wcd->dev, "Unable to configure IRQ\n"); 5135 5136 return wcd->intr1; 5137 } 5138 5139 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5140 IRQF_TRIGGER_HIGH, 0, 5141 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5142 if (ret) 5143 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret); 5144 5145 return ret; 5146 } 5147 5148 static int wcd9335_slim_probe(struct slim_device *slim) 5149 { 5150 struct device *dev = &slim->dev; 5151 struct wcd9335_codec *wcd; 5152 int ret; 5153 5154 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5155 if (!wcd) 5156 return -ENOMEM; 5157 5158 wcd->dev = dev; 5159 ret = wcd9335_parse_dt(wcd); 5160 if (ret) { 5161 dev_err(dev, "Error parsing DT: %d\n", ret); 5162 return ret; 5163 } 5164 5165 ret = wcd9335_power_on_reset(wcd); 5166 if (ret) 5167 return ret; 5168 5169 dev_set_drvdata(dev, wcd); 5170 5171 return 0; 5172 } 5173 5174 static int wcd9335_slim_status(struct slim_device *sdev, 5175 enum slim_device_status status) 5176 { 5177 struct device *dev = &sdev->dev; 5178 struct device_node *ifc_dev_np; 5179 struct wcd9335_codec *wcd; 5180 int ret; 5181 5182 wcd = dev_get_drvdata(dev); 5183 5184 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5185 if (!ifc_dev_np) { 5186 dev_err(dev, "No Interface device found\n"); 5187 return -EINVAL; 5188 } 5189 5190 wcd->slim = sdev; 5191 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5192 of_node_put(ifc_dev_np); 5193 if (!wcd->slim_ifc_dev) { 5194 dev_err(dev, "Unable to get SLIM Interface device\n"); 5195 return -EINVAL; 5196 } 5197 5198 slim_get_logical_addr(wcd->slim_ifc_dev); 5199 5200 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5201 if (IS_ERR(wcd->regmap)) { 5202 dev_err(dev, "Failed to allocate slim register map\n"); 5203 return PTR_ERR(wcd->regmap); 5204 } 5205 5206 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5207 &wcd9335_ifc_regmap_config); 5208 if (IS_ERR(wcd->if_regmap)) { 5209 dev_err(dev, "Failed to allocate ifc register map\n"); 5210 return PTR_ERR(wcd->if_regmap); 5211 } 5212 5213 ret = wcd9335_bring_up(wcd); 5214 if (ret) { 5215 dev_err(dev, "Failed to bringup WCD9335\n"); 5216 return ret; 5217 } 5218 5219 ret = wcd9335_irq_init(wcd); 5220 if (ret) 5221 return ret; 5222 5223 wcd9335_probe(wcd); 5224 5225 return 0; 5226 } 5227 5228 static const struct slim_device_id wcd9335_slim_id[] = { 5229 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5230 {} 5231 }; 5232 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5233 5234 static struct slim_driver wcd9335_slim_driver = { 5235 .driver = { 5236 .name = "wcd9335-slim", 5237 }, 5238 .probe = wcd9335_slim_probe, 5239 .device_status = wcd9335_slim_status, 5240 .id_table = wcd9335_slim_id, 5241 }; 5242 5243 module_slim_driver(wcd9335_slim_driver); 5244 MODULE_DESCRIPTION("WCD9335 slim driver"); 5245 MODULE_LICENSE("GPL v2"); 5246 MODULE_ALIAS("slim:217:1a0:*"); 5247