1 /* 2 * ALSA SoC TWL4030 codec driver 3 * 4 * Author: Steve Sakoman, <steve@sakoman.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/pm.h> 27 #include <linux/i2c.h> 28 #include <linux/platform_device.h> 29 #include <linux/i2c/twl4030.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc.h> 34 #include <sound/soc-dapm.h> 35 #include <sound/initval.h> 36 #include <sound/tlv.h> 37 38 #include "twl4030.h" 39 40 /* 41 * twl4030 register cache & default register settings 42 */ 43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { 44 0x00, /* this register not used */ 45 0x91, /* REG_CODEC_MODE (0x1) */ 46 0xc3, /* REG_OPTION (0x2) */ 47 0x00, /* REG_UNKNOWN (0x3) */ 48 0x00, /* REG_MICBIAS_CTL (0x4) */ 49 0x20, /* REG_ANAMICL (0x5) */ 50 0x00, /* REG_ANAMICR (0x6) */ 51 0x00, /* REG_AVADC_CTL (0x7) */ 52 0x00, /* REG_ADCMICSEL (0x8) */ 53 0x00, /* REG_DIGMIXING (0x9) */ 54 0x0c, /* REG_ATXL1PGA (0xA) */ 55 0x0c, /* REG_ATXR1PGA (0xB) */ 56 0x00, /* REG_AVTXL2PGA (0xC) */ 57 0x00, /* REG_AVTXR2PGA (0xD) */ 58 0x01, /* REG_AUDIO_IF (0xE) */ 59 0x00, /* REG_VOICE_IF (0xF) */ 60 0x00, /* REG_ARXR1PGA (0x10) */ 61 0x00, /* REG_ARXL1PGA (0x11) */ 62 0x6c, /* REG_ARXR2PGA (0x12) */ 63 0x6c, /* REG_ARXL2PGA (0x13) */ 64 0x00, /* REG_VRXPGA (0x14) */ 65 0x00, /* REG_VSTPGA (0x15) */ 66 0x00, /* REG_VRX2ARXPGA (0x16) */ 67 0x0c, /* REG_AVDAC_CTL (0x17) */ 68 0x00, /* REG_ARX2VTXPGA (0x18) */ 69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ 70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ 71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ 72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ 73 0x00, /* REG_ATX2ARXPGA (0x1D) */ 74 0x00, /* REG_BT_IF (0x1E) */ 75 0x00, /* REG_BTPGA (0x1F) */ 76 0x00, /* REG_BTSTPGA (0x20) */ 77 0x00, /* REG_EAR_CTL (0x21) */ 78 0x24, /* REG_HS_SEL (0x22) */ 79 0x0a, /* REG_HS_GAIN_SET (0x23) */ 80 0x00, /* REG_HS_POPN_SET (0x24) */ 81 0x00, /* REG_PREDL_CTL (0x25) */ 82 0x00, /* REG_PREDR_CTL (0x26) */ 83 0x00, /* REG_PRECKL_CTL (0x27) */ 84 0x00, /* REG_PRECKR_CTL (0x28) */ 85 0x00, /* REG_HFL_CTL (0x29) */ 86 0x00, /* REG_HFR_CTL (0x2A) */ 87 0x00, /* REG_ALC_CTL (0x2B) */ 88 0x00, /* REG_ALC_SET1 (0x2C) */ 89 0x00, /* REG_ALC_SET2 (0x2D) */ 90 0x00, /* REG_BOOST_CTL (0x2E) */ 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */ 92 0x00, /* REG_DTMF_FREQSEL (0x30) */ 93 0x00, /* REG_DTMF_TONEXT1H (0x31) */ 94 0x00, /* REG_DTMF_TONEXT1L (0x32) */ 95 0x00, /* REG_DTMF_TONEXT2H (0x33) */ 96 0x00, /* REG_DTMF_TONEXT2L (0x34) */ 97 0x00, /* REG_DTMF_TONOFF (0x35) */ 98 0x00, /* REG_DTMF_WANONOFF (0x36) */ 99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ 100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ 101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ 102 0x16, /* REG_APLL_CTL (0x3A) */ 103 0x00, /* REG_DTMF_CTL (0x3B) */ 104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ 105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ 106 0x00, /* REG_MISC_SET_1 (0x3E) */ 107 0x00, /* REG_PCMBTMUX (0x3F) */ 108 0x00, /* not used (0x40) */ 109 0x00, /* not used (0x41) */ 110 0x00, /* not used (0x42) */ 111 0x00, /* REG_RX_PATH_SEL (0x43) */ 112 0x00, /* REG_VDL_APGA_CTL (0x44) */ 113 0x00, /* REG_VIBRA_CTL (0x45) */ 114 0x00, /* REG_VIBRA_SET (0x46) */ 115 0x00, /* REG_VIBRA_PWM_SET (0x47) */ 116 0x00, /* REG_ANAMIC_GAIN (0x48) */ 117 0x00, /* REG_MISC_SET_2 (0x49) */ 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */ 119 }; 120 121 /* codec private data */ 122 struct twl4030_priv { 123 unsigned int bypass_state; 124 unsigned int codec_powered; 125 unsigned int codec_muted; 126 127 struct snd_pcm_substream *master_substream; 128 struct snd_pcm_substream *slave_substream; 129 130 unsigned int configured; 131 unsigned int rate; 132 unsigned int sample_bits; 133 unsigned int channels; 134 135 unsigned int sysclk; 136 137 /* Headset output state handling */ 138 unsigned int hsl_enabled; 139 unsigned int hsr_enabled; 140 }; 141 142 /* 143 * read twl4030 register cache 144 */ 145 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, 146 unsigned int reg) 147 { 148 u8 *cache = codec->reg_cache; 149 150 if (reg >= TWL4030_CACHEREGNUM) 151 return -EIO; 152 153 return cache[reg]; 154 } 155 156 /* 157 * write twl4030 register cache 158 */ 159 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, 160 u8 reg, u8 value) 161 { 162 u8 *cache = codec->reg_cache; 163 164 if (reg >= TWL4030_CACHEREGNUM) 165 return; 166 cache[reg] = value; 167 } 168 169 /* 170 * write to the twl4030 register space 171 */ 172 static int twl4030_write(struct snd_soc_codec *codec, 173 unsigned int reg, unsigned int value) 174 { 175 twl4030_write_reg_cache(codec, reg, value); 176 if (likely(reg < TWL4030_REG_SW_SHADOW)) 177 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, 178 reg); 179 else 180 return 0; 181 } 182 183 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) 184 { 185 struct twl4030_priv *twl4030 = codec->private_data; 186 u8 mode; 187 188 if (enable == twl4030->codec_powered) 189 return; 190 191 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); 192 if (enable) 193 mode |= TWL4030_CODECPDZ; 194 else 195 mode &= ~TWL4030_CODECPDZ; 196 197 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); 198 twl4030->codec_powered = enable; 199 200 /* REVISIT: this delay is present in TI sample drivers */ 201 /* but there seems to be no TRM requirement for it */ 202 udelay(10); 203 } 204 205 static void twl4030_init_chip(struct snd_soc_codec *codec) 206 { 207 u8 *cache = codec->reg_cache; 208 int i; 209 210 /* clear CODECPDZ prior to setting register defaults */ 211 twl4030_codec_enable(codec, 0); 212 213 /* set all audio section registers to reasonable defaults */ 214 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) 215 twl4030_write(codec, i, cache[i]); 216 217 } 218 219 static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute) 220 { 221 struct twl4030_priv *twl4030 = codec->private_data; 222 u8 reg_val; 223 224 if (mute == twl4030->codec_muted) 225 return; 226 227 if (mute) { 228 /* Disable PLL */ 229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL); 230 reg_val &= ~TWL4030_APLL_EN; 231 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val); 232 } else { 233 /* Enable PLL */ 234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL); 235 reg_val |= TWL4030_APLL_EN; 236 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val); 237 } 238 239 twl4030->codec_muted = mute; 240 } 241 242 static void twl4030_power_up(struct snd_soc_codec *codec) 243 { 244 struct twl4030_priv *twl4030 = codec->private_data; 245 u8 anamicl, regmisc1, byte; 246 int i = 0; 247 248 if (twl4030->codec_powered) 249 return; 250 251 /* set CODECPDZ to turn on codec */ 252 twl4030_codec_enable(codec, 1); 253 254 /* initiate offset cancellation */ 255 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); 256 twl4030_write(codec, TWL4030_REG_ANAMICL, 257 anamicl | TWL4030_CNCL_OFFSET_START); 258 259 /* wait for offset cancellation to complete */ 260 do { 261 /* this takes a little while, so don't slam i2c */ 262 udelay(2000); 263 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, 264 TWL4030_REG_ANAMICL); 265 } while ((i++ < 100) && 266 ((byte & TWL4030_CNCL_OFFSET_START) == 267 TWL4030_CNCL_OFFSET_START)); 268 269 /* Make sure that the reg_cache has the same value as the HW */ 270 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); 271 272 /* anti-pop when changing analog gain */ 273 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); 274 twl4030_write(codec, TWL4030_REG_MISC_SET_1, 275 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); 276 277 /* toggle CODECPDZ as per TRM */ 278 twl4030_codec_enable(codec, 0); 279 twl4030_codec_enable(codec, 1); 280 } 281 282 /* 283 * Unconditional power down 284 */ 285 static void twl4030_power_down(struct snd_soc_codec *codec) 286 { 287 /* power down */ 288 twl4030_codec_enable(codec, 0); 289 } 290 291 /* Earpiece */ 292 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = { 293 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0), 294 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0), 295 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0), 296 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0), 297 }; 298 299 /* PreDrive Left */ 300 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = { 301 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0), 302 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0), 303 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0), 304 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0), 305 }; 306 307 /* PreDrive Right */ 308 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = { 309 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0), 310 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0), 311 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0), 312 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0), 313 }; 314 315 /* Headset Left */ 316 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = { 317 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0), 318 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0), 319 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0), 320 }; 321 322 /* Headset Right */ 323 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = { 324 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0), 325 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0), 326 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0), 327 }; 328 329 /* Carkit Left */ 330 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = { 331 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0), 332 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0), 333 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0), 334 }; 335 336 /* Carkit Right */ 337 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = { 338 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0), 339 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0), 340 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0), 341 }; 342 343 /* Handsfree Left */ 344 static const char *twl4030_handsfreel_texts[] = 345 {"Voice", "AudioL1", "AudioL2", "AudioR2"}; 346 347 static const struct soc_enum twl4030_handsfreel_enum = 348 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, 349 ARRAY_SIZE(twl4030_handsfreel_texts), 350 twl4030_handsfreel_texts); 351 352 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = 353 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); 354 355 /* Handsfree Left virtual mute */ 356 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control = 357 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0); 358 359 /* Handsfree Right */ 360 static const char *twl4030_handsfreer_texts[] = 361 {"Voice", "AudioR1", "AudioR2", "AudioL2"}; 362 363 static const struct soc_enum twl4030_handsfreer_enum = 364 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, 365 ARRAY_SIZE(twl4030_handsfreer_texts), 366 twl4030_handsfreer_texts); 367 368 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = 369 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); 370 371 /* Handsfree Right virtual mute */ 372 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control = 373 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0); 374 375 /* Vibra */ 376 /* Vibra audio path selection */ 377 static const char *twl4030_vibra_texts[] = 378 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"}; 379 380 static const struct soc_enum twl4030_vibra_enum = 381 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2, 382 ARRAY_SIZE(twl4030_vibra_texts), 383 twl4030_vibra_texts); 384 385 static const struct snd_kcontrol_new twl4030_dapm_vibra_control = 386 SOC_DAPM_ENUM("Route", twl4030_vibra_enum); 387 388 /* Vibra path selection: local vibrator (PWM) or audio driven */ 389 static const char *twl4030_vibrapath_texts[] = 390 {"Local vibrator", "Audio"}; 391 392 static const struct soc_enum twl4030_vibrapath_enum = 393 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4, 394 ARRAY_SIZE(twl4030_vibrapath_texts), 395 twl4030_vibrapath_texts); 396 397 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control = 398 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum); 399 400 /* Left analog microphone selection */ 401 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = { 402 SOC_DAPM_SINGLE("Main Mic Capture Switch", 403 TWL4030_REG_ANAMICL, 0, 1, 0), 404 SOC_DAPM_SINGLE("Headset Mic Capture Switch", 405 TWL4030_REG_ANAMICL, 1, 1, 0), 406 SOC_DAPM_SINGLE("AUXL Capture Switch", 407 TWL4030_REG_ANAMICL, 2, 1, 0), 408 SOC_DAPM_SINGLE("Carkit Mic Capture Switch", 409 TWL4030_REG_ANAMICL, 3, 1, 0), 410 }; 411 412 /* Right analog microphone selection */ 413 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = { 414 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0), 415 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0), 416 }; 417 418 /* TX1 L/R Analog/Digital microphone selection */ 419 static const char *twl4030_micpathtx1_texts[] = 420 {"Analog", "Digimic0"}; 421 422 static const struct soc_enum twl4030_micpathtx1_enum = 423 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, 424 ARRAY_SIZE(twl4030_micpathtx1_texts), 425 twl4030_micpathtx1_texts); 426 427 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = 428 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); 429 430 /* TX2 L/R Analog/Digital microphone selection */ 431 static const char *twl4030_micpathtx2_texts[] = 432 {"Analog", "Digimic1"}; 433 434 static const struct soc_enum twl4030_micpathtx2_enum = 435 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, 436 ARRAY_SIZE(twl4030_micpathtx2_texts), 437 twl4030_micpathtx2_texts); 438 439 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = 440 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); 441 442 /* Analog bypass for AudioR1 */ 443 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = 444 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); 445 446 /* Analog bypass for AudioL1 */ 447 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = 448 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); 449 450 /* Analog bypass for AudioR2 */ 451 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = 452 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); 453 454 /* Analog bypass for AudioL2 */ 455 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = 456 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); 457 458 /* Analog bypass for Voice */ 459 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control = 460 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0); 461 462 /* Digital bypass gain, 0 mutes the bypass */ 463 static const unsigned int twl4030_dapm_dbypass_tlv[] = { 464 TLV_DB_RANGE_HEAD(2), 465 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1), 466 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), 467 }; 468 469 /* Digital bypass left (TX1L -> RX2L) */ 470 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = 471 SOC_DAPM_SINGLE_TLV("Volume", 472 TWL4030_REG_ATX2ARXPGA, 3, 7, 0, 473 twl4030_dapm_dbypass_tlv); 474 475 /* Digital bypass right (TX1R -> RX2R) */ 476 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = 477 SOC_DAPM_SINGLE_TLV("Volume", 478 TWL4030_REG_ATX2ARXPGA, 0, 7, 0, 479 twl4030_dapm_dbypass_tlv); 480 481 /* 482 * Voice Sidetone GAIN volume control: 483 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB) 484 */ 485 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1); 486 487 /* Digital bypass voice: sidetone (VUL -> VDL)*/ 488 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control = 489 SOC_DAPM_SINGLE_TLV("Volume", 490 TWL4030_REG_VSTPGA, 0, 0x29, 0, 491 twl4030_dapm_dbypassv_tlv); 492 493 static int micpath_event(struct snd_soc_dapm_widget *w, 494 struct snd_kcontrol *kcontrol, int event) 495 { 496 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; 497 unsigned char adcmicsel, micbias_ctl; 498 499 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL); 500 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL); 501 /* Prepare the bits for the given TX path: 502 * shift_l == 0: TX1 microphone path 503 * shift_l == 2: TX2 microphone path */ 504 if (e->shift_l) { 505 /* TX2 microphone path */ 506 if (adcmicsel & TWL4030_TX2IN_SEL) 507 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */ 508 else 509 micbias_ctl &= ~TWL4030_MICBIAS2_CTL; 510 } else { 511 /* TX1 microphone path */ 512 if (adcmicsel & TWL4030_TX1IN_SEL) 513 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */ 514 else 515 micbias_ctl &= ~TWL4030_MICBIAS1_CTL; 516 } 517 518 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl); 519 520 return 0; 521 } 522 523 /* 524 * Output PGA builder: 525 * Handle the muting and unmuting of the given output (turning off the 526 * amplifier associated with the output pin) 527 * On mute bypass the reg_cache and mute the volume 528 * On unmute: restore the register content 529 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R 530 */ 531 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ 532 static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \ 533 struct snd_kcontrol *kcontrol, int event) \ 534 { \ 535 u8 reg_val; \ 536 \ 537 switch (event) { \ 538 case SND_SOC_DAPM_POST_PMU: \ 539 twl4030_write(w->codec, reg, \ 540 twl4030_read_reg_cache(w->codec, reg)); \ 541 break; \ 542 case SND_SOC_DAPM_POST_PMD: \ 543 reg_val = twl4030_read_reg_cache(w->codec, reg); \ 544 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \ 545 reg_val & (~mask), \ 546 reg); \ 547 break; \ 548 } \ 549 return 0; \ 550 } 551 552 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN); 553 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN); 554 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN); 555 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN); 556 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN); 557 558 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp) 559 { 560 unsigned char hs_ctl; 561 562 hs_ctl = twl4030_read_reg_cache(codec, reg); 563 564 if (ramp) { 565 /* HF ramp-up */ 566 hs_ctl |= TWL4030_HF_CTL_REF_EN; 567 twl4030_write(codec, reg, hs_ctl); 568 udelay(10); 569 hs_ctl |= TWL4030_HF_CTL_RAMP_EN; 570 twl4030_write(codec, reg, hs_ctl); 571 udelay(40); 572 hs_ctl |= TWL4030_HF_CTL_LOOP_EN; 573 hs_ctl |= TWL4030_HF_CTL_HB_EN; 574 twl4030_write(codec, reg, hs_ctl); 575 } else { 576 /* HF ramp-down */ 577 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN; 578 hs_ctl &= ~TWL4030_HF_CTL_HB_EN; 579 twl4030_write(codec, reg, hs_ctl); 580 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN; 581 twl4030_write(codec, reg, hs_ctl); 582 udelay(40); 583 hs_ctl &= ~TWL4030_HF_CTL_REF_EN; 584 twl4030_write(codec, reg, hs_ctl); 585 } 586 } 587 588 static int handsfreelpga_event(struct snd_soc_dapm_widget *w, 589 struct snd_kcontrol *kcontrol, int event) 590 { 591 switch (event) { 592 case SND_SOC_DAPM_POST_PMU: 593 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1); 594 break; 595 case SND_SOC_DAPM_POST_PMD: 596 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0); 597 break; 598 } 599 return 0; 600 } 601 602 static int handsfreerpga_event(struct snd_soc_dapm_widget *w, 603 struct snd_kcontrol *kcontrol, int event) 604 { 605 switch (event) { 606 case SND_SOC_DAPM_POST_PMU: 607 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1); 608 break; 609 case SND_SOC_DAPM_POST_PMD: 610 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0); 611 break; 612 } 613 return 0; 614 } 615 616 static void headset_ramp(struct snd_soc_codec *codec, int ramp) 617 { 618 struct snd_soc_device *socdev = codec->socdev; 619 struct twl4030_setup_data *setup = socdev->codec_data; 620 621 unsigned char hs_gain, hs_pop; 622 struct twl4030_priv *twl4030 = codec->private_data; 623 /* Base values for ramp delay calculation: 2^19 - 2^26 */ 624 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, 625 8388608, 16777216, 33554432, 67108864}; 626 627 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET); 628 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); 629 630 /* Enable external mute control, this dramatically reduces 631 * the pop-noise */ 632 if (setup && setup->hs_extmute) { 633 if (setup->set_hs_extmute) { 634 setup->set_hs_extmute(1); 635 } else { 636 hs_pop |= TWL4030_EXTMUTE; 637 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 638 } 639 } 640 641 if (ramp) { 642 /* Headset ramp-up according to the TRM */ 643 hs_pop |= TWL4030_VMID_EN; 644 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 645 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain); 646 hs_pop |= TWL4030_RAMP_EN; 647 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 648 /* Wait ramp delay time + 1, so the VMID can settle */ 649 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / 650 twl4030->sysclk) + 1); 651 } else { 652 /* Headset ramp-down _not_ according to 653 * the TRM, but in a way that it is working */ 654 hs_pop &= ~TWL4030_RAMP_EN; 655 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 656 /* Wait ramp delay time + 1, so the VMID can settle */ 657 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / 658 twl4030->sysclk) + 1); 659 /* Bypass the reg_cache to mute the headset */ 660 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 661 hs_gain & (~0x0f), 662 TWL4030_REG_HS_GAIN_SET); 663 664 hs_pop &= ~TWL4030_VMID_EN; 665 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 666 } 667 668 /* Disable external mute */ 669 if (setup && setup->hs_extmute) { 670 if (setup->set_hs_extmute) { 671 setup->set_hs_extmute(0); 672 } else { 673 hs_pop &= ~TWL4030_EXTMUTE; 674 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 675 } 676 } 677 } 678 679 static int headsetlpga_event(struct snd_soc_dapm_widget *w, 680 struct snd_kcontrol *kcontrol, int event) 681 { 682 struct twl4030_priv *twl4030 = w->codec->private_data; 683 684 switch (event) { 685 case SND_SOC_DAPM_POST_PMU: 686 /* Do the ramp-up only once */ 687 if (!twl4030->hsr_enabled) 688 headset_ramp(w->codec, 1); 689 690 twl4030->hsl_enabled = 1; 691 break; 692 case SND_SOC_DAPM_POST_PMD: 693 /* Do the ramp-down only if both headsetL/R is disabled */ 694 if (!twl4030->hsr_enabled) 695 headset_ramp(w->codec, 0); 696 697 twl4030->hsl_enabled = 0; 698 break; 699 } 700 return 0; 701 } 702 703 static int headsetrpga_event(struct snd_soc_dapm_widget *w, 704 struct snd_kcontrol *kcontrol, int event) 705 { 706 struct twl4030_priv *twl4030 = w->codec->private_data; 707 708 switch (event) { 709 case SND_SOC_DAPM_POST_PMU: 710 /* Do the ramp-up only once */ 711 if (!twl4030->hsl_enabled) 712 headset_ramp(w->codec, 1); 713 714 twl4030->hsr_enabled = 1; 715 break; 716 case SND_SOC_DAPM_POST_PMD: 717 /* Do the ramp-down only if both headsetL/R is disabled */ 718 if (!twl4030->hsl_enabled) 719 headset_ramp(w->codec, 0); 720 721 twl4030->hsr_enabled = 0; 722 break; 723 } 724 return 0; 725 } 726 727 static int bypass_event(struct snd_soc_dapm_widget *w, 728 struct snd_kcontrol *kcontrol, int event) 729 { 730 struct soc_mixer_control *m = 731 (struct soc_mixer_control *)w->kcontrols->private_value; 732 struct twl4030_priv *twl4030 = w->codec->private_data; 733 unsigned char reg, misc; 734 735 reg = twl4030_read_reg_cache(w->codec, m->reg); 736 737 /* 738 * bypass_state[0:3] - analog HiFi bypass 739 * bypass_state[4] - analog voice bypass 740 * bypass_state[5] - digital voice bypass 741 * bypass_state[6:7] - digital HiFi bypass 742 */ 743 if (m->reg == TWL4030_REG_VSTPGA) { 744 /* Voice digital bypass */ 745 if (reg) 746 twl4030->bypass_state |= (1 << 5); 747 else 748 twl4030->bypass_state &= ~(1 << 5); 749 } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) { 750 /* Analog bypass */ 751 if (reg & (1 << m->shift)) 752 twl4030->bypass_state |= 753 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL)); 754 else 755 twl4030->bypass_state &= 756 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL)); 757 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) { 758 /* Analog voice bypass */ 759 if (reg & (1 << m->shift)) 760 twl4030->bypass_state |= (1 << 4); 761 else 762 twl4030->bypass_state &= ~(1 << 4); 763 } else { 764 /* Digital bypass */ 765 if (reg & (0x7 << m->shift)) 766 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6)); 767 else 768 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6)); 769 } 770 771 /* Enable master analog loopback mode if any analog switch is enabled*/ 772 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1); 773 if (twl4030->bypass_state & 0x1F) 774 misc |= TWL4030_FMLOOP_EN; 775 else 776 misc &= ~TWL4030_FMLOOP_EN; 777 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc); 778 779 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) { 780 if (twl4030->bypass_state) 781 twl4030_codec_mute(w->codec, 0); 782 else 783 twl4030_codec_mute(w->codec, 1); 784 } 785 return 0; 786 } 787 788 /* 789 * Some of the gain controls in TWL (mostly those which are associated with 790 * the outputs) are implemented in an interesting way: 791 * 0x0 : Power down (mute) 792 * 0x1 : 6dB 793 * 0x2 : 0 dB 794 * 0x3 : -6 dB 795 * Inverting not going to help with these. 796 * Custom volsw and volsw_2r get/put functions to handle these gain bits. 797 */ 798 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ 799 xinvert, tlv_array) \ 800 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ 801 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 802 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 803 .tlv.p = (tlv_array), \ 804 .info = snd_soc_info_volsw, \ 805 .get = snd_soc_get_volsw_twl4030, \ 806 .put = snd_soc_put_volsw_twl4030, \ 807 .private_value = (unsigned long)&(struct soc_mixer_control) \ 808 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ 809 .max = xmax, .invert = xinvert} } 810 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ 811 xinvert, tlv_array) \ 812 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ 813 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 814 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 815 .tlv.p = (tlv_array), \ 816 .info = snd_soc_info_volsw_2r, \ 817 .get = snd_soc_get_volsw_r2_twl4030,\ 818 .put = snd_soc_put_volsw_r2_twl4030, \ 819 .private_value = (unsigned long)&(struct soc_mixer_control) \ 820 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ 821 .rshift = xshift, .max = xmax, .invert = xinvert} } 822 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ 823 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ 824 xinvert, tlv_array) 825 826 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, 827 struct snd_ctl_elem_value *ucontrol) 828 { 829 struct soc_mixer_control *mc = 830 (struct soc_mixer_control *)kcontrol->private_value; 831 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 832 unsigned int reg = mc->reg; 833 unsigned int shift = mc->shift; 834 unsigned int rshift = mc->rshift; 835 int max = mc->max; 836 int mask = (1 << fls(max)) - 1; 837 838 ucontrol->value.integer.value[0] = 839 (snd_soc_read(codec, reg) >> shift) & mask; 840 if (ucontrol->value.integer.value[0]) 841 ucontrol->value.integer.value[0] = 842 max + 1 - ucontrol->value.integer.value[0]; 843 844 if (shift != rshift) { 845 ucontrol->value.integer.value[1] = 846 (snd_soc_read(codec, reg) >> rshift) & mask; 847 if (ucontrol->value.integer.value[1]) 848 ucontrol->value.integer.value[1] = 849 max + 1 - ucontrol->value.integer.value[1]; 850 } 851 852 return 0; 853 } 854 855 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, 856 struct snd_ctl_elem_value *ucontrol) 857 { 858 struct soc_mixer_control *mc = 859 (struct soc_mixer_control *)kcontrol->private_value; 860 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 861 unsigned int reg = mc->reg; 862 unsigned int shift = mc->shift; 863 unsigned int rshift = mc->rshift; 864 int max = mc->max; 865 int mask = (1 << fls(max)) - 1; 866 unsigned short val, val2, val_mask; 867 868 val = (ucontrol->value.integer.value[0] & mask); 869 870 val_mask = mask << shift; 871 if (val) 872 val = max + 1 - val; 873 val = val << shift; 874 if (shift != rshift) { 875 val2 = (ucontrol->value.integer.value[1] & mask); 876 val_mask |= mask << rshift; 877 if (val2) 878 val2 = max + 1 - val2; 879 val |= val2 << rshift; 880 } 881 return snd_soc_update_bits(codec, reg, val_mask, val); 882 } 883 884 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, 885 struct snd_ctl_elem_value *ucontrol) 886 { 887 struct soc_mixer_control *mc = 888 (struct soc_mixer_control *)kcontrol->private_value; 889 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 890 unsigned int reg = mc->reg; 891 unsigned int reg2 = mc->rreg; 892 unsigned int shift = mc->shift; 893 int max = mc->max; 894 int mask = (1<<fls(max))-1; 895 896 ucontrol->value.integer.value[0] = 897 (snd_soc_read(codec, reg) >> shift) & mask; 898 ucontrol->value.integer.value[1] = 899 (snd_soc_read(codec, reg2) >> shift) & mask; 900 901 if (ucontrol->value.integer.value[0]) 902 ucontrol->value.integer.value[0] = 903 max + 1 - ucontrol->value.integer.value[0]; 904 if (ucontrol->value.integer.value[1]) 905 ucontrol->value.integer.value[1] = 906 max + 1 - ucontrol->value.integer.value[1]; 907 908 return 0; 909 } 910 911 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, 912 struct snd_ctl_elem_value *ucontrol) 913 { 914 struct soc_mixer_control *mc = 915 (struct soc_mixer_control *)kcontrol->private_value; 916 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 917 unsigned int reg = mc->reg; 918 unsigned int reg2 = mc->rreg; 919 unsigned int shift = mc->shift; 920 int max = mc->max; 921 int mask = (1 << fls(max)) - 1; 922 int err; 923 unsigned short val, val2, val_mask; 924 925 val_mask = mask << shift; 926 val = (ucontrol->value.integer.value[0] & mask); 927 val2 = (ucontrol->value.integer.value[1] & mask); 928 929 if (val) 930 val = max + 1 - val; 931 if (val2) 932 val2 = max + 1 - val2; 933 934 val = val << shift; 935 val2 = val2 << shift; 936 937 err = snd_soc_update_bits(codec, reg, val_mask, val); 938 if (err < 0) 939 return err; 940 941 err = snd_soc_update_bits(codec, reg2, val_mask, val2); 942 return err; 943 } 944 945 /* Codec operation modes */ 946 static const char *twl4030_op_modes_texts[] = { 947 "Option 2 (voice/audio)", "Option 1 (audio)" 948 }; 949 950 static const struct soc_enum twl4030_op_modes_enum = 951 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0, 952 ARRAY_SIZE(twl4030_op_modes_texts), 953 twl4030_op_modes_texts); 954 955 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, 956 struct snd_ctl_elem_value *ucontrol) 957 { 958 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 959 struct twl4030_priv *twl4030 = codec->private_data; 960 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 961 unsigned short val; 962 unsigned short mask, bitmask; 963 964 if (twl4030->configured) { 965 printk(KERN_ERR "twl4030 operation mode cannot be " 966 "changed on-the-fly\n"); 967 return -EBUSY; 968 } 969 970 for (bitmask = 1; bitmask < e->max; bitmask <<= 1) 971 ; 972 if (ucontrol->value.enumerated.item[0] > e->max - 1) 973 return -EINVAL; 974 975 val = ucontrol->value.enumerated.item[0] << e->shift_l; 976 mask = (bitmask - 1) << e->shift_l; 977 if (e->shift_l != e->shift_r) { 978 if (ucontrol->value.enumerated.item[1] > e->max - 1) 979 return -EINVAL; 980 val |= ucontrol->value.enumerated.item[1] << e->shift_r; 981 mask |= (bitmask - 1) << e->shift_r; 982 } 983 984 return snd_soc_update_bits(codec, e->reg, mask, val); 985 } 986 987 /* 988 * FGAIN volume control: 989 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) 990 */ 991 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); 992 993 /* 994 * CGAIN volume control: 995 * 0 dB to 12 dB in 6 dB steps 996 * value 2 and 3 means 12 dB 997 */ 998 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); 999 1000 /* 1001 * Voice Downlink GAIN volume control: 1002 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB) 1003 */ 1004 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1); 1005 1006 /* 1007 * Analog playback gain 1008 * -24 dB to 12 dB in 2 dB steps 1009 */ 1010 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); 1011 1012 /* 1013 * Gain controls tied to outputs 1014 * -6 dB to 6 dB in 6 dB steps (mute instead of -12) 1015 */ 1016 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); 1017 1018 /* 1019 * Gain control for earpiece amplifier 1020 * 0 dB to 12 dB in 6 dB steps (mute instead of -6) 1021 */ 1022 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1); 1023 1024 /* 1025 * Capture gain after the ADCs 1026 * from 0 dB to 31 dB in 1 dB steps 1027 */ 1028 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); 1029 1030 /* 1031 * Gain control for input amplifiers 1032 * 0 dB to 30 dB in 6 dB steps 1033 */ 1034 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); 1035 1036 /* AVADC clock priority */ 1037 static const char *twl4030_avadc_clk_priority_texts[] = { 1038 "Voice high priority", "HiFi high priority" 1039 }; 1040 1041 static const struct soc_enum twl4030_avadc_clk_priority_enum = 1042 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2, 1043 ARRAY_SIZE(twl4030_avadc_clk_priority_texts), 1044 twl4030_avadc_clk_priority_texts); 1045 1046 static const char *twl4030_rampdelay_texts[] = { 1047 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", 1048 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", 1049 "3495/2581/1748 ms" 1050 }; 1051 1052 static const struct soc_enum twl4030_rampdelay_enum = 1053 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2, 1054 ARRAY_SIZE(twl4030_rampdelay_texts), 1055 twl4030_rampdelay_texts); 1056 1057 /* Vibra H-bridge direction mode */ 1058 static const char *twl4030_vibradirmode_texts[] = { 1059 "Vibra H-bridge direction", "Audio data MSB", 1060 }; 1061 1062 static const struct soc_enum twl4030_vibradirmode_enum = 1063 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5, 1064 ARRAY_SIZE(twl4030_vibradirmode_texts), 1065 twl4030_vibradirmode_texts); 1066 1067 /* Vibra H-bridge direction */ 1068 static const char *twl4030_vibradir_texts[] = { 1069 "Positive polarity", "Negative polarity", 1070 }; 1071 1072 static const struct soc_enum twl4030_vibradir_enum = 1073 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1, 1074 ARRAY_SIZE(twl4030_vibradir_texts), 1075 twl4030_vibradir_texts); 1076 1077 static const struct snd_kcontrol_new twl4030_snd_controls[] = { 1078 /* Codec operation mode control */ 1079 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum, 1080 snd_soc_get_enum_double, 1081 snd_soc_put_twl4030_opmode_enum_double), 1082 1083 /* Common playback gain controls */ 1084 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", 1085 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, 1086 0, 0x3f, 0, digital_fine_tlv), 1087 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", 1088 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, 1089 0, 0x3f, 0, digital_fine_tlv), 1090 1091 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", 1092 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, 1093 6, 0x2, 0, digital_coarse_tlv), 1094 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", 1095 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, 1096 6, 0x2, 0, digital_coarse_tlv), 1097 1098 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", 1099 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, 1100 3, 0x12, 1, analog_tlv), 1101 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", 1102 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, 1103 3, 0x12, 1, analog_tlv), 1104 SOC_DOUBLE_R("DAC1 Analog Playback Switch", 1105 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, 1106 1, 1, 0), 1107 SOC_DOUBLE_R("DAC2 Analog Playback Switch", 1108 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, 1109 1, 1, 0), 1110 1111 /* Common voice downlink gain controls */ 1112 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume", 1113 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv), 1114 1115 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume", 1116 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv), 1117 1118 SOC_SINGLE("DAC Voice Analog Downlink Switch", 1119 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0), 1120 1121 /* Separate output gain controls */ 1122 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", 1123 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, 1124 4, 3, 0, output_tvl), 1125 1126 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume", 1127 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl), 1128 1129 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume", 1130 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, 1131 4, 3, 0, output_tvl), 1132 1133 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume", 1134 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl), 1135 1136 /* Common capture gain controls */ 1137 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", 1138 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, 1139 0, 0x1f, 0, digital_capture_tlv), 1140 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", 1141 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, 1142 0, 0x1f, 0, digital_capture_tlv), 1143 1144 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, 1145 0, 3, 5, 0, input_gain_tlv), 1146 1147 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum), 1148 1149 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), 1150 1151 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum), 1152 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum), 1153 }; 1154 1155 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { 1156 /* Left channel inputs */ 1157 SND_SOC_DAPM_INPUT("MAINMIC"), 1158 SND_SOC_DAPM_INPUT("HSMIC"), 1159 SND_SOC_DAPM_INPUT("AUXL"), 1160 SND_SOC_DAPM_INPUT("CARKITMIC"), 1161 /* Right channel inputs */ 1162 SND_SOC_DAPM_INPUT("SUBMIC"), 1163 SND_SOC_DAPM_INPUT("AUXR"), 1164 /* Digital microphones (Stereo) */ 1165 SND_SOC_DAPM_INPUT("DIGIMIC0"), 1166 SND_SOC_DAPM_INPUT("DIGIMIC1"), 1167 1168 /* Outputs */ 1169 SND_SOC_DAPM_OUTPUT("OUTL"), 1170 SND_SOC_DAPM_OUTPUT("OUTR"), 1171 SND_SOC_DAPM_OUTPUT("EARPIECE"), 1172 SND_SOC_DAPM_OUTPUT("PREDRIVEL"), 1173 SND_SOC_DAPM_OUTPUT("PREDRIVER"), 1174 SND_SOC_DAPM_OUTPUT("HSOL"), 1175 SND_SOC_DAPM_OUTPUT("HSOR"), 1176 SND_SOC_DAPM_OUTPUT("CARKITL"), 1177 SND_SOC_DAPM_OUTPUT("CARKITR"), 1178 SND_SOC_DAPM_OUTPUT("HFL"), 1179 SND_SOC_DAPM_OUTPUT("HFR"), 1180 SND_SOC_DAPM_OUTPUT("VIBRA"), 1181 1182 /* DACs */ 1183 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback", 1184 SND_SOC_NOPM, 0, 0), 1185 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback", 1186 SND_SOC_NOPM, 0, 0), 1187 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback", 1188 SND_SOC_NOPM, 0, 0), 1189 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback", 1190 SND_SOC_NOPM, 0, 0), 1191 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback", 1192 SND_SOC_NOPM, 0, 0), 1193 1194 /* Analog bypasses */ 1195 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, 1196 &twl4030_dapm_abypassr1_control, bypass_event, 1197 SND_SOC_DAPM_POST_REG), 1198 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, 1199 &twl4030_dapm_abypassl1_control, 1200 bypass_event, SND_SOC_DAPM_POST_REG), 1201 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, 1202 &twl4030_dapm_abypassr2_control, 1203 bypass_event, SND_SOC_DAPM_POST_REG), 1204 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, 1205 &twl4030_dapm_abypassl2_control, 1206 bypass_event, SND_SOC_DAPM_POST_REG), 1207 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0, 1208 &twl4030_dapm_abypassv_control, 1209 bypass_event, SND_SOC_DAPM_POST_REG), 1210 1211 /* Digital bypasses */ 1212 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0, 1213 &twl4030_dapm_dbypassl_control, bypass_event, 1214 SND_SOC_DAPM_POST_REG), 1215 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0, 1216 &twl4030_dapm_dbypassr_control, bypass_event, 1217 SND_SOC_DAPM_POST_REG), 1218 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0, 1219 &twl4030_dapm_dbypassv_control, bypass_event, 1220 SND_SOC_DAPM_POST_REG), 1221 1222 /* Digital mixers, power control for the physical DACs */ 1223 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer", 1224 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0), 1225 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer", 1226 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0), 1227 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer", 1228 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0), 1229 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer", 1230 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0), 1231 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer", 1232 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0), 1233 1234 /* Analog mixers, power control for the physical PGAs */ 1235 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", 1236 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0), 1237 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", 1238 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0), 1239 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", 1240 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0), 1241 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", 1242 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0), 1243 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", 1244 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0), 1245 1246 /* Output MIXER controls */ 1247 /* Earpiece */ 1248 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0, 1249 &twl4030_dapm_earpiece_controls[0], 1250 ARRAY_SIZE(twl4030_dapm_earpiece_controls)), 1251 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM, 1252 0, 0, NULL, 0, earpiecepga_event, 1253 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1254 /* PreDrivL/R */ 1255 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0, 1256 &twl4030_dapm_predrivel_controls[0], 1257 ARRAY_SIZE(twl4030_dapm_predrivel_controls)), 1258 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM, 1259 0, 0, NULL, 0, predrivelpga_event, 1260 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1261 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0, 1262 &twl4030_dapm_predriver_controls[0], 1263 ARRAY_SIZE(twl4030_dapm_predriver_controls)), 1264 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM, 1265 0, 0, NULL, 0, predriverpga_event, 1266 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1267 /* HeadsetL/R */ 1268 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0, 1269 &twl4030_dapm_hsol_controls[0], 1270 ARRAY_SIZE(twl4030_dapm_hsol_controls)), 1271 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM, 1272 0, 0, NULL, 0, headsetlpga_event, 1273 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1274 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0, 1275 &twl4030_dapm_hsor_controls[0], 1276 ARRAY_SIZE(twl4030_dapm_hsor_controls)), 1277 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM, 1278 0, 0, NULL, 0, headsetrpga_event, 1279 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1280 /* CarkitL/R */ 1281 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0, 1282 &twl4030_dapm_carkitl_controls[0], 1283 ARRAY_SIZE(twl4030_dapm_carkitl_controls)), 1284 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM, 1285 0, 0, NULL, 0, carkitlpga_event, 1286 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1287 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0, 1288 &twl4030_dapm_carkitr_controls[0], 1289 ARRAY_SIZE(twl4030_dapm_carkitr_controls)), 1290 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM, 1291 0, 0, NULL, 0, carkitrpga_event, 1292 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1293 1294 /* Output MUX controls */ 1295 /* HandsfreeL/R */ 1296 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0, 1297 &twl4030_dapm_handsfreel_control), 1298 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0, 1299 &twl4030_dapm_handsfreelmute_control), 1300 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM, 1301 0, 0, NULL, 0, handsfreelpga_event, 1302 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1303 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0, 1304 &twl4030_dapm_handsfreer_control), 1305 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0, 1306 &twl4030_dapm_handsfreermute_control), 1307 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM, 1308 0, 0, NULL, 0, handsfreerpga_event, 1309 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1310 /* Vibra */ 1311 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0, 1312 &twl4030_dapm_vibra_control), 1313 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0, 1314 &twl4030_dapm_vibrapath_control), 1315 1316 /* Introducing four virtual ADC, since TWL4030 have four channel for 1317 capture */ 1318 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture", 1319 SND_SOC_NOPM, 0, 0), 1320 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture", 1321 SND_SOC_NOPM, 0, 0), 1322 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture", 1323 SND_SOC_NOPM, 0, 0), 1324 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture", 1325 SND_SOC_NOPM, 0, 0), 1326 1327 /* Analog/Digital mic path selection. 1328 TX1 Left/Right: either analog Left/Right or Digimic0 1329 TX2 Left/Right: either analog Left/Right or Digimic1 */ 1330 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0, 1331 &twl4030_dapm_micpathtx1_control, micpath_event, 1332 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| 1333 SND_SOC_DAPM_POST_REG), 1334 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0, 1335 &twl4030_dapm_micpathtx2_control, micpath_event, 1336 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| 1337 SND_SOC_DAPM_POST_REG), 1338 1339 /* Analog input mixers for the capture amplifiers */ 1340 SND_SOC_DAPM_MIXER("Analog Left", 1341 TWL4030_REG_ANAMICL, 4, 0, 1342 &twl4030_dapm_analoglmic_controls[0], 1343 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)), 1344 SND_SOC_DAPM_MIXER("Analog Right", 1345 TWL4030_REG_ANAMICR, 4, 0, 1346 &twl4030_dapm_analogrmic_controls[0], 1347 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)), 1348 1349 SND_SOC_DAPM_PGA("ADC Physical Left", 1350 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), 1351 SND_SOC_DAPM_PGA("ADC Physical Right", 1352 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), 1353 1354 SND_SOC_DAPM_PGA("Digimic0 Enable", 1355 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0), 1356 SND_SOC_DAPM_PGA("Digimic1 Enable", 1357 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0), 1358 1359 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), 1360 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), 1361 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), 1362 1363 }; 1364 1365 static const struct snd_soc_dapm_route intercon[] = { 1366 {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, 1367 {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, 1368 {"Digital L2 Playback Mixer", NULL, "DAC Left2"}, 1369 {"Digital R2 Playback Mixer", NULL, "DAC Right2"}, 1370 {"Digital Voice Playback Mixer", NULL, "DAC Voice"}, 1371 1372 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"}, 1373 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"}, 1374 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"}, 1375 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"}, 1376 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"}, 1377 1378 /* Internal playback routings */ 1379 /* Earpiece */ 1380 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"}, 1381 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"}, 1382 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"}, 1383 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"}, 1384 {"Earpiece PGA", NULL, "Earpiece Mixer"}, 1385 /* PreDrivL */ 1386 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"}, 1387 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, 1388 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, 1389 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"}, 1390 {"PredriveL PGA", NULL, "PredriveL Mixer"}, 1391 /* PreDrivR */ 1392 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"}, 1393 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, 1394 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, 1395 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"}, 1396 {"PredriveR PGA", NULL, "PredriveR Mixer"}, 1397 /* HeadsetL */ 1398 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"}, 1399 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, 1400 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, 1401 {"HeadsetL PGA", NULL, "HeadsetL Mixer"}, 1402 /* HeadsetR */ 1403 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"}, 1404 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, 1405 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, 1406 {"HeadsetR PGA", NULL, "HeadsetR Mixer"}, 1407 /* CarkitL */ 1408 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"}, 1409 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, 1410 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, 1411 {"CarkitL PGA", NULL, "CarkitL Mixer"}, 1412 /* CarkitR */ 1413 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"}, 1414 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, 1415 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, 1416 {"CarkitR PGA", NULL, "CarkitR Mixer"}, 1417 /* HandsfreeL */ 1418 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"}, 1419 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"}, 1420 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"}, 1421 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"}, 1422 {"HandsfreeL", "Switch", "HandsfreeL Mux"}, 1423 {"HandsfreeL PGA", NULL, "HandsfreeL"}, 1424 /* HandsfreeR */ 1425 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"}, 1426 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"}, 1427 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"}, 1428 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"}, 1429 {"HandsfreeR", "Switch", "HandsfreeR Mux"}, 1430 {"HandsfreeR PGA", NULL, "HandsfreeR"}, 1431 /* Vibra */ 1432 {"Vibra Mux", "AudioL1", "DAC Left1"}, 1433 {"Vibra Mux", "AudioR1", "DAC Right1"}, 1434 {"Vibra Mux", "AudioL2", "DAC Left2"}, 1435 {"Vibra Mux", "AudioR2", "DAC Right2"}, 1436 1437 /* outputs */ 1438 {"OUTL", NULL, "Analog L2 Playback Mixer"}, 1439 {"OUTR", NULL, "Analog R2 Playback Mixer"}, 1440 {"EARPIECE", NULL, "Earpiece PGA"}, 1441 {"PREDRIVEL", NULL, "PredriveL PGA"}, 1442 {"PREDRIVER", NULL, "PredriveR PGA"}, 1443 {"HSOL", NULL, "HeadsetL PGA"}, 1444 {"HSOR", NULL, "HeadsetR PGA"}, 1445 {"CARKITL", NULL, "CarkitL PGA"}, 1446 {"CARKITR", NULL, "CarkitR PGA"}, 1447 {"HFL", NULL, "HandsfreeL PGA"}, 1448 {"HFR", NULL, "HandsfreeR PGA"}, 1449 {"Vibra Route", "Audio", "Vibra Mux"}, 1450 {"VIBRA", NULL, "Vibra Route"}, 1451 1452 /* Capture path */ 1453 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"}, 1454 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"}, 1455 {"Analog Left", "AUXL Capture Switch", "AUXL"}, 1456 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"}, 1457 1458 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"}, 1459 {"Analog Right", "AUXR Capture Switch", "AUXR"}, 1460 1461 {"ADC Physical Left", NULL, "Analog Left"}, 1462 {"ADC Physical Right", NULL, "Analog Right"}, 1463 1464 {"Digimic0 Enable", NULL, "DIGIMIC0"}, 1465 {"Digimic1 Enable", NULL, "DIGIMIC1"}, 1466 1467 /* TX1 Left capture path */ 1468 {"TX1 Capture Route", "Analog", "ADC Physical Left"}, 1469 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, 1470 /* TX1 Right capture path */ 1471 {"TX1 Capture Route", "Analog", "ADC Physical Right"}, 1472 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, 1473 /* TX2 Left capture path */ 1474 {"TX2 Capture Route", "Analog", "ADC Physical Left"}, 1475 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, 1476 /* TX2 Right capture path */ 1477 {"TX2 Capture Route", "Analog", "ADC Physical Right"}, 1478 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, 1479 1480 {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, 1481 {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, 1482 {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, 1483 {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, 1484 1485 /* Analog bypass routes */ 1486 {"Right1 Analog Loopback", "Switch", "Analog Right"}, 1487 {"Left1 Analog Loopback", "Switch", "Analog Left"}, 1488 {"Right2 Analog Loopback", "Switch", "Analog Right"}, 1489 {"Left2 Analog Loopback", "Switch", "Analog Left"}, 1490 {"Voice Analog Loopback", "Switch", "Analog Left"}, 1491 1492 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, 1493 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, 1494 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, 1495 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, 1496 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"}, 1497 1498 /* Digital bypass routes */ 1499 {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, 1500 {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, 1501 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"}, 1502 1503 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"}, 1504 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"}, 1505 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"}, 1506 1507 }; 1508 1509 static int twl4030_add_widgets(struct snd_soc_codec *codec) 1510 { 1511 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, 1512 ARRAY_SIZE(twl4030_dapm_widgets)); 1513 1514 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 1515 1516 snd_soc_dapm_new_widgets(codec); 1517 return 0; 1518 } 1519 1520 static int twl4030_set_bias_level(struct snd_soc_codec *codec, 1521 enum snd_soc_bias_level level) 1522 { 1523 struct twl4030_priv *twl4030 = codec->private_data; 1524 1525 switch (level) { 1526 case SND_SOC_BIAS_ON: 1527 twl4030_codec_mute(codec, 0); 1528 break; 1529 case SND_SOC_BIAS_PREPARE: 1530 twl4030_power_up(codec); 1531 if (twl4030->bypass_state) 1532 twl4030_codec_mute(codec, 0); 1533 else 1534 twl4030_codec_mute(codec, 1); 1535 break; 1536 case SND_SOC_BIAS_STANDBY: 1537 twl4030_power_up(codec); 1538 if (twl4030->bypass_state) 1539 twl4030_codec_mute(codec, 0); 1540 else 1541 twl4030_codec_mute(codec, 1); 1542 break; 1543 case SND_SOC_BIAS_OFF: 1544 twl4030_power_down(codec); 1545 break; 1546 } 1547 codec->bias_level = level; 1548 1549 return 0; 1550 } 1551 1552 static void twl4030_constraints(struct twl4030_priv *twl4030, 1553 struct snd_pcm_substream *mst_substream) 1554 { 1555 struct snd_pcm_substream *slv_substream; 1556 1557 /* Pick the stream, which need to be constrained */ 1558 if (mst_substream == twl4030->master_substream) 1559 slv_substream = twl4030->slave_substream; 1560 else if (mst_substream == twl4030->slave_substream) 1561 slv_substream = twl4030->master_substream; 1562 else /* This should not happen.. */ 1563 return; 1564 1565 /* Set the constraints according to the already configured stream */ 1566 snd_pcm_hw_constraint_minmax(slv_substream->runtime, 1567 SNDRV_PCM_HW_PARAM_RATE, 1568 twl4030->rate, 1569 twl4030->rate); 1570 1571 snd_pcm_hw_constraint_minmax(slv_substream->runtime, 1572 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1573 twl4030->sample_bits, 1574 twl4030->sample_bits); 1575 1576 snd_pcm_hw_constraint_minmax(slv_substream->runtime, 1577 SNDRV_PCM_HW_PARAM_CHANNELS, 1578 twl4030->channels, 1579 twl4030->channels); 1580 } 1581 1582 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for 1583 * capture has to be enabled/disabled. */ 1584 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction, 1585 int enable) 1586 { 1587 u8 reg, mask; 1588 1589 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); 1590 1591 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 1592 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; 1593 else 1594 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; 1595 1596 if (enable) 1597 reg |= mask; 1598 else 1599 reg &= ~mask; 1600 1601 twl4030_write(codec, TWL4030_REG_OPTION, reg); 1602 } 1603 1604 static int twl4030_startup(struct snd_pcm_substream *substream, 1605 struct snd_soc_dai *dai) 1606 { 1607 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1608 struct snd_soc_device *socdev = rtd->socdev; 1609 struct snd_soc_codec *codec = socdev->card->codec; 1610 struct twl4030_priv *twl4030 = codec->private_data; 1611 1612 if (twl4030->master_substream) { 1613 twl4030->slave_substream = substream; 1614 /* The DAI has one configuration for playback and capture, so 1615 * if the DAI has been already configured then constrain this 1616 * substream to match it. */ 1617 if (twl4030->configured) 1618 twl4030_constraints(twl4030, twl4030->master_substream); 1619 } else { 1620 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) & 1621 TWL4030_OPTION_1)) { 1622 /* In option2 4 channel is not supported, set the 1623 * constraint for the first stream for channels, the 1624 * second stream will 'inherit' this cosntraint */ 1625 snd_pcm_hw_constraint_minmax(substream->runtime, 1626 SNDRV_PCM_HW_PARAM_CHANNELS, 1627 2, 2); 1628 } 1629 twl4030->master_substream = substream; 1630 } 1631 1632 return 0; 1633 } 1634 1635 static void twl4030_shutdown(struct snd_pcm_substream *substream, 1636 struct snd_soc_dai *dai) 1637 { 1638 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1639 struct snd_soc_device *socdev = rtd->socdev; 1640 struct snd_soc_codec *codec = socdev->card->codec; 1641 struct twl4030_priv *twl4030 = codec->private_data; 1642 1643 if (twl4030->master_substream == substream) 1644 twl4030->master_substream = twl4030->slave_substream; 1645 1646 twl4030->slave_substream = NULL; 1647 1648 /* If all streams are closed, or the remaining stream has not yet 1649 * been configured than set the DAI as not configured. */ 1650 if (!twl4030->master_substream) 1651 twl4030->configured = 0; 1652 else if (!twl4030->master_substream->runtime->channels) 1653 twl4030->configured = 0; 1654 1655 /* If the closing substream had 4 channel, do the necessary cleanup */ 1656 if (substream->runtime->channels == 4) 1657 twl4030_tdm_enable(codec, substream->stream, 0); 1658 } 1659 1660 static int twl4030_hw_params(struct snd_pcm_substream *substream, 1661 struct snd_pcm_hw_params *params, 1662 struct snd_soc_dai *dai) 1663 { 1664 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1665 struct snd_soc_device *socdev = rtd->socdev; 1666 struct snd_soc_codec *codec = socdev->card->codec; 1667 struct twl4030_priv *twl4030 = codec->private_data; 1668 u8 mode, old_mode, format, old_format; 1669 1670 /* If the substream has 4 channel, do the necessary setup */ 1671 if (params_channels(params) == 4) { 1672 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); 1673 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); 1674 1675 /* Safety check: are we in the correct operating mode and 1676 * the interface is in TDM mode? */ 1677 if ((mode & TWL4030_OPTION_1) && 1678 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM)) 1679 twl4030_tdm_enable(codec, substream->stream, 1); 1680 else 1681 return -EINVAL; 1682 } 1683 1684 if (twl4030->configured) 1685 /* Ignoring hw_params for already configured DAI */ 1686 return 0; 1687 1688 /* bit rate */ 1689 old_mode = twl4030_read_reg_cache(codec, 1690 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; 1691 mode = old_mode & ~TWL4030_APLL_RATE; 1692 1693 switch (params_rate(params)) { 1694 case 8000: 1695 mode |= TWL4030_APLL_RATE_8000; 1696 break; 1697 case 11025: 1698 mode |= TWL4030_APLL_RATE_11025; 1699 break; 1700 case 12000: 1701 mode |= TWL4030_APLL_RATE_12000; 1702 break; 1703 case 16000: 1704 mode |= TWL4030_APLL_RATE_16000; 1705 break; 1706 case 22050: 1707 mode |= TWL4030_APLL_RATE_22050; 1708 break; 1709 case 24000: 1710 mode |= TWL4030_APLL_RATE_24000; 1711 break; 1712 case 32000: 1713 mode |= TWL4030_APLL_RATE_32000; 1714 break; 1715 case 44100: 1716 mode |= TWL4030_APLL_RATE_44100; 1717 break; 1718 case 48000: 1719 mode |= TWL4030_APLL_RATE_48000; 1720 break; 1721 case 96000: 1722 mode |= TWL4030_APLL_RATE_96000; 1723 break; 1724 default: 1725 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", 1726 params_rate(params)); 1727 return -EINVAL; 1728 } 1729 1730 if (mode != old_mode) { 1731 /* change rate and set CODECPDZ */ 1732 twl4030_codec_enable(codec, 0); 1733 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); 1734 twl4030_codec_enable(codec, 1); 1735 } 1736 1737 /* sample size */ 1738 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); 1739 format = old_format; 1740 format &= ~TWL4030_DATA_WIDTH; 1741 switch (params_format(params)) { 1742 case SNDRV_PCM_FORMAT_S16_LE: 1743 format |= TWL4030_DATA_WIDTH_16S_16W; 1744 break; 1745 case SNDRV_PCM_FORMAT_S24_LE: 1746 format |= TWL4030_DATA_WIDTH_32S_24W; 1747 break; 1748 default: 1749 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", 1750 params_format(params)); 1751 return -EINVAL; 1752 } 1753 1754 if (format != old_format) { 1755 1756 /* clear CODECPDZ before changing format (codec requirement) */ 1757 twl4030_codec_enable(codec, 0); 1758 1759 /* change format */ 1760 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); 1761 1762 /* set CODECPDZ afterwards */ 1763 twl4030_codec_enable(codec, 1); 1764 } 1765 1766 /* Store the important parameters for the DAI configuration and set 1767 * the DAI as configured */ 1768 twl4030->configured = 1; 1769 twl4030->rate = params_rate(params); 1770 twl4030->sample_bits = hw_param_interval(params, 1771 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 1772 twl4030->channels = params_channels(params); 1773 1774 /* If both playback and capture streams are open, and one of them 1775 * is setting the hw parameters right now (since we are here), set 1776 * constraints to the other stream to match the current one. */ 1777 if (twl4030->slave_substream) 1778 twl4030_constraints(twl4030, substream); 1779 1780 return 0; 1781 } 1782 1783 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1784 int clk_id, unsigned int freq, int dir) 1785 { 1786 struct snd_soc_codec *codec = codec_dai->codec; 1787 struct twl4030_priv *twl4030 = codec->private_data; 1788 u8 infreq; 1789 1790 switch (freq) { 1791 case 19200000: 1792 infreq = TWL4030_APLL_INFREQ_19200KHZ; 1793 twl4030->sysclk = 19200; 1794 break; 1795 case 26000000: 1796 infreq = TWL4030_APLL_INFREQ_26000KHZ; 1797 twl4030->sysclk = 26000; 1798 break; 1799 case 38400000: 1800 infreq = TWL4030_APLL_INFREQ_38400KHZ; 1801 twl4030->sysclk = 38400; 1802 break; 1803 default: 1804 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", 1805 freq); 1806 return -EINVAL; 1807 } 1808 1809 infreq |= TWL4030_APLL_EN; 1810 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); 1811 1812 return 0; 1813 } 1814 1815 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, 1816 unsigned int fmt) 1817 { 1818 struct snd_soc_codec *codec = codec_dai->codec; 1819 u8 old_format, format; 1820 1821 /* get format */ 1822 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); 1823 format = old_format; 1824 1825 /* set master/slave audio interface */ 1826 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1827 case SND_SOC_DAIFMT_CBM_CFM: 1828 format &= ~(TWL4030_AIF_SLAVE_EN); 1829 format &= ~(TWL4030_CLK256FS_EN); 1830 break; 1831 case SND_SOC_DAIFMT_CBS_CFS: 1832 format |= TWL4030_AIF_SLAVE_EN; 1833 format |= TWL4030_CLK256FS_EN; 1834 break; 1835 default: 1836 return -EINVAL; 1837 } 1838 1839 /* interface format */ 1840 format &= ~TWL4030_AIF_FORMAT; 1841 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1842 case SND_SOC_DAIFMT_I2S: 1843 format |= TWL4030_AIF_FORMAT_CODEC; 1844 break; 1845 case SND_SOC_DAIFMT_DSP_A: 1846 format |= TWL4030_AIF_FORMAT_TDM; 1847 break; 1848 default: 1849 return -EINVAL; 1850 } 1851 1852 if (format != old_format) { 1853 1854 /* clear CODECPDZ before changing format (codec requirement) */ 1855 twl4030_codec_enable(codec, 0); 1856 1857 /* change format */ 1858 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); 1859 1860 /* set CODECPDZ afterwards */ 1861 twl4030_codec_enable(codec, 1); 1862 } 1863 1864 return 0; 1865 } 1866 1867 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate) 1868 { 1869 struct snd_soc_codec *codec = dai->codec; 1870 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); 1871 1872 if (tristate) 1873 reg |= TWL4030_AIF_TRI_EN; 1874 else 1875 reg &= ~TWL4030_AIF_TRI_EN; 1876 1877 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg); 1878 } 1879 1880 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R 1881 * (VTXL, VTXR) for uplink has to be enabled/disabled. */ 1882 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction, 1883 int enable) 1884 { 1885 u8 reg, mask; 1886 1887 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); 1888 1889 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 1890 mask = TWL4030_ARXL1_VRX_EN; 1891 else 1892 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; 1893 1894 if (enable) 1895 reg |= mask; 1896 else 1897 reg &= ~mask; 1898 1899 twl4030_write(codec, TWL4030_REG_OPTION, reg); 1900 } 1901 1902 static int twl4030_voice_startup(struct snd_pcm_substream *substream, 1903 struct snd_soc_dai *dai) 1904 { 1905 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1906 struct snd_soc_device *socdev = rtd->socdev; 1907 struct snd_soc_codec *codec = socdev->card->codec; 1908 u8 infreq; 1909 u8 mode; 1910 1911 /* If the system master clock is not 26MHz, the voice PCM interface is 1912 * not avilable. 1913 */ 1914 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL) 1915 & TWL4030_APLL_INFREQ; 1916 1917 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) { 1918 printk(KERN_ERR "TWL4030 voice startup: " 1919 "MCLK is not 26MHz, call set_sysclk() on init\n"); 1920 return -EINVAL; 1921 } 1922 1923 /* If the codec mode is not option2, the voice PCM interface is not 1924 * avilable. 1925 */ 1926 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) 1927 & TWL4030_OPT_MODE; 1928 1929 if (mode != TWL4030_OPTION_2) { 1930 printk(KERN_ERR "TWL4030 voice startup: " 1931 "the codec mode is not option2\n"); 1932 return -EINVAL; 1933 } 1934 1935 return 0; 1936 } 1937 1938 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, 1939 struct snd_soc_dai *dai) 1940 { 1941 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1942 struct snd_soc_device *socdev = rtd->socdev; 1943 struct snd_soc_codec *codec = socdev->card->codec; 1944 1945 /* Enable voice digital filters */ 1946 twl4030_voice_enable(codec, substream->stream, 0); 1947 } 1948 1949 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, 1950 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1951 { 1952 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1953 struct snd_soc_device *socdev = rtd->socdev; 1954 struct snd_soc_codec *codec = socdev->card->codec; 1955 u8 old_mode, mode; 1956 1957 /* Enable voice digital filters */ 1958 twl4030_voice_enable(codec, substream->stream, 1); 1959 1960 /* bit rate */ 1961 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) 1962 & ~(TWL4030_CODECPDZ); 1963 mode = old_mode; 1964 1965 switch (params_rate(params)) { 1966 case 8000: 1967 mode &= ~(TWL4030_SEL_16K); 1968 break; 1969 case 16000: 1970 mode |= TWL4030_SEL_16K; 1971 break; 1972 default: 1973 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n", 1974 params_rate(params)); 1975 return -EINVAL; 1976 } 1977 1978 if (mode != old_mode) { 1979 /* change rate and set CODECPDZ */ 1980 twl4030_codec_enable(codec, 0); 1981 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); 1982 twl4030_codec_enable(codec, 1); 1983 } 1984 1985 return 0; 1986 } 1987 1988 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1989 int clk_id, unsigned int freq, int dir) 1990 { 1991 struct snd_soc_codec *codec = codec_dai->codec; 1992 u8 infreq; 1993 1994 switch (freq) { 1995 case 26000000: 1996 infreq = TWL4030_APLL_INFREQ_26000KHZ; 1997 break; 1998 default: 1999 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n", 2000 freq); 2001 return -EINVAL; 2002 } 2003 2004 infreq |= TWL4030_APLL_EN; 2005 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); 2006 2007 return 0; 2008 } 2009 2010 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, 2011 unsigned int fmt) 2012 { 2013 struct snd_soc_codec *codec = codec_dai->codec; 2014 u8 old_format, format; 2015 2016 /* get format */ 2017 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); 2018 format = old_format; 2019 2020 /* set master/slave audio interface */ 2021 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2022 case SND_SOC_DAIFMT_CBM_CFM: 2023 format &= ~(TWL4030_VIF_SLAVE_EN); 2024 break; 2025 case SND_SOC_DAIFMT_CBS_CFS: 2026 format |= TWL4030_VIF_SLAVE_EN; 2027 break; 2028 default: 2029 return -EINVAL; 2030 } 2031 2032 /* clock inversion */ 2033 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2034 case SND_SOC_DAIFMT_IB_NF: 2035 format &= ~(TWL4030_VIF_FORMAT); 2036 break; 2037 case SND_SOC_DAIFMT_NB_IF: 2038 format |= TWL4030_VIF_FORMAT; 2039 break; 2040 default: 2041 return -EINVAL; 2042 } 2043 2044 if (format != old_format) { 2045 /* change format and set CODECPDZ */ 2046 twl4030_codec_enable(codec, 0); 2047 twl4030_write(codec, TWL4030_REG_VOICE_IF, format); 2048 twl4030_codec_enable(codec, 1); 2049 } 2050 2051 return 0; 2052 } 2053 2054 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate) 2055 { 2056 struct snd_soc_codec *codec = dai->codec; 2057 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); 2058 2059 if (tristate) 2060 reg |= TWL4030_VIF_TRI_EN; 2061 else 2062 reg &= ~TWL4030_VIF_TRI_EN; 2063 2064 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg); 2065 } 2066 2067 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) 2068 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) 2069 2070 static struct snd_soc_dai_ops twl4030_dai_ops = { 2071 .startup = twl4030_startup, 2072 .shutdown = twl4030_shutdown, 2073 .hw_params = twl4030_hw_params, 2074 .set_sysclk = twl4030_set_dai_sysclk, 2075 .set_fmt = twl4030_set_dai_fmt, 2076 .set_tristate = twl4030_set_tristate, 2077 }; 2078 2079 static struct snd_soc_dai_ops twl4030_dai_voice_ops = { 2080 .startup = twl4030_voice_startup, 2081 .shutdown = twl4030_voice_shutdown, 2082 .hw_params = twl4030_voice_hw_params, 2083 .set_sysclk = twl4030_voice_set_dai_sysclk, 2084 .set_fmt = twl4030_voice_set_dai_fmt, 2085 .set_tristate = twl4030_voice_set_tristate, 2086 }; 2087 2088 struct snd_soc_dai twl4030_dai[] = { 2089 { 2090 .name = "twl4030", 2091 .playback = { 2092 .stream_name = "HiFi Playback", 2093 .channels_min = 2, 2094 .channels_max = 4, 2095 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, 2096 .formats = TWL4030_FORMATS,}, 2097 .capture = { 2098 .stream_name = "Capture", 2099 .channels_min = 2, 2100 .channels_max = 4, 2101 .rates = TWL4030_RATES, 2102 .formats = TWL4030_FORMATS,}, 2103 .ops = &twl4030_dai_ops, 2104 }, 2105 { 2106 .name = "twl4030 Voice", 2107 .playback = { 2108 .stream_name = "Voice Playback", 2109 .channels_min = 1, 2110 .channels_max = 1, 2111 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, 2112 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 2113 .capture = { 2114 .stream_name = "Capture", 2115 .channels_min = 1, 2116 .channels_max = 2, 2117 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, 2118 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 2119 .ops = &twl4030_dai_voice_ops, 2120 }, 2121 }; 2122 EXPORT_SYMBOL_GPL(twl4030_dai); 2123 2124 static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) 2125 { 2126 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2127 struct snd_soc_codec *codec = socdev->card->codec; 2128 2129 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); 2130 2131 return 0; 2132 } 2133 2134 static int twl4030_resume(struct platform_device *pdev) 2135 { 2136 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2137 struct snd_soc_codec *codec = socdev->card->codec; 2138 2139 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2140 twl4030_set_bias_level(codec, codec->suspend_bias_level); 2141 return 0; 2142 } 2143 2144 /* 2145 * initialize the driver 2146 * register the mixer and dsp interfaces with the kernel 2147 */ 2148 2149 static int twl4030_init(struct snd_soc_device *socdev) 2150 { 2151 struct snd_soc_codec *codec = socdev->card->codec; 2152 struct twl4030_setup_data *setup = socdev->codec_data; 2153 struct twl4030_priv *twl4030 = codec->private_data; 2154 int ret = 0; 2155 2156 printk(KERN_INFO "TWL4030 Audio Codec init \n"); 2157 2158 codec->name = "twl4030"; 2159 codec->owner = THIS_MODULE; 2160 codec->read = twl4030_read_reg_cache; 2161 codec->write = twl4030_write; 2162 codec->set_bias_level = twl4030_set_bias_level; 2163 codec->dai = twl4030_dai; 2164 codec->num_dai = ARRAY_SIZE(twl4030_dai), 2165 codec->reg_cache_size = sizeof(twl4030_reg); 2166 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), 2167 GFP_KERNEL); 2168 if (codec->reg_cache == NULL) 2169 return -ENOMEM; 2170 2171 /* Configuration for headset ramp delay from setup data */ 2172 if (setup) { 2173 unsigned char hs_pop; 2174 2175 if (setup->sysclk) 2176 twl4030->sysclk = setup->sysclk; 2177 else 2178 twl4030->sysclk = 26000; 2179 2180 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); 2181 hs_pop &= ~TWL4030_RAMP_DELAY; 2182 hs_pop |= (setup->ramp_delay_value << 2); 2183 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 2184 } else { 2185 twl4030->sysclk = 26000; 2186 } 2187 2188 /* register pcms */ 2189 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 2190 if (ret < 0) { 2191 printk(KERN_ERR "twl4030: failed to create pcms\n"); 2192 goto pcm_err; 2193 } 2194 2195 twl4030_init_chip(codec); 2196 2197 /* power on device */ 2198 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2199 2200 snd_soc_add_controls(codec, twl4030_snd_controls, 2201 ARRAY_SIZE(twl4030_snd_controls)); 2202 twl4030_add_widgets(codec); 2203 2204 ret = snd_soc_init_card(socdev); 2205 if (ret < 0) { 2206 printk(KERN_ERR "twl4030: failed to register card\n"); 2207 goto card_err; 2208 } 2209 2210 return ret; 2211 2212 card_err: 2213 snd_soc_free_pcms(socdev); 2214 snd_soc_dapm_free(socdev); 2215 pcm_err: 2216 kfree(codec->reg_cache); 2217 return ret; 2218 } 2219 2220 static struct snd_soc_device *twl4030_socdev; 2221 2222 static int twl4030_probe(struct platform_device *pdev) 2223 { 2224 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2225 struct snd_soc_codec *codec; 2226 struct twl4030_priv *twl4030; 2227 2228 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); 2229 if (codec == NULL) 2230 return -ENOMEM; 2231 2232 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); 2233 if (twl4030 == NULL) { 2234 kfree(codec); 2235 return -ENOMEM; 2236 } 2237 2238 codec->private_data = twl4030; 2239 socdev->card->codec = codec; 2240 mutex_init(&codec->mutex); 2241 INIT_LIST_HEAD(&codec->dapm_widgets); 2242 INIT_LIST_HEAD(&codec->dapm_paths); 2243 2244 twl4030_socdev = socdev; 2245 twl4030_init(socdev); 2246 2247 return 0; 2248 } 2249 2250 static int twl4030_remove(struct platform_device *pdev) 2251 { 2252 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 2253 struct snd_soc_codec *codec = socdev->card->codec; 2254 2255 printk(KERN_INFO "TWL4030 Audio Codec remove\n"); 2256 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); 2257 snd_soc_free_pcms(socdev); 2258 snd_soc_dapm_free(socdev); 2259 kfree(codec->private_data); 2260 kfree(codec); 2261 2262 return 0; 2263 } 2264 2265 struct snd_soc_codec_device soc_codec_dev_twl4030 = { 2266 .probe = twl4030_probe, 2267 .remove = twl4030_remove, 2268 .suspend = twl4030_suspend, 2269 .resume = twl4030_resume, 2270 }; 2271 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); 2272 2273 static int __init twl4030_modinit(void) 2274 { 2275 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); 2276 } 2277 module_init(twl4030_modinit); 2278 2279 static void __exit twl4030_exit(void) 2280 { 2281 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); 2282 } 2283 module_exit(twl4030_exit); 2284 2285 MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); 2286 MODULE_AUTHOR("Steve Sakoman"); 2287 MODULE_LICENSE("GPL"); 2288