1 // SPDX-License-Identifier: GPL-2.0 2 // tscs454.c -- TSCS454 ALSA SoC Audio driver 3 // Copyright 2018 Tempo Semiconductor, Inc. 4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> 5 6 #include <linux/kernel.h> 7 #include <linux/cleanup.h> 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/regmap.h> 11 #include <linux/i2c.h> 12 #include <linux/err.h> 13 #include <linux/string.h> 14 #include <linux/string_choices.h> 15 #include <linux/module.h> 16 #include <linux/delay.h> 17 #include <linux/mutex.h> 18 19 #include <sound/tlv.h> 20 #include <sound/pcm_params.h> 21 #include <sound/pcm.h> 22 #include <sound/soc.h> 23 #include <sound/soc-dapm.h> 24 25 #include "tscs454.h" 26 27 static const unsigned int PLL_44_1K_RATE = (44100 * 256); 28 29 #define COEFF_SIZE 3 30 #define BIQUAD_COEFF_COUNT 5 31 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) 32 33 #define COEFF_RAM_MAX_ADDR 0xcd 34 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) 35 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) 36 37 enum { 38 TSCS454_DAI1_ID, 39 TSCS454_DAI2_ID, 40 TSCS454_DAI3_ID, 41 TSCS454_DAI_COUNT, 42 }; 43 44 struct pll { 45 int id; 46 unsigned int users; 47 struct mutex lock; 48 }; 49 50 static inline void pll_init(struct pll *pll, int id) 51 { 52 pll->id = id; 53 mutex_init(&pll->lock); 54 } 55 56 struct internal_rate { 57 struct pll *pll; 58 }; 59 60 struct aif { 61 unsigned int id; 62 bool provider; 63 struct pll *pll; 64 }; 65 66 static inline void aif_init(struct aif *aif, unsigned int id) 67 { 68 aif->id = id; 69 } 70 71 struct coeff_ram { 72 u8 cache[COEFF_RAM_SIZE]; 73 bool synced; 74 struct mutex lock; 75 }; 76 77 static inline void init_coeff_ram_cache(u8 *cache) 78 { 79 static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 80 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 81 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 82 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 83 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9}; 84 int i; 85 86 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) 87 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; 88 } 89 90 static inline void coeff_ram_init(struct coeff_ram *ram) 91 { 92 init_coeff_ram_cache(ram->cache); 93 mutex_init(&ram->lock); 94 } 95 96 struct aifs_status { 97 u8 streams; 98 }; 99 100 static inline void set_aif_status_active(struct aifs_status *status, 101 int aif_id, bool playback) 102 { 103 u8 mask = 0x01 << (aif_id * 2 + !playback); 104 105 status->streams |= mask; 106 } 107 108 static inline void set_aif_status_inactive(struct aifs_status *status, 109 int aif_id, bool playback) 110 { 111 u8 mask = ~(0x01 << (aif_id * 2 + !playback)); 112 113 status->streams &= mask; 114 } 115 116 static bool aifs_active(struct aifs_status *status) 117 { 118 return status->streams; 119 } 120 121 static bool aif_active(struct aifs_status *status, int aif_id) 122 { 123 return (0x03 << aif_id * 2) & status->streams; 124 } 125 126 struct tscs454 { 127 struct regmap *regmap; 128 struct aif aifs[TSCS454_DAI_COUNT]; 129 130 struct aifs_status aifs_status; 131 struct mutex aifs_status_lock; 132 133 struct pll pll1; 134 struct pll pll2; 135 struct internal_rate internal_rate; 136 137 struct coeff_ram dac_ram; 138 struct coeff_ram spk_ram; 139 struct coeff_ram sub_ram; 140 141 struct clk *sysclk; 142 int sysclk_src_id; 143 unsigned int bclk_freq; 144 }; 145 146 struct coeff_ram_ctl { 147 unsigned int addr; 148 struct soc_bytes_ext bytes_ext; 149 }; 150 151 static const struct reg_sequence tscs454_patch[] = { 152 /* Assign ASRC out of the box so DAI 1 just works */ 153 { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 }, 154 { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 }, 155 { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR }, 156 { R_TDMCTL0, FV_TDMMD_256 }, 157 { VIRT_ADDR(0x0A, 0x13), 1 << 3 }, 158 }; 159 160 static bool tscs454_volatile(struct device *dev, unsigned int reg) 161 { 162 switch (reg) { 163 case R_PLLSTAT: 164 165 case R_SPKCRRDL: 166 case R_SPKCRRDM: 167 case R_SPKCRRDH: 168 case R_SPKCRS: 169 170 case R_DACCRRDL: 171 case R_DACCRRDM: 172 case R_DACCRRDH: 173 case R_DACCRS: 174 175 case R_SUBCRRDL: 176 case R_SUBCRRDM: 177 case R_SUBCRRDH: 178 case R_SUBCRS: 179 return true; 180 default: 181 return false; 182 } 183 } 184 185 static bool tscs454_writable(struct device *dev, unsigned int reg) 186 { 187 switch (reg) { 188 case R_SPKCRRDL: 189 case R_SPKCRRDM: 190 case R_SPKCRRDH: 191 192 case R_DACCRRDL: 193 case R_DACCRRDM: 194 case R_DACCRRDH: 195 196 case R_SUBCRRDL: 197 case R_SUBCRRDM: 198 case R_SUBCRRDH: 199 return false; 200 default: 201 return true; 202 } 203 } 204 205 static bool tscs454_readable(struct device *dev, unsigned int reg) 206 { 207 switch (reg) { 208 case R_SPKCRWDL: 209 case R_SPKCRWDM: 210 case R_SPKCRWDH: 211 212 case R_DACCRWDL: 213 case R_DACCRWDM: 214 case R_DACCRWDH: 215 216 case R_SUBCRWDL: 217 case R_SUBCRWDM: 218 case R_SUBCRWDH: 219 return false; 220 default: 221 return true; 222 } 223 } 224 225 static bool tscs454_precious(struct device *dev, unsigned int reg) 226 { 227 switch (reg) { 228 case R_SPKCRWDL: 229 case R_SPKCRWDM: 230 case R_SPKCRWDH: 231 case R_SPKCRRDL: 232 case R_SPKCRRDM: 233 case R_SPKCRRDH: 234 235 case R_DACCRWDL: 236 case R_DACCRWDM: 237 case R_DACCRWDH: 238 case R_DACCRRDL: 239 case R_DACCRRDM: 240 case R_DACCRRDH: 241 242 case R_SUBCRWDL: 243 case R_SUBCRWDM: 244 case R_SUBCRWDH: 245 case R_SUBCRRDL: 246 case R_SUBCRRDM: 247 case R_SUBCRRDH: 248 return true; 249 default: 250 return false; 251 } 252 } 253 254 static const struct regmap_range_cfg tscs454_regmap_range_cfg = { 255 .name = "Pages", 256 .range_min = VIRT_BASE, 257 .range_max = VIRT_ADDR(0xFE, 0x02), 258 .selector_reg = R_PAGESEL, 259 .selector_mask = 0xff, 260 .selector_shift = 0, 261 .window_start = 0, 262 .window_len = 0x100, 263 }; 264 265 static struct regmap_config const tscs454_regmap_cfg = { 266 .reg_bits = 8, 267 .val_bits = 8, 268 .writeable_reg = tscs454_writable, 269 .readable_reg = tscs454_readable, 270 .volatile_reg = tscs454_volatile, 271 .precious_reg = tscs454_precious, 272 .ranges = &tscs454_regmap_range_cfg, 273 .num_ranges = 1, 274 .max_register = VIRT_ADDR(0xFE, 0x02), 275 .cache_type = REGCACHE_RBTREE, 276 }; 277 278 static inline int tscs454_data_init(struct tscs454 *tscs454, 279 struct i2c_client *i2c) 280 { 281 int i; 282 int ret; 283 284 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg); 285 if (IS_ERR(tscs454->regmap)) { 286 ret = PTR_ERR(tscs454->regmap); 287 return ret; 288 } 289 290 for (i = 0; i < TSCS454_DAI_COUNT; i++) 291 aif_init(&tscs454->aifs[i], i); 292 293 mutex_init(&tscs454->aifs_status_lock); 294 pll_init(&tscs454->pll1, 1); 295 pll_init(&tscs454->pll2, 2); 296 297 coeff_ram_init(&tscs454->dac_ram); 298 coeff_ram_init(&tscs454->spk_ram); 299 coeff_ram_init(&tscs454->sub_ram); 300 301 return 0; 302 } 303 304 struct reg_setting { 305 unsigned int addr; 306 unsigned int val; 307 }; 308 309 static int coeff_ram_get(struct snd_kcontrol *kcontrol, 310 struct snd_ctl_elem_value *ucontrol) 311 { 312 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 313 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 314 struct coeff_ram_ctl *ctl = 315 (struct coeff_ram_ctl *)kcontrol->private_value; 316 struct soc_bytes_ext *params = &ctl->bytes_ext; 317 u8 *coeff_ram; 318 struct mutex *coeff_ram_lock; 319 320 if (strstr(kcontrol->id.name, "DAC")) { 321 coeff_ram = tscs454->dac_ram.cache; 322 coeff_ram_lock = &tscs454->dac_ram.lock; 323 } else if (strstr(kcontrol->id.name, "Speaker")) { 324 coeff_ram = tscs454->spk_ram.cache; 325 coeff_ram_lock = &tscs454->spk_ram.lock; 326 } else if (strstr(kcontrol->id.name, "Sub")) { 327 coeff_ram = tscs454->sub_ram.cache; 328 coeff_ram_lock = &tscs454->sub_ram.lock; 329 } else { 330 return -EINVAL; 331 } 332 333 scoped_guard(mutex, coeff_ram_lock) { 334 memcpy(ucontrol->value.bytes.data, 335 &coeff_ram[ctl->addr * COEFF_SIZE], params->max); 336 } 337 338 return 0; 339 } 340 341 #define DACCRSTAT_MAX_TRYS 10 342 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram, 343 unsigned int r_stat, unsigned int r_addr, unsigned int r_wr, 344 unsigned int coeff_addr, unsigned int coeff_cnt) 345 { 346 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 347 unsigned int val; 348 int cnt; 349 int trys; 350 int ret; 351 352 for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) { 353 354 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { 355 val = snd_soc_component_read(component, r_stat); 356 if (!val) 357 break; 358 } 359 360 if (trys == DACCRSTAT_MAX_TRYS) { 361 ret = -EIO; 362 dev_err(component->dev, 363 "Coefficient write error (%d)\n", ret); 364 return ret; 365 } 366 367 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr); 368 if (ret < 0) { 369 dev_err(component->dev, 370 "Failed to write dac ram address (%d)\n", ret); 371 return ret; 372 } 373 374 ret = regmap_bulk_write(tscs454->regmap, r_wr, 375 &coeff_ram[coeff_addr * COEFF_SIZE], 376 COEFF_SIZE); 377 if (ret < 0) { 378 dev_err(component->dev, 379 "Failed to write dac ram (%d)\n", ret); 380 return ret; 381 } 382 } 383 384 return 0; 385 } 386 387 static int coeff_ram_put(struct snd_kcontrol *kcontrol, 388 struct snd_ctl_elem_value *ucontrol) 389 { 390 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 391 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 392 struct coeff_ram_ctl *ctl = 393 (struct coeff_ram_ctl *)kcontrol->private_value; 394 struct soc_bytes_ext *params = &ctl->bytes_ext; 395 unsigned int coeff_cnt = params->max / COEFF_SIZE; 396 u8 *coeff_ram; 397 struct mutex *coeff_ram_lock; 398 bool *coeff_ram_synced; 399 unsigned int r_stat; 400 unsigned int r_addr; 401 unsigned int r_wr; 402 unsigned int val; 403 int ret; 404 405 if (strstr(kcontrol->id.name, "DAC")) { 406 coeff_ram = tscs454->dac_ram.cache; 407 coeff_ram_lock = &tscs454->dac_ram.lock; 408 coeff_ram_synced = &tscs454->dac_ram.synced; 409 r_stat = R_DACCRS; 410 r_addr = R_DACCRADD; 411 r_wr = R_DACCRWDL; 412 } else if (strstr(kcontrol->id.name, "Speaker")) { 413 coeff_ram = tscs454->spk_ram.cache; 414 coeff_ram_lock = &tscs454->spk_ram.lock; 415 coeff_ram_synced = &tscs454->spk_ram.synced; 416 r_stat = R_SPKCRS; 417 r_addr = R_SPKCRADD; 418 r_wr = R_SPKCRWDL; 419 } else if (strstr(kcontrol->id.name, "Sub")) { 420 coeff_ram = tscs454->sub_ram.cache; 421 coeff_ram_lock = &tscs454->sub_ram.lock; 422 coeff_ram_synced = &tscs454->sub_ram.synced; 423 r_stat = R_SUBCRS; 424 r_addr = R_SUBCRADD; 425 r_wr = R_SUBCRWDL; 426 } else { 427 return -EINVAL; 428 } 429 430 guard(mutex)(coeff_ram_lock); 431 432 *coeff_ram_synced = false; 433 434 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE], 435 ucontrol->value.bytes.data, params->max); 436 437 guard(mutex)(&tscs454->pll1.lock); 438 guard(mutex)(&tscs454->pll2.lock); 439 440 val = snd_soc_component_read(component, R_PLLSTAT); 441 if (val) { /* PLLs locked */ 442 ret = write_coeff_ram(component, coeff_ram, 443 r_stat, r_addr, r_wr, 444 ctl->addr, coeff_cnt); 445 if (ret < 0) { 446 dev_err(component->dev, 447 "Failed to flush coeff ram cache (%d)\n", ret); 448 return ret; 449 } 450 *coeff_ram_synced = true; 451 } 452 453 return 0; 454 } 455 456 static inline int coeff_ram_sync(struct snd_soc_component *component, 457 struct tscs454 *tscs454) 458 { 459 int ret; 460 461 scoped_guard(mutex, &tscs454->dac_ram.lock) { 462 if (!tscs454->dac_ram.synced) { 463 ret = write_coeff_ram(component, tscs454->dac_ram.cache, 464 R_DACCRS, R_DACCRADD, R_DACCRWDL, 465 0x00, COEFF_RAM_COEFF_COUNT); 466 if (ret < 0) 467 return ret; 468 } 469 } 470 471 scoped_guard(mutex, &tscs454->spk_ram.lock) { 472 if (!tscs454->spk_ram.synced) { 473 ret = write_coeff_ram(component, tscs454->spk_ram.cache, 474 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL, 475 0x00, COEFF_RAM_COEFF_COUNT); 476 if (ret < 0) 477 return ret; 478 } 479 } 480 481 scoped_guard(mutex, &tscs454->sub_ram.lock) { 482 if (!tscs454->sub_ram.synced) { 483 ret = write_coeff_ram(component, tscs454->sub_ram.cache, 484 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL, 485 0x00, COEFF_RAM_COEFF_COUNT); 486 if (ret < 0) 487 return ret; 488 } 489 } 490 491 return 0; 492 } 493 494 #define PLL_REG_SETTINGS_COUNT 11 495 struct pll_ctl { 496 int freq_in; 497 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; 498 }; 499 500 #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \ 501 { \ 502 .freq_in = f, \ 503 .settings = { \ 504 {R_PLL1CTL, c1}, \ 505 {R_PLL1RDIV, r1}, \ 506 {R_PLL1ODIV, o1}, \ 507 {R_PLL1FDIVL, f1l}, \ 508 {R_PLL1FDIVH, f1h}, \ 509 {R_PLL2CTL, c2}, \ 510 {R_PLL2RDIV, r2}, \ 511 {R_PLL2ODIV, o2}, \ 512 {R_PLL2FDIVL, f2l}, \ 513 {R_PLL2FDIVH, f2h}, \ 514 {R_TIMEBASE, t}, \ 515 }, \ 516 } 517 518 static const struct pll_ctl pll_ctls[] = { 519 PLL_CTL(1411200, 0x05, 520 0xB9, 0x07, 0x02, 0xC3, 0x04, 521 0x5A, 0x02, 0x03, 0xE0, 0x01), 522 PLL_CTL(1536000, 0x05, 523 0x5A, 0x02, 0x03, 0xE0, 0x01, 524 0x5A, 0x02, 0x03, 0xB9, 0x01), 525 PLL_CTL(2822400, 0x0A, 526 0x63, 0x07, 0x04, 0xC3, 0x04, 527 0x62, 0x07, 0x03, 0x48, 0x03), 528 PLL_CTL(3072000, 0x0B, 529 0x62, 0x07, 0x03, 0x48, 0x03, 530 0x5A, 0x04, 0x03, 0xB9, 0x01), 531 PLL_CTL(5644800, 0x15, 532 0x63, 0x0E, 0x04, 0xC3, 0x04, 533 0x5A, 0x08, 0x03, 0xE0, 0x01), 534 PLL_CTL(6144000, 0x17, 535 0x5A, 0x08, 0x03, 0xE0, 0x01, 536 0x5A, 0x08, 0x03, 0xB9, 0x01), 537 PLL_CTL(12000000, 0x2E, 538 0x5B, 0x19, 0x03, 0x00, 0x03, 539 0x6A, 0x19, 0x05, 0x98, 0x04), 540 PLL_CTL(19200000, 0x4A, 541 0x53, 0x14, 0x03, 0x80, 0x01, 542 0x5A, 0x19, 0x03, 0xB9, 0x01), 543 PLL_CTL(22000000, 0x55, 544 0x6A, 0x37, 0x05, 0x00, 0x06, 545 0x62, 0x26, 0x03, 0x49, 0x02), 546 PLL_CTL(22579200, 0x57, 547 0x62, 0x31, 0x03, 0x20, 0x03, 548 0x53, 0x1D, 0x03, 0xB3, 0x01), 549 PLL_CTL(24000000, 0x5D, 550 0x53, 0x19, 0x03, 0x80, 0x01, 551 0x5B, 0x19, 0x05, 0x4C, 0x02), 552 PLL_CTL(24576000, 0x5F, 553 0x53, 0x1D, 0x03, 0xB3, 0x01, 554 0x62, 0x40, 0x03, 0x72, 0x03), 555 PLL_CTL(27000000, 0x68, 556 0x62, 0x4B, 0x03, 0x00, 0x04, 557 0x6A, 0x7D, 0x03, 0x20, 0x06), 558 PLL_CTL(36000000, 0x8C, 559 0x5B, 0x4B, 0x03, 0x00, 0x03, 560 0x6A, 0x7D, 0x03, 0x98, 0x04), 561 PLL_CTL(11289600, 0x2B, 562 0x6A, 0x31, 0x03, 0x40, 0x06, 563 0x5A, 0x12, 0x03, 0x1C, 0x02), 564 PLL_CTL(26000000, 0x65, 565 0x63, 0x41, 0x05, 0x00, 0x06, 566 0x5A, 0x26, 0x03, 0xEF, 0x01), 567 PLL_CTL(12288000, 0x2F, 568 0x5A, 0x12, 0x03, 0x1C, 0x02, 569 0x62, 0x20, 0x03, 0x72, 0x03), 570 PLL_CTL(40000000, 0x9B, 571 0xA2, 0x7D, 0x03, 0x80, 0x04, 572 0x63, 0x7D, 0x05, 0xE4, 0x06), 573 PLL_CTL(512000, 0x01, 574 0x62, 0x01, 0x03, 0xD0, 0x02, 575 0x5B, 0x01, 0x04, 0x72, 0x03), 576 PLL_CTL(705600, 0x02, 577 0x62, 0x02, 0x03, 0x15, 0x04, 578 0x62, 0x01, 0x04, 0x80, 0x02), 579 PLL_CTL(1024000, 0x03, 580 0x62, 0x02, 0x03, 0xD0, 0x02, 581 0x5B, 0x02, 0x04, 0x72, 0x03), 582 PLL_CTL(2048000, 0x07, 583 0x62, 0x04, 0x03, 0xD0, 0x02, 584 0x5B, 0x04, 0x04, 0x72, 0x03), 585 PLL_CTL(2400000, 0x08, 586 0x62, 0x05, 0x03, 0x00, 0x03, 587 0x63, 0x05, 0x05, 0x98, 0x04), 588 }; 589 590 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in) 591 { 592 int i; 593 struct pll_ctl const *pll_ctl = NULL; 594 595 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) 596 if (pll_ctls[i].freq_in == freq_in) { 597 pll_ctl = &pll_ctls[i]; 598 break; 599 } 600 601 return pll_ctl; 602 } 603 604 enum { 605 PLL_INPUT_XTAL = 0, 606 PLL_INPUT_MCLK1, 607 PLL_INPUT_MCLK2, 608 PLL_INPUT_BCLK, 609 }; 610 611 static int set_sysclk(struct snd_soc_component *component) 612 { 613 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 614 struct pll_ctl const *pll_ctl; 615 unsigned long freq; 616 int i; 617 int ret; 618 619 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) 620 freq = clk_get_rate(tscs454->sysclk); 621 else 622 freq = tscs454->bclk_freq; 623 pll_ctl = get_pll_ctl(freq); 624 if (!pll_ctl) { 625 ret = -EINVAL; 626 dev_err(component->dev, 627 "Invalid PLL input %lu (%d)\n", freq, ret); 628 return ret; 629 } 630 631 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { 632 ret = snd_soc_component_write(component, 633 pll_ctl->settings[i].addr, 634 pll_ctl->settings[i].val); 635 if (ret < 0) { 636 dev_err(component->dev, 637 "Failed to set pll setting (%d)\n", 638 ret); 639 return ret; 640 } 641 } 642 643 return 0; 644 } 645 646 static inline void reserve_pll(struct pll *pll) 647 { 648 guard(mutex)(&pll->lock); 649 pll->users++; 650 } 651 652 static inline void free_pll(struct pll *pll) 653 { 654 guard(mutex)(&pll->lock); 655 pll->users--; 656 } 657 658 static int pll_connected(struct snd_soc_dapm_widget *source, 659 struct snd_soc_dapm_widget *sink) 660 { 661 struct snd_soc_component *component = 662 snd_soc_dapm_to_component(source->dapm); 663 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 664 int users; 665 666 if (strstr(source->name, "PLL 1")) { 667 scoped_guard(mutex, &tscs454->pll1.lock) 668 users = tscs454->pll1.users; 669 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__, 670 users); 671 } else { 672 scoped_guard(mutex, &tscs454->pll2.lock) 673 users = tscs454->pll2.users; 674 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__, 675 users); 676 } 677 678 return users; 679 } 680 681 /* 682 * PLL must be enabled after power up and must be disabled before power down 683 * for proper clock switching. 684 */ 685 static int pll_power_event(struct snd_soc_dapm_widget *w, 686 struct snd_kcontrol *kcontrol, int event) 687 { 688 struct snd_soc_component *component = 689 snd_soc_dapm_to_component(w->dapm); 690 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 691 bool enable; 692 bool pll1; 693 unsigned int msk; 694 unsigned int val; 695 int ret; 696 697 if (strstr(w->name, "PLL 1")) 698 pll1 = true; 699 else 700 pll1 = false; 701 702 msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN; 703 704 if (event == SND_SOC_DAPM_POST_PMU) 705 enable = true; 706 else 707 enable = false; 708 709 if (enable) 710 val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE; 711 else 712 /* 713 * FV_PLL1CLKEN_DISABLE and FV_PLL2CLKEN_DISABLE are 714 * identical zero vzalues, there is no need to test 715 * the PLL index 716 */ 717 val = FV_PLL1CLKEN_DISABLE; 718 719 ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val); 720 if (ret < 0) { 721 dev_err(component->dev, "Failed to %s PLL %d (%d)\n", 722 str_enable_disable(enable), pll1 ? 1 : 2, ret); 723 return ret; 724 } 725 726 if (enable) { 727 msleep(20); // Wait for lock 728 ret = coeff_ram_sync(component, tscs454); 729 if (ret < 0) { 730 dev_err(component->dev, 731 "Failed to sync coeff ram (%d)\n", ret); 732 return ret; 733 } 734 } 735 736 return 0; 737 } 738 739 static inline int aif_set_provider(struct snd_soc_component *component, 740 unsigned int aif_id, bool provider) 741 { 742 unsigned int reg; 743 unsigned int mask; 744 unsigned int val; 745 int ret; 746 747 switch (aif_id) { 748 case TSCS454_DAI1_ID: 749 reg = R_I2SP1CTL; 750 break; 751 case TSCS454_DAI2_ID: 752 reg = R_I2SP2CTL; 753 break; 754 case TSCS454_DAI3_ID: 755 reg = R_I2SP3CTL; 756 break; 757 default: 758 ret = -ENODEV; 759 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret); 760 return ret; 761 } 762 mask = FM_I2SPCTL_PORTMS; 763 val = provider ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE; 764 765 ret = snd_soc_component_update_bits(component, reg, mask, val); 766 if (ret < 0) { 767 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n", 768 aif_id, provider ? "provider" : "consumer", ret); 769 return ret; 770 } 771 772 return 0; 773 } 774 775 static inline 776 int aif_prepare(struct snd_soc_component *component, struct aif *aif) 777 { 778 int ret; 779 780 ret = aif_set_provider(component, aif->id, aif->provider); 781 if (ret < 0) 782 return ret; 783 784 return 0; 785 } 786 787 static inline int aif_free(struct snd_soc_component *component, 788 struct aif *aif, bool playback) 789 { 790 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 791 792 guard(mutex)(&tscs454->aifs_status_lock); 793 794 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id); 795 796 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback); 797 798 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n", 799 aif->id, tscs454->aifs_status.streams); 800 801 if (!aif_active(&tscs454->aifs_status, aif->id)) { 802 /* Do config in slave mode */ 803 aif_set_provider(component, aif->id, false); 804 dev_dbg(component->dev, "Freeing pll %d from aif %d\n", 805 aif->pll->id, aif->id); 806 free_pll(aif->pll); 807 } 808 809 if (!aifs_active(&tscs454->aifs_status)) { 810 dev_dbg(component->dev, "Freeing pll %d from ir\n", 811 tscs454->internal_rate.pll->id); 812 free_pll(tscs454->internal_rate.pll); 813 } 814 815 return 0; 816 } 817 818 /* R_PLLCTL PG 0 ADDR 0x15 */ 819 static char const * const bclk_sel_txt[] = { 820 "BCLK 1", "BCLK 2", "BCLK 3"}; 821 822 static struct soc_enum const bclk_sel_enum = 823 SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL, 824 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt); 825 826 /* R_ISRC PG 0 ADDR 0x16 */ 827 static char const * const isrc_br_txt[] = { 828 "44.1kHz", "48kHz"}; 829 830 static struct soc_enum const isrc_br_enum = 831 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR, 832 ARRAY_SIZE(isrc_br_txt), isrc_br_txt); 833 834 static char const * const isrc_bm_txt[] = { 835 "0.25x", "0.5x", "1.0x", "2.0x"}; 836 837 static struct soc_enum const isrc_bm_enum = 838 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM, 839 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt); 840 841 /* R_SCLKCTL PG 0 ADDR 0x18 */ 842 static char const * const modular_rate_txt[] = { 843 "Reserved", "Half", "Full", "Auto",}; 844 845 static struct soc_enum const adc_modular_rate_enum = 846 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM, 847 ARRAY_SIZE(modular_rate_txt), modular_rate_txt); 848 849 static struct soc_enum const dac_modular_rate_enum = 850 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM, 851 ARRAY_SIZE(modular_rate_txt), modular_rate_txt); 852 853 /* R_I2SIDCTL PG 0 ADDR 0x38 */ 854 static char const * const data_ctrl_txt[] = { 855 "L/R", "L/L", "R/R", "R/L"}; 856 857 static struct soc_enum const data_in_ctrl_enums[] = { 858 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL, 859 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 860 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL, 861 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 862 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL, 863 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 864 }; 865 866 /* R_I2SODCTL PG 0 ADDR 0x39 */ 867 static struct soc_enum const data_out_ctrl_enums[] = { 868 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL, 869 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 870 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL, 871 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 872 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL, 873 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 874 }; 875 876 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ 877 static char const * const asrc_mux_txt[] = { 878 "None", "DAI 1", "DAI 2", "DAI 3"}; 879 880 static struct soc_enum const asrc_in_mux_enum = 881 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX, 882 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt); 883 884 static char const * const dai_mux_txt[] = { 885 "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1", 886 "DMic 2", "ClassD", "DAC", "Sub"}; 887 888 static struct soc_enum const dai2_mux_enum = 889 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX, 890 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 891 892 static struct snd_kcontrol_new const dai2_mux_dapm_enum = 893 SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum); 894 895 static struct soc_enum const dai1_mux_enum = 896 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX, 897 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 898 899 static struct snd_kcontrol_new const dai1_mux_dapm_enum = 900 SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum); 901 902 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ 903 static struct soc_enum const asrc_out_mux_enum = 904 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX, 905 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt); 906 907 static struct soc_enum const dac_mux_enum = 908 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX, 909 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 910 911 static struct snd_kcontrol_new const dac_mux_dapm_enum = 912 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum); 913 914 static struct soc_enum const dai3_mux_enum = 915 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX, 916 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 917 918 static struct snd_kcontrol_new const dai3_mux_dapm_enum = 919 SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum); 920 921 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */ 922 static char const * const sub_mux_txt[] = { 923 "CH 0", "CH 1", "CH 0 + 1", 924 "CH 2", "CH 3", "CH 2 + 3", 925 "CH 4", "CH 5", "CH 4 + 5", 926 "ADC/DMic 1 Left", "ADC/DMic 1 Right", 927 "ADC/DMic 1 Left Plus Right", 928 "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right", 929 "ClassD Left", "ClassD Right", "ClassD Left Plus Right"}; 930 931 static struct soc_enum const sub_mux_enum = 932 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX, 933 ARRAY_SIZE(sub_mux_txt), sub_mux_txt); 934 935 static struct snd_kcontrol_new const sub_mux_dapm_enum = 936 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum); 937 938 static struct soc_enum const classd_mux_enum = 939 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX, 940 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 941 942 static struct snd_kcontrol_new const classd_mux_dapm_enum = 943 SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum); 944 945 /* R_HSDCTL1 PG 1 ADDR 0x01 */ 946 static char const * const jack_type_txt[] = { 947 "3 Terminal", "4 Terminal"}; 948 949 static struct soc_enum const hp_jack_type_enum = 950 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE, 951 ARRAY_SIZE(jack_type_txt), jack_type_txt); 952 953 static char const * const hs_det_pol_txt[] = { 954 "Rising", "Falling"}; 955 956 static struct soc_enum const hs_det_pol_enum = 957 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL, 958 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt); 959 960 /* R_HSDCTL1 PG 1 ADDR 0x02 */ 961 static char const * const hs_mic_bias_force_txt[] = { 962 "Off", "Ring", "Sleeve"}; 963 964 static struct soc_enum const hs_mic_bias_force_enum = 965 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1, 966 ARRAY_SIZE(hs_mic_bias_force_txt), 967 hs_mic_bias_force_txt); 968 969 static char const * const plug_type_txt[] = { 970 "OMTP", "CTIA", "Reserved", "Headphone"}; 971 972 static struct soc_enum const plug_type_force_enum = 973 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE, 974 ARRAY_SIZE(plug_type_txt), plug_type_txt); 975 976 977 /* R_CH0AIC PG 1 ADDR 0x06 */ 978 static char const * const in_bst_mux_txt[] = { 979 "Input 1", "Input 2", "Input 3", "D2S"}; 980 981 static struct soc_enum const in_bst_mux_ch0_enum = 982 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL, 983 ARRAY_SIZE(in_bst_mux_txt), 984 in_bst_mux_txt); 985 static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum = 986 SOC_DAPM_ENUM("Input Boost Channel 0 Enum", 987 in_bst_mux_ch0_enum); 988 989 static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0); 990 991 static char const * const adc_mux_txt[] = { 992 "Input 1 Boost Bypass", "Input 2 Boost Bypass", 993 "Input 3 Boost Bypass", "Input Boost"}; 994 995 static struct soc_enum const adc_mux_ch0_enum = 996 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN, 997 ARRAY_SIZE(adc_mux_txt), adc_mux_txt); 998 static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum = 999 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum); 1000 1001 static char const * const in_proc_mux_txt[] = { 1002 "ADC", "DMic"}; 1003 1004 static struct soc_enum const in_proc_ch0_enum = 1005 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S, 1006 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt); 1007 static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum = 1008 SOC_DAPM_ENUM("Input Processor Channel 0 Enum", 1009 in_proc_ch0_enum); 1010 1011 /* R_CH1AIC PG 1 ADDR 0x07 */ 1012 static struct soc_enum const in_bst_mux_ch1_enum = 1013 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR, 1014 ARRAY_SIZE(in_bst_mux_txt), 1015 in_bst_mux_txt); 1016 static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum = 1017 SOC_DAPM_ENUM("Input Boost Channel 1 Enum", 1018 in_bst_mux_ch1_enum); 1019 1020 static struct soc_enum const adc_mux_ch1_enum = 1021 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN, 1022 ARRAY_SIZE(adc_mux_txt), adc_mux_txt); 1023 static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum = 1024 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum); 1025 1026 static struct soc_enum const in_proc_ch1_enum = 1027 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S, 1028 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt); 1029 static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum = 1030 SOC_DAPM_ENUM("Input Processor Channel 1 Enum", 1031 in_proc_ch1_enum); 1032 1033 /* R_ICTL0 PG 1 ADDR 0x0A */ 1034 static char const * const pol_txt[] = { 1035 "Normal", "Invert"}; 1036 1037 static struct soc_enum const in_pol_ch1_enum = 1038 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL, 1039 ARRAY_SIZE(pol_txt), pol_txt); 1040 1041 static struct soc_enum const in_pol_ch0_enum = 1042 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL, 1043 ARRAY_SIZE(pol_txt), pol_txt); 1044 1045 static char const * const in_proc_ch_sel_txt[] = { 1046 "Normal", "Mono Mix to Channel 0", 1047 "Mono Mix to Channel 1", "Add"}; 1048 1049 static struct soc_enum const in_proc_ch01_sel_enum = 1050 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL, 1051 ARRAY_SIZE(in_proc_ch_sel_txt), 1052 in_proc_ch_sel_txt); 1053 1054 /* R_ICTL1 PG 1 ADDR 0x0B */ 1055 static struct soc_enum const in_pol_ch3_enum = 1056 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL, 1057 ARRAY_SIZE(pol_txt), pol_txt); 1058 1059 static struct soc_enum const in_pol_ch2_enum = 1060 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL, 1061 ARRAY_SIZE(pol_txt), pol_txt); 1062 1063 static struct soc_enum const in_proc_ch23_sel_enum = 1064 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL, 1065 ARRAY_SIZE(in_proc_ch_sel_txt), 1066 in_proc_ch_sel_txt); 1067 1068 /* R_MICBIAS PG 1 ADDR 0x0C */ 1069 static char const * const mic_bias_txt[] = { 1070 "2.5V", "2.1V", "1.8V", "Vdd"}; 1071 1072 static struct soc_enum const mic_bias_2_enum = 1073 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2, 1074 ARRAY_SIZE(mic_bias_txt), mic_bias_txt); 1075 1076 static struct soc_enum const mic_bias_1_enum = 1077 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1, 1078 ARRAY_SIZE(mic_bias_txt), mic_bias_txt); 1079 1080 /* R_PGACTL0 PG 1 ADDR 0x0D */ 1081 /* R_PGACTL1 PG 1 ADDR 0x0E */ 1082 /* R_PGACTL2 PG 1 ADDR 0x0F */ 1083 /* R_PGACTL3 PG 1 ADDR 0x10 */ 1084 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0); 1085 1086 /* R_ICH0VOL PG1 ADDR 0x12 */ 1087 /* R_ICH1VOL PG1 ADDR 0x13 */ 1088 /* R_ICH2VOL PG1 ADDR 0x14 */ 1089 /* R_ICH3VOL PG1 ADDR 0x15 */ 1090 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400); 1091 1092 /* R_ASRCILVOL PG1 ADDR 0x16 */ 1093 /* R_ASRCIRVOL PG1 ADDR 0x17 */ 1094 /* R_ASRCOLVOL PG1 ADDR 0x18 */ 1095 /* R_ASRCORVOL PG1 ADDR 0x19 */ 1096 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600); 1097 1098 /* R_ALCCTL0 PG1 ADDR 0x1D */ 1099 static char const * const alc_mode_txt[] = { 1100 "ALC", "Limiter"}; 1101 1102 static struct soc_enum const alc_mode_enum = 1103 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE, 1104 ARRAY_SIZE(alc_mode_txt), alc_mode_txt); 1105 1106 static char const * const alc_ref_text[] = { 1107 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"}; 1108 1109 static struct soc_enum const alc_ref_enum = 1110 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF, 1111 ARRAY_SIZE(alc_ref_text), alc_ref_text); 1112 1113 /* R_ALCCTL1 PG 1 ADDR 0x1E */ 1114 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0); 1115 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0); 1116 1117 /* R_ALCCTL2 PG 1 ADDR 0x1F */ 1118 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0); 1119 1120 /* R_NGATE PG 1 ADDR 0x21 */ 1121 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0); 1122 1123 static char const * const ngate_type_txt[] = { 1124 "PGA Constant", "ADC Mute"}; 1125 1126 static struct soc_enum const ngate_type_enum = 1127 SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG, 1128 ARRAY_SIZE(ngate_type_txt), ngate_type_txt); 1129 1130 /* R_DMICCTL PG 1 ADDR 0x22 */ 1131 static char const * const dmic_mono_sel_txt[] = { 1132 "Stereo", "Mono"}; 1133 1134 static struct soc_enum const dmic_mono_sel_enum = 1135 SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO, 1136 ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt); 1137 1138 /* R_DACCTL PG 2 ADDR 0x01 */ 1139 static struct soc_enum const dac_pol_r_enum = 1140 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR, 1141 ARRAY_SIZE(pol_txt), pol_txt); 1142 1143 static struct soc_enum const dac_pol_l_enum = 1144 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL, 1145 ARRAY_SIZE(pol_txt), pol_txt); 1146 1147 static char const * const dac_dith_txt[] = { 1148 "Half", "Full", "Disabled", "Static"}; 1149 1150 static struct soc_enum const dac_dith_enum = 1151 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH, 1152 ARRAY_SIZE(dac_dith_txt), dac_dith_txt); 1153 1154 /* R_SPKCTL PG 2 ADDR 0x02 */ 1155 static struct soc_enum const spk_pol_r_enum = 1156 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR, 1157 ARRAY_SIZE(pol_txt), pol_txt); 1158 1159 static struct soc_enum const spk_pol_l_enum = 1160 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL, 1161 ARRAY_SIZE(pol_txt), pol_txt); 1162 1163 /* R_SUBCTL PG 2 ADDR 0x03 */ 1164 static struct soc_enum const sub_pol_enum = 1165 SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL, 1166 ARRAY_SIZE(pol_txt), pol_txt); 1167 1168 /* R_MVOLL PG 2 ADDR 0x08 */ 1169 /* R_MVOLR PG 2 ADDR 0x09 */ 1170 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0); 1171 1172 /* R_HPVOLL PG 2 ADDR 0x0A */ 1173 /* R_HPVOLR PG 2 ADDR 0x0B */ 1174 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0); 1175 1176 /* R_SPKVOLL PG 2 ADDR 0x0C */ 1177 /* R_SPKVOLR PG 2 ADDR 0x0D */ 1178 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0); 1179 1180 /* R_SPKEQFILT PG 3 ADDR 0x01 */ 1181 static char const * const eq_txt[] = { 1182 "Pre Scale", 1183 "Pre Scale + EQ Band 0", 1184 "Pre Scale + EQ Band 0 - 1", 1185 "Pre Scale + EQ Band 0 - 2", 1186 "Pre Scale + EQ Band 0 - 3", 1187 "Pre Scale + EQ Band 0 - 4", 1188 "Pre Scale + EQ Band 0 - 5", 1189 }; 1190 1191 static struct soc_enum const spk_eq_enums[] = { 1192 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE, 1193 ARRAY_SIZE(eq_txt), eq_txt), 1194 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE, 1195 ARRAY_SIZE(eq_txt), eq_txt), 1196 }; 1197 1198 /* R_SPKMBCCTL PG 3 ADDR 0x0B */ 1199 static char const * const lvl_mode_txt[] = { 1200 "Average", "Peak"}; 1201 1202 static struct soc_enum const spk_mbc3_lvl_det_mode_enum = 1203 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3, 1204 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1205 1206 static char const * const win_sel_txt[] = { 1207 "512", "64"}; 1208 1209 static struct soc_enum const spk_mbc3_win_sel_enum = 1210 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3, 1211 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1212 1213 static struct soc_enum const spk_mbc2_lvl_det_mode_enum = 1214 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2, 1215 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1216 1217 static struct soc_enum const spk_mbc2_win_sel_enum = 1218 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2, 1219 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1220 1221 static struct soc_enum const spk_mbc1_lvl_det_mode_enum = 1222 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1, 1223 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1224 1225 static struct soc_enum const spk_mbc1_win_sel_enum = 1226 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1, 1227 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1228 1229 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */ 1230 static struct soc_enum const spk_mbc1_phase_pol_enum = 1231 SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE, 1232 ARRAY_SIZE(pol_txt), pol_txt); 1233 1234 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0); 1235 1236 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */ 1237 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0); 1238 1239 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */ 1240 static char const * const comp_rat_txt[] = { 1241 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", 1242 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", 1243 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"}; 1244 1245 static struct soc_enum const spk_mbc1_comp_rat_enum = 1246 SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO, 1247 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1248 1249 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */ 1250 static struct soc_enum const spk_mbc2_phase_pol_enum = 1251 SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE, 1252 ARRAY_SIZE(pol_txt), pol_txt); 1253 1254 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */ 1255 static struct soc_enum const spk_mbc2_comp_rat_enum = 1256 SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO, 1257 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1258 1259 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */ 1260 static struct soc_enum const spk_mbc3_phase_pol_enum = 1261 SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE, 1262 ARRAY_SIZE(pol_txt), pol_txt); 1263 1264 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */ 1265 static struct soc_enum const spk_mbc3_comp_rat_enum = 1266 SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO, 1267 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1268 1269 /* R_SPKCLECTL PG 3 ADDR 0x21 */ 1270 static struct soc_enum const spk_cle_lvl_mode_enum = 1271 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE, 1272 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1273 1274 static struct soc_enum const spk_cle_win_sel_enum = 1275 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL, 1276 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1277 1278 /* R_SPKCLEMUG PG 3 ADDR 0x22 */ 1279 static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650); 1280 1281 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */ 1282 static struct soc_enum const spk_comp_rat_enum = 1283 SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO, 1284 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1285 1286 /* R_SPKEXPTHR PG 3 ADDR 0x2F */ 1287 static char const * const exp_rat_txt[] = { 1288 "Reserved", "Reserved", "1:2", "1:3", 1289 "1:4", "1:5", "1:6", "1:7"}; 1290 1291 static struct soc_enum const spk_exp_rat_enum = 1292 SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO, 1293 ARRAY_SIZE(exp_rat_txt), exp_rat_txt); 1294 1295 /* R_DACEQFILT PG 4 ADDR 0x01 */ 1296 static struct soc_enum const dac_eq_enums[] = { 1297 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE, 1298 ARRAY_SIZE(eq_txt), eq_txt), 1299 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE, 1300 ARRAY_SIZE(eq_txt), eq_txt), 1301 }; 1302 1303 /* R_DACMBCCTL PG 4 ADDR 0x0B */ 1304 static struct soc_enum const dac_mbc3_lvl_det_mode_enum = 1305 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, 1306 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1307 1308 static struct soc_enum const dac_mbc3_win_sel_enum = 1309 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, 1310 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1311 1312 static struct soc_enum const dac_mbc2_lvl_det_mode_enum = 1313 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, 1314 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1315 1316 static struct soc_enum const dac_mbc2_win_sel_enum = 1317 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, 1318 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1319 1320 static struct soc_enum const dac_mbc1_lvl_det_mode_enum = 1321 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, 1322 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1323 1324 static struct soc_enum const dac_mbc1_win_sel_enum = 1325 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, 1326 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1327 1328 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */ 1329 static struct soc_enum const dac_mbc1_phase_pol_enum = 1330 SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE, 1331 ARRAY_SIZE(pol_txt), pol_txt); 1332 1333 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */ 1334 static struct soc_enum const dac_mbc1_comp_rat_enum = 1335 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO, 1336 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1337 1338 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */ 1339 static struct soc_enum const dac_mbc2_phase_pol_enum = 1340 SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE, 1341 ARRAY_SIZE(pol_txt), pol_txt); 1342 1343 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */ 1344 static struct soc_enum const dac_mbc2_comp_rat_enum = 1345 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO, 1346 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1347 1348 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */ 1349 static struct soc_enum const dac_mbc3_phase_pol_enum = 1350 SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE, 1351 ARRAY_SIZE(pol_txt), pol_txt); 1352 1353 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */ 1354 static struct soc_enum const dac_mbc3_comp_rat_enum = 1355 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO, 1356 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1357 1358 /* R_DACCLECTL PG 4 ADDR 0x21 */ 1359 static struct soc_enum const dac_cle_lvl_mode_enum = 1360 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE, 1361 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1362 1363 static struct soc_enum const dac_cle_win_sel_enum = 1364 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL, 1365 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1366 1367 /* R_DACCOMPRAT PG 4 ADDR 0x24 */ 1368 static struct soc_enum const dac_comp_rat_enum = 1369 SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO, 1370 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1371 1372 /* R_DACEXPRAT PG 4 ADDR 0x30 */ 1373 static struct soc_enum const dac_exp_rat_enum = 1374 SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO, 1375 ARRAY_SIZE(exp_rat_txt), exp_rat_txt); 1376 1377 /* R_SUBEQFILT PG 5 ADDR 0x01 */ 1378 static struct soc_enum const sub_eq_enums[] = { 1379 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE, 1380 ARRAY_SIZE(eq_txt), eq_txt), 1381 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE, 1382 ARRAY_SIZE(eq_txt), eq_txt), 1383 }; 1384 1385 /* R_SUBMBCCTL PG 5 ADDR 0x0B */ 1386 static struct soc_enum const sub_mbc3_lvl_det_mode_enum = 1387 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3, 1388 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1389 1390 static struct soc_enum const sub_mbc3_win_sel_enum = 1391 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3, 1392 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1393 1394 static struct soc_enum const sub_mbc2_lvl_det_mode_enum = 1395 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2, 1396 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1397 1398 static struct soc_enum const sub_mbc2_win_sel_enum = 1399 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2, 1400 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1401 1402 static struct soc_enum const sub_mbc1_lvl_det_mode_enum = 1403 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1, 1404 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1405 1406 static struct soc_enum const sub_mbc1_win_sel_enum = 1407 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1, 1408 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1409 1410 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */ 1411 static struct soc_enum const sub_mbc1_phase_pol_enum = 1412 SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE, 1413 ARRAY_SIZE(pol_txt), pol_txt); 1414 1415 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */ 1416 static struct soc_enum const sub_mbc1_comp_rat_enum = 1417 SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO, 1418 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1419 1420 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */ 1421 static struct soc_enum const sub_mbc2_phase_pol_enum = 1422 SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE, 1423 ARRAY_SIZE(pol_txt), pol_txt); 1424 1425 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */ 1426 static struct soc_enum const sub_mbc2_comp_rat_enum = 1427 SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO, 1428 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1429 1430 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */ 1431 static struct soc_enum const sub_mbc3_phase_pol_enum = 1432 SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE, 1433 ARRAY_SIZE(pol_txt), pol_txt); 1434 1435 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */ 1436 static struct soc_enum const sub_mbc3_comp_rat_enum = 1437 SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO, 1438 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1439 1440 /* R_SUBCLECTL PG 5 ADDR 0x21 */ 1441 static struct soc_enum const sub_cle_lvl_mode_enum = 1442 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE, 1443 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1444 static struct soc_enum const sub_cle_win_sel_enum = 1445 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL, 1446 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1447 1448 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */ 1449 static struct soc_enum const sub_comp_rat_enum = 1450 SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO, 1451 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1452 1453 /* R_SUBEXPRAT PG 5 ADDR 0x30 */ 1454 static struct soc_enum const sub_exp_rat_enum = 1455 SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO, 1456 ARRAY_SIZE(exp_rat_txt), exp_rat_txt); 1457 1458 static int bytes_info_ext(struct snd_kcontrol *kcontrol, 1459 struct snd_ctl_elem_info *ucontrol) 1460 { 1461 struct coeff_ram_ctl *ctl = 1462 (struct coeff_ram_ctl *)kcontrol->private_value; 1463 struct soc_bytes_ext *params = &ctl->bytes_ext; 1464 1465 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1466 ucontrol->count = params->max; 1467 1468 return 0; 1469 } 1470 1471 /* CH 0_1 Input Mux */ 1472 static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"}; 1473 1474 static struct soc_enum const ch_0_1_mux_enum = 1475 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 1476 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt); 1477 1478 static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum = 1479 SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum); 1480 1481 /* CH 2_3 Input Mux */ 1482 static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"}; 1483 1484 static struct soc_enum const ch_2_3_mux_enum = 1485 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 1486 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt); 1487 1488 static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum = 1489 SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum); 1490 1491 /* CH 4_5 Input Mux */ 1492 static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"}; 1493 1494 static struct soc_enum const ch_4_5_mux_enum = 1495 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 1496 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt); 1497 1498 static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum = 1499 SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum); 1500 1501 #define COEFF_RAM_CTL(xname, xcount, xaddr) \ 1502 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1503 .info = bytes_info_ext, \ 1504 .get = coeff_ram_get, .put = coeff_ram_put, \ 1505 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ 1506 .addr = xaddr, \ 1507 .bytes_ext = {.max = xcount, }, \ 1508 } \ 1509 } 1510 1511 static struct snd_kcontrol_new const tscs454_snd_controls[] = { 1512 /* R_PLLCTL PG 0 ADDR 0x15 */ 1513 SOC_ENUM("PLL BCLK Input", bclk_sel_enum), 1514 /* R_ISRC PG 0 ADDR 0x16 */ 1515 SOC_ENUM("Internal Rate", isrc_br_enum), 1516 SOC_ENUM("Internal Rate Multiple", isrc_bm_enum), 1517 /* R_SCLKCTL PG 0 ADDR 0x18 */ 1518 SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum), 1519 SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum), 1520 /* R_ASRC PG 0 ADDR 0x28 */ 1521 SOC_SINGLE("ASRC Out High Bandwidth Switch", 1522 R_ASRC, FB_ASRC_ASRCOBW, 1, 0), 1523 SOC_SINGLE("ASRC In High Bandwidth Switch", 1524 R_ASRC, FB_ASRC_ASRCIBW, 1, 0), 1525 /* R_I2SIDCTL PG 0 ADDR 0x38 */ 1526 SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]), 1527 SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]), 1528 SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]), 1529 /* R_I2SODCTL PG 0 ADDR 0x39 */ 1530 SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]), 1531 SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]), 1532 SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]), 1533 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ 1534 SOC_ENUM("ASRC In", asrc_in_mux_enum), 1535 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ 1536 SOC_ENUM("ASRC Out", asrc_out_mux_enum), 1537 /* R_HSDCTL1 PG 1 ADDR 0x01 */ 1538 SOC_ENUM("Headphone Jack Type", hp_jack_type_enum), 1539 SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum), 1540 SOC_SINGLE("Headphone Detection Switch", 1541 R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0), 1542 SOC_SINGLE("Headset OMTP/CTIA Switch", 1543 R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0), 1544 /* R_HSDCTL1 PG 1 ADDR 0x02 */ 1545 SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum), 1546 SOC_SINGLE("Manual Mic Bias Switch", 1547 R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0), 1548 SOC_SINGLE("Ring/Sleeve Auto Switch", 1549 R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0), 1550 SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum), 1551 /* R_CH0AIC PG 1 ADDR 0x06 */ 1552 SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC, 1553 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1554 /* R_CH1AIC PG 1 ADDR 0x07 */ 1555 SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC, 1556 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1557 /* R_CH2AIC PG 1 ADDR 0x08 */ 1558 SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC, 1559 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1560 /* R_CH3AIC PG 1 ADDR 0x09 */ 1561 SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC, 1562 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1563 /* R_ICTL0 PG 1 ADDR 0x0A */ 1564 SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum), 1565 SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum), 1566 SOC_ENUM("Input Processor Channel 0/1 Operation", 1567 in_proc_ch01_sel_enum), 1568 SOC_SINGLE("Input Channel 1 Mute Switch", 1569 R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0), 1570 SOC_SINGLE("Input Channel 0 Mute Switch", 1571 R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0), 1572 SOC_SINGLE("Input Channel 1 HPF Disable Switch", 1573 R_ICTL0, FB_ICTL0_IN1HP, 1, 0), 1574 SOC_SINGLE("Input Channel 0 HPF Disable Switch", 1575 R_ICTL0, FB_ICTL0_IN0HP, 1, 0), 1576 /* R_ICTL1 PG 1 ADDR 0x0B */ 1577 SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum), 1578 SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum), 1579 SOC_ENUM("Input Processor Channel 2/3 Operation", 1580 in_proc_ch23_sel_enum), 1581 SOC_SINGLE("Input Channel 3 Mute Switch", 1582 R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0), 1583 SOC_SINGLE("Input Channel 2 Mute Switch", 1584 R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0), 1585 SOC_SINGLE("Input Channel 3 HPF Disable Switch", 1586 R_ICTL1, FB_ICTL1_IN3HP, 1, 0), 1587 SOC_SINGLE("Input Channel 2 HPF Disable Switch", 1588 R_ICTL1, FB_ICTL1_IN2HP, 1, 0), 1589 /* R_MICBIAS PG 1 ADDR 0x0C */ 1590 SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum), 1591 SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum), 1592 /* R_PGACTL0 PG 1 ADDR 0x0D */ 1593 SOC_SINGLE("Input Channel 0 PGA Mute Switch", 1594 R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0), 1595 SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0, 1596 FB_PGACTL_PGAVOL, 1597 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1598 /* R_PGACTL1 PG 1 ADDR 0x0E */ 1599 SOC_SINGLE("Input Channel 1 PGA Mute Switch", 1600 R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0), 1601 SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1, 1602 FB_PGACTL_PGAVOL, 1603 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1604 /* R_PGACTL2 PG 1 ADDR 0x0F */ 1605 SOC_SINGLE("Input Channel 2 PGA Mute Switch", 1606 R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0), 1607 SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2, 1608 FB_PGACTL_PGAVOL, 1609 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1610 /* R_PGACTL3 PG 1 ADDR 0x10 */ 1611 SOC_SINGLE("Input Channel 3 PGA Mute Switch", 1612 R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0), 1613 SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3, 1614 FB_PGACTL_PGAVOL, 1615 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1616 /* R_ICH0VOL PG 1 ADDR 0x12 */ 1617 SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL, 1618 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1619 /* R_ICH1VOL PG 1 ADDR 0x13 */ 1620 SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL, 1621 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1622 /* R_ICH2VOL PG 1 ADDR 0x14 */ 1623 SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL, 1624 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1625 /* R_ICH3VOL PG 1 ADDR 0x15 */ 1626 SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL, 1627 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1628 /* R_ASRCILVOL PG 1 ADDR 0x16 */ 1629 SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL, 1630 FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL, 1631 0, asrc_vol_tlv_arr), 1632 /* R_ASRCIRVOL PG 1 ADDR 0x17 */ 1633 SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL, 1634 FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL, 1635 0, asrc_vol_tlv_arr), 1636 /* R_ASRCOLVOL PG 1 ADDR 0x18 */ 1637 SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL, 1638 FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL, 1639 0, asrc_vol_tlv_arr), 1640 /* R_ASRCORVOL PG 1 ADDR 0x19 */ 1641 SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL, 1642 FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL, 1643 0, asrc_vol_tlv_arr), 1644 /* R_IVOLCTLU PG 1 ADDR 0x1C */ 1645 /* R_ALCCTL0 PG 1 ADDR 0x1D */ 1646 SOC_ENUM("ALC Mode", alc_mode_enum), 1647 SOC_ENUM("ALC Reference", alc_ref_enum), 1648 SOC_SINGLE("Input Channel 3 ALC Switch", 1649 R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0), 1650 SOC_SINGLE("Input Channel 2 ALC Switch", 1651 R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0), 1652 SOC_SINGLE("Input Channel 1 ALC Switch", 1653 R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0), 1654 SOC_SINGLE("Input Channel 0 ALC Switch", 1655 R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0), 1656 /* R_ALCCTL1 PG 1 ADDR 0x1E */ 1657 SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1, 1658 FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN, 1659 0, alc_max_gain_tlv_arr), 1660 SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1, 1661 FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL, 1662 0, alc_target_tlv_arr), 1663 /* R_ALCCTL2 PG 1 ADDR 0x1F */ 1664 SOC_SINGLE("ALC Zero Cross Switch", 1665 R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0), 1666 SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2, 1667 FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN, 1668 0, alc_min_gain_tlv_arr), 1669 SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2, 1670 FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0), 1671 /* R_ALCCTL3 PG 1 ADDR 0x20 */ 1672 SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3, 1673 FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0), 1674 SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3, 1675 FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0), 1676 /* R_NGATE PG 1 ADDR 0x21 */ 1677 SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE, 1678 FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr), 1679 SOC_ENUM("Noise Gate Type", ngate_type_enum), 1680 SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0), 1681 /* R_DMICCTL PG 1 ADDR 0x22 */ 1682 SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0), 1683 SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0), 1684 SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum), 1685 /* R_DACCTL PG 2 ADDR 0x01 */ 1686 SOC_ENUM("DAC Polarity Left", dac_pol_r_enum), 1687 SOC_ENUM("DAC Polarity Right", dac_pol_l_enum), 1688 SOC_ENUM("DAC Dither", dac_dith_enum), 1689 SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0), 1690 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0), 1691 /* R_SPKCTL PG 2 ADDR 0x02 */ 1692 SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum), 1693 SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum), 1694 SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0), 1695 SOC_SINGLE("Speaker De-Emphasis Switch", 1696 R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0), 1697 /* R_SUBCTL PG 2 ADDR 0x03 */ 1698 SOC_ENUM("Sub Polarity", sub_pol_enum), 1699 SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0), 1700 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0), 1701 /* R_DCCTL PG 2 ADDR 0x04 */ 1702 SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1), 1703 SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1), 1704 SOC_SINGLE("Speaker DC Removal Switch", 1705 R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1), 1706 SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL, 1707 FM_DCCTL_DCCOEFSEL, 0), 1708 /* R_OVOLCTLU PG 2 ADDR 0x06 */ 1709 SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0), 1710 /* R_MVOLL PG 2 ADDR 0x08 */ 1711 /* R_MVOLR PG 2 ADDR 0x09 */ 1712 SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR, 1713 FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr), 1714 /* R_HPVOLL PG 2 ADDR 0x0A */ 1715 /* R_HPVOLR PG 2 ADDR 0x0B */ 1716 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR, 1717 FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0, 1718 hp_vol_tlv_arr), 1719 /* R_SPKVOLL PG 2 ADDR 0x0C */ 1720 /* R_SPKVOLR PG 2 ADDR 0x0D */ 1721 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR, 1722 FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0, 1723 spk_vol_tlv_arr), 1724 /* R_SUBVOL PG 2 ADDR 0x10 */ 1725 SOC_SINGLE_TLV("Sub Volume", R_SUBVOL, 1726 FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr), 1727 /* R_SPKEQFILT PG 3 ADDR 0x01 */ 1728 SOC_SINGLE("Speaker EQ 2 Switch", 1729 R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0), 1730 SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]), 1731 SOC_SINGLE("Speaker EQ 1 Switch", 1732 R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0), 1733 SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]), 1734 /* R_SPKMBCEN PG 3 ADDR 0x0A */ 1735 SOC_SINGLE("Speaker MBC 3 Switch", 1736 R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0), 1737 SOC_SINGLE("Speaker MBC 2 Switch", 1738 R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0), 1739 SOC_SINGLE("Speaker MBC 1 Switch", 1740 R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0), 1741 /* R_SPKMBCCTL PG 3 ADDR 0x0B */ 1742 SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum), 1743 SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum), 1744 SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum), 1745 SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum), 1746 SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum), 1747 SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum), 1748 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */ 1749 SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum), 1750 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1, 1751 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, 1752 0, mbc_mug_tlv_arr), 1753 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */ 1754 SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume", 1755 R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, 1756 0, thr_tlv_arr), 1757 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */ 1758 SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum), 1759 /* R_SPKMBCATK1L PG 3 ADDR 0x0F */ 1760 /* R_SPKMBCATK1H PG 3 ADDR 0x10 */ 1761 SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2), 1762 /* R_SPKMBCREL1L PG 3 ADDR 0x11 */ 1763 /* R_SPKMBCREL1H PG 3 ADDR 0x12 */ 1764 SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2), 1765 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */ 1766 SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum), 1767 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2, 1768 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, 1769 0, mbc_mug_tlv_arr), 1770 /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */ 1771 SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume", 1772 R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, 1773 0, thr_tlv_arr), 1774 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */ 1775 SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum), 1776 /* R_SPKMBCATK2L PG 3 ADDR 0x16 */ 1777 /* R_SPKMBCATK2H PG 3 ADDR 0x17 */ 1778 SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2), 1779 /* R_SPKMBCREL2L PG 3 ADDR 0x18 */ 1780 /* R_SPKMBCREL2H PG 3 ADDR 0x19 */ 1781 SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2), 1782 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */ 1783 SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum), 1784 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3, 1785 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, 1786 0, mbc_mug_tlv_arr), 1787 /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */ 1788 SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3, 1789 FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, 1790 0, thr_tlv_arr), 1791 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */ 1792 SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum), 1793 /* R_SPKMBCATK3L PG 3 ADDR 0x1D */ 1794 /* R_SPKMBCATK3H PG 3 ADDR 0x1E */ 1795 SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3), 1796 /* R_SPKMBCREL3L PG 3 ADDR 0x1F */ 1797 /* R_SPKMBCREL3H PG 3 ADDR 0x20 */ 1798 SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3), 1799 /* R_SPKCLECTL PG 3 ADDR 0x21 */ 1800 SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum), 1801 SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum), 1802 SOC_SINGLE("Speaker CLE Expander Switch", 1803 R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0), 1804 SOC_SINGLE("Speaker CLE Limiter Switch", 1805 R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0), 1806 SOC_SINGLE("Speaker CLE Compressor Switch", 1807 R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0), 1808 /* R_SPKCLEMUG PG 3 ADDR 0x22 */ 1809 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG, 1810 FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN, 1811 0, cle_mug_tlv_arr), 1812 /* R_SPKCOMPTHR PG 3 ADDR 0x23 */ 1813 SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR, 1814 FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH, 1815 0, thr_tlv_arr), 1816 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */ 1817 SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum), 1818 /* R_SPKCOMPATKL PG 3 ADDR 0x25 */ 1819 /* R_SPKCOMPATKH PG 3 ADDR 0x26 */ 1820 SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2), 1821 /* R_SPKCOMPRELL PG 3 ADDR 0x27 */ 1822 /* R_SPKCOMPRELH PG 3 ADDR 0x28 */ 1823 SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2), 1824 /* R_SPKLIMTHR PG 3 ADDR 0x29 */ 1825 SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR, 1826 FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH, 1827 0, thr_tlv_arr), 1828 /* R_SPKLIMTGT PG 3 ADDR 0x2A */ 1829 SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT, 1830 FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET, 1831 0, thr_tlv_arr), 1832 /* R_SPKLIMATKL PG 3 ADDR 0x2B */ 1833 /* R_SPKLIMATKH PG 3 ADDR 0x2C */ 1834 SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2), 1835 /* R_SPKLIMRELL PG 3 ADDR 0x2D */ 1836 /* R_SPKLIMRELR PG 3 ADDR 0x2E */ 1837 SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2), 1838 /* R_SPKEXPTHR PG 3 ADDR 0x2F */ 1839 SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR, 1840 FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH, 1841 0, thr_tlv_arr), 1842 /* R_SPKEXPRAT PG 3 ADDR 0x30 */ 1843 SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum), 1844 /* R_SPKEXPATKL PG 3 ADDR 0x31 */ 1845 /* R_SPKEXPATKR PG 3 ADDR 0x32 */ 1846 SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2), 1847 /* R_SPKEXPRELL PG 3 ADDR 0x33 */ 1848 /* R_SPKEXPRELR PG 3 ADDR 0x34 */ 1849 SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2), 1850 /* R_SPKFXCTL PG 3 ADDR 0x35 */ 1851 SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0), 1852 SOC_SINGLE("Speaker Treble Enhancement Switch", 1853 R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0), 1854 SOC_SINGLE("Speaker Treble NLF Switch", 1855 R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1), 1856 SOC_SINGLE("Speaker Bass Enhancement Switch", 1857 R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0), 1858 SOC_SINGLE("Speaker Bass NLF Switch", 1859 R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1), 1860 /* R_DACEQFILT PG 4 ADDR 0x01 */ 1861 SOC_SINGLE("DAC EQ 2 Switch", 1862 R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0), 1863 SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]), 1864 SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0), 1865 SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]), 1866 /* R_DACMBCEN PG 4 ADDR 0x0A */ 1867 SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), 1868 SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), 1869 SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), 1870 /* R_DACMBCCTL PG 4 ADDR 0x0B */ 1871 SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum), 1872 SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum), 1873 SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum), 1874 SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum), 1875 SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum), 1876 SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum), 1877 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */ 1878 SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum), 1879 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1, 1880 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, 1881 0, mbc_mug_tlv_arr), 1882 /* R_DACMBCTHR1 PG 4 ADDR 0x0D */ 1883 SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1, 1884 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, 1885 0, thr_tlv_arr), 1886 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */ 1887 SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum), 1888 /* R_DACMBCATK1L PG 4 ADDR 0x0F */ 1889 /* R_DACMBCATK1H PG 4 ADDR 0x10 */ 1890 SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2), 1891 /* R_DACMBCREL1L PG 4 ADDR 0x11 */ 1892 /* R_DACMBCREL1H PG 4 ADDR 0x12 */ 1893 SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2), 1894 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */ 1895 SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum), 1896 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2, 1897 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, 1898 0, mbc_mug_tlv_arr), 1899 /* R_DACMBCTHR2 PG 4 ADDR 0x14 */ 1900 SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2, 1901 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, 1902 0, thr_tlv_arr), 1903 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */ 1904 SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum), 1905 /* R_DACMBCATK2L PG 4 ADDR 0x16 */ 1906 /* R_DACMBCATK2H PG 4 ADDR 0x17 */ 1907 SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2), 1908 /* R_DACMBCREL2L PG 4 ADDR 0x18 */ 1909 /* R_DACMBCREL2H PG 4 ADDR 0x19 */ 1910 SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2), 1911 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */ 1912 SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum), 1913 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3, 1914 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, 1915 0, mbc_mug_tlv_arr), 1916 /* R_DACMBCTHR3 PG 4 ADDR 0x1B */ 1917 SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3, 1918 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, 1919 0, thr_tlv_arr), 1920 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */ 1921 SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum), 1922 /* R_DACMBCATK3L PG 4 ADDR 0x1D */ 1923 /* R_DACMBCATK3H PG 4 ADDR 0x1E */ 1924 SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3), 1925 /* R_DACMBCREL3L PG 4 ADDR 0x1F */ 1926 /* R_DACMBCREL3H PG 4 ADDR 0x20 */ 1927 SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3), 1928 /* R_DACCLECTL PG 4 ADDR 0x21 */ 1929 SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum), 1930 SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum), 1931 SOC_SINGLE("DAC CLE Expander Switch", 1932 R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0), 1933 SOC_SINGLE("DAC CLE Limiter Switch", 1934 R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0), 1935 SOC_SINGLE("DAC CLE Compressor Switch", 1936 R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0), 1937 /* R_DACCLEMUG PG 4 ADDR 0x22 */ 1938 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG, 1939 FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN, 1940 0, cle_mug_tlv_arr), 1941 /* R_DACCOMPTHR PG 4 ADDR 0x23 */ 1942 SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR, 1943 FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH, 1944 0, thr_tlv_arr), 1945 /* R_DACCOMPRAT PG 4 ADDR 0x24 */ 1946 SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum), 1947 /* R_DACCOMPATKL PG 4 ADDR 0x25 */ 1948 /* R_DACCOMPATKH PG 4 ADDR 0x26 */ 1949 SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2), 1950 /* R_DACCOMPRELL PG 4 ADDR 0x27 */ 1951 /* R_DACCOMPRELH PG 4 ADDR 0x28 */ 1952 SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2), 1953 /* R_DACLIMTHR PG 4 ADDR 0x29 */ 1954 SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR, 1955 FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH, 1956 0, thr_tlv_arr), 1957 /* R_DACLIMTGT PG 4 ADDR 0x2A */ 1958 SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT, 1959 FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET, 1960 0, thr_tlv_arr), 1961 /* R_DACLIMATKL PG 4 ADDR 0x2B */ 1962 /* R_DACLIMATKH PG 4 ADDR 0x2C */ 1963 SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2), 1964 /* R_DACLIMRELL PG 4 ADDR 0x2D */ 1965 /* R_DACLIMRELR PG 4 ADDR 0x2E */ 1966 SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2), 1967 /* R_DACEXPTHR PG 4 ADDR 0x2F */ 1968 SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR, 1969 FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH, 1970 0, thr_tlv_arr), 1971 /* R_DACEXPRAT PG 4 ADDR 0x30 */ 1972 SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum), 1973 /* R_DACEXPATKL PG 4 ADDR 0x31 */ 1974 /* R_DACEXPATKR PG 4 ADDR 0x32 */ 1975 SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2), 1976 /* R_DACEXPRELL PG 4 ADDR 0x33 */ 1977 /* R_DACEXPRELR PG 4 ADDR 0x34 */ 1978 SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2), 1979 /* R_DACFXCTL PG 4 ADDR 0x35 */ 1980 SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0), 1981 SOC_SINGLE("DAC Treble Enhancement Switch", 1982 R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0), 1983 SOC_SINGLE("DAC Treble NLF Switch", 1984 R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1), 1985 SOC_SINGLE("DAC Bass Enhancement Switch", 1986 R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0), 1987 SOC_SINGLE("DAC Bass NLF Switch", 1988 R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1), 1989 /* R_SUBEQFILT PG 5 ADDR 0x01 */ 1990 SOC_SINGLE("Sub EQ 2 Switch", 1991 R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0), 1992 SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]), 1993 SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0), 1994 SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]), 1995 /* R_SUBMBCEN PG 5 ADDR 0x0A */ 1996 SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0), 1997 SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0), 1998 SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0), 1999 /* R_SUBMBCCTL PG 5 ADDR 0x0B */ 2000 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum), 2001 SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum), 2002 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum), 2003 SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum), 2004 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum), 2005 SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum), 2006 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */ 2007 SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum), 2008 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1, 2009 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, 2010 0, mbc_mug_tlv_arr), 2011 /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */ 2012 SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1, 2013 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, 2014 0, thr_tlv_arr), 2015 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */ 2016 SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum), 2017 /* R_SUBMBCATK1L PG 5 ADDR 0x0F */ 2018 /* R_SUBMBCATK1H PG 5 ADDR 0x10 */ 2019 SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2), 2020 /* R_SUBMBCREL1L PG 5 ADDR 0x11 */ 2021 /* R_SUBMBCREL1H PG 5 ADDR 0x12 */ 2022 SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2), 2023 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */ 2024 SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum), 2025 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2, 2026 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, 2027 0, mbc_mug_tlv_arr), 2028 /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */ 2029 SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2, 2030 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, 2031 0, thr_tlv_arr), 2032 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */ 2033 SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum), 2034 /* R_SUBMBCATK2L PG 5 ADDR 0x16 */ 2035 /* R_SUBMBCATK2H PG 5 ADDR 0x17 */ 2036 SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2), 2037 /* R_SUBMBCREL2L PG 5 ADDR 0x18 */ 2038 /* R_SUBMBCREL2H PG 5 ADDR 0x19 */ 2039 SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2), 2040 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */ 2041 SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum), 2042 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3, 2043 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, 2044 0, mbc_mug_tlv_arr), 2045 /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */ 2046 SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3, 2047 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, 2048 0, thr_tlv_arr), 2049 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */ 2050 SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum), 2051 /* R_SUBMBCATK3L PG 5 ADDR 0x1D */ 2052 /* R_SUBMBCATK3H PG 5 ADDR 0x1E */ 2053 SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3), 2054 /* R_SUBMBCREL3L PG 5 ADDR 0x1F */ 2055 /* R_SUBMBCREL3H PG 5 ADDR 0x20 */ 2056 SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3), 2057 /* R_SUBCLECTL PG 5 ADDR 0x21 */ 2058 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum), 2059 SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum), 2060 SOC_SINGLE("Sub CLE Expander Switch", 2061 R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0), 2062 SOC_SINGLE("Sub CLE Limiter Switch", 2063 R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0), 2064 SOC_SINGLE("Sub CLE Compressor Switch", 2065 R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0), 2066 /* R_SUBCLEMUG PG 5 ADDR 0x22 */ 2067 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG, 2068 FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN, 2069 0, cle_mug_tlv_arr), 2070 /* R_SUBCOMPTHR PG 5 ADDR 0x23 */ 2071 SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR, 2072 FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH, 2073 0, thr_tlv_arr), 2074 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */ 2075 SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum), 2076 /* R_SUBCOMPATKL PG 5 ADDR 0x25 */ 2077 /* R_SUBCOMPATKH PG 5 ADDR 0x26 */ 2078 SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2), 2079 /* R_SUBCOMPRELL PG 5 ADDR 0x27 */ 2080 /* R_SUBCOMPRELH PG 5 ADDR 0x28 */ 2081 SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2), 2082 /* R_SUBLIMTHR PG 5 ADDR 0x29 */ 2083 SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR, 2084 FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH, 2085 0, thr_tlv_arr), 2086 /* R_SUBLIMTGT PG 5 ADDR 0x2A */ 2087 SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT, 2088 FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET, 2089 0, thr_tlv_arr), 2090 /* R_SUBLIMATKL PG 5 ADDR 0x2B */ 2091 /* R_SUBLIMATKH PG 5 ADDR 0x2C */ 2092 SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2), 2093 /* R_SUBLIMRELL PG 5 ADDR 0x2D */ 2094 /* R_SUBLIMRELR PG 5 ADDR 0x2E */ 2095 SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2), 2096 /* R_SUBEXPTHR PG 5 ADDR 0x2F */ 2097 SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR, 2098 FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH, 2099 0, thr_tlv_arr), 2100 /* R_SUBEXPRAT PG 5 ADDR 0x30 */ 2101 SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum), 2102 /* R_SUBEXPATKL PG 5 ADDR 0x31 */ 2103 /* R_SUBEXPATKR PG 5 ADDR 0x32 */ 2104 SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2), 2105 /* R_SUBEXPRELL PG 5 ADDR 0x33 */ 2106 /* R_SUBEXPRELR PG 5 ADDR 0x34 */ 2107 SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2), 2108 /* R_SUBFXCTL PG 5 ADDR 0x35 */ 2109 SOC_SINGLE("Sub Treble Enhancement Switch", 2110 R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0), 2111 SOC_SINGLE("Sub Treble NLF Switch", 2112 R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1), 2113 SOC_SINGLE("Sub Bass Enhancement Switch", 2114 R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0), 2115 SOC_SINGLE("Sub Bass NLF Switch", 2116 R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1), 2117 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), 2118 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), 2119 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), 2120 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), 2121 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), 2122 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), 2123 2124 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), 2125 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), 2126 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), 2127 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), 2128 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), 2129 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), 2130 2131 COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), 2132 COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), 2133 2134 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), 2135 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), 2136 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), 2137 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), 2138 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), 2139 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), 2140 2141 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), 2142 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), 2143 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), 2144 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), 2145 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), 2146 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), 2147 2148 COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), 2149 COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), 2150 2151 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), 2152 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), 2153 2154 COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 2155 COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 2156 2157 COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 2158 2159 COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 2160 2161 COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96), 2162 2163 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), 2164 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), 2165 2166 COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 2167 COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 2168 2169 COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 2170 2171 COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 2172 2173 COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad), 2174 2175 COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae), 2176 2177 COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf), 2178 2179 COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), 2180 COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), 2181 2182 COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), 2183 COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), 2184 2185 COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), 2186 COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), 2187 2188 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), 2189 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), 2190 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), 2191 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), 2192 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), 2193 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), 2194 2195 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), 2196 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), 2197 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), 2198 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), 2199 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), 2200 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), 2201 2202 COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), 2203 COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), 2204 2205 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), 2206 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), 2207 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), 2208 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), 2209 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), 2210 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), 2211 2212 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), 2213 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), 2214 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), 2215 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), 2216 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), 2217 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), 2218 2219 COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), 2220 COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), 2221 2222 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), 2223 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), 2224 2225 COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 2226 COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 2227 2228 COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 2229 2230 COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 2231 2232 COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96), 2233 2234 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), 2235 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), 2236 2237 COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 2238 COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 2239 2240 COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 2241 2242 COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 2243 2244 COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad), 2245 2246 COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae), 2247 2248 COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf), 2249 2250 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), 2251 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), 2252 2253 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), 2254 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), 2255 2256 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), 2257 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), 2258 2259 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), 2260 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), 2261 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), 2262 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), 2263 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), 2264 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), 2265 2266 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), 2267 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), 2268 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), 2269 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), 2270 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), 2271 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), 2272 2273 COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), 2274 COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), 2275 2276 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), 2277 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), 2278 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), 2279 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), 2280 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), 2281 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), 2282 2283 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), 2284 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), 2285 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), 2286 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), 2287 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), 2288 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), 2289 2290 COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), 2291 COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), 2292 2293 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), 2294 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), 2295 2296 COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 2297 COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 2298 2299 COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 2300 2301 COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 2302 2303 COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96), 2304 2305 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), 2306 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), 2307 2308 COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 2309 COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 2310 2311 COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 2312 2313 COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 2314 2315 COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad), 2316 2317 COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae), 2318 2319 COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf), 2320 2321 COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), 2322 COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), 2323 2324 COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), 2325 COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), 2326 2327 COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), 2328 COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), 2329 }; 2330 2331 static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = { 2332 /* R_PLLCTL PG 0 ADDR 0x15 */ 2333 SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0, 2334 pll_power_event, 2335 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 2336 SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0, 2337 pll_power_event, 2338 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 2339 /* R_I2SPINC0 PG 0 ADDR 0x22 */ 2340 SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0, 2341 R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1), 2342 SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0, 2343 R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1), 2344 SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0, 2345 R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1), 2346 /* R_PWRM0 PG 0 ADDR 0x33 */ 2347 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL, 2348 R_PWRM0, FB_PWRM0_INPROC3PU, 0), 2349 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL, 2350 R_PWRM0, FB_PWRM0_INPROC2PU, 0), 2351 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL, 2352 R_PWRM0, FB_PWRM0_INPROC1PU, 0), 2353 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL, 2354 R_PWRM0, FB_PWRM0_INPROC0PU, 0), 2355 SND_SOC_DAPM_SUPPLY("Mic Bias 2", 2356 R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0), 2357 SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0, 2358 FB_PWRM0_MICB1PU, 0, NULL, 0), 2359 /* R_PWRM1 PG 0 ADDR 0x34 */ 2360 SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0), 2361 SND_SOC_DAPM_SUPPLY("Headphone Left Power", 2362 R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0), 2363 SND_SOC_DAPM_SUPPLY("Headphone Right Power", 2364 R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0), 2365 SND_SOC_DAPM_SUPPLY("Speaker Left Power", 2366 R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0), 2367 SND_SOC_DAPM_SUPPLY("Speaker Right Power", 2368 R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0), 2369 SND_SOC_DAPM_SUPPLY("Differential Input 2 Power", 2370 R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0), 2371 SND_SOC_DAPM_SUPPLY("Differential Input 1 Power", 2372 R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0), 2373 /* R_PWRM2 PG 0 ADDR 0x35 */ 2374 SND_SOC_DAPM_SUPPLY("DAI 3 Out Power", 2375 R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0), 2376 SND_SOC_DAPM_SUPPLY("DAI 2 Out Power", 2377 R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0), 2378 SND_SOC_DAPM_SUPPLY("DAI 1 Out Power", 2379 R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0), 2380 SND_SOC_DAPM_SUPPLY("DAI 3 In Power", 2381 R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0), 2382 SND_SOC_DAPM_SUPPLY("DAI 2 In Power", 2383 R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0), 2384 SND_SOC_DAPM_SUPPLY("DAI 1 In Power", 2385 R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0), 2386 /* R_PWRM3 PG 0 ADDR 0x36 */ 2387 SND_SOC_DAPM_SUPPLY("Line Out Left Power", 2388 R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0), 2389 SND_SOC_DAPM_SUPPLY("Line Out Right Power", 2390 R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0), 2391 /* R_PWRM4 PG 0 ADDR 0x37 */ 2392 SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0), 2393 SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0), 2394 SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0), 2395 SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0), 2396 SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0), 2397 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ 2398 SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0, 2399 &dai2_mux_dapm_enum), 2400 SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0, 2401 &dai1_mux_dapm_enum), 2402 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ 2403 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0, 2404 &dac_mux_dapm_enum), 2405 SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0, 2406 &dai3_mux_dapm_enum), 2407 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */ 2408 SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0, 2409 &sub_mux_dapm_enum), 2410 SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0, 2411 &classd_mux_dapm_enum), 2412 /* R_HSDCTL1 PG 1 ADDR 0x01 */ 2413 SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1, 2414 FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0), 2415 /* R_CH0AIC PG 1 ADDR 0x06 */ 2416 SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0, 2417 &in_bst_mux_ch0_dapm_enum), 2418 SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0, 2419 &adc_mux_ch0_dapm_enum), 2420 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0, 2421 &in_proc_mux_ch0_dapm_enum), 2422 /* R_CH1AIC PG 1 ADDR 0x07 */ 2423 SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0, 2424 &in_bst_mux_ch1_dapm_enum), 2425 SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0, 2426 &adc_mux_ch1_dapm_enum), 2427 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0, 2428 &in_proc_mux_ch1_dapm_enum), 2429 /* Virtual */ 2430 SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0, 2431 SND_SOC_NOPM, 0, 0), 2432 SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0, 2433 SND_SOC_NOPM, 0, 0), 2434 SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0, 2435 SND_SOC_NOPM, 0, 0), 2436 SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0), 2437 SND_SOC_DAPM_OUTPUT("Sub Out"), 2438 SND_SOC_DAPM_OUTPUT("Headphone Left"), 2439 SND_SOC_DAPM_OUTPUT("Headphone Right"), 2440 SND_SOC_DAPM_OUTPUT("Speaker Left"), 2441 SND_SOC_DAPM_OUTPUT("Speaker Right"), 2442 SND_SOC_DAPM_OUTPUT("Line Out Left"), 2443 SND_SOC_DAPM_OUTPUT("Line Out Right"), 2444 SND_SOC_DAPM_INPUT("D2S 2"), 2445 SND_SOC_DAPM_INPUT("D2S 1"), 2446 SND_SOC_DAPM_INPUT("Line In 1 Left"), 2447 SND_SOC_DAPM_INPUT("Line In 1 Right"), 2448 SND_SOC_DAPM_INPUT("Line In 2 Left"), 2449 SND_SOC_DAPM_INPUT("Line In 2 Right"), 2450 SND_SOC_DAPM_INPUT("Line In 3 Left"), 2451 SND_SOC_DAPM_INPUT("Line In 3 Right"), 2452 SND_SOC_DAPM_INPUT("DMic 1"), 2453 SND_SOC_DAPM_INPUT("DMic 2"), 2454 2455 SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0, 2456 &ch_0_1_mux_dapm_enum), 2457 SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0, 2458 &ch_2_3_mux_dapm_enum), 2459 SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0, 2460 &ch_4_5_mux_dapm_enum), 2461 }; 2462 2463 static struct snd_soc_dapm_route const tscs454_intercon[] = { 2464 /* PLLs */ 2465 {"PLLs", NULL, "PLL 1 Power", pll_connected}, 2466 {"PLLs", NULL, "PLL 2 Power", pll_connected}, 2467 /* Inputs */ 2468 {"DAI 3 In", NULL, "DAI 3 In Power"}, 2469 {"DAI 2 In", NULL, "DAI 2 In Power"}, 2470 {"DAI 1 In", NULL, "DAI 1 In Power"}, 2471 /* Outputs */ 2472 {"DAI 3 Out", NULL, "DAI 3 Out Power"}, 2473 {"DAI 2 Out", NULL, "DAI 2 Out Power"}, 2474 {"DAI 1 Out", NULL, "DAI 1 Out Power"}, 2475 /* Ch Muxing */ 2476 {"CH 0_1 Mux", "DAI 1", "DAI 1 In"}, 2477 {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"}, 2478 {"CH 2_3 Mux", "DAI 2", "DAI 2 In"}, 2479 {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"}, 2480 {"CH 4_5 Mux", "DAI 3", "DAI 2 In"}, 2481 {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"}, 2482 /* In/Out Muxing */ 2483 {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"}, 2484 {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"}, 2485 {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"}, 2486 {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"}, 2487 {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"}, 2488 {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"}, 2489 {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"}, 2490 {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"}, 2491 {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"}, 2492 /****************** 2493 * Playback Paths * 2494 ******************/ 2495 /* DAC Path */ 2496 {"DAC Mux", "CH 4_5", "CH 4_5 Mux"}, 2497 {"DAC Mux", "CH 2_3", "CH 2_3 Mux"}, 2498 {"DAC Mux", "CH 0_1", "CH 0_1 Mux"}, 2499 {"DAC Left", NULL, "DAC Mux"}, 2500 {"DAC Right", NULL, "DAC Mux"}, 2501 {"DAC Left", NULL, "PLLs"}, 2502 {"DAC Right", NULL, "PLLs"}, 2503 {"Headphone Left", NULL, "Headphone Left Power"}, 2504 {"Headphone Right", NULL, "Headphone Right Power"}, 2505 {"Headphone Left", NULL, "DAC Left"}, 2506 {"Headphone Right", NULL, "DAC Right"}, 2507 /* Line Out */ 2508 {"Line Out Left", NULL, "Line Out Left Power"}, 2509 {"Line Out Right", NULL, "Line Out Right Power"}, 2510 {"Line Out Left", NULL, "DAC Left"}, 2511 {"Line Out Right", NULL, "DAC Right"}, 2512 /* ClassD Path */ 2513 {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"}, 2514 {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"}, 2515 {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"}, 2516 {"ClassD Left", NULL, "Speaker Mux"}, 2517 {"ClassD Right", NULL, "Speaker Mux"}, 2518 {"ClassD Left", NULL, "PLLs"}, 2519 {"ClassD Right", NULL, "PLLs"}, 2520 {"Speaker Left", NULL, "Speaker Left Power"}, 2521 {"Speaker Right", NULL, "Speaker Right Power"}, 2522 {"Speaker Left", NULL, "ClassD Left"}, 2523 {"Speaker Right", NULL, "ClassD Right"}, 2524 /* Sub Path */ 2525 {"Sub Mux", "CH 4", "CH 4_5 Mux"}, 2526 {"Sub Mux", "CH 5", "CH 4_5 Mux"}, 2527 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"}, 2528 {"Sub Mux", "CH 2", "CH 2_3 Mux"}, 2529 {"Sub Mux", "CH 3", "CH 2_3 Mux"}, 2530 {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"}, 2531 {"Sub Mux", "CH 0", "CH 0_1 Mux"}, 2532 {"Sub Mux", "CH 1", "CH 0_1 Mux"}, 2533 {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"}, 2534 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"}, 2535 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"}, 2536 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"}, 2537 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"}, 2538 {"Sub Mux", "DMic 2 Left", "DMic 2"}, 2539 {"Sub Mux", "DMic 2 Right", "DMic 2"}, 2540 {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"}, 2541 {"Sub Mux", "ClassD Left", "ClassD Left"}, 2542 {"Sub Mux", "ClassD Right", "ClassD Right"}, 2543 {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"}, 2544 {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"}, 2545 {"Sub", NULL, "Sub Mux"}, 2546 {"Sub", NULL, "PLLs"}, 2547 {"Sub Out", NULL, "Sub Power"}, 2548 {"Sub Out", NULL, "Sub"}, 2549 /***************** 2550 * Capture Paths * 2551 *****************/ 2552 {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"}, 2553 {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"}, 2554 {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"}, 2555 {"Input Boost Channel 0 Mux", "D2S", "D2S 1"}, 2556 2557 {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"}, 2558 {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"}, 2559 {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"}, 2560 {"Input Boost Channel 1 Mux", "D2S", "D2S 2"}, 2561 2562 {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"}, 2563 {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"}, 2564 {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"}, 2565 {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"}, 2566 2567 {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"}, 2568 {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"}, 2569 {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"}, 2570 {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"}, 2571 2572 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"}, 2573 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"}, 2574 2575 {"Input Processor Channel 0", NULL, "PLLs"}, 2576 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"}, 2577 2578 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"}, 2579 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"}, 2580 2581 {"Input Processor Channel 1", NULL, "PLLs"}, 2582 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"}, 2583 2584 {"Input Processor Channel 2", NULL, "PLLs"}, 2585 {"Input Processor Channel 2", NULL, "DMic 2"}, 2586 2587 {"Input Processor Channel 3", NULL, "PLLs"}, 2588 {"Input Processor Channel 3", NULL, "DMic 2"}, 2589 2590 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, 2591 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, 2592 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"}, 2593 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"}, 2594 2595 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, 2596 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, 2597 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"}, 2598 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"}, 2599 2600 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, 2601 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, 2602 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"}, 2603 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"}, 2604 2605 {"DAI 1 Out", NULL, "DAI 1 Out Mux"}, 2606 {"DAI 2 Out", NULL, "DAI 2 Out Mux"}, 2607 {"DAI 3 Out", NULL, "DAI 3 Out Mux"}, 2608 }; 2609 2610 /* This is used when BCLK is sourcing the PLLs */ 2611 static int tscs454_set_sysclk(struct snd_soc_dai *dai, 2612 int clk_id, unsigned int freq, int dir) 2613 { 2614 struct snd_soc_component *component = dai->component; 2615 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 2616 unsigned int val; 2617 int bclk_dai; 2618 2619 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq); 2620 2621 val = snd_soc_component_read(component, R_PLLCTL); 2622 2623 bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL; 2624 if (bclk_dai != dai->id) 2625 return 0; 2626 2627 tscs454->bclk_freq = freq; 2628 return set_sysclk(component); 2629 } 2630 2631 static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai, 2632 unsigned int ratio) 2633 { 2634 unsigned int mask; 2635 int ret; 2636 struct snd_soc_component *component = dai->component; 2637 unsigned int val; 2638 int shift; 2639 2640 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n", 2641 dai->id, ratio); 2642 2643 switch (dai->id) { 2644 case TSCS454_DAI1_ID: 2645 mask = FM_I2SCMC_BCMP1; 2646 shift = FB_I2SCMC_BCMP1; 2647 break; 2648 case TSCS454_DAI2_ID: 2649 mask = FM_I2SCMC_BCMP2; 2650 shift = FB_I2SCMC_BCMP2; 2651 break; 2652 case TSCS454_DAI3_ID: 2653 mask = FM_I2SCMC_BCMP3; 2654 shift = FB_I2SCMC_BCMP3; 2655 break; 2656 default: 2657 ret = -EINVAL; 2658 dev_err(component->dev, "Unknown audio interface (%d)\n", ret); 2659 return ret; 2660 } 2661 2662 switch (ratio) { 2663 case 32: 2664 val = I2SCMC_BCMP_32X; 2665 break; 2666 case 40: 2667 val = I2SCMC_BCMP_40X; 2668 break; 2669 case 64: 2670 val = I2SCMC_BCMP_64X; 2671 break; 2672 default: 2673 ret = -EINVAL; 2674 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); 2675 return ret; 2676 } 2677 2678 ret = snd_soc_component_update_bits(component, 2679 R_I2SCMC, mask, val << shift); 2680 if (ret < 0) { 2681 dev_err(component->dev, 2682 "Failed to set DAI BCLK ratio (%d)\n", ret); 2683 return ret; 2684 } 2685 2686 return 0; 2687 } 2688 2689 static inline int set_aif_provider_from_fmt(struct snd_soc_component *component, 2690 struct aif *aif, unsigned int fmt) 2691 { 2692 int ret; 2693 2694 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2695 case SND_SOC_DAIFMT_CBP_CFP: 2696 aif->provider = true; 2697 break; 2698 case SND_SOC_DAIFMT_CBC_CFC: 2699 aif->provider = false; 2700 break; 2701 default: 2702 ret = -EINVAL; 2703 dev_err(component->dev, "Unsupported format (%d)\n", ret); 2704 return ret; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static inline int set_aif_tdm_delay(struct snd_soc_component *component, 2711 unsigned int dai_id, bool delay) 2712 { 2713 unsigned int reg; 2714 int ret; 2715 2716 switch (dai_id) { 2717 case TSCS454_DAI1_ID: 2718 reg = R_TDMCTL0; 2719 break; 2720 case TSCS454_DAI2_ID: 2721 reg = R_PCMP2CTL0; 2722 break; 2723 case TSCS454_DAI3_ID: 2724 reg = R_PCMP3CTL0; 2725 break; 2726 default: 2727 ret = -EINVAL; 2728 dev_err(component->dev, 2729 "DAI %d unknown (%d)\n", dai_id + 1, ret); 2730 return ret; 2731 } 2732 ret = snd_soc_component_update_bits(component, 2733 reg, FM_TDMCTL0_BDELAY, delay); 2734 if (ret < 0) { 2735 dev_err(component->dev, "Failed to setup tdm format (%d)\n", 2736 ret); 2737 return ret; 2738 } 2739 2740 return 0; 2741 } 2742 2743 static inline int set_aif_format_from_fmt(struct snd_soc_component *component, 2744 unsigned int dai_id, unsigned int fmt) 2745 { 2746 unsigned int reg; 2747 unsigned int val; 2748 int ret; 2749 2750 switch (dai_id) { 2751 case TSCS454_DAI1_ID: 2752 reg = R_I2SP1CTL; 2753 break; 2754 case TSCS454_DAI2_ID: 2755 reg = R_I2SP2CTL; 2756 break; 2757 case TSCS454_DAI3_ID: 2758 reg = R_I2SP3CTL; 2759 break; 2760 default: 2761 ret = -EINVAL; 2762 dev_err(component->dev, 2763 "DAI %d unknown (%d)\n", dai_id + 1, ret); 2764 return ret; 2765 } 2766 2767 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2768 case SND_SOC_DAIFMT_RIGHT_J: 2769 val = FV_FORMAT_RIGHT; 2770 break; 2771 case SND_SOC_DAIFMT_LEFT_J: 2772 val = FV_FORMAT_LEFT; 2773 break; 2774 case SND_SOC_DAIFMT_I2S: 2775 val = FV_FORMAT_I2S; 2776 break; 2777 case SND_SOC_DAIFMT_DSP_A: 2778 ret = set_aif_tdm_delay(component, dai_id, true); 2779 if (ret < 0) 2780 return ret; 2781 val = FV_FORMAT_TDM; 2782 break; 2783 case SND_SOC_DAIFMT_DSP_B: 2784 ret = set_aif_tdm_delay(component, dai_id, false); 2785 if (ret < 0) 2786 return ret; 2787 val = FV_FORMAT_TDM; 2788 break; 2789 default: 2790 ret = -EINVAL; 2791 dev_err(component->dev, "Format unsupported (%d)\n", ret); 2792 return ret; 2793 } 2794 2795 ret = snd_soc_component_update_bits(component, 2796 reg, FM_I2SPCTL_FORMAT, val); 2797 if (ret < 0) { 2798 dev_err(component->dev, "Failed to set DAI %d format (%d)\n", 2799 dai_id + 1, ret); 2800 return ret; 2801 } 2802 2803 return 0; 2804 } 2805 2806 static inline int 2807 set_aif_clock_format_from_fmt(struct snd_soc_component *component, 2808 unsigned int dai_id, unsigned int fmt) 2809 { 2810 unsigned int reg; 2811 unsigned int val; 2812 int ret; 2813 2814 switch (dai_id) { 2815 case TSCS454_DAI1_ID: 2816 reg = R_I2SP1CTL; 2817 break; 2818 case TSCS454_DAI2_ID: 2819 reg = R_I2SP2CTL; 2820 break; 2821 case TSCS454_DAI3_ID: 2822 reg = R_I2SP3CTL; 2823 break; 2824 default: 2825 ret = -EINVAL; 2826 dev_err(component->dev, 2827 "DAI %d unknown (%d)\n", dai_id + 1, ret); 2828 return ret; 2829 } 2830 2831 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2832 case SND_SOC_DAIFMT_NB_NF: 2833 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED; 2834 break; 2835 case SND_SOC_DAIFMT_NB_IF: 2836 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED; 2837 break; 2838 case SND_SOC_DAIFMT_IB_NF: 2839 val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED; 2840 break; 2841 case SND_SOC_DAIFMT_IB_IF: 2842 val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED; 2843 break; 2844 default: 2845 ret = -EINVAL; 2846 dev_err(component->dev, "Format unknown (%d)\n", ret); 2847 return ret; 2848 } 2849 2850 ret = snd_soc_component_update_bits(component, reg, 2851 FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val); 2852 if (ret < 0) { 2853 dev_err(component->dev, 2854 "Failed to set clock polarity for DAI%d (%d)\n", 2855 dai_id + 1, ret); 2856 return ret; 2857 } 2858 2859 return 0; 2860 } 2861 2862 static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2863 { 2864 struct snd_soc_component *component = dai->component; 2865 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 2866 struct aif *aif = &tscs454->aifs[dai->id]; 2867 int ret; 2868 2869 ret = set_aif_provider_from_fmt(component, aif, fmt); 2870 if (ret < 0) 2871 return ret; 2872 2873 ret = set_aif_format_from_fmt(component, dai->id, fmt); 2874 if (ret < 0) 2875 return ret; 2876 2877 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt); 2878 if (ret < 0) 2879 return ret; 2880 2881 return 0; 2882 } 2883 2884 static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai, 2885 unsigned int tx_mask, unsigned int rx_mask, int slots, 2886 int slot_width) 2887 { 2888 struct snd_soc_component *component = dai->component; 2889 unsigned int val; 2890 int ret; 2891 2892 if (!slots) 2893 return 0; 2894 2895 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) { 2896 ret = -EINVAL; 2897 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); 2898 return ret; 2899 } 2900 2901 switch (slots) { 2902 case 2: 2903 val = FV_TDMSO_2 | FV_TDMSI_2; 2904 break; 2905 case 4: 2906 val = FV_TDMSO_4 | FV_TDMSI_4; 2907 break; 2908 case 6: 2909 val = FV_TDMSO_6 | FV_TDMSI_6; 2910 break; 2911 default: 2912 ret = -EINVAL; 2913 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); 2914 return ret; 2915 } 2916 2917 switch (slot_width) { 2918 case 16: 2919 val = val | FV_TDMDSS_16; 2920 break; 2921 case 24: 2922 val = val | FV_TDMDSS_24; 2923 break; 2924 case 32: 2925 val = val | FV_TDMDSS_32; 2926 break; 2927 default: 2928 ret = -EINVAL; 2929 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); 2930 return ret; 2931 } 2932 ret = snd_soc_component_write(component, R_TDMCTL1, val); 2933 if (ret < 0) { 2934 dev_err(component->dev, "Failed to set slots (%d)\n", ret); 2935 return ret; 2936 } 2937 2938 return 0; 2939 } 2940 2941 static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai, 2942 unsigned int tx_mask, unsigned int rx_mask, int slots, 2943 int slot_width) 2944 { 2945 struct snd_soc_component *component = dai->component; 2946 unsigned int reg; 2947 unsigned int val; 2948 int ret; 2949 2950 if (!slots) 2951 return 0; 2952 2953 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) { 2954 ret = -EINVAL; 2955 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); 2956 return ret; 2957 } 2958 2959 switch (dai->id) { 2960 case TSCS454_DAI2_ID: 2961 reg = R_PCMP2CTL1; 2962 break; 2963 case TSCS454_DAI3_ID: 2964 reg = R_PCMP3CTL1; 2965 break; 2966 default: 2967 ret = -EINVAL; 2968 dev_err(component->dev, "Unrecognized interface %d (%d)\n", 2969 dai->id, ret); 2970 return ret; 2971 } 2972 2973 switch (slots) { 2974 case 1: 2975 val = FV_PCMSOP_1 | FV_PCMSIP_1; 2976 break; 2977 case 2: 2978 val = FV_PCMSOP_2 | FV_PCMSIP_2; 2979 break; 2980 default: 2981 ret = -EINVAL; 2982 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); 2983 return ret; 2984 } 2985 2986 switch (slot_width) { 2987 case 16: 2988 val = val | FV_PCMDSSP_16; 2989 break; 2990 case 24: 2991 val = val | FV_PCMDSSP_24; 2992 break; 2993 case 32: 2994 val = val | FV_PCMDSSP_32; 2995 break; 2996 default: 2997 ret = -EINVAL; 2998 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); 2999 return ret; 3000 } 3001 ret = snd_soc_component_write(component, reg, val); 3002 if (ret < 0) { 3003 dev_err(component->dev, "Failed to set slots (%d)\n", ret); 3004 return ret; 3005 } 3006 3007 return 0; 3008 } 3009 3010 static int set_aif_fs(struct snd_soc_component *component, 3011 unsigned int id, 3012 unsigned int rate) 3013 { 3014 unsigned int reg; 3015 unsigned int br; 3016 unsigned int bm; 3017 int ret; 3018 3019 switch (rate) { 3020 case 8000: 3021 br = FV_I2SMBR_32; 3022 bm = FV_I2SMBM_0PT25; 3023 break; 3024 case 16000: 3025 br = FV_I2SMBR_32; 3026 bm = FV_I2SMBM_0PT5; 3027 break; 3028 case 24000: 3029 br = FV_I2SMBR_48; 3030 bm = FV_I2SMBM_0PT5; 3031 break; 3032 case 32000: 3033 br = FV_I2SMBR_32; 3034 bm = FV_I2SMBM_1; 3035 break; 3036 case 48000: 3037 br = FV_I2SMBR_48; 3038 bm = FV_I2SMBM_1; 3039 break; 3040 case 96000: 3041 br = FV_I2SMBR_48; 3042 bm = FV_I2SMBM_2; 3043 break; 3044 case 11025: 3045 br = FV_I2SMBR_44PT1; 3046 bm = FV_I2SMBM_0PT25; 3047 break; 3048 case 22050: 3049 br = FV_I2SMBR_44PT1; 3050 bm = FV_I2SMBM_0PT5; 3051 break; 3052 case 44100: 3053 br = FV_I2SMBR_44PT1; 3054 bm = FV_I2SMBM_1; 3055 break; 3056 case 88200: 3057 br = FV_I2SMBR_44PT1; 3058 bm = FV_I2SMBM_2; 3059 break; 3060 default: 3061 ret = -EINVAL; 3062 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret); 3063 return ret; 3064 } 3065 3066 switch (id) { 3067 case TSCS454_DAI1_ID: 3068 reg = R_I2S1MRATE; 3069 break; 3070 case TSCS454_DAI2_ID: 3071 reg = R_I2S2MRATE; 3072 break; 3073 case TSCS454_DAI3_ID: 3074 reg = R_I2S3MRATE; 3075 break; 3076 default: 3077 ret = -EINVAL; 3078 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret); 3079 return ret; 3080 } 3081 3082 ret = snd_soc_component_update_bits(component, reg, 3083 FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm); 3084 if (ret < 0) { 3085 dev_err(component->dev, 3086 "Failed to update register (%d)\n", ret); 3087 return ret; 3088 } 3089 3090 return 0; 3091 } 3092 3093 static int set_aif_sample_format(struct snd_soc_component *component, 3094 snd_pcm_format_t format, 3095 int aif_id) 3096 { 3097 unsigned int reg; 3098 unsigned int width; 3099 int ret; 3100 3101 switch (snd_pcm_format_width(format)) { 3102 case 16: 3103 width = FV_WL_16; 3104 break; 3105 case 20: 3106 width = FV_WL_20; 3107 break; 3108 case 24: 3109 width = FV_WL_24; 3110 break; 3111 case 32: 3112 width = FV_WL_32; 3113 break; 3114 default: 3115 ret = -EINVAL; 3116 dev_err(component->dev, "Unsupported format width (%d)\n", ret); 3117 return ret; 3118 } 3119 3120 switch (aif_id) { 3121 case TSCS454_DAI1_ID: 3122 reg = R_I2SP1CTL; 3123 break; 3124 case TSCS454_DAI2_ID: 3125 reg = R_I2SP2CTL; 3126 break; 3127 case TSCS454_DAI3_ID: 3128 reg = R_I2SP3CTL; 3129 break; 3130 default: 3131 ret = -EINVAL; 3132 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret); 3133 return ret; 3134 } 3135 3136 ret = snd_soc_component_update_bits(component, 3137 reg, FM_I2SPCTL_WL, width); 3138 if (ret < 0) { 3139 dev_err(component->dev, 3140 "Failed to set sample width (%d)\n", ret); 3141 return ret; 3142 } 3143 3144 return 0; 3145 } 3146 3147 static int tscs454_hw_params(struct snd_pcm_substream *substream, 3148 struct snd_pcm_hw_params *params, 3149 struct snd_soc_dai *dai) 3150 { 3151 struct snd_soc_component *component = dai->component; 3152 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3153 unsigned int fs = params_rate(params); 3154 struct aif *aif = &tscs454->aifs[dai->id]; 3155 unsigned int val; 3156 int ret; 3157 3158 guard(mutex)(&tscs454->aifs_status_lock); 3159 3160 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__, 3161 aif->id, fs); 3162 3163 if (!aif_active(&tscs454->aifs_status, aif->id)) { 3164 if (PLL_44_1K_RATE % fs) 3165 aif->pll = &tscs454->pll1; 3166 else 3167 aif->pll = &tscs454->pll2; 3168 3169 dev_dbg(component->dev, "Reserving pll %d for aif %d\n", 3170 aif->pll->id, aif->id); 3171 3172 reserve_pll(aif->pll); 3173 } 3174 3175 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */ 3176 val = snd_soc_component_read(component, R_ISRC); 3177 if ((val & FM_ISRC_IBR) == FV_IBR_48) 3178 tscs454->internal_rate.pll = &tscs454->pll1; 3179 else 3180 tscs454->internal_rate.pll = &tscs454->pll2; 3181 3182 dev_dbg(component->dev, "Reserving pll %d for ir\n", 3183 tscs454->internal_rate.pll->id); 3184 3185 reserve_pll(tscs454->internal_rate.pll); 3186 } 3187 3188 ret = set_aif_fs(component, aif->id, fs); 3189 if (ret < 0) { 3190 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret); 3191 return ret; 3192 } 3193 3194 ret = set_aif_sample_format(component, params_format(params), aif->id); 3195 if (ret < 0) { 3196 dev_err(component->dev, 3197 "Failed to set aif sample format (%d)\n", ret); 3198 return ret; 3199 } 3200 3201 set_aif_status_active(&tscs454->aifs_status, aif->id, 3202 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 3203 3204 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n", 3205 aif->id, tscs454->aifs_status.streams); 3206 3207 return 0; 3208 } 3209 3210 static int tscs454_hw_free(struct snd_pcm_substream *substream, 3211 struct snd_soc_dai *dai) 3212 { 3213 struct snd_soc_component *component = dai->component; 3214 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3215 struct aif *aif = &tscs454->aifs[dai->id]; 3216 3217 return aif_free(component, aif, 3218 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 3219 } 3220 3221 static int tscs454_prepare(struct snd_pcm_substream *substream, 3222 struct snd_soc_dai *dai) 3223 { 3224 int ret; 3225 struct snd_soc_component *component = dai->component; 3226 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3227 struct aif *aif = &tscs454->aifs[dai->id]; 3228 3229 ret = aif_prepare(component, aif); 3230 if (ret < 0) 3231 return ret; 3232 3233 return 0; 3234 } 3235 3236 static struct snd_soc_dai_ops const tscs454_dai1_ops = { 3237 .set_sysclk = tscs454_set_sysclk, 3238 .set_bclk_ratio = tscs454_set_bclk_ratio, 3239 .set_fmt = tscs454_set_dai_fmt, 3240 .set_tdm_slot = tscs454_dai1_set_tdm_slot, 3241 .hw_params = tscs454_hw_params, 3242 .hw_free = tscs454_hw_free, 3243 .prepare = tscs454_prepare, 3244 }; 3245 3246 static struct snd_soc_dai_ops const tscs454_dai23_ops = { 3247 .set_sysclk = tscs454_set_sysclk, 3248 .set_bclk_ratio = tscs454_set_bclk_ratio, 3249 .set_fmt = tscs454_set_dai_fmt, 3250 .set_tdm_slot = tscs454_dai23_set_tdm_slot, 3251 .hw_params = tscs454_hw_params, 3252 .hw_free = tscs454_hw_free, 3253 .prepare = tscs454_prepare, 3254 }; 3255 3256 static int tscs454_probe(struct snd_soc_component *component) 3257 { 3258 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3259 unsigned int val; 3260 int ret = 0; 3261 3262 switch (tscs454->sysclk_src_id) { 3263 case PLL_INPUT_XTAL: 3264 val = FV_PLLISEL_XTAL; 3265 break; 3266 case PLL_INPUT_MCLK1: 3267 val = FV_PLLISEL_MCLK1; 3268 break; 3269 case PLL_INPUT_MCLK2: 3270 val = FV_PLLISEL_MCLK2; 3271 break; 3272 case PLL_INPUT_BCLK: 3273 val = FV_PLLISEL_BCLK; 3274 break; 3275 default: 3276 ret = -EINVAL; 3277 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret); 3278 return ret; 3279 } 3280 3281 ret = snd_soc_component_update_bits(component, R_PLLCTL, 3282 FM_PLLCTL_PLLISEL, val); 3283 if (ret < 0) { 3284 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret); 3285 return ret; 3286 } 3287 3288 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) 3289 ret = set_sysclk(component); 3290 3291 return ret; 3292 } 3293 3294 static const struct snd_soc_component_driver soc_component_dev_tscs454 = { 3295 .probe = tscs454_probe, 3296 .dapm_widgets = tscs454_dapm_widgets, 3297 .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets), 3298 .dapm_routes = tscs454_intercon, 3299 .num_dapm_routes = ARRAY_SIZE(tscs454_intercon), 3300 .controls = tscs454_snd_controls, 3301 .num_controls = ARRAY_SIZE(tscs454_snd_controls), 3302 .endianness = 1, 3303 }; 3304 3305 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000 3306 3307 #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 3308 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \ 3309 | SNDRV_PCM_FMTBIT_S32_LE) 3310 3311 static struct snd_soc_dai_driver tscs454_dais[] = { 3312 { 3313 .name = "tscs454-dai1", 3314 .id = TSCS454_DAI1_ID, 3315 .playback = { 3316 .stream_name = "DAI 1 Playback", 3317 .channels_min = 1, 3318 .channels_max = 6, 3319 .rates = TSCS454_RATES, 3320 .formats = TSCS454_FORMATS,}, 3321 .capture = { 3322 .stream_name = "DAI 1 Capture", 3323 .channels_min = 1, 3324 .channels_max = 6, 3325 .rates = TSCS454_RATES, 3326 .formats = TSCS454_FORMATS,}, 3327 .ops = &tscs454_dai1_ops, 3328 .symmetric_rate = 1, 3329 .symmetric_channels = 1, 3330 .symmetric_sample_bits = 1, 3331 }, 3332 { 3333 .name = "tscs454-dai2", 3334 .id = TSCS454_DAI2_ID, 3335 .playback = { 3336 .stream_name = "DAI 2 Playback", 3337 .channels_min = 1, 3338 .channels_max = 2, 3339 .rates = TSCS454_RATES, 3340 .formats = TSCS454_FORMATS,}, 3341 .capture = { 3342 .stream_name = "DAI 2 Capture", 3343 .channels_min = 1, 3344 .channels_max = 2, 3345 .rates = TSCS454_RATES, 3346 .formats = TSCS454_FORMATS,}, 3347 .ops = &tscs454_dai23_ops, 3348 .symmetric_rate = 1, 3349 .symmetric_channels = 1, 3350 .symmetric_sample_bits = 1, 3351 }, 3352 { 3353 .name = "tscs454-dai3", 3354 .id = TSCS454_DAI3_ID, 3355 .playback = { 3356 .stream_name = "DAI 3 Playback", 3357 .channels_min = 1, 3358 .channels_max = 2, 3359 .rates = TSCS454_RATES, 3360 .formats = TSCS454_FORMATS,}, 3361 .capture = { 3362 .stream_name = "DAI 3 Capture", 3363 .channels_min = 1, 3364 .channels_max = 2, 3365 .rates = TSCS454_RATES, 3366 .formats = TSCS454_FORMATS,}, 3367 .ops = &tscs454_dai23_ops, 3368 .symmetric_rate = 1, 3369 .symmetric_channels = 1, 3370 .symmetric_sample_bits = 1, 3371 }, 3372 }; 3373 3374 static char const * const src_names[] = { 3375 "xtal", "mclk1", "mclk2", "bclk"}; 3376 3377 static int tscs454_i2c_probe(struct i2c_client *i2c) 3378 { 3379 struct tscs454 *tscs454; 3380 int src; 3381 int ret; 3382 3383 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL); 3384 if (!tscs454) 3385 return -ENOMEM; 3386 3387 ret = tscs454_data_init(tscs454, i2c); 3388 if (ret < 0) 3389 return ret; 3390 3391 i2c_set_clientdata(i2c, tscs454); 3392 3393 for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) { 3394 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]); 3395 if (!IS_ERR(tscs454->sysclk)) { 3396 break; 3397 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) { 3398 ret = PTR_ERR(tscs454->sysclk); 3399 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); 3400 return ret; 3401 } 3402 } 3403 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]); 3404 tscs454->sysclk_src_id = src; 3405 3406 ret = regmap_write(tscs454->regmap, 3407 R_RESET, FV_RESET_PWR_ON_DEFAULTS); 3408 if (ret < 0) { 3409 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret); 3410 return ret; 3411 } 3412 regcache_mark_dirty(tscs454->regmap); 3413 3414 ret = regmap_register_patch(tscs454->regmap, tscs454_patch, 3415 ARRAY_SIZE(tscs454_patch)); 3416 if (ret < 0) { 3417 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); 3418 return ret; 3419 } 3420 /* Sync pg sel reg with cache */ 3421 regmap_write(tscs454->regmap, R_PAGESEL, 0x00); 3422 3423 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454, 3424 tscs454_dais, ARRAY_SIZE(tscs454_dais)); 3425 if (ret) { 3426 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret); 3427 return ret; 3428 } 3429 3430 return 0; 3431 } 3432 3433 static const struct i2c_device_id tscs454_i2c_id[] = { 3434 { .name = "tscs454" }, 3435 { } 3436 }; 3437 MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id); 3438 3439 static const struct of_device_id tscs454_of_match[] = { 3440 { .compatible = "tempo,tscs454", }, 3441 { } 3442 }; 3443 MODULE_DEVICE_TABLE(of, tscs454_of_match); 3444 3445 static struct i2c_driver tscs454_i2c_driver = { 3446 .driver = { 3447 .name = "tscs454", 3448 .of_match_table = tscs454_of_match, 3449 }, 3450 .probe = tscs454_i2c_probe, 3451 .id_table = tscs454_i2c_id, 3452 }; 3453 3454 module_i2c_driver(tscs454_i2c_driver); 3455 3456 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); 3457 MODULE_DESCRIPTION("ASoC TSCS454 driver"); 3458 MODULE_LICENSE("GPL v2"); 3459