1 // SPDX-License-Identifier: GPL-2.0 2 // tscs454.c -- TSCS454 ALSA SoC Audio driver 3 // Copyright 2018 Tempo Semiconductor, Inc. 4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> 5 6 #include <linux/kernel.h> 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/regmap.h> 10 #include <linux/i2c.h> 11 #include <linux/err.h> 12 #include <linux/string.h> 13 #include <linux/string_choices.h> 14 #include <linux/module.h> 15 #include <linux/delay.h> 16 #include <linux/mutex.h> 17 18 #include <sound/tlv.h> 19 #include <sound/pcm_params.h> 20 #include <sound/pcm.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dapm.h> 23 24 #include "tscs454.h" 25 26 static const unsigned int PLL_44_1K_RATE = (44100 * 256); 27 28 #define COEFF_SIZE 3 29 #define BIQUAD_COEFF_COUNT 5 30 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) 31 32 #define COEFF_RAM_MAX_ADDR 0xcd 33 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) 34 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) 35 36 enum { 37 TSCS454_DAI1_ID, 38 TSCS454_DAI2_ID, 39 TSCS454_DAI3_ID, 40 TSCS454_DAI_COUNT, 41 }; 42 43 struct pll { 44 int id; 45 unsigned int users; 46 struct mutex lock; 47 }; 48 49 static inline void pll_init(struct pll *pll, int id) 50 { 51 pll->id = id; 52 mutex_init(&pll->lock); 53 } 54 55 struct internal_rate { 56 struct pll *pll; 57 }; 58 59 struct aif { 60 unsigned int id; 61 bool provider; 62 struct pll *pll; 63 }; 64 65 static inline void aif_init(struct aif *aif, unsigned int id) 66 { 67 aif->id = id; 68 } 69 70 struct coeff_ram { 71 u8 cache[COEFF_RAM_SIZE]; 72 bool synced; 73 struct mutex lock; 74 }; 75 76 static inline void init_coeff_ram_cache(u8 *cache) 77 { 78 static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 79 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 80 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 81 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 82 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9}; 83 int i; 84 85 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) 86 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; 87 } 88 89 static inline void coeff_ram_init(struct coeff_ram *ram) 90 { 91 init_coeff_ram_cache(ram->cache); 92 mutex_init(&ram->lock); 93 } 94 95 struct aifs_status { 96 u8 streams; 97 }; 98 99 static inline void set_aif_status_active(struct aifs_status *status, 100 int aif_id, bool playback) 101 { 102 u8 mask = 0x01 << (aif_id * 2 + !playback); 103 104 status->streams |= mask; 105 } 106 107 static inline void set_aif_status_inactive(struct aifs_status *status, 108 int aif_id, bool playback) 109 { 110 u8 mask = ~(0x01 << (aif_id * 2 + !playback)); 111 112 status->streams &= mask; 113 } 114 115 static bool aifs_active(struct aifs_status *status) 116 { 117 return status->streams; 118 } 119 120 static bool aif_active(struct aifs_status *status, int aif_id) 121 { 122 return (0x03 << aif_id * 2) & status->streams; 123 } 124 125 struct tscs454 { 126 struct regmap *regmap; 127 struct aif aifs[TSCS454_DAI_COUNT]; 128 129 struct aifs_status aifs_status; 130 struct mutex aifs_status_lock; 131 132 struct pll pll1; 133 struct pll pll2; 134 struct internal_rate internal_rate; 135 136 struct coeff_ram dac_ram; 137 struct coeff_ram spk_ram; 138 struct coeff_ram sub_ram; 139 140 struct clk *sysclk; 141 int sysclk_src_id; 142 unsigned int bclk_freq; 143 }; 144 145 struct coeff_ram_ctl { 146 unsigned int addr; 147 struct soc_bytes_ext bytes_ext; 148 }; 149 150 static const struct reg_sequence tscs454_patch[] = { 151 /* Assign ASRC out of the box so DAI 1 just works */ 152 { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 }, 153 { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 }, 154 { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR }, 155 { R_TDMCTL0, FV_TDMMD_256 }, 156 { VIRT_ADDR(0x0A, 0x13), 1 << 3 }, 157 }; 158 159 static bool tscs454_volatile(struct device *dev, unsigned int reg) 160 { 161 switch (reg) { 162 case R_PLLSTAT: 163 164 case R_SPKCRRDL: 165 case R_SPKCRRDM: 166 case R_SPKCRRDH: 167 case R_SPKCRS: 168 169 case R_DACCRRDL: 170 case R_DACCRRDM: 171 case R_DACCRRDH: 172 case R_DACCRS: 173 174 case R_SUBCRRDL: 175 case R_SUBCRRDM: 176 case R_SUBCRRDH: 177 case R_SUBCRS: 178 return true; 179 default: 180 return false; 181 } 182 } 183 184 static bool tscs454_writable(struct device *dev, unsigned int reg) 185 { 186 switch (reg) { 187 case R_SPKCRRDL: 188 case R_SPKCRRDM: 189 case R_SPKCRRDH: 190 191 case R_DACCRRDL: 192 case R_DACCRRDM: 193 case R_DACCRRDH: 194 195 case R_SUBCRRDL: 196 case R_SUBCRRDM: 197 case R_SUBCRRDH: 198 return false; 199 default: 200 return true; 201 } 202 } 203 204 static bool tscs454_readable(struct device *dev, unsigned int reg) 205 { 206 switch (reg) { 207 case R_SPKCRWDL: 208 case R_SPKCRWDM: 209 case R_SPKCRWDH: 210 211 case R_DACCRWDL: 212 case R_DACCRWDM: 213 case R_DACCRWDH: 214 215 case R_SUBCRWDL: 216 case R_SUBCRWDM: 217 case R_SUBCRWDH: 218 return false; 219 default: 220 return true; 221 } 222 } 223 224 static bool tscs454_precious(struct device *dev, unsigned int reg) 225 { 226 switch (reg) { 227 case R_SPKCRWDL: 228 case R_SPKCRWDM: 229 case R_SPKCRWDH: 230 case R_SPKCRRDL: 231 case R_SPKCRRDM: 232 case R_SPKCRRDH: 233 234 case R_DACCRWDL: 235 case R_DACCRWDM: 236 case R_DACCRWDH: 237 case R_DACCRRDL: 238 case R_DACCRRDM: 239 case R_DACCRRDH: 240 241 case R_SUBCRWDL: 242 case R_SUBCRWDM: 243 case R_SUBCRWDH: 244 case R_SUBCRRDL: 245 case R_SUBCRRDM: 246 case R_SUBCRRDH: 247 return true; 248 default: 249 return false; 250 } 251 } 252 253 static const struct regmap_range_cfg tscs454_regmap_range_cfg = { 254 .name = "Pages", 255 .range_min = VIRT_BASE, 256 .range_max = VIRT_ADDR(0xFE, 0x02), 257 .selector_reg = R_PAGESEL, 258 .selector_mask = 0xff, 259 .selector_shift = 0, 260 .window_start = 0, 261 .window_len = 0x100, 262 }; 263 264 static struct regmap_config const tscs454_regmap_cfg = { 265 .reg_bits = 8, 266 .val_bits = 8, 267 .writeable_reg = tscs454_writable, 268 .readable_reg = tscs454_readable, 269 .volatile_reg = tscs454_volatile, 270 .precious_reg = tscs454_precious, 271 .ranges = &tscs454_regmap_range_cfg, 272 .num_ranges = 1, 273 .max_register = VIRT_ADDR(0xFE, 0x02), 274 .cache_type = REGCACHE_RBTREE, 275 }; 276 277 static inline int tscs454_data_init(struct tscs454 *tscs454, 278 struct i2c_client *i2c) 279 { 280 int i; 281 int ret; 282 283 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg); 284 if (IS_ERR(tscs454->regmap)) { 285 ret = PTR_ERR(tscs454->regmap); 286 return ret; 287 } 288 289 for (i = 0; i < TSCS454_DAI_COUNT; i++) 290 aif_init(&tscs454->aifs[i], i); 291 292 mutex_init(&tscs454->aifs_status_lock); 293 pll_init(&tscs454->pll1, 1); 294 pll_init(&tscs454->pll2, 2); 295 296 coeff_ram_init(&tscs454->dac_ram); 297 coeff_ram_init(&tscs454->spk_ram); 298 coeff_ram_init(&tscs454->sub_ram); 299 300 return 0; 301 } 302 303 struct reg_setting { 304 unsigned int addr; 305 unsigned int val; 306 }; 307 308 static int coeff_ram_get(struct snd_kcontrol *kcontrol, 309 struct snd_ctl_elem_value *ucontrol) 310 { 311 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 312 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 313 struct coeff_ram_ctl *ctl = 314 (struct coeff_ram_ctl *)kcontrol->private_value; 315 struct soc_bytes_ext *params = &ctl->bytes_ext; 316 u8 *coeff_ram; 317 struct mutex *coeff_ram_lock; 318 319 if (strstr(kcontrol->id.name, "DAC")) { 320 coeff_ram = tscs454->dac_ram.cache; 321 coeff_ram_lock = &tscs454->dac_ram.lock; 322 } else if (strstr(kcontrol->id.name, "Speaker")) { 323 coeff_ram = tscs454->spk_ram.cache; 324 coeff_ram_lock = &tscs454->spk_ram.lock; 325 } else if (strstr(kcontrol->id.name, "Sub")) { 326 coeff_ram = tscs454->sub_ram.cache; 327 coeff_ram_lock = &tscs454->sub_ram.lock; 328 } else { 329 return -EINVAL; 330 } 331 332 mutex_lock(coeff_ram_lock); 333 334 memcpy(ucontrol->value.bytes.data, 335 &coeff_ram[ctl->addr * COEFF_SIZE], params->max); 336 337 mutex_unlock(coeff_ram_lock); 338 339 return 0; 340 } 341 342 #define DACCRSTAT_MAX_TRYS 10 343 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram, 344 unsigned int r_stat, unsigned int r_addr, unsigned int r_wr, 345 unsigned int coeff_addr, unsigned int coeff_cnt) 346 { 347 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 348 unsigned int val; 349 int cnt; 350 int trys; 351 int ret; 352 353 for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) { 354 355 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { 356 val = snd_soc_component_read(component, r_stat); 357 if (!val) 358 break; 359 } 360 361 if (trys == DACCRSTAT_MAX_TRYS) { 362 ret = -EIO; 363 dev_err(component->dev, 364 "Coefficient write error (%d)\n", ret); 365 return ret; 366 } 367 368 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr); 369 if (ret < 0) { 370 dev_err(component->dev, 371 "Failed to write dac ram address (%d)\n", ret); 372 return ret; 373 } 374 375 ret = regmap_bulk_write(tscs454->regmap, r_wr, 376 &coeff_ram[coeff_addr * COEFF_SIZE], 377 COEFF_SIZE); 378 if (ret < 0) { 379 dev_err(component->dev, 380 "Failed to write dac ram (%d)\n", ret); 381 return ret; 382 } 383 } 384 385 return 0; 386 } 387 388 static int coeff_ram_put(struct snd_kcontrol *kcontrol, 389 struct snd_ctl_elem_value *ucontrol) 390 { 391 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 392 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 393 struct coeff_ram_ctl *ctl = 394 (struct coeff_ram_ctl *)kcontrol->private_value; 395 struct soc_bytes_ext *params = &ctl->bytes_ext; 396 unsigned int coeff_cnt = params->max / COEFF_SIZE; 397 u8 *coeff_ram; 398 struct mutex *coeff_ram_lock; 399 bool *coeff_ram_synced; 400 unsigned int r_stat; 401 unsigned int r_addr; 402 unsigned int r_wr; 403 unsigned int val; 404 int ret; 405 406 if (strstr(kcontrol->id.name, "DAC")) { 407 coeff_ram = tscs454->dac_ram.cache; 408 coeff_ram_lock = &tscs454->dac_ram.lock; 409 coeff_ram_synced = &tscs454->dac_ram.synced; 410 r_stat = R_DACCRS; 411 r_addr = R_DACCRADD; 412 r_wr = R_DACCRWDL; 413 } else if (strstr(kcontrol->id.name, "Speaker")) { 414 coeff_ram = tscs454->spk_ram.cache; 415 coeff_ram_lock = &tscs454->spk_ram.lock; 416 coeff_ram_synced = &tscs454->spk_ram.synced; 417 r_stat = R_SPKCRS; 418 r_addr = R_SPKCRADD; 419 r_wr = R_SPKCRWDL; 420 } else if (strstr(kcontrol->id.name, "Sub")) { 421 coeff_ram = tscs454->sub_ram.cache; 422 coeff_ram_lock = &tscs454->sub_ram.lock; 423 coeff_ram_synced = &tscs454->sub_ram.synced; 424 r_stat = R_SUBCRS; 425 r_addr = R_SUBCRADD; 426 r_wr = R_SUBCRWDL; 427 } else { 428 return -EINVAL; 429 } 430 431 mutex_lock(coeff_ram_lock); 432 433 *coeff_ram_synced = false; 434 435 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE], 436 ucontrol->value.bytes.data, params->max); 437 438 mutex_lock(&tscs454->pll1.lock); 439 mutex_lock(&tscs454->pll2.lock); 440 441 val = snd_soc_component_read(component, R_PLLSTAT); 442 if (val) { /* PLLs locked */ 443 ret = write_coeff_ram(component, coeff_ram, 444 r_stat, r_addr, r_wr, 445 ctl->addr, coeff_cnt); 446 if (ret < 0) { 447 dev_err(component->dev, 448 "Failed to flush coeff ram cache (%d)\n", ret); 449 goto exit; 450 } 451 *coeff_ram_synced = true; 452 } 453 454 ret = 0; 455 exit: 456 mutex_unlock(&tscs454->pll2.lock); 457 mutex_unlock(&tscs454->pll1.lock); 458 mutex_unlock(coeff_ram_lock); 459 460 return ret; 461 } 462 463 static inline int coeff_ram_sync(struct snd_soc_component *component, 464 struct tscs454 *tscs454) 465 { 466 int ret; 467 468 mutex_lock(&tscs454->dac_ram.lock); 469 if (!tscs454->dac_ram.synced) { 470 ret = write_coeff_ram(component, tscs454->dac_ram.cache, 471 R_DACCRS, R_DACCRADD, R_DACCRWDL, 472 0x00, COEFF_RAM_COEFF_COUNT); 473 if (ret < 0) { 474 mutex_unlock(&tscs454->dac_ram.lock); 475 return ret; 476 } 477 } 478 mutex_unlock(&tscs454->dac_ram.lock); 479 480 mutex_lock(&tscs454->spk_ram.lock); 481 if (!tscs454->spk_ram.synced) { 482 ret = write_coeff_ram(component, tscs454->spk_ram.cache, 483 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL, 484 0x00, COEFF_RAM_COEFF_COUNT); 485 if (ret < 0) { 486 mutex_unlock(&tscs454->spk_ram.lock); 487 return ret; 488 } 489 } 490 mutex_unlock(&tscs454->spk_ram.lock); 491 492 mutex_lock(&tscs454->sub_ram.lock); 493 if (!tscs454->sub_ram.synced) { 494 ret = write_coeff_ram(component, tscs454->sub_ram.cache, 495 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL, 496 0x00, COEFF_RAM_COEFF_COUNT); 497 if (ret < 0) { 498 mutex_unlock(&tscs454->sub_ram.lock); 499 return ret; 500 } 501 } 502 mutex_unlock(&tscs454->sub_ram.lock); 503 504 return 0; 505 } 506 507 #define PLL_REG_SETTINGS_COUNT 11 508 struct pll_ctl { 509 int freq_in; 510 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; 511 }; 512 513 #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \ 514 { \ 515 .freq_in = f, \ 516 .settings = { \ 517 {R_PLL1CTL, c1}, \ 518 {R_PLL1RDIV, r1}, \ 519 {R_PLL1ODIV, o1}, \ 520 {R_PLL1FDIVL, f1l}, \ 521 {R_PLL1FDIVH, f1h}, \ 522 {R_PLL2CTL, c2}, \ 523 {R_PLL2RDIV, r2}, \ 524 {R_PLL2ODIV, o2}, \ 525 {R_PLL2FDIVL, f2l}, \ 526 {R_PLL2FDIVH, f2h}, \ 527 {R_TIMEBASE, t}, \ 528 }, \ 529 } 530 531 static const struct pll_ctl pll_ctls[] = { 532 PLL_CTL(1411200, 0x05, 533 0xB9, 0x07, 0x02, 0xC3, 0x04, 534 0x5A, 0x02, 0x03, 0xE0, 0x01), 535 PLL_CTL(1536000, 0x05, 536 0x5A, 0x02, 0x03, 0xE0, 0x01, 537 0x5A, 0x02, 0x03, 0xB9, 0x01), 538 PLL_CTL(2822400, 0x0A, 539 0x63, 0x07, 0x04, 0xC3, 0x04, 540 0x62, 0x07, 0x03, 0x48, 0x03), 541 PLL_CTL(3072000, 0x0B, 542 0x62, 0x07, 0x03, 0x48, 0x03, 543 0x5A, 0x04, 0x03, 0xB9, 0x01), 544 PLL_CTL(5644800, 0x15, 545 0x63, 0x0E, 0x04, 0xC3, 0x04, 546 0x5A, 0x08, 0x03, 0xE0, 0x01), 547 PLL_CTL(6144000, 0x17, 548 0x5A, 0x08, 0x03, 0xE0, 0x01, 549 0x5A, 0x08, 0x03, 0xB9, 0x01), 550 PLL_CTL(12000000, 0x2E, 551 0x5B, 0x19, 0x03, 0x00, 0x03, 552 0x6A, 0x19, 0x05, 0x98, 0x04), 553 PLL_CTL(19200000, 0x4A, 554 0x53, 0x14, 0x03, 0x80, 0x01, 555 0x5A, 0x19, 0x03, 0xB9, 0x01), 556 PLL_CTL(22000000, 0x55, 557 0x6A, 0x37, 0x05, 0x00, 0x06, 558 0x62, 0x26, 0x03, 0x49, 0x02), 559 PLL_CTL(22579200, 0x57, 560 0x62, 0x31, 0x03, 0x20, 0x03, 561 0x53, 0x1D, 0x03, 0xB3, 0x01), 562 PLL_CTL(24000000, 0x5D, 563 0x53, 0x19, 0x03, 0x80, 0x01, 564 0x5B, 0x19, 0x05, 0x4C, 0x02), 565 PLL_CTL(24576000, 0x5F, 566 0x53, 0x1D, 0x03, 0xB3, 0x01, 567 0x62, 0x40, 0x03, 0x72, 0x03), 568 PLL_CTL(27000000, 0x68, 569 0x62, 0x4B, 0x03, 0x00, 0x04, 570 0x6A, 0x7D, 0x03, 0x20, 0x06), 571 PLL_CTL(36000000, 0x8C, 572 0x5B, 0x4B, 0x03, 0x00, 0x03, 573 0x6A, 0x7D, 0x03, 0x98, 0x04), 574 PLL_CTL(11289600, 0x2B, 575 0x6A, 0x31, 0x03, 0x40, 0x06, 576 0x5A, 0x12, 0x03, 0x1C, 0x02), 577 PLL_CTL(26000000, 0x65, 578 0x63, 0x41, 0x05, 0x00, 0x06, 579 0x5A, 0x26, 0x03, 0xEF, 0x01), 580 PLL_CTL(12288000, 0x2F, 581 0x5A, 0x12, 0x03, 0x1C, 0x02, 582 0x62, 0x20, 0x03, 0x72, 0x03), 583 PLL_CTL(40000000, 0x9B, 584 0xA2, 0x7D, 0x03, 0x80, 0x04, 585 0x63, 0x7D, 0x05, 0xE4, 0x06), 586 PLL_CTL(512000, 0x01, 587 0x62, 0x01, 0x03, 0xD0, 0x02, 588 0x5B, 0x01, 0x04, 0x72, 0x03), 589 PLL_CTL(705600, 0x02, 590 0x62, 0x02, 0x03, 0x15, 0x04, 591 0x62, 0x01, 0x04, 0x80, 0x02), 592 PLL_CTL(1024000, 0x03, 593 0x62, 0x02, 0x03, 0xD0, 0x02, 594 0x5B, 0x02, 0x04, 0x72, 0x03), 595 PLL_CTL(2048000, 0x07, 596 0x62, 0x04, 0x03, 0xD0, 0x02, 597 0x5B, 0x04, 0x04, 0x72, 0x03), 598 PLL_CTL(2400000, 0x08, 599 0x62, 0x05, 0x03, 0x00, 0x03, 600 0x63, 0x05, 0x05, 0x98, 0x04), 601 }; 602 603 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in) 604 { 605 int i; 606 struct pll_ctl const *pll_ctl = NULL; 607 608 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) 609 if (pll_ctls[i].freq_in == freq_in) { 610 pll_ctl = &pll_ctls[i]; 611 break; 612 } 613 614 return pll_ctl; 615 } 616 617 enum { 618 PLL_INPUT_XTAL = 0, 619 PLL_INPUT_MCLK1, 620 PLL_INPUT_MCLK2, 621 PLL_INPUT_BCLK, 622 }; 623 624 static int set_sysclk(struct snd_soc_component *component) 625 { 626 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 627 struct pll_ctl const *pll_ctl; 628 unsigned long freq; 629 int i; 630 int ret; 631 632 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) 633 freq = clk_get_rate(tscs454->sysclk); 634 else 635 freq = tscs454->bclk_freq; 636 pll_ctl = get_pll_ctl(freq); 637 if (!pll_ctl) { 638 ret = -EINVAL; 639 dev_err(component->dev, 640 "Invalid PLL input %lu (%d)\n", freq, ret); 641 return ret; 642 } 643 644 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { 645 ret = snd_soc_component_write(component, 646 pll_ctl->settings[i].addr, 647 pll_ctl->settings[i].val); 648 if (ret < 0) { 649 dev_err(component->dev, 650 "Failed to set pll setting (%d)\n", 651 ret); 652 return ret; 653 } 654 } 655 656 return 0; 657 } 658 659 static inline void reserve_pll(struct pll *pll) 660 { 661 mutex_lock(&pll->lock); 662 pll->users++; 663 mutex_unlock(&pll->lock); 664 } 665 666 static inline void free_pll(struct pll *pll) 667 { 668 mutex_lock(&pll->lock); 669 pll->users--; 670 mutex_unlock(&pll->lock); 671 } 672 673 static int pll_connected(struct snd_soc_dapm_widget *source, 674 struct snd_soc_dapm_widget *sink) 675 { 676 struct snd_soc_component *component = 677 snd_soc_dapm_to_component(source->dapm); 678 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 679 int users; 680 681 if (strstr(source->name, "PLL 1")) { 682 mutex_lock(&tscs454->pll1.lock); 683 users = tscs454->pll1.users; 684 mutex_unlock(&tscs454->pll1.lock); 685 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__, 686 users); 687 } else { 688 mutex_lock(&tscs454->pll2.lock); 689 users = tscs454->pll2.users; 690 mutex_unlock(&tscs454->pll2.lock); 691 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__, 692 users); 693 } 694 695 return users; 696 } 697 698 /* 699 * PLL must be enabled after power up and must be disabled before power down 700 * for proper clock switching. 701 */ 702 static int pll_power_event(struct snd_soc_dapm_widget *w, 703 struct snd_kcontrol *kcontrol, int event) 704 { 705 struct snd_soc_component *component = 706 snd_soc_dapm_to_component(w->dapm); 707 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 708 bool enable; 709 bool pll1; 710 unsigned int msk; 711 unsigned int val; 712 int ret; 713 714 if (strstr(w->name, "PLL 1")) 715 pll1 = true; 716 else 717 pll1 = false; 718 719 msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN; 720 721 if (event == SND_SOC_DAPM_POST_PMU) 722 enable = true; 723 else 724 enable = false; 725 726 if (enable) 727 val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE; 728 else 729 /* 730 * FV_PLL1CLKEN_DISABLE and FV_PLL2CLKEN_DISABLE are 731 * identical zero vzalues, there is no need to test 732 * the PLL index 733 */ 734 val = FV_PLL1CLKEN_DISABLE; 735 736 ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val); 737 if (ret < 0) { 738 dev_err(component->dev, "Failed to %s PLL %d (%d)\n", 739 str_enable_disable(enable), pll1 ? 1 : 2, ret); 740 return ret; 741 } 742 743 if (enable) { 744 msleep(20); // Wait for lock 745 ret = coeff_ram_sync(component, tscs454); 746 if (ret < 0) { 747 dev_err(component->dev, 748 "Failed to sync coeff ram (%d)\n", ret); 749 return ret; 750 } 751 } 752 753 return 0; 754 } 755 756 static inline int aif_set_provider(struct snd_soc_component *component, 757 unsigned int aif_id, bool provider) 758 { 759 unsigned int reg; 760 unsigned int mask; 761 unsigned int val; 762 int ret; 763 764 switch (aif_id) { 765 case TSCS454_DAI1_ID: 766 reg = R_I2SP1CTL; 767 break; 768 case TSCS454_DAI2_ID: 769 reg = R_I2SP2CTL; 770 break; 771 case TSCS454_DAI3_ID: 772 reg = R_I2SP3CTL; 773 break; 774 default: 775 ret = -ENODEV; 776 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret); 777 return ret; 778 } 779 mask = FM_I2SPCTL_PORTMS; 780 val = provider ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE; 781 782 ret = snd_soc_component_update_bits(component, reg, mask, val); 783 if (ret < 0) { 784 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n", 785 aif_id, provider ? "provider" : "consumer", ret); 786 return ret; 787 } 788 789 return 0; 790 } 791 792 static inline 793 int aif_prepare(struct snd_soc_component *component, struct aif *aif) 794 { 795 int ret; 796 797 ret = aif_set_provider(component, aif->id, aif->provider); 798 if (ret < 0) 799 return ret; 800 801 return 0; 802 } 803 804 static inline int aif_free(struct snd_soc_component *component, 805 struct aif *aif, bool playback) 806 { 807 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 808 809 mutex_lock(&tscs454->aifs_status_lock); 810 811 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id); 812 813 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback); 814 815 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n", 816 aif->id, tscs454->aifs_status.streams); 817 818 if (!aif_active(&tscs454->aifs_status, aif->id)) { 819 /* Do config in slave mode */ 820 aif_set_provider(component, aif->id, false); 821 dev_dbg(component->dev, "Freeing pll %d from aif %d\n", 822 aif->pll->id, aif->id); 823 free_pll(aif->pll); 824 } 825 826 if (!aifs_active(&tscs454->aifs_status)) { 827 dev_dbg(component->dev, "Freeing pll %d from ir\n", 828 tscs454->internal_rate.pll->id); 829 free_pll(tscs454->internal_rate.pll); 830 } 831 832 mutex_unlock(&tscs454->aifs_status_lock); 833 834 return 0; 835 } 836 837 /* R_PLLCTL PG 0 ADDR 0x15 */ 838 static char const * const bclk_sel_txt[] = { 839 "BCLK 1", "BCLK 2", "BCLK 3"}; 840 841 static struct soc_enum const bclk_sel_enum = 842 SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL, 843 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt); 844 845 /* R_ISRC PG 0 ADDR 0x16 */ 846 static char const * const isrc_br_txt[] = { 847 "44.1kHz", "48kHz"}; 848 849 static struct soc_enum const isrc_br_enum = 850 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR, 851 ARRAY_SIZE(isrc_br_txt), isrc_br_txt); 852 853 static char const * const isrc_bm_txt[] = { 854 "0.25x", "0.5x", "1.0x", "2.0x"}; 855 856 static struct soc_enum const isrc_bm_enum = 857 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM, 858 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt); 859 860 /* R_SCLKCTL PG 0 ADDR 0x18 */ 861 static char const * const modular_rate_txt[] = { 862 "Reserved", "Half", "Full", "Auto",}; 863 864 static struct soc_enum const adc_modular_rate_enum = 865 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM, 866 ARRAY_SIZE(modular_rate_txt), modular_rate_txt); 867 868 static struct soc_enum const dac_modular_rate_enum = 869 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM, 870 ARRAY_SIZE(modular_rate_txt), modular_rate_txt); 871 872 /* R_I2SIDCTL PG 0 ADDR 0x38 */ 873 static char const * const data_ctrl_txt[] = { 874 "L/R", "L/L", "R/R", "R/L"}; 875 876 static struct soc_enum const data_in_ctrl_enums[] = { 877 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL, 878 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 879 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL, 880 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 881 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL, 882 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 883 }; 884 885 /* R_I2SODCTL PG 0 ADDR 0x39 */ 886 static struct soc_enum const data_out_ctrl_enums[] = { 887 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL, 888 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 889 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL, 890 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 891 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL, 892 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt), 893 }; 894 895 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ 896 static char const * const asrc_mux_txt[] = { 897 "None", "DAI 1", "DAI 2", "DAI 3"}; 898 899 static struct soc_enum const asrc_in_mux_enum = 900 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX, 901 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt); 902 903 static char const * const dai_mux_txt[] = { 904 "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1", 905 "DMic 2", "ClassD", "DAC", "Sub"}; 906 907 static struct soc_enum const dai2_mux_enum = 908 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX, 909 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 910 911 static struct snd_kcontrol_new const dai2_mux_dapm_enum = 912 SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum); 913 914 static struct soc_enum const dai1_mux_enum = 915 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX, 916 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 917 918 static struct snd_kcontrol_new const dai1_mux_dapm_enum = 919 SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum); 920 921 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ 922 static struct soc_enum const asrc_out_mux_enum = 923 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX, 924 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt); 925 926 static struct soc_enum const dac_mux_enum = 927 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX, 928 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 929 930 static struct snd_kcontrol_new const dac_mux_dapm_enum = 931 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum); 932 933 static struct soc_enum const dai3_mux_enum = 934 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX, 935 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 936 937 static struct snd_kcontrol_new const dai3_mux_dapm_enum = 938 SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum); 939 940 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */ 941 static char const * const sub_mux_txt[] = { 942 "CH 0", "CH 1", "CH 0 + 1", 943 "CH 2", "CH 3", "CH 2 + 3", 944 "CH 4", "CH 5", "CH 4 + 5", 945 "ADC/DMic 1 Left", "ADC/DMic 1 Right", 946 "ADC/DMic 1 Left Plus Right", 947 "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right", 948 "ClassD Left", "ClassD Right", "ClassD Left Plus Right"}; 949 950 static struct soc_enum const sub_mux_enum = 951 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX, 952 ARRAY_SIZE(sub_mux_txt), sub_mux_txt); 953 954 static struct snd_kcontrol_new const sub_mux_dapm_enum = 955 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum); 956 957 static struct soc_enum const classd_mux_enum = 958 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX, 959 ARRAY_SIZE(dai_mux_txt), dai_mux_txt); 960 961 static struct snd_kcontrol_new const classd_mux_dapm_enum = 962 SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum); 963 964 /* R_HSDCTL1 PG 1 ADDR 0x01 */ 965 static char const * const jack_type_txt[] = { 966 "3 Terminal", "4 Terminal"}; 967 968 static struct soc_enum const hp_jack_type_enum = 969 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE, 970 ARRAY_SIZE(jack_type_txt), jack_type_txt); 971 972 static char const * const hs_det_pol_txt[] = { 973 "Rising", "Falling"}; 974 975 static struct soc_enum const hs_det_pol_enum = 976 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL, 977 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt); 978 979 /* R_HSDCTL1 PG 1 ADDR 0x02 */ 980 static char const * const hs_mic_bias_force_txt[] = { 981 "Off", "Ring", "Sleeve"}; 982 983 static struct soc_enum const hs_mic_bias_force_enum = 984 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1, 985 ARRAY_SIZE(hs_mic_bias_force_txt), 986 hs_mic_bias_force_txt); 987 988 static char const * const plug_type_txt[] = { 989 "OMTP", "CTIA", "Reserved", "Headphone"}; 990 991 static struct soc_enum const plug_type_force_enum = 992 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE, 993 ARRAY_SIZE(plug_type_txt), plug_type_txt); 994 995 996 /* R_CH0AIC PG 1 ADDR 0x06 */ 997 static char const * const in_bst_mux_txt[] = { 998 "Input 1", "Input 2", "Input 3", "D2S"}; 999 1000 static struct soc_enum const in_bst_mux_ch0_enum = 1001 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL, 1002 ARRAY_SIZE(in_bst_mux_txt), 1003 in_bst_mux_txt); 1004 static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum = 1005 SOC_DAPM_ENUM("Input Boost Channel 0 Enum", 1006 in_bst_mux_ch0_enum); 1007 1008 static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0); 1009 1010 static char const * const adc_mux_txt[] = { 1011 "Input 1 Boost Bypass", "Input 2 Boost Bypass", 1012 "Input 3 Boost Bypass", "Input Boost"}; 1013 1014 static struct soc_enum const adc_mux_ch0_enum = 1015 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN, 1016 ARRAY_SIZE(adc_mux_txt), adc_mux_txt); 1017 static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum = 1018 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum); 1019 1020 static char const * const in_proc_mux_txt[] = { 1021 "ADC", "DMic"}; 1022 1023 static struct soc_enum const in_proc_ch0_enum = 1024 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S, 1025 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt); 1026 static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum = 1027 SOC_DAPM_ENUM("Input Processor Channel 0 Enum", 1028 in_proc_ch0_enum); 1029 1030 /* R_CH1AIC PG 1 ADDR 0x07 */ 1031 static struct soc_enum const in_bst_mux_ch1_enum = 1032 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR, 1033 ARRAY_SIZE(in_bst_mux_txt), 1034 in_bst_mux_txt); 1035 static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum = 1036 SOC_DAPM_ENUM("Input Boost Channel 1 Enum", 1037 in_bst_mux_ch1_enum); 1038 1039 static struct soc_enum const adc_mux_ch1_enum = 1040 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN, 1041 ARRAY_SIZE(adc_mux_txt), adc_mux_txt); 1042 static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum = 1043 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum); 1044 1045 static struct soc_enum const in_proc_ch1_enum = 1046 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S, 1047 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt); 1048 static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum = 1049 SOC_DAPM_ENUM("Input Processor Channel 1 Enum", 1050 in_proc_ch1_enum); 1051 1052 /* R_ICTL0 PG 1 ADDR 0x0A */ 1053 static char const * const pol_txt[] = { 1054 "Normal", "Invert"}; 1055 1056 static struct soc_enum const in_pol_ch1_enum = 1057 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL, 1058 ARRAY_SIZE(pol_txt), pol_txt); 1059 1060 static struct soc_enum const in_pol_ch0_enum = 1061 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL, 1062 ARRAY_SIZE(pol_txt), pol_txt); 1063 1064 static char const * const in_proc_ch_sel_txt[] = { 1065 "Normal", "Mono Mix to Channel 0", 1066 "Mono Mix to Channel 1", "Add"}; 1067 1068 static struct soc_enum const in_proc_ch01_sel_enum = 1069 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL, 1070 ARRAY_SIZE(in_proc_ch_sel_txt), 1071 in_proc_ch_sel_txt); 1072 1073 /* R_ICTL1 PG 1 ADDR 0x0B */ 1074 static struct soc_enum const in_pol_ch3_enum = 1075 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL, 1076 ARRAY_SIZE(pol_txt), pol_txt); 1077 1078 static struct soc_enum const in_pol_ch2_enum = 1079 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL, 1080 ARRAY_SIZE(pol_txt), pol_txt); 1081 1082 static struct soc_enum const in_proc_ch23_sel_enum = 1083 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL, 1084 ARRAY_SIZE(in_proc_ch_sel_txt), 1085 in_proc_ch_sel_txt); 1086 1087 /* R_MICBIAS PG 1 ADDR 0x0C */ 1088 static char const * const mic_bias_txt[] = { 1089 "2.5V", "2.1V", "1.8V", "Vdd"}; 1090 1091 static struct soc_enum const mic_bias_2_enum = 1092 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2, 1093 ARRAY_SIZE(mic_bias_txt), mic_bias_txt); 1094 1095 static struct soc_enum const mic_bias_1_enum = 1096 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1, 1097 ARRAY_SIZE(mic_bias_txt), mic_bias_txt); 1098 1099 /* R_PGACTL0 PG 1 ADDR 0x0D */ 1100 /* R_PGACTL1 PG 1 ADDR 0x0E */ 1101 /* R_PGACTL2 PG 1 ADDR 0x0F */ 1102 /* R_PGACTL3 PG 1 ADDR 0x10 */ 1103 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0); 1104 1105 /* R_ICH0VOL PG1 ADDR 0x12 */ 1106 /* R_ICH1VOL PG1 ADDR 0x13 */ 1107 /* R_ICH2VOL PG1 ADDR 0x14 */ 1108 /* R_ICH3VOL PG1 ADDR 0x15 */ 1109 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400); 1110 1111 /* R_ASRCILVOL PG1 ADDR 0x16 */ 1112 /* R_ASRCIRVOL PG1 ADDR 0x17 */ 1113 /* R_ASRCOLVOL PG1 ADDR 0x18 */ 1114 /* R_ASRCORVOL PG1 ADDR 0x19 */ 1115 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600); 1116 1117 /* R_ALCCTL0 PG1 ADDR 0x1D */ 1118 static char const * const alc_mode_txt[] = { 1119 "ALC", "Limiter"}; 1120 1121 static struct soc_enum const alc_mode_enum = 1122 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE, 1123 ARRAY_SIZE(alc_mode_txt), alc_mode_txt); 1124 1125 static char const * const alc_ref_text[] = { 1126 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"}; 1127 1128 static struct soc_enum const alc_ref_enum = 1129 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF, 1130 ARRAY_SIZE(alc_ref_text), alc_ref_text); 1131 1132 /* R_ALCCTL1 PG 1 ADDR 0x1E */ 1133 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0); 1134 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0); 1135 1136 /* R_ALCCTL2 PG 1 ADDR 0x1F */ 1137 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0); 1138 1139 /* R_NGATE PG 1 ADDR 0x21 */ 1140 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0); 1141 1142 static char const * const ngate_type_txt[] = { 1143 "PGA Constant", "ADC Mute"}; 1144 1145 static struct soc_enum const ngate_type_enum = 1146 SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG, 1147 ARRAY_SIZE(ngate_type_txt), ngate_type_txt); 1148 1149 /* R_DMICCTL PG 1 ADDR 0x22 */ 1150 static char const * const dmic_mono_sel_txt[] = { 1151 "Stereo", "Mono"}; 1152 1153 static struct soc_enum const dmic_mono_sel_enum = 1154 SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO, 1155 ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt); 1156 1157 /* R_DACCTL PG 2 ADDR 0x01 */ 1158 static struct soc_enum const dac_pol_r_enum = 1159 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR, 1160 ARRAY_SIZE(pol_txt), pol_txt); 1161 1162 static struct soc_enum const dac_pol_l_enum = 1163 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL, 1164 ARRAY_SIZE(pol_txt), pol_txt); 1165 1166 static char const * const dac_dith_txt[] = { 1167 "Half", "Full", "Disabled", "Static"}; 1168 1169 static struct soc_enum const dac_dith_enum = 1170 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH, 1171 ARRAY_SIZE(dac_dith_txt), dac_dith_txt); 1172 1173 /* R_SPKCTL PG 2 ADDR 0x02 */ 1174 static struct soc_enum const spk_pol_r_enum = 1175 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR, 1176 ARRAY_SIZE(pol_txt), pol_txt); 1177 1178 static struct soc_enum const spk_pol_l_enum = 1179 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL, 1180 ARRAY_SIZE(pol_txt), pol_txt); 1181 1182 /* R_SUBCTL PG 2 ADDR 0x03 */ 1183 static struct soc_enum const sub_pol_enum = 1184 SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL, 1185 ARRAY_SIZE(pol_txt), pol_txt); 1186 1187 /* R_MVOLL PG 2 ADDR 0x08 */ 1188 /* R_MVOLR PG 2 ADDR 0x09 */ 1189 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0); 1190 1191 /* R_HPVOLL PG 2 ADDR 0x0A */ 1192 /* R_HPVOLR PG 2 ADDR 0x0B */ 1193 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0); 1194 1195 /* R_SPKVOLL PG 2 ADDR 0x0C */ 1196 /* R_SPKVOLR PG 2 ADDR 0x0D */ 1197 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0); 1198 1199 /* R_SPKEQFILT PG 3 ADDR 0x01 */ 1200 static char const * const eq_txt[] = { 1201 "Pre Scale", 1202 "Pre Scale + EQ Band 0", 1203 "Pre Scale + EQ Band 0 - 1", 1204 "Pre Scale + EQ Band 0 - 2", 1205 "Pre Scale + EQ Band 0 - 3", 1206 "Pre Scale + EQ Band 0 - 4", 1207 "Pre Scale + EQ Band 0 - 5", 1208 }; 1209 1210 static struct soc_enum const spk_eq_enums[] = { 1211 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE, 1212 ARRAY_SIZE(eq_txt), eq_txt), 1213 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE, 1214 ARRAY_SIZE(eq_txt), eq_txt), 1215 }; 1216 1217 /* R_SPKMBCCTL PG 3 ADDR 0x0B */ 1218 static char const * const lvl_mode_txt[] = { 1219 "Average", "Peak"}; 1220 1221 static struct soc_enum const spk_mbc3_lvl_det_mode_enum = 1222 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3, 1223 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1224 1225 static char const * const win_sel_txt[] = { 1226 "512", "64"}; 1227 1228 static struct soc_enum const spk_mbc3_win_sel_enum = 1229 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3, 1230 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1231 1232 static struct soc_enum const spk_mbc2_lvl_det_mode_enum = 1233 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2, 1234 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1235 1236 static struct soc_enum const spk_mbc2_win_sel_enum = 1237 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2, 1238 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1239 1240 static struct soc_enum const spk_mbc1_lvl_det_mode_enum = 1241 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1, 1242 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1243 1244 static struct soc_enum const spk_mbc1_win_sel_enum = 1245 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1, 1246 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1247 1248 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */ 1249 static struct soc_enum const spk_mbc1_phase_pol_enum = 1250 SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE, 1251 ARRAY_SIZE(pol_txt), pol_txt); 1252 1253 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0); 1254 1255 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */ 1256 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0); 1257 1258 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */ 1259 static char const * const comp_rat_txt[] = { 1260 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", 1261 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", 1262 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"}; 1263 1264 static struct soc_enum const spk_mbc1_comp_rat_enum = 1265 SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO, 1266 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1267 1268 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */ 1269 static struct soc_enum const spk_mbc2_phase_pol_enum = 1270 SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE, 1271 ARRAY_SIZE(pol_txt), pol_txt); 1272 1273 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */ 1274 static struct soc_enum const spk_mbc2_comp_rat_enum = 1275 SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO, 1276 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1277 1278 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */ 1279 static struct soc_enum const spk_mbc3_phase_pol_enum = 1280 SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE, 1281 ARRAY_SIZE(pol_txt), pol_txt); 1282 1283 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */ 1284 static struct soc_enum const spk_mbc3_comp_rat_enum = 1285 SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO, 1286 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1287 1288 /* R_SPKCLECTL PG 3 ADDR 0x21 */ 1289 static struct soc_enum const spk_cle_lvl_mode_enum = 1290 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE, 1291 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1292 1293 static struct soc_enum const spk_cle_win_sel_enum = 1294 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL, 1295 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1296 1297 /* R_SPKCLEMUG PG 3 ADDR 0x22 */ 1298 static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650); 1299 1300 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */ 1301 static struct soc_enum const spk_comp_rat_enum = 1302 SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO, 1303 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1304 1305 /* R_SPKEXPTHR PG 3 ADDR 0x2F */ 1306 static char const * const exp_rat_txt[] = { 1307 "Reserved", "Reserved", "1:2", "1:3", 1308 "1:4", "1:5", "1:6", "1:7"}; 1309 1310 static struct soc_enum const spk_exp_rat_enum = 1311 SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO, 1312 ARRAY_SIZE(exp_rat_txt), exp_rat_txt); 1313 1314 /* R_DACEQFILT PG 4 ADDR 0x01 */ 1315 static struct soc_enum const dac_eq_enums[] = { 1316 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE, 1317 ARRAY_SIZE(eq_txt), eq_txt), 1318 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE, 1319 ARRAY_SIZE(eq_txt), eq_txt), 1320 }; 1321 1322 /* R_DACMBCCTL PG 4 ADDR 0x0B */ 1323 static struct soc_enum const dac_mbc3_lvl_det_mode_enum = 1324 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, 1325 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1326 1327 static struct soc_enum const dac_mbc3_win_sel_enum = 1328 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, 1329 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1330 1331 static struct soc_enum const dac_mbc2_lvl_det_mode_enum = 1332 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, 1333 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1334 1335 static struct soc_enum const dac_mbc2_win_sel_enum = 1336 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, 1337 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1338 1339 static struct soc_enum const dac_mbc1_lvl_det_mode_enum = 1340 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, 1341 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1342 1343 static struct soc_enum const dac_mbc1_win_sel_enum = 1344 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, 1345 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1346 1347 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */ 1348 static struct soc_enum const dac_mbc1_phase_pol_enum = 1349 SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE, 1350 ARRAY_SIZE(pol_txt), pol_txt); 1351 1352 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */ 1353 static struct soc_enum const dac_mbc1_comp_rat_enum = 1354 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO, 1355 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1356 1357 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */ 1358 static struct soc_enum const dac_mbc2_phase_pol_enum = 1359 SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE, 1360 ARRAY_SIZE(pol_txt), pol_txt); 1361 1362 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */ 1363 static struct soc_enum const dac_mbc2_comp_rat_enum = 1364 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO, 1365 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1366 1367 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */ 1368 static struct soc_enum const dac_mbc3_phase_pol_enum = 1369 SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE, 1370 ARRAY_SIZE(pol_txt), pol_txt); 1371 1372 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */ 1373 static struct soc_enum const dac_mbc3_comp_rat_enum = 1374 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO, 1375 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1376 1377 /* R_DACCLECTL PG 4 ADDR 0x21 */ 1378 static struct soc_enum const dac_cle_lvl_mode_enum = 1379 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE, 1380 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1381 1382 static struct soc_enum const dac_cle_win_sel_enum = 1383 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL, 1384 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1385 1386 /* R_DACCOMPRAT PG 4 ADDR 0x24 */ 1387 static struct soc_enum const dac_comp_rat_enum = 1388 SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO, 1389 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1390 1391 /* R_DACEXPRAT PG 4 ADDR 0x30 */ 1392 static struct soc_enum const dac_exp_rat_enum = 1393 SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO, 1394 ARRAY_SIZE(exp_rat_txt), exp_rat_txt); 1395 1396 /* R_SUBEQFILT PG 5 ADDR 0x01 */ 1397 static struct soc_enum const sub_eq_enums[] = { 1398 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE, 1399 ARRAY_SIZE(eq_txt), eq_txt), 1400 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE, 1401 ARRAY_SIZE(eq_txt), eq_txt), 1402 }; 1403 1404 /* R_SUBMBCCTL PG 5 ADDR 0x0B */ 1405 static struct soc_enum const sub_mbc3_lvl_det_mode_enum = 1406 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3, 1407 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1408 1409 static struct soc_enum const sub_mbc3_win_sel_enum = 1410 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3, 1411 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1412 1413 static struct soc_enum const sub_mbc2_lvl_det_mode_enum = 1414 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2, 1415 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1416 1417 static struct soc_enum const sub_mbc2_win_sel_enum = 1418 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2, 1419 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1420 1421 static struct soc_enum const sub_mbc1_lvl_det_mode_enum = 1422 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1, 1423 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1424 1425 static struct soc_enum const sub_mbc1_win_sel_enum = 1426 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1, 1427 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1428 1429 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */ 1430 static struct soc_enum const sub_mbc1_phase_pol_enum = 1431 SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE, 1432 ARRAY_SIZE(pol_txt), pol_txt); 1433 1434 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */ 1435 static struct soc_enum const sub_mbc1_comp_rat_enum = 1436 SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO, 1437 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1438 1439 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */ 1440 static struct soc_enum const sub_mbc2_phase_pol_enum = 1441 SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE, 1442 ARRAY_SIZE(pol_txt), pol_txt); 1443 1444 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */ 1445 static struct soc_enum const sub_mbc2_comp_rat_enum = 1446 SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO, 1447 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1448 1449 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */ 1450 static struct soc_enum const sub_mbc3_phase_pol_enum = 1451 SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE, 1452 ARRAY_SIZE(pol_txt), pol_txt); 1453 1454 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */ 1455 static struct soc_enum const sub_mbc3_comp_rat_enum = 1456 SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO, 1457 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1458 1459 /* R_SUBCLECTL PG 5 ADDR 0x21 */ 1460 static struct soc_enum const sub_cle_lvl_mode_enum = 1461 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE, 1462 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt); 1463 static struct soc_enum const sub_cle_win_sel_enum = 1464 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL, 1465 ARRAY_SIZE(win_sel_txt), win_sel_txt); 1466 1467 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */ 1468 static struct soc_enum const sub_comp_rat_enum = 1469 SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO, 1470 ARRAY_SIZE(comp_rat_txt), comp_rat_txt); 1471 1472 /* R_SUBEXPRAT PG 5 ADDR 0x30 */ 1473 static struct soc_enum const sub_exp_rat_enum = 1474 SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO, 1475 ARRAY_SIZE(exp_rat_txt), exp_rat_txt); 1476 1477 static int bytes_info_ext(struct snd_kcontrol *kcontrol, 1478 struct snd_ctl_elem_info *ucontrol) 1479 { 1480 struct coeff_ram_ctl *ctl = 1481 (struct coeff_ram_ctl *)kcontrol->private_value; 1482 struct soc_bytes_ext *params = &ctl->bytes_ext; 1483 1484 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1485 ucontrol->count = params->max; 1486 1487 return 0; 1488 } 1489 1490 /* CH 0_1 Input Mux */ 1491 static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"}; 1492 1493 static struct soc_enum const ch_0_1_mux_enum = 1494 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 1495 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt); 1496 1497 static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum = 1498 SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum); 1499 1500 /* CH 2_3 Input Mux */ 1501 static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"}; 1502 1503 static struct soc_enum const ch_2_3_mux_enum = 1504 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 1505 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt); 1506 1507 static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum = 1508 SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum); 1509 1510 /* CH 4_5 Input Mux */ 1511 static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"}; 1512 1513 static struct soc_enum const ch_4_5_mux_enum = 1514 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 1515 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt); 1516 1517 static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum = 1518 SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum); 1519 1520 #define COEFF_RAM_CTL(xname, xcount, xaddr) \ 1521 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1522 .info = bytes_info_ext, \ 1523 .get = coeff_ram_get, .put = coeff_ram_put, \ 1524 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ 1525 .addr = xaddr, \ 1526 .bytes_ext = {.max = xcount, }, \ 1527 } \ 1528 } 1529 1530 static struct snd_kcontrol_new const tscs454_snd_controls[] = { 1531 /* R_PLLCTL PG 0 ADDR 0x15 */ 1532 SOC_ENUM("PLL BCLK Input", bclk_sel_enum), 1533 /* R_ISRC PG 0 ADDR 0x16 */ 1534 SOC_ENUM("Internal Rate", isrc_br_enum), 1535 SOC_ENUM("Internal Rate Multiple", isrc_bm_enum), 1536 /* R_SCLKCTL PG 0 ADDR 0x18 */ 1537 SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum), 1538 SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum), 1539 /* R_ASRC PG 0 ADDR 0x28 */ 1540 SOC_SINGLE("ASRC Out High Bandwidth Switch", 1541 R_ASRC, FB_ASRC_ASRCOBW, 1, 0), 1542 SOC_SINGLE("ASRC In High Bandwidth Switch", 1543 R_ASRC, FB_ASRC_ASRCIBW, 1, 0), 1544 /* R_I2SIDCTL PG 0 ADDR 0x38 */ 1545 SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]), 1546 SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]), 1547 SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]), 1548 /* R_I2SODCTL PG 0 ADDR 0x39 */ 1549 SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]), 1550 SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]), 1551 SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]), 1552 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ 1553 SOC_ENUM("ASRC In", asrc_in_mux_enum), 1554 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ 1555 SOC_ENUM("ASRC Out", asrc_out_mux_enum), 1556 /* R_HSDCTL1 PG 1 ADDR 0x01 */ 1557 SOC_ENUM("Headphone Jack Type", hp_jack_type_enum), 1558 SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum), 1559 SOC_SINGLE("Headphone Detection Switch", 1560 R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0), 1561 SOC_SINGLE("Headset OMTP/CTIA Switch", 1562 R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0), 1563 /* R_HSDCTL1 PG 1 ADDR 0x02 */ 1564 SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum), 1565 SOC_SINGLE("Manual Mic Bias Switch", 1566 R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0), 1567 SOC_SINGLE("Ring/Sleeve Auto Switch", 1568 R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0), 1569 SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum), 1570 /* R_CH0AIC PG 1 ADDR 0x06 */ 1571 SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC, 1572 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1573 /* R_CH1AIC PG 1 ADDR 0x07 */ 1574 SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC, 1575 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1576 /* R_CH2AIC PG 1 ADDR 0x08 */ 1577 SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC, 1578 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1579 /* R_CH3AIC PG 1 ADDR 0x09 */ 1580 SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC, 1581 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr), 1582 /* R_ICTL0 PG 1 ADDR 0x0A */ 1583 SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum), 1584 SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum), 1585 SOC_ENUM("Input Processor Channel 0/1 Operation", 1586 in_proc_ch01_sel_enum), 1587 SOC_SINGLE("Input Channel 1 Mute Switch", 1588 R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0), 1589 SOC_SINGLE("Input Channel 0 Mute Switch", 1590 R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0), 1591 SOC_SINGLE("Input Channel 1 HPF Disable Switch", 1592 R_ICTL0, FB_ICTL0_IN1HP, 1, 0), 1593 SOC_SINGLE("Input Channel 0 HPF Disable Switch", 1594 R_ICTL0, FB_ICTL0_IN0HP, 1, 0), 1595 /* R_ICTL1 PG 1 ADDR 0x0B */ 1596 SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum), 1597 SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum), 1598 SOC_ENUM("Input Processor Channel 2/3 Operation", 1599 in_proc_ch23_sel_enum), 1600 SOC_SINGLE("Input Channel 3 Mute Switch", 1601 R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0), 1602 SOC_SINGLE("Input Channel 2 Mute Switch", 1603 R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0), 1604 SOC_SINGLE("Input Channel 3 HPF Disable Switch", 1605 R_ICTL1, FB_ICTL1_IN3HP, 1, 0), 1606 SOC_SINGLE("Input Channel 2 HPF Disable Switch", 1607 R_ICTL1, FB_ICTL1_IN2HP, 1, 0), 1608 /* R_MICBIAS PG 1 ADDR 0x0C */ 1609 SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum), 1610 SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum), 1611 /* R_PGACTL0 PG 1 ADDR 0x0D */ 1612 SOC_SINGLE("Input Channel 0 PGA Mute Switch", 1613 R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0), 1614 SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0, 1615 FB_PGACTL_PGAVOL, 1616 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1617 /* R_PGACTL1 PG 1 ADDR 0x0E */ 1618 SOC_SINGLE("Input Channel 1 PGA Mute Switch", 1619 R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0), 1620 SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1, 1621 FB_PGACTL_PGAVOL, 1622 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1623 /* R_PGACTL2 PG 1 ADDR 0x0F */ 1624 SOC_SINGLE("Input Channel 2 PGA Mute Switch", 1625 R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0), 1626 SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2, 1627 FB_PGACTL_PGAVOL, 1628 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1629 /* R_PGACTL3 PG 1 ADDR 0x10 */ 1630 SOC_SINGLE("Input Channel 3 PGA Mute Switch", 1631 R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0), 1632 SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3, 1633 FB_PGACTL_PGAVOL, 1634 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr), 1635 /* R_ICH0VOL PG 1 ADDR 0x12 */ 1636 SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL, 1637 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1638 /* R_ICH1VOL PG 1 ADDR 0x13 */ 1639 SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL, 1640 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1641 /* R_ICH2VOL PG 1 ADDR 0x14 */ 1642 SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL, 1643 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1644 /* R_ICH3VOL PG 1 ADDR 0x15 */ 1645 SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL, 1646 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr), 1647 /* R_ASRCILVOL PG 1 ADDR 0x16 */ 1648 SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL, 1649 FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL, 1650 0, asrc_vol_tlv_arr), 1651 /* R_ASRCIRVOL PG 1 ADDR 0x17 */ 1652 SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL, 1653 FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL, 1654 0, asrc_vol_tlv_arr), 1655 /* R_ASRCOLVOL PG 1 ADDR 0x18 */ 1656 SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL, 1657 FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL, 1658 0, asrc_vol_tlv_arr), 1659 /* R_ASRCORVOL PG 1 ADDR 0x19 */ 1660 SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL, 1661 FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL, 1662 0, asrc_vol_tlv_arr), 1663 /* R_IVOLCTLU PG 1 ADDR 0x1C */ 1664 /* R_ALCCTL0 PG 1 ADDR 0x1D */ 1665 SOC_ENUM("ALC Mode", alc_mode_enum), 1666 SOC_ENUM("ALC Reference", alc_ref_enum), 1667 SOC_SINGLE("Input Channel 3 ALC Switch", 1668 R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0), 1669 SOC_SINGLE("Input Channel 2 ALC Switch", 1670 R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0), 1671 SOC_SINGLE("Input Channel 1 ALC Switch", 1672 R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0), 1673 SOC_SINGLE("Input Channel 0 ALC Switch", 1674 R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0), 1675 /* R_ALCCTL1 PG 1 ADDR 0x1E */ 1676 SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1, 1677 FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN, 1678 0, alc_max_gain_tlv_arr), 1679 SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1, 1680 FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL, 1681 0, alc_target_tlv_arr), 1682 /* R_ALCCTL2 PG 1 ADDR 0x1F */ 1683 SOC_SINGLE("ALC Zero Cross Switch", 1684 R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0), 1685 SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2, 1686 FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN, 1687 0, alc_min_gain_tlv_arr), 1688 SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2, 1689 FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0), 1690 /* R_ALCCTL3 PG 1 ADDR 0x20 */ 1691 SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3, 1692 FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0), 1693 SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3, 1694 FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0), 1695 /* R_NGATE PG 1 ADDR 0x21 */ 1696 SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE, 1697 FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr), 1698 SOC_ENUM("Noise Gate Type", ngate_type_enum), 1699 SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0), 1700 /* R_DMICCTL PG 1 ADDR 0x22 */ 1701 SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0), 1702 SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0), 1703 SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum), 1704 /* R_DACCTL PG 2 ADDR 0x01 */ 1705 SOC_ENUM("DAC Polarity Left", dac_pol_r_enum), 1706 SOC_ENUM("DAC Polarity Right", dac_pol_l_enum), 1707 SOC_ENUM("DAC Dither", dac_dith_enum), 1708 SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0), 1709 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0), 1710 /* R_SPKCTL PG 2 ADDR 0x02 */ 1711 SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum), 1712 SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum), 1713 SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0), 1714 SOC_SINGLE("Speaker De-Emphasis Switch", 1715 R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0), 1716 /* R_SUBCTL PG 2 ADDR 0x03 */ 1717 SOC_ENUM("Sub Polarity", sub_pol_enum), 1718 SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0), 1719 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0), 1720 /* R_DCCTL PG 2 ADDR 0x04 */ 1721 SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1), 1722 SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1), 1723 SOC_SINGLE("Speaker DC Removal Switch", 1724 R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1), 1725 SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL, 1726 FM_DCCTL_DCCOEFSEL, 0), 1727 /* R_OVOLCTLU PG 2 ADDR 0x06 */ 1728 SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0), 1729 /* R_MVOLL PG 2 ADDR 0x08 */ 1730 /* R_MVOLR PG 2 ADDR 0x09 */ 1731 SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR, 1732 FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr), 1733 /* R_HPVOLL PG 2 ADDR 0x0A */ 1734 /* R_HPVOLR PG 2 ADDR 0x0B */ 1735 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR, 1736 FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0, 1737 hp_vol_tlv_arr), 1738 /* R_SPKVOLL PG 2 ADDR 0x0C */ 1739 /* R_SPKVOLR PG 2 ADDR 0x0D */ 1740 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR, 1741 FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0, 1742 spk_vol_tlv_arr), 1743 /* R_SUBVOL PG 2 ADDR 0x10 */ 1744 SOC_SINGLE_TLV("Sub Volume", R_SUBVOL, 1745 FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr), 1746 /* R_SPKEQFILT PG 3 ADDR 0x01 */ 1747 SOC_SINGLE("Speaker EQ 2 Switch", 1748 R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0), 1749 SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]), 1750 SOC_SINGLE("Speaker EQ 1 Switch", 1751 R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0), 1752 SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]), 1753 /* R_SPKMBCEN PG 3 ADDR 0x0A */ 1754 SOC_SINGLE("Speaker MBC 3 Switch", 1755 R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0), 1756 SOC_SINGLE("Speaker MBC 2 Switch", 1757 R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0), 1758 SOC_SINGLE("Speaker MBC 1 Switch", 1759 R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0), 1760 /* R_SPKMBCCTL PG 3 ADDR 0x0B */ 1761 SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum), 1762 SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum), 1763 SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum), 1764 SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum), 1765 SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum), 1766 SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum), 1767 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */ 1768 SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum), 1769 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1, 1770 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, 1771 0, mbc_mug_tlv_arr), 1772 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */ 1773 SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume", 1774 R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, 1775 0, thr_tlv_arr), 1776 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */ 1777 SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum), 1778 /* R_SPKMBCATK1L PG 3 ADDR 0x0F */ 1779 /* R_SPKMBCATK1H PG 3 ADDR 0x10 */ 1780 SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2), 1781 /* R_SPKMBCREL1L PG 3 ADDR 0x11 */ 1782 /* R_SPKMBCREL1H PG 3 ADDR 0x12 */ 1783 SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2), 1784 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */ 1785 SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum), 1786 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2, 1787 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, 1788 0, mbc_mug_tlv_arr), 1789 /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */ 1790 SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume", 1791 R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, 1792 0, thr_tlv_arr), 1793 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */ 1794 SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum), 1795 /* R_SPKMBCATK2L PG 3 ADDR 0x16 */ 1796 /* R_SPKMBCATK2H PG 3 ADDR 0x17 */ 1797 SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2), 1798 /* R_SPKMBCREL2L PG 3 ADDR 0x18 */ 1799 /* R_SPKMBCREL2H PG 3 ADDR 0x19 */ 1800 SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2), 1801 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */ 1802 SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum), 1803 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3, 1804 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN, 1805 0, mbc_mug_tlv_arr), 1806 /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */ 1807 SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3, 1808 FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH, 1809 0, thr_tlv_arr), 1810 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */ 1811 SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum), 1812 /* R_SPKMBCATK3L PG 3 ADDR 0x1D */ 1813 /* R_SPKMBCATK3H PG 3 ADDR 0x1E */ 1814 SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3), 1815 /* R_SPKMBCREL3L PG 3 ADDR 0x1F */ 1816 /* R_SPKMBCREL3H PG 3 ADDR 0x20 */ 1817 SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3), 1818 /* R_SPKCLECTL PG 3 ADDR 0x21 */ 1819 SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum), 1820 SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum), 1821 SOC_SINGLE("Speaker CLE Expander Switch", 1822 R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0), 1823 SOC_SINGLE("Speaker CLE Limiter Switch", 1824 R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0), 1825 SOC_SINGLE("Speaker CLE Compressor Switch", 1826 R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0), 1827 /* R_SPKCLEMUG PG 3 ADDR 0x22 */ 1828 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG, 1829 FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN, 1830 0, cle_mug_tlv_arr), 1831 /* R_SPKCOMPTHR PG 3 ADDR 0x23 */ 1832 SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR, 1833 FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH, 1834 0, thr_tlv_arr), 1835 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */ 1836 SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum), 1837 /* R_SPKCOMPATKL PG 3 ADDR 0x25 */ 1838 /* R_SPKCOMPATKH PG 3 ADDR 0x26 */ 1839 SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2), 1840 /* R_SPKCOMPRELL PG 3 ADDR 0x27 */ 1841 /* R_SPKCOMPRELH PG 3 ADDR 0x28 */ 1842 SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2), 1843 /* R_SPKLIMTHR PG 3 ADDR 0x29 */ 1844 SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR, 1845 FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH, 1846 0, thr_tlv_arr), 1847 /* R_SPKLIMTGT PG 3 ADDR 0x2A */ 1848 SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT, 1849 FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET, 1850 0, thr_tlv_arr), 1851 /* R_SPKLIMATKL PG 3 ADDR 0x2B */ 1852 /* R_SPKLIMATKH PG 3 ADDR 0x2C */ 1853 SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2), 1854 /* R_SPKLIMRELL PG 3 ADDR 0x2D */ 1855 /* R_SPKLIMRELR PG 3 ADDR 0x2E */ 1856 SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2), 1857 /* R_SPKEXPTHR PG 3 ADDR 0x2F */ 1858 SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR, 1859 FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH, 1860 0, thr_tlv_arr), 1861 /* R_SPKEXPRAT PG 3 ADDR 0x30 */ 1862 SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum), 1863 /* R_SPKEXPATKL PG 3 ADDR 0x31 */ 1864 /* R_SPKEXPATKR PG 3 ADDR 0x32 */ 1865 SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2), 1866 /* R_SPKEXPRELL PG 3 ADDR 0x33 */ 1867 /* R_SPKEXPRELR PG 3 ADDR 0x34 */ 1868 SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2), 1869 /* R_SPKFXCTL PG 3 ADDR 0x35 */ 1870 SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0), 1871 SOC_SINGLE("Speaker Treble Enhancement Switch", 1872 R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0), 1873 SOC_SINGLE("Speaker Treble NLF Switch", 1874 R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1), 1875 SOC_SINGLE("Speaker Bass Enhancement Switch", 1876 R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0), 1877 SOC_SINGLE("Speaker Bass NLF Switch", 1878 R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1), 1879 /* R_DACEQFILT PG 4 ADDR 0x01 */ 1880 SOC_SINGLE("DAC EQ 2 Switch", 1881 R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0), 1882 SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]), 1883 SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0), 1884 SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]), 1885 /* R_DACMBCEN PG 4 ADDR 0x0A */ 1886 SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), 1887 SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), 1888 SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), 1889 /* R_DACMBCCTL PG 4 ADDR 0x0B */ 1890 SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum), 1891 SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum), 1892 SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum), 1893 SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum), 1894 SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum), 1895 SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum), 1896 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */ 1897 SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum), 1898 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1, 1899 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, 1900 0, mbc_mug_tlv_arr), 1901 /* R_DACMBCTHR1 PG 4 ADDR 0x0D */ 1902 SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1, 1903 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, 1904 0, thr_tlv_arr), 1905 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */ 1906 SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum), 1907 /* R_DACMBCATK1L PG 4 ADDR 0x0F */ 1908 /* R_DACMBCATK1H PG 4 ADDR 0x10 */ 1909 SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2), 1910 /* R_DACMBCREL1L PG 4 ADDR 0x11 */ 1911 /* R_DACMBCREL1H PG 4 ADDR 0x12 */ 1912 SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2), 1913 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */ 1914 SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum), 1915 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2, 1916 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, 1917 0, mbc_mug_tlv_arr), 1918 /* R_DACMBCTHR2 PG 4 ADDR 0x14 */ 1919 SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2, 1920 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, 1921 0, thr_tlv_arr), 1922 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */ 1923 SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum), 1924 /* R_DACMBCATK2L PG 4 ADDR 0x16 */ 1925 /* R_DACMBCATK2H PG 4 ADDR 0x17 */ 1926 SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2), 1927 /* R_DACMBCREL2L PG 4 ADDR 0x18 */ 1928 /* R_DACMBCREL2H PG 4 ADDR 0x19 */ 1929 SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2), 1930 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */ 1931 SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum), 1932 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3, 1933 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN, 1934 0, mbc_mug_tlv_arr), 1935 /* R_DACMBCTHR3 PG 4 ADDR 0x1B */ 1936 SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3, 1937 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH, 1938 0, thr_tlv_arr), 1939 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */ 1940 SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum), 1941 /* R_DACMBCATK3L PG 4 ADDR 0x1D */ 1942 /* R_DACMBCATK3H PG 4 ADDR 0x1E */ 1943 SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3), 1944 /* R_DACMBCREL3L PG 4 ADDR 0x1F */ 1945 /* R_DACMBCREL3H PG 4 ADDR 0x20 */ 1946 SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3), 1947 /* R_DACCLECTL PG 4 ADDR 0x21 */ 1948 SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum), 1949 SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum), 1950 SOC_SINGLE("DAC CLE Expander Switch", 1951 R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0), 1952 SOC_SINGLE("DAC CLE Limiter Switch", 1953 R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0), 1954 SOC_SINGLE("DAC CLE Compressor Switch", 1955 R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0), 1956 /* R_DACCLEMUG PG 4 ADDR 0x22 */ 1957 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG, 1958 FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN, 1959 0, cle_mug_tlv_arr), 1960 /* R_DACCOMPTHR PG 4 ADDR 0x23 */ 1961 SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR, 1962 FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH, 1963 0, thr_tlv_arr), 1964 /* R_DACCOMPRAT PG 4 ADDR 0x24 */ 1965 SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum), 1966 /* R_DACCOMPATKL PG 4 ADDR 0x25 */ 1967 /* R_DACCOMPATKH PG 4 ADDR 0x26 */ 1968 SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2), 1969 /* R_DACCOMPRELL PG 4 ADDR 0x27 */ 1970 /* R_DACCOMPRELH PG 4 ADDR 0x28 */ 1971 SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2), 1972 /* R_DACLIMTHR PG 4 ADDR 0x29 */ 1973 SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR, 1974 FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH, 1975 0, thr_tlv_arr), 1976 /* R_DACLIMTGT PG 4 ADDR 0x2A */ 1977 SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT, 1978 FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET, 1979 0, thr_tlv_arr), 1980 /* R_DACLIMATKL PG 4 ADDR 0x2B */ 1981 /* R_DACLIMATKH PG 4 ADDR 0x2C */ 1982 SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2), 1983 /* R_DACLIMRELL PG 4 ADDR 0x2D */ 1984 /* R_DACLIMRELR PG 4 ADDR 0x2E */ 1985 SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2), 1986 /* R_DACEXPTHR PG 4 ADDR 0x2F */ 1987 SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR, 1988 FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH, 1989 0, thr_tlv_arr), 1990 /* R_DACEXPRAT PG 4 ADDR 0x30 */ 1991 SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum), 1992 /* R_DACEXPATKL PG 4 ADDR 0x31 */ 1993 /* R_DACEXPATKR PG 4 ADDR 0x32 */ 1994 SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2), 1995 /* R_DACEXPRELL PG 4 ADDR 0x33 */ 1996 /* R_DACEXPRELR PG 4 ADDR 0x34 */ 1997 SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2), 1998 /* R_DACFXCTL PG 4 ADDR 0x35 */ 1999 SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0), 2000 SOC_SINGLE("DAC Treble Enhancement Switch", 2001 R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0), 2002 SOC_SINGLE("DAC Treble NLF Switch", 2003 R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1), 2004 SOC_SINGLE("DAC Bass Enhancement Switch", 2005 R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0), 2006 SOC_SINGLE("DAC Bass NLF Switch", 2007 R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1), 2008 /* R_SUBEQFILT PG 5 ADDR 0x01 */ 2009 SOC_SINGLE("Sub EQ 2 Switch", 2010 R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0), 2011 SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]), 2012 SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0), 2013 SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]), 2014 /* R_SUBMBCEN PG 5 ADDR 0x0A */ 2015 SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0), 2016 SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0), 2017 SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0), 2018 /* R_SUBMBCCTL PG 5 ADDR 0x0B */ 2019 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum), 2020 SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum), 2021 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum), 2022 SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum), 2023 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum), 2024 SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum), 2025 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */ 2026 SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum), 2027 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1, 2028 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, 2029 0, mbc_mug_tlv_arr), 2030 /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */ 2031 SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1, 2032 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, 2033 0, thr_tlv_arr), 2034 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */ 2035 SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum), 2036 /* R_SUBMBCATK1L PG 5 ADDR 0x0F */ 2037 /* R_SUBMBCATK1H PG 5 ADDR 0x10 */ 2038 SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2), 2039 /* R_SUBMBCREL1L PG 5 ADDR 0x11 */ 2040 /* R_SUBMBCREL1H PG 5 ADDR 0x12 */ 2041 SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2), 2042 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */ 2043 SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum), 2044 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2, 2045 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, 2046 0, mbc_mug_tlv_arr), 2047 /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */ 2048 SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2, 2049 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, 2050 0, thr_tlv_arr), 2051 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */ 2052 SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum), 2053 /* R_SUBMBCATK2L PG 5 ADDR 0x16 */ 2054 /* R_SUBMBCATK2H PG 5 ADDR 0x17 */ 2055 SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2), 2056 /* R_SUBMBCREL2L PG 5 ADDR 0x18 */ 2057 /* R_SUBMBCREL2H PG 5 ADDR 0x19 */ 2058 SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2), 2059 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */ 2060 SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum), 2061 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3, 2062 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN, 2063 0, mbc_mug_tlv_arr), 2064 /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */ 2065 SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3, 2066 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH, 2067 0, thr_tlv_arr), 2068 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */ 2069 SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum), 2070 /* R_SUBMBCATK3L PG 5 ADDR 0x1D */ 2071 /* R_SUBMBCATK3H PG 5 ADDR 0x1E */ 2072 SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3), 2073 /* R_SUBMBCREL3L PG 5 ADDR 0x1F */ 2074 /* R_SUBMBCREL3H PG 5 ADDR 0x20 */ 2075 SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3), 2076 /* R_SUBCLECTL PG 5 ADDR 0x21 */ 2077 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum), 2078 SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum), 2079 SOC_SINGLE("Sub CLE Expander Switch", 2080 R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0), 2081 SOC_SINGLE("Sub CLE Limiter Switch", 2082 R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0), 2083 SOC_SINGLE("Sub CLE Compressor Switch", 2084 R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0), 2085 /* R_SUBCLEMUG PG 5 ADDR 0x22 */ 2086 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG, 2087 FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN, 2088 0, cle_mug_tlv_arr), 2089 /* R_SUBCOMPTHR PG 5 ADDR 0x23 */ 2090 SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR, 2091 FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH, 2092 0, thr_tlv_arr), 2093 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */ 2094 SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum), 2095 /* R_SUBCOMPATKL PG 5 ADDR 0x25 */ 2096 /* R_SUBCOMPATKH PG 5 ADDR 0x26 */ 2097 SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2), 2098 /* R_SUBCOMPRELL PG 5 ADDR 0x27 */ 2099 /* R_SUBCOMPRELH PG 5 ADDR 0x28 */ 2100 SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2), 2101 /* R_SUBLIMTHR PG 5 ADDR 0x29 */ 2102 SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR, 2103 FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH, 2104 0, thr_tlv_arr), 2105 /* R_SUBLIMTGT PG 5 ADDR 0x2A */ 2106 SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT, 2107 FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET, 2108 0, thr_tlv_arr), 2109 /* R_SUBLIMATKL PG 5 ADDR 0x2B */ 2110 /* R_SUBLIMATKH PG 5 ADDR 0x2C */ 2111 SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2), 2112 /* R_SUBLIMRELL PG 5 ADDR 0x2D */ 2113 /* R_SUBLIMRELR PG 5 ADDR 0x2E */ 2114 SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2), 2115 /* R_SUBEXPTHR PG 5 ADDR 0x2F */ 2116 SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR, 2117 FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH, 2118 0, thr_tlv_arr), 2119 /* R_SUBEXPRAT PG 5 ADDR 0x30 */ 2120 SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum), 2121 /* R_SUBEXPATKL PG 5 ADDR 0x31 */ 2122 /* R_SUBEXPATKR PG 5 ADDR 0x32 */ 2123 SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2), 2124 /* R_SUBEXPRELL PG 5 ADDR 0x33 */ 2125 /* R_SUBEXPRELR PG 5 ADDR 0x34 */ 2126 SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2), 2127 /* R_SUBFXCTL PG 5 ADDR 0x35 */ 2128 SOC_SINGLE("Sub Treble Enhancement Switch", 2129 R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0), 2130 SOC_SINGLE("Sub Treble NLF Switch", 2131 R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1), 2132 SOC_SINGLE("Sub Bass Enhancement Switch", 2133 R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0), 2134 SOC_SINGLE("Sub Bass NLF Switch", 2135 R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1), 2136 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), 2137 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), 2138 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), 2139 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), 2140 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), 2141 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), 2142 2143 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), 2144 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), 2145 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), 2146 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), 2147 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), 2148 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), 2149 2150 COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), 2151 COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), 2152 2153 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), 2154 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), 2155 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), 2156 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), 2157 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), 2158 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), 2159 2160 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), 2161 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), 2162 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), 2163 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), 2164 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), 2165 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), 2166 2167 COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), 2168 COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), 2169 2170 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), 2171 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), 2172 2173 COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 2174 COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 2175 2176 COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 2177 2178 COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 2179 2180 COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96), 2181 2182 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), 2183 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), 2184 2185 COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 2186 COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 2187 2188 COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 2189 2190 COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 2191 2192 COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad), 2193 2194 COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae), 2195 2196 COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf), 2197 2198 COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), 2199 COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), 2200 2201 COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), 2202 COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), 2203 2204 COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), 2205 COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), 2206 2207 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), 2208 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), 2209 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), 2210 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), 2211 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), 2212 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), 2213 2214 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), 2215 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), 2216 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), 2217 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), 2218 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), 2219 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), 2220 2221 COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), 2222 COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), 2223 2224 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), 2225 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), 2226 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), 2227 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), 2228 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), 2229 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), 2230 2231 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), 2232 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), 2233 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), 2234 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), 2235 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), 2236 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), 2237 2238 COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), 2239 COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), 2240 2241 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), 2242 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), 2243 2244 COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 2245 COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 2246 2247 COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 2248 2249 COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 2250 2251 COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96), 2252 2253 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), 2254 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), 2255 2256 COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 2257 COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 2258 2259 COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 2260 2261 COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 2262 2263 COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad), 2264 2265 COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae), 2266 2267 COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf), 2268 2269 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), 2270 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), 2271 2272 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), 2273 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), 2274 2275 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), 2276 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), 2277 2278 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00), 2279 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05), 2280 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a), 2281 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f), 2282 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14), 2283 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19), 2284 2285 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20), 2286 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25), 2287 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a), 2288 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f), 2289 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34), 2290 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39), 2291 2292 COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f), 2293 COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f), 2294 2295 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40), 2296 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45), 2297 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a), 2298 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f), 2299 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54), 2300 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59), 2301 2302 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60), 2303 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65), 2304 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a), 2305 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f), 2306 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74), 2307 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79), 2308 2309 COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f), 2310 COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f), 2311 2312 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80), 2313 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85), 2314 2315 COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 2316 COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 2317 2318 COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 2319 2320 COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 2321 2322 COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96), 2323 2324 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97), 2325 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c), 2326 2327 COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 2328 COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 2329 2330 COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 2331 2332 COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 2333 2334 COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad), 2335 2336 COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae), 2337 2338 COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf), 2339 2340 COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0), 2341 COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5), 2342 2343 COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba), 2344 COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf), 2345 2346 COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4), 2347 COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9), 2348 }; 2349 2350 static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = { 2351 /* R_PLLCTL PG 0 ADDR 0x15 */ 2352 SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0, 2353 pll_power_event, 2354 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 2355 SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0, 2356 pll_power_event, 2357 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 2358 /* R_I2SPINC0 PG 0 ADDR 0x22 */ 2359 SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0, 2360 R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1), 2361 SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0, 2362 R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1), 2363 SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0, 2364 R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1), 2365 /* R_PWRM0 PG 0 ADDR 0x33 */ 2366 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL, 2367 R_PWRM0, FB_PWRM0_INPROC3PU, 0), 2368 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL, 2369 R_PWRM0, FB_PWRM0_INPROC2PU, 0), 2370 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL, 2371 R_PWRM0, FB_PWRM0_INPROC1PU, 0), 2372 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL, 2373 R_PWRM0, FB_PWRM0_INPROC0PU, 0), 2374 SND_SOC_DAPM_SUPPLY("Mic Bias 2", 2375 R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0), 2376 SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0, 2377 FB_PWRM0_MICB1PU, 0, NULL, 0), 2378 /* R_PWRM1 PG 0 ADDR 0x34 */ 2379 SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0), 2380 SND_SOC_DAPM_SUPPLY("Headphone Left Power", 2381 R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0), 2382 SND_SOC_DAPM_SUPPLY("Headphone Right Power", 2383 R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0), 2384 SND_SOC_DAPM_SUPPLY("Speaker Left Power", 2385 R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0), 2386 SND_SOC_DAPM_SUPPLY("Speaker Right Power", 2387 R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0), 2388 SND_SOC_DAPM_SUPPLY("Differential Input 2 Power", 2389 R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0), 2390 SND_SOC_DAPM_SUPPLY("Differential Input 1 Power", 2391 R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0), 2392 /* R_PWRM2 PG 0 ADDR 0x35 */ 2393 SND_SOC_DAPM_SUPPLY("DAI 3 Out Power", 2394 R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0), 2395 SND_SOC_DAPM_SUPPLY("DAI 2 Out Power", 2396 R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0), 2397 SND_SOC_DAPM_SUPPLY("DAI 1 Out Power", 2398 R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0), 2399 SND_SOC_DAPM_SUPPLY("DAI 3 In Power", 2400 R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0), 2401 SND_SOC_DAPM_SUPPLY("DAI 2 In Power", 2402 R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0), 2403 SND_SOC_DAPM_SUPPLY("DAI 1 In Power", 2404 R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0), 2405 /* R_PWRM3 PG 0 ADDR 0x36 */ 2406 SND_SOC_DAPM_SUPPLY("Line Out Left Power", 2407 R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0), 2408 SND_SOC_DAPM_SUPPLY("Line Out Right Power", 2409 R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0), 2410 /* R_PWRM4 PG 0 ADDR 0x37 */ 2411 SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0), 2412 SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0), 2413 SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0), 2414 SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0), 2415 SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0), 2416 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */ 2417 SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0, 2418 &dai2_mux_dapm_enum), 2419 SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0, 2420 &dai1_mux_dapm_enum), 2421 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */ 2422 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0, 2423 &dac_mux_dapm_enum), 2424 SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0, 2425 &dai3_mux_dapm_enum), 2426 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */ 2427 SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0, 2428 &sub_mux_dapm_enum), 2429 SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0, 2430 &classd_mux_dapm_enum), 2431 /* R_HSDCTL1 PG 1 ADDR 0x01 */ 2432 SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1, 2433 FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0), 2434 /* R_CH0AIC PG 1 ADDR 0x06 */ 2435 SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0, 2436 &in_bst_mux_ch0_dapm_enum), 2437 SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0, 2438 &adc_mux_ch0_dapm_enum), 2439 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0, 2440 &in_proc_mux_ch0_dapm_enum), 2441 /* R_CH1AIC PG 1 ADDR 0x07 */ 2442 SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0, 2443 &in_bst_mux_ch1_dapm_enum), 2444 SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0, 2445 &adc_mux_ch1_dapm_enum), 2446 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0, 2447 &in_proc_mux_ch1_dapm_enum), 2448 /* Virtual */ 2449 SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0, 2450 SND_SOC_NOPM, 0, 0), 2451 SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0, 2452 SND_SOC_NOPM, 0, 0), 2453 SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0, 2454 SND_SOC_NOPM, 0, 0), 2455 SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0), 2456 SND_SOC_DAPM_OUTPUT("Sub Out"), 2457 SND_SOC_DAPM_OUTPUT("Headphone Left"), 2458 SND_SOC_DAPM_OUTPUT("Headphone Right"), 2459 SND_SOC_DAPM_OUTPUT("Speaker Left"), 2460 SND_SOC_DAPM_OUTPUT("Speaker Right"), 2461 SND_SOC_DAPM_OUTPUT("Line Out Left"), 2462 SND_SOC_DAPM_OUTPUT("Line Out Right"), 2463 SND_SOC_DAPM_INPUT("D2S 2"), 2464 SND_SOC_DAPM_INPUT("D2S 1"), 2465 SND_SOC_DAPM_INPUT("Line In 1 Left"), 2466 SND_SOC_DAPM_INPUT("Line In 1 Right"), 2467 SND_SOC_DAPM_INPUT("Line In 2 Left"), 2468 SND_SOC_DAPM_INPUT("Line In 2 Right"), 2469 SND_SOC_DAPM_INPUT("Line In 3 Left"), 2470 SND_SOC_DAPM_INPUT("Line In 3 Right"), 2471 SND_SOC_DAPM_INPUT("DMic 1"), 2472 SND_SOC_DAPM_INPUT("DMic 2"), 2473 2474 SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0, 2475 &ch_0_1_mux_dapm_enum), 2476 SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0, 2477 &ch_2_3_mux_dapm_enum), 2478 SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0, 2479 &ch_4_5_mux_dapm_enum), 2480 }; 2481 2482 static struct snd_soc_dapm_route const tscs454_intercon[] = { 2483 /* PLLs */ 2484 {"PLLs", NULL, "PLL 1 Power", pll_connected}, 2485 {"PLLs", NULL, "PLL 2 Power", pll_connected}, 2486 /* Inputs */ 2487 {"DAI 3 In", NULL, "DAI 3 In Power"}, 2488 {"DAI 2 In", NULL, "DAI 2 In Power"}, 2489 {"DAI 1 In", NULL, "DAI 1 In Power"}, 2490 /* Outputs */ 2491 {"DAI 3 Out", NULL, "DAI 3 Out Power"}, 2492 {"DAI 2 Out", NULL, "DAI 2 Out Power"}, 2493 {"DAI 1 Out", NULL, "DAI 1 Out Power"}, 2494 /* Ch Muxing */ 2495 {"CH 0_1 Mux", "DAI 1", "DAI 1 In"}, 2496 {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"}, 2497 {"CH 2_3 Mux", "DAI 2", "DAI 2 In"}, 2498 {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"}, 2499 {"CH 4_5 Mux", "DAI 3", "DAI 2 In"}, 2500 {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"}, 2501 /* In/Out Muxing */ 2502 {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"}, 2503 {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"}, 2504 {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"}, 2505 {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"}, 2506 {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"}, 2507 {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"}, 2508 {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"}, 2509 {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"}, 2510 {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"}, 2511 /****************** 2512 * Playback Paths * 2513 ******************/ 2514 /* DAC Path */ 2515 {"DAC Mux", "CH 4_5", "CH 4_5 Mux"}, 2516 {"DAC Mux", "CH 2_3", "CH 2_3 Mux"}, 2517 {"DAC Mux", "CH 0_1", "CH 0_1 Mux"}, 2518 {"DAC Left", NULL, "DAC Mux"}, 2519 {"DAC Right", NULL, "DAC Mux"}, 2520 {"DAC Left", NULL, "PLLs"}, 2521 {"DAC Right", NULL, "PLLs"}, 2522 {"Headphone Left", NULL, "Headphone Left Power"}, 2523 {"Headphone Right", NULL, "Headphone Right Power"}, 2524 {"Headphone Left", NULL, "DAC Left"}, 2525 {"Headphone Right", NULL, "DAC Right"}, 2526 /* Line Out */ 2527 {"Line Out Left", NULL, "Line Out Left Power"}, 2528 {"Line Out Right", NULL, "Line Out Right Power"}, 2529 {"Line Out Left", NULL, "DAC Left"}, 2530 {"Line Out Right", NULL, "DAC Right"}, 2531 /* ClassD Path */ 2532 {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"}, 2533 {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"}, 2534 {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"}, 2535 {"ClassD Left", NULL, "Speaker Mux"}, 2536 {"ClassD Right", NULL, "Speaker Mux"}, 2537 {"ClassD Left", NULL, "PLLs"}, 2538 {"ClassD Right", NULL, "PLLs"}, 2539 {"Speaker Left", NULL, "Speaker Left Power"}, 2540 {"Speaker Right", NULL, "Speaker Right Power"}, 2541 {"Speaker Left", NULL, "ClassD Left"}, 2542 {"Speaker Right", NULL, "ClassD Right"}, 2543 /* Sub Path */ 2544 {"Sub Mux", "CH 4", "CH 4_5 Mux"}, 2545 {"Sub Mux", "CH 5", "CH 4_5 Mux"}, 2546 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"}, 2547 {"Sub Mux", "CH 2", "CH 2_3 Mux"}, 2548 {"Sub Mux", "CH 3", "CH 2_3 Mux"}, 2549 {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"}, 2550 {"Sub Mux", "CH 0", "CH 0_1 Mux"}, 2551 {"Sub Mux", "CH 1", "CH 0_1 Mux"}, 2552 {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"}, 2553 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"}, 2554 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"}, 2555 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"}, 2556 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"}, 2557 {"Sub Mux", "DMic 2 Left", "DMic 2"}, 2558 {"Sub Mux", "DMic 2 Right", "DMic 2"}, 2559 {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"}, 2560 {"Sub Mux", "ClassD Left", "ClassD Left"}, 2561 {"Sub Mux", "ClassD Right", "ClassD Right"}, 2562 {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"}, 2563 {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"}, 2564 {"Sub", NULL, "Sub Mux"}, 2565 {"Sub", NULL, "PLLs"}, 2566 {"Sub Out", NULL, "Sub Power"}, 2567 {"Sub Out", NULL, "Sub"}, 2568 /***************** 2569 * Capture Paths * 2570 *****************/ 2571 {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"}, 2572 {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"}, 2573 {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"}, 2574 {"Input Boost Channel 0 Mux", "D2S", "D2S 1"}, 2575 2576 {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"}, 2577 {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"}, 2578 {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"}, 2579 {"Input Boost Channel 1 Mux", "D2S", "D2S 2"}, 2580 2581 {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"}, 2582 {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"}, 2583 {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"}, 2584 {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"}, 2585 2586 {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"}, 2587 {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"}, 2588 {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"}, 2589 {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"}, 2590 2591 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"}, 2592 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"}, 2593 2594 {"Input Processor Channel 0", NULL, "PLLs"}, 2595 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"}, 2596 2597 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"}, 2598 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"}, 2599 2600 {"Input Processor Channel 1", NULL, "PLLs"}, 2601 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"}, 2602 2603 {"Input Processor Channel 2", NULL, "PLLs"}, 2604 {"Input Processor Channel 2", NULL, "DMic 2"}, 2605 2606 {"Input Processor Channel 3", NULL, "PLLs"}, 2607 {"Input Processor Channel 3", NULL, "DMic 2"}, 2608 2609 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, 2610 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, 2611 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"}, 2612 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"}, 2613 2614 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, 2615 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, 2616 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"}, 2617 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"}, 2618 2619 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"}, 2620 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"}, 2621 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"}, 2622 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"}, 2623 2624 {"DAI 1 Out", NULL, "DAI 1 Out Mux"}, 2625 {"DAI 2 Out", NULL, "DAI 2 Out Mux"}, 2626 {"DAI 3 Out", NULL, "DAI 3 Out Mux"}, 2627 }; 2628 2629 /* This is used when BCLK is sourcing the PLLs */ 2630 static int tscs454_set_sysclk(struct snd_soc_dai *dai, 2631 int clk_id, unsigned int freq, int dir) 2632 { 2633 struct snd_soc_component *component = dai->component; 2634 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 2635 unsigned int val; 2636 int bclk_dai; 2637 2638 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq); 2639 2640 val = snd_soc_component_read(component, R_PLLCTL); 2641 2642 bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL; 2643 if (bclk_dai != dai->id) 2644 return 0; 2645 2646 tscs454->bclk_freq = freq; 2647 return set_sysclk(component); 2648 } 2649 2650 static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai, 2651 unsigned int ratio) 2652 { 2653 unsigned int mask; 2654 int ret; 2655 struct snd_soc_component *component = dai->component; 2656 unsigned int val; 2657 int shift; 2658 2659 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n", 2660 dai->id, ratio); 2661 2662 switch (dai->id) { 2663 case TSCS454_DAI1_ID: 2664 mask = FM_I2SCMC_BCMP1; 2665 shift = FB_I2SCMC_BCMP1; 2666 break; 2667 case TSCS454_DAI2_ID: 2668 mask = FM_I2SCMC_BCMP2; 2669 shift = FB_I2SCMC_BCMP2; 2670 break; 2671 case TSCS454_DAI3_ID: 2672 mask = FM_I2SCMC_BCMP3; 2673 shift = FB_I2SCMC_BCMP3; 2674 break; 2675 default: 2676 ret = -EINVAL; 2677 dev_err(component->dev, "Unknown audio interface (%d)\n", ret); 2678 return ret; 2679 } 2680 2681 switch (ratio) { 2682 case 32: 2683 val = I2SCMC_BCMP_32X; 2684 break; 2685 case 40: 2686 val = I2SCMC_BCMP_40X; 2687 break; 2688 case 64: 2689 val = I2SCMC_BCMP_64X; 2690 break; 2691 default: 2692 ret = -EINVAL; 2693 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); 2694 return ret; 2695 } 2696 2697 ret = snd_soc_component_update_bits(component, 2698 R_I2SCMC, mask, val << shift); 2699 if (ret < 0) { 2700 dev_err(component->dev, 2701 "Failed to set DAI BCLK ratio (%d)\n", ret); 2702 return ret; 2703 } 2704 2705 return 0; 2706 } 2707 2708 static inline int set_aif_provider_from_fmt(struct snd_soc_component *component, 2709 struct aif *aif, unsigned int fmt) 2710 { 2711 int ret; 2712 2713 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2714 case SND_SOC_DAIFMT_CBP_CFP: 2715 aif->provider = true; 2716 break; 2717 case SND_SOC_DAIFMT_CBC_CFC: 2718 aif->provider = false; 2719 break; 2720 default: 2721 ret = -EINVAL; 2722 dev_err(component->dev, "Unsupported format (%d)\n", ret); 2723 return ret; 2724 } 2725 2726 return 0; 2727 } 2728 2729 static inline int set_aif_tdm_delay(struct snd_soc_component *component, 2730 unsigned int dai_id, bool delay) 2731 { 2732 unsigned int reg; 2733 int ret; 2734 2735 switch (dai_id) { 2736 case TSCS454_DAI1_ID: 2737 reg = R_TDMCTL0; 2738 break; 2739 case TSCS454_DAI2_ID: 2740 reg = R_PCMP2CTL0; 2741 break; 2742 case TSCS454_DAI3_ID: 2743 reg = R_PCMP3CTL0; 2744 break; 2745 default: 2746 ret = -EINVAL; 2747 dev_err(component->dev, 2748 "DAI %d unknown (%d)\n", dai_id + 1, ret); 2749 return ret; 2750 } 2751 ret = snd_soc_component_update_bits(component, 2752 reg, FM_TDMCTL0_BDELAY, delay); 2753 if (ret < 0) { 2754 dev_err(component->dev, "Failed to setup tdm format (%d)\n", 2755 ret); 2756 return ret; 2757 } 2758 2759 return 0; 2760 } 2761 2762 static inline int set_aif_format_from_fmt(struct snd_soc_component *component, 2763 unsigned int dai_id, unsigned int fmt) 2764 { 2765 unsigned int reg; 2766 unsigned int val; 2767 int ret; 2768 2769 switch (dai_id) { 2770 case TSCS454_DAI1_ID: 2771 reg = R_I2SP1CTL; 2772 break; 2773 case TSCS454_DAI2_ID: 2774 reg = R_I2SP2CTL; 2775 break; 2776 case TSCS454_DAI3_ID: 2777 reg = R_I2SP3CTL; 2778 break; 2779 default: 2780 ret = -EINVAL; 2781 dev_err(component->dev, 2782 "DAI %d unknown (%d)\n", dai_id + 1, ret); 2783 return ret; 2784 } 2785 2786 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2787 case SND_SOC_DAIFMT_RIGHT_J: 2788 val = FV_FORMAT_RIGHT; 2789 break; 2790 case SND_SOC_DAIFMT_LEFT_J: 2791 val = FV_FORMAT_LEFT; 2792 break; 2793 case SND_SOC_DAIFMT_I2S: 2794 val = FV_FORMAT_I2S; 2795 break; 2796 case SND_SOC_DAIFMT_DSP_A: 2797 ret = set_aif_tdm_delay(component, dai_id, true); 2798 if (ret < 0) 2799 return ret; 2800 val = FV_FORMAT_TDM; 2801 break; 2802 case SND_SOC_DAIFMT_DSP_B: 2803 ret = set_aif_tdm_delay(component, dai_id, false); 2804 if (ret < 0) 2805 return ret; 2806 val = FV_FORMAT_TDM; 2807 break; 2808 default: 2809 ret = -EINVAL; 2810 dev_err(component->dev, "Format unsupported (%d)\n", ret); 2811 return ret; 2812 } 2813 2814 ret = snd_soc_component_update_bits(component, 2815 reg, FM_I2SPCTL_FORMAT, val); 2816 if (ret < 0) { 2817 dev_err(component->dev, "Failed to set DAI %d format (%d)\n", 2818 dai_id + 1, ret); 2819 return ret; 2820 } 2821 2822 return 0; 2823 } 2824 2825 static inline int 2826 set_aif_clock_format_from_fmt(struct snd_soc_component *component, 2827 unsigned int dai_id, unsigned int fmt) 2828 { 2829 unsigned int reg; 2830 unsigned int val; 2831 int ret; 2832 2833 switch (dai_id) { 2834 case TSCS454_DAI1_ID: 2835 reg = R_I2SP1CTL; 2836 break; 2837 case TSCS454_DAI2_ID: 2838 reg = R_I2SP2CTL; 2839 break; 2840 case TSCS454_DAI3_ID: 2841 reg = R_I2SP3CTL; 2842 break; 2843 default: 2844 ret = -EINVAL; 2845 dev_err(component->dev, 2846 "DAI %d unknown (%d)\n", dai_id + 1, ret); 2847 return ret; 2848 } 2849 2850 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2851 case SND_SOC_DAIFMT_NB_NF: 2852 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED; 2853 break; 2854 case SND_SOC_DAIFMT_NB_IF: 2855 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED; 2856 break; 2857 case SND_SOC_DAIFMT_IB_NF: 2858 val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED; 2859 break; 2860 case SND_SOC_DAIFMT_IB_IF: 2861 val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED; 2862 break; 2863 default: 2864 ret = -EINVAL; 2865 dev_err(component->dev, "Format unknown (%d)\n", ret); 2866 return ret; 2867 } 2868 2869 ret = snd_soc_component_update_bits(component, reg, 2870 FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val); 2871 if (ret < 0) { 2872 dev_err(component->dev, 2873 "Failed to set clock polarity for DAI%d (%d)\n", 2874 dai_id + 1, ret); 2875 return ret; 2876 } 2877 2878 return 0; 2879 } 2880 2881 static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2882 { 2883 struct snd_soc_component *component = dai->component; 2884 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 2885 struct aif *aif = &tscs454->aifs[dai->id]; 2886 int ret; 2887 2888 ret = set_aif_provider_from_fmt(component, aif, fmt); 2889 if (ret < 0) 2890 return ret; 2891 2892 ret = set_aif_format_from_fmt(component, dai->id, fmt); 2893 if (ret < 0) 2894 return ret; 2895 2896 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt); 2897 if (ret < 0) 2898 return ret; 2899 2900 return 0; 2901 } 2902 2903 static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai, 2904 unsigned int tx_mask, unsigned int rx_mask, int slots, 2905 int slot_width) 2906 { 2907 struct snd_soc_component *component = dai->component; 2908 unsigned int val; 2909 int ret; 2910 2911 if (!slots) 2912 return 0; 2913 2914 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) { 2915 ret = -EINVAL; 2916 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); 2917 return ret; 2918 } 2919 2920 switch (slots) { 2921 case 2: 2922 val = FV_TDMSO_2 | FV_TDMSI_2; 2923 break; 2924 case 4: 2925 val = FV_TDMSO_4 | FV_TDMSI_4; 2926 break; 2927 case 6: 2928 val = FV_TDMSO_6 | FV_TDMSI_6; 2929 break; 2930 default: 2931 ret = -EINVAL; 2932 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); 2933 return ret; 2934 } 2935 2936 switch (slot_width) { 2937 case 16: 2938 val = val | FV_TDMDSS_16; 2939 break; 2940 case 24: 2941 val = val | FV_TDMDSS_24; 2942 break; 2943 case 32: 2944 val = val | FV_TDMDSS_32; 2945 break; 2946 default: 2947 ret = -EINVAL; 2948 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); 2949 return ret; 2950 } 2951 ret = snd_soc_component_write(component, R_TDMCTL1, val); 2952 if (ret < 0) { 2953 dev_err(component->dev, "Failed to set slots (%d)\n", ret); 2954 return ret; 2955 } 2956 2957 return 0; 2958 } 2959 2960 static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai, 2961 unsigned int tx_mask, unsigned int rx_mask, int slots, 2962 int slot_width) 2963 { 2964 struct snd_soc_component *component = dai->component; 2965 unsigned int reg; 2966 unsigned int val; 2967 int ret; 2968 2969 if (!slots) 2970 return 0; 2971 2972 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) { 2973 ret = -EINVAL; 2974 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); 2975 return ret; 2976 } 2977 2978 switch (dai->id) { 2979 case TSCS454_DAI2_ID: 2980 reg = R_PCMP2CTL1; 2981 break; 2982 case TSCS454_DAI3_ID: 2983 reg = R_PCMP3CTL1; 2984 break; 2985 default: 2986 ret = -EINVAL; 2987 dev_err(component->dev, "Unrecognized interface %d (%d)\n", 2988 dai->id, ret); 2989 return ret; 2990 } 2991 2992 switch (slots) { 2993 case 1: 2994 val = FV_PCMSOP_1 | FV_PCMSIP_1; 2995 break; 2996 case 2: 2997 val = FV_PCMSOP_2 | FV_PCMSIP_2; 2998 break; 2999 default: 3000 ret = -EINVAL; 3001 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); 3002 return ret; 3003 } 3004 3005 switch (slot_width) { 3006 case 16: 3007 val = val | FV_PCMDSSP_16; 3008 break; 3009 case 24: 3010 val = val | FV_PCMDSSP_24; 3011 break; 3012 case 32: 3013 val = val | FV_PCMDSSP_32; 3014 break; 3015 default: 3016 ret = -EINVAL; 3017 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); 3018 return ret; 3019 } 3020 ret = snd_soc_component_write(component, reg, val); 3021 if (ret < 0) { 3022 dev_err(component->dev, "Failed to set slots (%d)\n", ret); 3023 return ret; 3024 } 3025 3026 return 0; 3027 } 3028 3029 static int set_aif_fs(struct snd_soc_component *component, 3030 unsigned int id, 3031 unsigned int rate) 3032 { 3033 unsigned int reg; 3034 unsigned int br; 3035 unsigned int bm; 3036 int ret; 3037 3038 switch (rate) { 3039 case 8000: 3040 br = FV_I2SMBR_32; 3041 bm = FV_I2SMBM_0PT25; 3042 break; 3043 case 16000: 3044 br = FV_I2SMBR_32; 3045 bm = FV_I2SMBM_0PT5; 3046 break; 3047 case 24000: 3048 br = FV_I2SMBR_48; 3049 bm = FV_I2SMBM_0PT5; 3050 break; 3051 case 32000: 3052 br = FV_I2SMBR_32; 3053 bm = FV_I2SMBM_1; 3054 break; 3055 case 48000: 3056 br = FV_I2SMBR_48; 3057 bm = FV_I2SMBM_1; 3058 break; 3059 case 96000: 3060 br = FV_I2SMBR_48; 3061 bm = FV_I2SMBM_2; 3062 break; 3063 case 11025: 3064 br = FV_I2SMBR_44PT1; 3065 bm = FV_I2SMBM_0PT25; 3066 break; 3067 case 22050: 3068 br = FV_I2SMBR_44PT1; 3069 bm = FV_I2SMBM_0PT5; 3070 break; 3071 case 44100: 3072 br = FV_I2SMBR_44PT1; 3073 bm = FV_I2SMBM_1; 3074 break; 3075 case 88200: 3076 br = FV_I2SMBR_44PT1; 3077 bm = FV_I2SMBM_2; 3078 break; 3079 default: 3080 ret = -EINVAL; 3081 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret); 3082 return ret; 3083 } 3084 3085 switch (id) { 3086 case TSCS454_DAI1_ID: 3087 reg = R_I2S1MRATE; 3088 break; 3089 case TSCS454_DAI2_ID: 3090 reg = R_I2S2MRATE; 3091 break; 3092 case TSCS454_DAI3_ID: 3093 reg = R_I2S3MRATE; 3094 break; 3095 default: 3096 ret = -EINVAL; 3097 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret); 3098 return ret; 3099 } 3100 3101 ret = snd_soc_component_update_bits(component, reg, 3102 FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm); 3103 if (ret < 0) { 3104 dev_err(component->dev, 3105 "Failed to update register (%d)\n", ret); 3106 return ret; 3107 } 3108 3109 return 0; 3110 } 3111 3112 static int set_aif_sample_format(struct snd_soc_component *component, 3113 snd_pcm_format_t format, 3114 int aif_id) 3115 { 3116 unsigned int reg; 3117 unsigned int width; 3118 int ret; 3119 3120 switch (snd_pcm_format_width(format)) { 3121 case 16: 3122 width = FV_WL_16; 3123 break; 3124 case 20: 3125 width = FV_WL_20; 3126 break; 3127 case 24: 3128 width = FV_WL_24; 3129 break; 3130 case 32: 3131 width = FV_WL_32; 3132 break; 3133 default: 3134 ret = -EINVAL; 3135 dev_err(component->dev, "Unsupported format width (%d)\n", ret); 3136 return ret; 3137 } 3138 3139 switch (aif_id) { 3140 case TSCS454_DAI1_ID: 3141 reg = R_I2SP1CTL; 3142 break; 3143 case TSCS454_DAI2_ID: 3144 reg = R_I2SP2CTL; 3145 break; 3146 case TSCS454_DAI3_ID: 3147 reg = R_I2SP3CTL; 3148 break; 3149 default: 3150 ret = -EINVAL; 3151 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret); 3152 return ret; 3153 } 3154 3155 ret = snd_soc_component_update_bits(component, 3156 reg, FM_I2SPCTL_WL, width); 3157 if (ret < 0) { 3158 dev_err(component->dev, 3159 "Failed to set sample width (%d)\n", ret); 3160 return ret; 3161 } 3162 3163 return 0; 3164 } 3165 3166 static int tscs454_hw_params(struct snd_pcm_substream *substream, 3167 struct snd_pcm_hw_params *params, 3168 struct snd_soc_dai *dai) 3169 { 3170 struct snd_soc_component *component = dai->component; 3171 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3172 unsigned int fs = params_rate(params); 3173 struct aif *aif = &tscs454->aifs[dai->id]; 3174 unsigned int val; 3175 int ret; 3176 3177 mutex_lock(&tscs454->aifs_status_lock); 3178 3179 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__, 3180 aif->id, fs); 3181 3182 if (!aif_active(&tscs454->aifs_status, aif->id)) { 3183 if (PLL_44_1K_RATE % fs) 3184 aif->pll = &tscs454->pll1; 3185 else 3186 aif->pll = &tscs454->pll2; 3187 3188 dev_dbg(component->dev, "Reserving pll %d for aif %d\n", 3189 aif->pll->id, aif->id); 3190 3191 reserve_pll(aif->pll); 3192 } 3193 3194 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */ 3195 val = snd_soc_component_read(component, R_ISRC); 3196 if ((val & FM_ISRC_IBR) == FV_IBR_48) 3197 tscs454->internal_rate.pll = &tscs454->pll1; 3198 else 3199 tscs454->internal_rate.pll = &tscs454->pll2; 3200 3201 dev_dbg(component->dev, "Reserving pll %d for ir\n", 3202 tscs454->internal_rate.pll->id); 3203 3204 reserve_pll(tscs454->internal_rate.pll); 3205 } 3206 3207 ret = set_aif_fs(component, aif->id, fs); 3208 if (ret < 0) { 3209 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret); 3210 goto exit; 3211 } 3212 3213 ret = set_aif_sample_format(component, params_format(params), aif->id); 3214 if (ret < 0) { 3215 dev_err(component->dev, 3216 "Failed to set aif sample format (%d)\n", ret); 3217 goto exit; 3218 } 3219 3220 set_aif_status_active(&tscs454->aifs_status, aif->id, 3221 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 3222 3223 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n", 3224 aif->id, tscs454->aifs_status.streams); 3225 3226 ret = 0; 3227 exit: 3228 mutex_unlock(&tscs454->aifs_status_lock); 3229 3230 return ret; 3231 } 3232 3233 static int tscs454_hw_free(struct snd_pcm_substream *substream, 3234 struct snd_soc_dai *dai) 3235 { 3236 struct snd_soc_component *component = dai->component; 3237 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3238 struct aif *aif = &tscs454->aifs[dai->id]; 3239 3240 return aif_free(component, aif, 3241 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 3242 } 3243 3244 static int tscs454_prepare(struct snd_pcm_substream *substream, 3245 struct snd_soc_dai *dai) 3246 { 3247 int ret; 3248 struct snd_soc_component *component = dai->component; 3249 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3250 struct aif *aif = &tscs454->aifs[dai->id]; 3251 3252 ret = aif_prepare(component, aif); 3253 if (ret < 0) 3254 return ret; 3255 3256 return 0; 3257 } 3258 3259 static struct snd_soc_dai_ops const tscs454_dai1_ops = { 3260 .set_sysclk = tscs454_set_sysclk, 3261 .set_bclk_ratio = tscs454_set_bclk_ratio, 3262 .set_fmt = tscs454_set_dai_fmt, 3263 .set_tdm_slot = tscs454_dai1_set_tdm_slot, 3264 .hw_params = tscs454_hw_params, 3265 .hw_free = tscs454_hw_free, 3266 .prepare = tscs454_prepare, 3267 }; 3268 3269 static struct snd_soc_dai_ops const tscs454_dai23_ops = { 3270 .set_sysclk = tscs454_set_sysclk, 3271 .set_bclk_ratio = tscs454_set_bclk_ratio, 3272 .set_fmt = tscs454_set_dai_fmt, 3273 .set_tdm_slot = tscs454_dai23_set_tdm_slot, 3274 .hw_params = tscs454_hw_params, 3275 .hw_free = tscs454_hw_free, 3276 .prepare = tscs454_prepare, 3277 }; 3278 3279 static int tscs454_probe(struct snd_soc_component *component) 3280 { 3281 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component); 3282 unsigned int val; 3283 int ret = 0; 3284 3285 switch (tscs454->sysclk_src_id) { 3286 case PLL_INPUT_XTAL: 3287 val = FV_PLLISEL_XTAL; 3288 break; 3289 case PLL_INPUT_MCLK1: 3290 val = FV_PLLISEL_MCLK1; 3291 break; 3292 case PLL_INPUT_MCLK2: 3293 val = FV_PLLISEL_MCLK2; 3294 break; 3295 case PLL_INPUT_BCLK: 3296 val = FV_PLLISEL_BCLK; 3297 break; 3298 default: 3299 ret = -EINVAL; 3300 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret); 3301 return ret; 3302 } 3303 3304 ret = snd_soc_component_update_bits(component, R_PLLCTL, 3305 FM_PLLCTL_PLLISEL, val); 3306 if (ret < 0) { 3307 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret); 3308 return ret; 3309 } 3310 3311 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) 3312 ret = set_sysclk(component); 3313 3314 return ret; 3315 } 3316 3317 static const struct snd_soc_component_driver soc_component_dev_tscs454 = { 3318 .probe = tscs454_probe, 3319 .dapm_widgets = tscs454_dapm_widgets, 3320 .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets), 3321 .dapm_routes = tscs454_intercon, 3322 .num_dapm_routes = ARRAY_SIZE(tscs454_intercon), 3323 .controls = tscs454_snd_controls, 3324 .num_controls = ARRAY_SIZE(tscs454_snd_controls), 3325 .endianness = 1, 3326 }; 3327 3328 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000 3329 3330 #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 3331 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \ 3332 | SNDRV_PCM_FMTBIT_S32_LE) 3333 3334 static struct snd_soc_dai_driver tscs454_dais[] = { 3335 { 3336 .name = "tscs454-dai1", 3337 .id = TSCS454_DAI1_ID, 3338 .playback = { 3339 .stream_name = "DAI 1 Playback", 3340 .channels_min = 1, 3341 .channels_max = 6, 3342 .rates = TSCS454_RATES, 3343 .formats = TSCS454_FORMATS,}, 3344 .capture = { 3345 .stream_name = "DAI 1 Capture", 3346 .channels_min = 1, 3347 .channels_max = 6, 3348 .rates = TSCS454_RATES, 3349 .formats = TSCS454_FORMATS,}, 3350 .ops = &tscs454_dai1_ops, 3351 .symmetric_rate = 1, 3352 .symmetric_channels = 1, 3353 .symmetric_sample_bits = 1, 3354 }, 3355 { 3356 .name = "tscs454-dai2", 3357 .id = TSCS454_DAI2_ID, 3358 .playback = { 3359 .stream_name = "DAI 2 Playback", 3360 .channels_min = 1, 3361 .channels_max = 2, 3362 .rates = TSCS454_RATES, 3363 .formats = TSCS454_FORMATS,}, 3364 .capture = { 3365 .stream_name = "DAI 2 Capture", 3366 .channels_min = 1, 3367 .channels_max = 2, 3368 .rates = TSCS454_RATES, 3369 .formats = TSCS454_FORMATS,}, 3370 .ops = &tscs454_dai23_ops, 3371 .symmetric_rate = 1, 3372 .symmetric_channels = 1, 3373 .symmetric_sample_bits = 1, 3374 }, 3375 { 3376 .name = "tscs454-dai3", 3377 .id = TSCS454_DAI3_ID, 3378 .playback = { 3379 .stream_name = "DAI 3 Playback", 3380 .channels_min = 1, 3381 .channels_max = 2, 3382 .rates = TSCS454_RATES, 3383 .formats = TSCS454_FORMATS,}, 3384 .capture = { 3385 .stream_name = "DAI 3 Capture", 3386 .channels_min = 1, 3387 .channels_max = 2, 3388 .rates = TSCS454_RATES, 3389 .formats = TSCS454_FORMATS,}, 3390 .ops = &tscs454_dai23_ops, 3391 .symmetric_rate = 1, 3392 .symmetric_channels = 1, 3393 .symmetric_sample_bits = 1, 3394 }, 3395 }; 3396 3397 static char const * const src_names[] = { 3398 "xtal", "mclk1", "mclk2", "bclk"}; 3399 3400 static int tscs454_i2c_probe(struct i2c_client *i2c) 3401 { 3402 struct tscs454 *tscs454; 3403 int src; 3404 int ret; 3405 3406 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL); 3407 if (!tscs454) 3408 return -ENOMEM; 3409 3410 ret = tscs454_data_init(tscs454, i2c); 3411 if (ret < 0) 3412 return ret; 3413 3414 i2c_set_clientdata(i2c, tscs454); 3415 3416 for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) { 3417 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]); 3418 if (!IS_ERR(tscs454->sysclk)) { 3419 break; 3420 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) { 3421 ret = PTR_ERR(tscs454->sysclk); 3422 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); 3423 return ret; 3424 } 3425 } 3426 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]); 3427 tscs454->sysclk_src_id = src; 3428 3429 ret = regmap_write(tscs454->regmap, 3430 R_RESET, FV_RESET_PWR_ON_DEFAULTS); 3431 if (ret < 0) { 3432 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret); 3433 return ret; 3434 } 3435 regcache_mark_dirty(tscs454->regmap); 3436 3437 ret = regmap_register_patch(tscs454->regmap, tscs454_patch, 3438 ARRAY_SIZE(tscs454_patch)); 3439 if (ret < 0) { 3440 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); 3441 return ret; 3442 } 3443 /* Sync pg sel reg with cache */ 3444 regmap_write(tscs454->regmap, R_PAGESEL, 0x00); 3445 3446 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454, 3447 tscs454_dais, ARRAY_SIZE(tscs454_dais)); 3448 if (ret) { 3449 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret); 3450 return ret; 3451 } 3452 3453 return 0; 3454 } 3455 3456 static const struct i2c_device_id tscs454_i2c_id[] = { 3457 { "tscs454" }, 3458 { } 3459 }; 3460 MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id); 3461 3462 static const struct of_device_id tscs454_of_match[] = { 3463 { .compatible = "tempo,tscs454", }, 3464 { } 3465 }; 3466 MODULE_DEVICE_TABLE(of, tscs454_of_match); 3467 3468 static struct i2c_driver tscs454_i2c_driver = { 3469 .driver = { 3470 .name = "tscs454", 3471 .of_match_table = tscs454_of_match, 3472 }, 3473 .probe = tscs454_i2c_probe, 3474 .id_table = tscs454_i2c_id, 3475 }; 3476 3477 module_i2c_driver(tscs454_i2c_driver); 3478 3479 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); 3480 MODULE_DESCRIPTION("ASoC TSCS454 driver"); 3481 MODULE_LICENSE("GPL v2"); 3482