1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC Texas Instruments TLV320DAC33 codec driver 4 * 5 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 6 * 7 * Copyright: (C) 2009 Nokia Corporation 8 */ 9 10 #include <linux/cleanup.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/interrupt.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/slab.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/initval.h> 26 #include <sound/tlv.h> 27 28 #include "tlv320dac33.h" 29 30 /* 31 * The internal FIFO is 24576 bytes long 32 * It can be configured to hold 16bit or 24bit samples 33 * In 16bit configuration the FIFO can hold 6144 stereo samples 34 * In 24bit configuration the FIFO can hold 4096 stereo samples 35 */ 36 #define DAC33_FIFO_SIZE_16BIT 6144 37 #define DAC33_FIFO_SIZE_24BIT 4096 38 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ 39 40 #define BURST_BASEFREQ_HZ 49152000 41 42 #define SAMPLES_TO_US(rate, samples) \ 43 (1000000000 / (((rate) * 1000) / (samples))) 44 45 #define US_TO_SAMPLES(rate, us) \ 46 ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000))) 47 48 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ 49 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) 50 51 static void dac33_calculate_times(struct snd_pcm_substream *substream, 52 struct snd_soc_component *component); 53 static int dac33_prepare_chip(struct snd_pcm_substream *substream, 54 struct snd_soc_component *component); 55 56 enum dac33_state { 57 DAC33_IDLE = 0, 58 DAC33_PREFILL, 59 DAC33_PLAYBACK, 60 DAC33_FLUSH, 61 }; 62 63 enum dac33_fifo_modes { 64 DAC33_FIFO_BYPASS = 0, 65 DAC33_FIFO_MODE1, 66 DAC33_FIFO_MODE7, 67 DAC33_FIFO_LAST_MODE, 68 }; 69 70 #define DAC33_NUM_SUPPLIES 3 71 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { 72 "AVDD", 73 "DVDD", 74 "IOVDD", 75 }; 76 77 struct tlv320dac33_priv { 78 struct mutex mutex; 79 struct work_struct work; 80 struct snd_soc_component *component; 81 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; 82 struct snd_pcm_substream *substream; 83 struct gpio_desc *reset_gpiod; 84 int chip_power; 85 int irq; 86 unsigned int refclk; 87 88 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ 89 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 90 unsigned int fifo_size; /* Size of the FIFO in samples */ 91 unsigned int nsample; /* burst read amount from host */ 92 int mode1_latency; /* latency caused by the i2c writes in 93 * us */ 94 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 95 unsigned int burst_rate; /* Interface speed in Burst modes */ 96 97 int keep_bclk; /* Keep the BCLK continuously running 98 * in FIFO modes */ 99 spinlock_t lock; 100 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ 101 unsigned long long t_stamp2; /* calculate the FIFO caused delay */ 102 103 unsigned int mode1_us_burst; /* Time to burst read n number of 104 * samples */ 105 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ 106 107 unsigned int uthr; 108 109 enum dac33_state state; 110 struct i2c_client *i2c; 111 112 u8 reg_cache[]; 113 }; 114 115 static const u8 dac33_reg[DAC33_CACHEREGNUM] = { 116 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ 117 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ 118 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ 119 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ 120 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ 121 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ 122 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ 123 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ 124 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ 125 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ 126 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ 127 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ 128 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ 129 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ 130 0x00, 0x00, /* 0x38 - 0x39 */ 131 /* Registers 0x3a - 0x3f are reserved */ 132 0x00, 0x00, /* 0x3a - 0x3b */ 133 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ 134 135 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ 136 0x00, 0x80, /* 0x44 - 0x45 */ 137 /* Registers 0x46 - 0x47 are reserved */ 138 0x80, 0x80, /* 0x46 - 0x47 */ 139 140 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ 141 /* Registers 0x4b - 0x7c are reserved */ 142 0x00, /* 0x4b */ 143 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ 144 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ 145 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ 146 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ 147 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ 148 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ 149 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ 150 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ 151 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ 152 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ 153 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ 154 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ 155 0x00, /* 0x7c */ 156 157 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ 158 }; 159 160 /* Register read and write */ 161 static inline unsigned int dac33_read_reg_cache(struct snd_soc_component *component, 162 unsigned reg) 163 { 164 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 165 u8 *cache = dac33->reg_cache; 166 if (reg >= DAC33_CACHEREGNUM) 167 return 0; 168 169 return cache[reg]; 170 } 171 172 static inline void dac33_write_reg_cache(struct snd_soc_component *component, 173 u8 reg, u8 value) 174 { 175 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 176 u8 *cache = dac33->reg_cache; 177 if (reg >= DAC33_CACHEREGNUM) 178 return; 179 180 cache[reg] = value; 181 } 182 183 static int dac33_read(struct snd_soc_component *component, unsigned int reg, 184 u8 *value) 185 { 186 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 187 int val, ret = 0; 188 189 *value = reg & 0xff; 190 191 /* If powered off, return the cached value */ 192 if (dac33->chip_power) { 193 val = i2c_smbus_read_byte_data(dac33->i2c, value[0]); 194 if (val < 0) { 195 dev_err(component->dev, "Read failed (%d)\n", val); 196 value[0] = dac33_read_reg_cache(component, reg); 197 ret = val; 198 } else { 199 value[0] = val; 200 dac33_write_reg_cache(component, reg, val); 201 } 202 } else { 203 value[0] = dac33_read_reg_cache(component, reg); 204 } 205 206 return ret; 207 } 208 209 static int dac33_write(struct snd_soc_component *component, unsigned int reg, 210 unsigned int value) 211 { 212 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 213 u8 data[2]; 214 int ret = 0; 215 216 /* 217 * data is 218 * D15..D8 dac33 register offset 219 * D7...D0 register data 220 */ 221 data[0] = reg & 0xff; 222 data[1] = value & 0xff; 223 224 dac33_write_reg_cache(component, data[0], data[1]); 225 if (dac33->chip_power) { 226 ret = i2c_master_send(dac33->i2c, data, 2); 227 if (ret != 2) 228 dev_err(component->dev, "Write failed (%d)\n", ret); 229 else 230 ret = 0; 231 } 232 233 return ret; 234 } 235 236 static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg, 237 unsigned int value) 238 { 239 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 240 241 guard(mutex)(&dac33->mutex); 242 243 return dac33_write(component, reg, value); 244 } 245 246 #define DAC33_I2C_ADDR_AUTOINC 0x80 247 static int dac33_write16(struct snd_soc_component *component, unsigned int reg, 248 unsigned int value) 249 { 250 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 251 u8 data[3]; 252 int ret = 0; 253 254 /* 255 * data is 256 * D23..D16 dac33 register offset 257 * D15..D8 register data MSB 258 * D7...D0 register data LSB 259 */ 260 data[0] = reg & 0xff; 261 data[1] = (value >> 8) & 0xff; 262 data[2] = value & 0xff; 263 264 dac33_write_reg_cache(component, data[0], data[1]); 265 dac33_write_reg_cache(component, data[0] + 1, data[2]); 266 267 if (dac33->chip_power) { 268 /* We need to set autoincrement mode for 16 bit writes */ 269 data[0] |= DAC33_I2C_ADDR_AUTOINC; 270 ret = i2c_master_send(dac33->i2c, data, 3); 271 if (ret != 3) 272 dev_err(component->dev, "Write failed (%d)\n", ret); 273 else 274 ret = 0; 275 } 276 277 return ret; 278 } 279 280 static void dac33_init_chip(struct snd_soc_component *component) 281 { 282 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 283 284 if (unlikely(!dac33->chip_power)) 285 return; 286 287 /* A : DAC sample rate Fsref/1.5 */ 288 dac33_write(component, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); 289 /* B : DAC src=normal, not muted */ 290 dac33_write(component, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | 291 DAC33_DACSRCL_LEFT); 292 /* C : (defaults) */ 293 dac33_write(component, DAC33_DAC_CTRL_C, 0x00); 294 295 /* 73 : volume soft stepping control, 296 clock source = internal osc (?) */ 297 dac33_write(component, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); 298 299 /* Restore only selected registers (gains mostly) */ 300 dac33_write(component, DAC33_LDAC_DIG_VOL_CTRL, 301 dac33_read_reg_cache(component, DAC33_LDAC_DIG_VOL_CTRL)); 302 dac33_write(component, DAC33_RDAC_DIG_VOL_CTRL, 303 dac33_read_reg_cache(component, DAC33_RDAC_DIG_VOL_CTRL)); 304 305 dac33_write(component, DAC33_LINEL_TO_LLO_VOL, 306 dac33_read_reg_cache(component, DAC33_LINEL_TO_LLO_VOL)); 307 dac33_write(component, DAC33_LINER_TO_RLO_VOL, 308 dac33_read_reg_cache(component, DAC33_LINER_TO_RLO_VOL)); 309 310 dac33_write(component, DAC33_OUT_AMP_CTRL, 311 dac33_read_reg_cache(component, DAC33_OUT_AMP_CTRL)); 312 313 dac33_write(component, DAC33_LDAC_PWR_CTRL, 314 dac33_read_reg_cache(component, DAC33_LDAC_PWR_CTRL)); 315 dac33_write(component, DAC33_RDAC_PWR_CTRL, 316 dac33_read_reg_cache(component, DAC33_RDAC_PWR_CTRL)); 317 } 318 319 static inline int dac33_read_id(struct snd_soc_component *component) 320 { 321 int i, ret = 0; 322 u8 reg; 323 324 for (i = 0; i < 3; i++) { 325 ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, ®); 326 if (ret < 0) 327 break; 328 } 329 330 return ret; 331 } 332 333 static inline void dac33_soft_power(struct snd_soc_component *component, int power) 334 { 335 u8 reg; 336 337 reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); 338 if (power) 339 reg |= DAC33_PDNALLB; 340 else 341 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | 342 DAC33_DACRPDNB | DAC33_DACLPDNB); 343 dac33_write(component, DAC33_PWR_CTRL, reg); 344 } 345 346 static inline void dac33_disable_digital(struct snd_soc_component *component) 347 { 348 u8 reg; 349 350 /* Stop the DAI clock */ 351 reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); 352 reg &= ~DAC33_BCLKON; 353 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, reg); 354 355 /* Power down the Oscillator, and DACs */ 356 reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); 357 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); 358 dac33_write(component, DAC33_PWR_CTRL, reg); 359 } 360 361 static int dac33_hard_power(struct snd_soc_component *component, int power) 362 { 363 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 364 int ret = 0; 365 366 guard(mutex)(&dac33->mutex); 367 368 /* Safety check */ 369 if (unlikely(power == dac33->chip_power)) { 370 dev_dbg(component->dev, "Trying to set the same power state: %s\n", 371 power ? "ON" : "OFF"); 372 return ret; 373 } 374 375 if (power) { 376 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), 377 dac33->supplies); 378 if (ret != 0) { 379 dev_err(component->dev, 380 "Failed to enable supplies: %d\n", ret); 381 return ret; 382 } 383 384 if (dac33->reset_gpiod) { 385 ret = gpiod_set_value(dac33->reset_gpiod, 1); 386 if (ret < 0) { 387 dev_err(&dac33->i2c->dev, 388 "Failed to set reset GPIO: %d\n", ret); 389 return ret; 390 } 391 } 392 393 dac33->chip_power = 1; 394 } else { 395 dac33_soft_power(component, 0); 396 if (dac33->reset_gpiod) { 397 ret = gpiod_set_value(dac33->reset_gpiod, 0); 398 if (ret < 0) { 399 dev_err(&dac33->i2c->dev, 400 "Failed to set reset GPIO: %d\n", ret); 401 return ret; 402 } 403 } 404 405 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), 406 dac33->supplies); 407 if (ret != 0) { 408 dev_err(component->dev, 409 "Failed to disable supplies: %d\n", ret); 410 return ret; 411 } 412 413 dac33->chip_power = 0; 414 } 415 416 return ret; 417 } 418 419 static int dac33_playback_event(struct snd_soc_dapm_widget *w, 420 struct snd_kcontrol *kcontrol, int event) 421 { 422 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 423 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 424 425 switch (event) { 426 case SND_SOC_DAPM_PRE_PMU: 427 if (likely(dac33->substream)) { 428 dac33_calculate_times(dac33->substream, component); 429 dac33_prepare_chip(dac33->substream, component); 430 } 431 break; 432 case SND_SOC_DAPM_POST_PMD: 433 dac33_disable_digital(component); 434 break; 435 } 436 return 0; 437 } 438 439 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 440 struct snd_ctl_elem_value *ucontrol) 441 { 442 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 443 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 444 445 ucontrol->value.enumerated.item[0] = dac33->fifo_mode; 446 447 return 0; 448 } 449 450 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, 451 struct snd_ctl_elem_value *ucontrol) 452 { 453 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 454 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 455 int ret = 0; 456 457 if (dac33->fifo_mode == ucontrol->value.enumerated.item[0]) 458 return 0; 459 /* Do not allow changes while stream is running*/ 460 if (snd_soc_component_active(component)) 461 return -EPERM; 462 463 if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE) 464 ret = -EINVAL; 465 else 466 dac33->fifo_mode = ucontrol->value.enumerated.item[0]; 467 468 return ret; 469 } 470 471 /* Codec operation modes */ 472 static const char *dac33_fifo_mode_texts[] = { 473 "Bypass", "Mode 1", "Mode 7" 474 }; 475 476 static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts); 477 478 /* L/R Line Output Gain */ 479 static const char *lr_lineout_gain_texts[] = { 480 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", 481 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", 482 }; 483 484 static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum, 485 DAC33_LDAC_PWR_CTRL, 0, 486 lr_lineout_gain_texts); 487 488 static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum, 489 DAC33_RDAC_PWR_CTRL, 0, 490 lr_lineout_gain_texts); 491 492 /* 493 * DACL/R digital volume control: 494 * from 0 dB to -63.5 in 0.5 dB steps 495 * Need to be inverted later on: 496 * 0x00 == 0 dB 497 * 0x7f == -63.5 dB 498 */ 499 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); 500 501 static const struct snd_kcontrol_new dac33_snd_controls[] = { 502 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", 503 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 504 0, 0x7f, 1, dac_digivol_tlv), 505 SOC_DOUBLE_R("DAC Digital Playback Switch", 506 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), 507 SOC_DOUBLE_R("Line to Line Out Volume", 508 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), 509 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), 510 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), 511 }; 512 513 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { 514 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, 515 dac33_get_fifo_mode, dac33_set_fifo_mode), 516 }; 517 518 /* Analog bypass */ 519 static const struct snd_kcontrol_new dac33_dapm_abypassl_control = 520 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); 521 522 static const struct snd_kcontrol_new dac33_dapm_abypassr_control = 523 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); 524 525 /* LOP L/R invert selection */ 526 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; 527 528 static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum, 529 DAC33_OUT_AMP_CTRL, 3, 530 dac33_lr_lom_texts); 531 532 static const struct snd_kcontrol_new dac33_dapm_left_lom_control = 533 SOC_DAPM_ENUM("Route", dac33_left_lom_enum); 534 535 static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum, 536 DAC33_OUT_AMP_CTRL, 2, 537 dac33_lr_lom_texts); 538 539 static const struct snd_kcontrol_new dac33_dapm_right_lom_control = 540 SOC_DAPM_ENUM("Route", dac33_right_lom_enum); 541 542 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { 543 SND_SOC_DAPM_OUTPUT("LEFT_LO"), 544 SND_SOC_DAPM_OUTPUT("RIGHT_LO"), 545 546 SND_SOC_DAPM_INPUT("LINEL"), 547 SND_SOC_DAPM_INPUT("LINER"), 548 549 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), 550 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), 551 552 /* Analog bypass */ 553 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, 554 &dac33_dapm_abypassl_control), 555 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, 556 &dac33_dapm_abypassr_control), 557 558 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, 559 &dac33_dapm_left_lom_control), 560 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, 561 &dac33_dapm_right_lom_control), 562 /* 563 * For DAPM path, when only the anlog bypass path is enabled, and the 564 * LOP inverted from the corresponding DAC side. 565 * This is needed, so we can attach the DAC power supply in this case. 566 */ 567 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 568 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 569 570 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", 571 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), 572 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", 573 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), 574 575 SND_SOC_DAPM_SUPPLY("Left DAC Power", 576 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), 577 SND_SOC_DAPM_SUPPLY("Right DAC Power", 578 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), 579 580 SND_SOC_DAPM_SUPPLY("Codec Power", 581 DAC33_PWR_CTRL, 4, 0, NULL, 0), 582 583 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), 584 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), 585 }; 586 587 static const struct snd_soc_dapm_route audio_map[] = { 588 /* Analog bypass */ 589 {"Analog Left Bypass", "Switch", "LINEL"}, 590 {"Analog Right Bypass", "Switch", "LINER"}, 591 592 {"Output Left Amplifier", NULL, "DACL"}, 593 {"Output Right Amplifier", NULL, "DACR"}, 594 595 {"Left Bypass PGA", NULL, "Analog Left Bypass"}, 596 {"Right Bypass PGA", NULL, "Analog Right Bypass"}, 597 598 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, 599 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, 600 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, 601 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, 602 603 {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, 604 {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, 605 606 {"DACL", NULL, "Left DAC Power"}, 607 {"DACR", NULL, "Right DAC Power"}, 608 609 {"Left Bypass PGA", NULL, "Left DAC Power"}, 610 {"Right Bypass PGA", NULL, "Right DAC Power"}, 611 612 /* output */ 613 {"LEFT_LO", NULL, "Output Left Amplifier"}, 614 {"RIGHT_LO", NULL, "Output Right Amplifier"}, 615 616 {"LEFT_LO", NULL, "Codec Power"}, 617 {"RIGHT_LO", NULL, "Codec Power"}, 618 }; 619 620 static int dac33_set_bias_level(struct snd_soc_component *component, 621 enum snd_soc_bias_level level) 622 { 623 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 624 int ret; 625 626 switch (level) { 627 case SND_SOC_BIAS_ON: 628 break; 629 case SND_SOC_BIAS_PREPARE: 630 break; 631 case SND_SOC_BIAS_STANDBY: 632 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 633 /* Coming from OFF, switch on the component */ 634 ret = dac33_hard_power(component, 1); 635 if (ret != 0) 636 return ret; 637 638 dac33_init_chip(component); 639 } 640 break; 641 case SND_SOC_BIAS_OFF: 642 /* Do not power off, when the component is already off */ 643 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) 644 return 0; 645 ret = dac33_hard_power(component, 0); 646 if (ret != 0) 647 return ret; 648 break; 649 } 650 651 return 0; 652 } 653 654 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) 655 { 656 struct snd_soc_component *component = dac33->component; 657 unsigned int delay; 658 659 switch (dac33->fifo_mode) { 660 case DAC33_FIFO_MODE1: 661 dac33_write16(component, DAC33_NSAMPLE_MSB, 662 DAC33_THRREG(dac33->nsample)); 663 664 /* Take the timestamps */ 665 scoped_guard(spinlock_irqsave, &dac33->lock) { 666 dac33->t_stamp2 = ktime_to_us(ktime_get()); 667 dac33->t_stamp1 = dac33->t_stamp2; 668 } 669 670 dac33_write16(component, DAC33_PREFILL_MSB, 671 DAC33_THRREG(dac33->alarm_threshold)); 672 /* Enable Alarm Threshold IRQ with a delay */ 673 delay = SAMPLES_TO_US(dac33->burst_rate, 674 dac33->alarm_threshold) + 1000; 675 usleep_range(delay, delay + 500); 676 dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MAT); 677 break; 678 case DAC33_FIFO_MODE7: 679 /* Take the timestamp */ 680 scoped_guard(spinlock_irqsave, &dac33->lock) { 681 dac33->t_stamp1 = ktime_to_us(ktime_get()); 682 /* Move back the timestamp with drain time */ 683 dac33->t_stamp1 -= dac33->mode7_us_to_lthr; 684 } 685 686 dac33_write16(component, DAC33_PREFILL_MSB, 687 DAC33_THRREG(DAC33_MODE7_MARGIN)); 688 689 /* Enable Upper Threshold IRQ */ 690 dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MUT); 691 break; 692 default: 693 dev_warn(component->dev, "Unhandled FIFO mode: %d\n", 694 dac33->fifo_mode); 695 break; 696 } 697 } 698 699 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) 700 { 701 struct snd_soc_component *component = dac33->component; 702 703 switch (dac33->fifo_mode) { 704 case DAC33_FIFO_MODE1: 705 /* Take the timestamp */ 706 scoped_guard(spinlock_irqsave, &dac33->lock) 707 dac33->t_stamp2 = ktime_to_us(ktime_get()); 708 709 dac33_write16(component, DAC33_NSAMPLE_MSB, 710 DAC33_THRREG(dac33->nsample)); 711 break; 712 case DAC33_FIFO_MODE7: 713 /* At the moment we are not using interrupts in mode7 */ 714 break; 715 default: 716 dev_warn(component->dev, "Unhandled FIFO mode: %d\n", 717 dac33->fifo_mode); 718 break; 719 } 720 } 721 722 static void dac33_work(struct work_struct *work) 723 { 724 struct snd_soc_component *component; 725 struct tlv320dac33_priv *dac33; 726 u8 reg; 727 728 dac33 = container_of(work, struct tlv320dac33_priv, work); 729 component = dac33->component; 730 731 guard(mutex)(&dac33->mutex); 732 switch (dac33->state) { 733 case DAC33_PREFILL: 734 dac33->state = DAC33_PLAYBACK; 735 dac33_prefill_handler(dac33); 736 break; 737 case DAC33_PLAYBACK: 738 dac33_playback_handler(dac33); 739 break; 740 case DAC33_IDLE: 741 break; 742 case DAC33_FLUSH: 743 dac33->state = DAC33_IDLE; 744 /* Mask all interrupts from dac33 */ 745 dac33_write(component, DAC33_FIFO_IRQ_MASK, 0); 746 747 /* flush fifo */ 748 reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A); 749 reg |= DAC33_FIFOFLUSH; 750 dac33_write(component, DAC33_FIFO_CTRL_A, reg); 751 break; 752 } 753 } 754 755 static irqreturn_t dac33_interrupt_handler(int irq, void *dev) 756 { 757 struct snd_soc_component *component = dev; 758 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 759 760 scoped_guard(spinlock_irqsave, &dac33->lock) 761 dac33->t_stamp1 = ktime_to_us(ktime_get()); 762 763 /* Do not schedule the workqueue in Mode7 */ 764 if (dac33->fifo_mode != DAC33_FIFO_MODE7) 765 schedule_work(&dac33->work); 766 767 return IRQ_HANDLED; 768 } 769 770 static void dac33_oscwait(struct snd_soc_component *component) 771 { 772 int timeout = 60; 773 u8 reg; 774 775 do { 776 usleep_range(1000, 2000); 777 dac33_read(component, DAC33_INT_OSC_STATUS, ®); 778 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); 779 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) 780 dev_err(component->dev, 781 "internal oscillator calibration failed\n"); 782 } 783 784 static int dac33_startup(struct snd_pcm_substream *substream, 785 struct snd_soc_dai *dai) 786 { 787 struct snd_soc_component *component = dai->component; 788 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 789 790 /* Stream started, save the substream pointer */ 791 dac33->substream = substream; 792 793 return 0; 794 } 795 796 static void dac33_shutdown(struct snd_pcm_substream *substream, 797 struct snd_soc_dai *dai) 798 { 799 struct snd_soc_component *component = dai->component; 800 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 801 802 dac33->substream = NULL; 803 } 804 805 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ 806 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) 807 static int dac33_hw_params(struct snd_pcm_substream *substream, 808 struct snd_pcm_hw_params *params, 809 struct snd_soc_dai *dai) 810 { 811 struct snd_soc_component *component = dai->component; 812 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 813 814 /* Check parameters for validity */ 815 switch (params_rate(params)) { 816 case 44100: 817 case 48000: 818 break; 819 default: 820 dev_err(component->dev, "unsupported rate %d\n", 821 params_rate(params)); 822 return -EINVAL; 823 } 824 825 switch (params_width(params)) { 826 case 16: 827 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; 828 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); 829 break; 830 case 32: 831 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; 832 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); 833 break; 834 default: 835 dev_err(component->dev, "unsupported width %d\n", 836 params_width(params)); 837 return -EINVAL; 838 } 839 840 return 0; 841 } 842 843 #define CALC_OSCSET(rate, refclk) ( \ 844 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) 845 #define CALC_RATIOSET(rate, refclk) ( \ 846 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) 847 848 /* 849 * tlv320dac33 is strict on the sequence of the register writes, if the register 850 * writes happens in different order, than dac33 might end up in unknown state. 851 * Use the known, working sequence of register writes to initialize the dac33. 852 */ 853 static int dac33_prepare_chip(struct snd_pcm_substream *substream, 854 struct snd_soc_component *component) 855 { 856 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 857 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 858 u8 aictrl_a, aictrl_b, fifoctrl_a; 859 860 switch (substream->runtime->rate) { 861 case 44100: 862 case 48000: 863 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); 864 ratioset = CALC_RATIOSET(substream->runtime->rate, 865 dac33->refclk); 866 break; 867 default: 868 dev_err(component->dev, "unsupported rate %d\n", 869 substream->runtime->rate); 870 return -EINVAL; 871 } 872 873 874 aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A); 875 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); 876 /* Read FIFO control A, and clear FIFO flush bit */ 877 fifoctrl_a = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A); 878 fifoctrl_a &= ~DAC33_FIFOFLUSH; 879 880 fifoctrl_a &= ~DAC33_WIDTH; 881 switch (substream->runtime->format) { 882 case SNDRV_PCM_FORMAT_S16_LE: 883 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); 884 fifoctrl_a |= DAC33_WIDTH; 885 break; 886 case SNDRV_PCM_FORMAT_S32_LE: 887 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); 888 break; 889 default: 890 dev_err(component->dev, "unsupported format %d\n", 891 substream->runtime->format); 892 return -EINVAL; 893 } 894 895 guard(mutex)(&dac33->mutex); 896 897 if (!dac33->chip_power) { 898 /* 899 * Chip is not powered yet. 900 * Do the init in the dac33_set_bias_level later. 901 */ 902 return 0; 903 } 904 905 dac33_soft_power(component, 0); 906 dac33_soft_power(component, 1); 907 908 reg_tmp = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL); 909 dac33_write(component, DAC33_INT_OSC_CTRL, reg_tmp); 910 911 /* Write registers 0x08 and 0x09 (MSB, LSB) */ 912 dac33_write16(component, DAC33_INT_OSC_FREQ_RAT_A, oscset); 913 914 /* OSC calibration time */ 915 dac33_write(component, DAC33_CALIB_TIME, 96); 916 917 /* adjustment treshold & step */ 918 dac33_write(component, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | 919 DAC33_ADJSTEP(1)); 920 921 /* div=4 / gain=1 / div */ 922 dac33_write(component, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); 923 924 pwr_ctrl = dac33_read_reg_cache(component, DAC33_PWR_CTRL); 925 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; 926 dac33_write(component, DAC33_PWR_CTRL, pwr_ctrl); 927 928 dac33_oscwait(component); 929 930 if (dac33->fifo_mode) { 931 /* Generic for all FIFO modes */ 932 /* 50-51 : ASRC Control registers */ 933 dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); 934 dac33_write(component, DAC33_ASRC_CTRL_B, 1); /* ??? */ 935 936 /* Write registers 0x34 and 0x35 (MSB, LSB) */ 937 dac33_write16(component, DAC33_SRC_REF_CLK_RATIO_A, ratioset); 938 939 /* Set interrupts to high active */ 940 dac33_write(component, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); 941 } else { 942 /* FIFO bypass mode */ 943 /* 50-51 : ASRC Control registers */ 944 dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); 945 dac33_write(component, DAC33_ASRC_CTRL_B, 0); /* ??? */ 946 } 947 948 /* Interrupt behaviour configuration */ 949 switch (dac33->fifo_mode) { 950 case DAC33_FIFO_MODE1: 951 dac33_write(component, DAC33_FIFO_IRQ_MODE_B, 952 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 953 break; 954 case DAC33_FIFO_MODE7: 955 dac33_write(component, DAC33_FIFO_IRQ_MODE_A, 956 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); 957 break; 958 default: 959 /* in FIFO bypass mode, the interrupts are not used */ 960 break; 961 } 962 963 aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); 964 965 switch (dac33->fifo_mode) { 966 case DAC33_FIFO_MODE1: 967 /* 968 * For mode1: 969 * Disable the FIFO bypass (Enable the use of FIFO) 970 * Select nSample mode 971 * BCLK is only running when data is needed by DAC33 972 */ 973 fifoctrl_a &= ~DAC33_FBYPAS; 974 fifoctrl_a &= ~DAC33_FAUTO; 975 if (dac33->keep_bclk) 976 aictrl_b |= DAC33_BCLKON; 977 else 978 aictrl_b &= ~DAC33_BCLKON; 979 break; 980 case DAC33_FIFO_MODE7: 981 /* 982 * For mode1: 983 * Disable the FIFO bypass (Enable the use of FIFO) 984 * Select Threshold mode 985 * BCLK is only running when data is needed by DAC33 986 */ 987 fifoctrl_a &= ~DAC33_FBYPAS; 988 fifoctrl_a |= DAC33_FAUTO; 989 if (dac33->keep_bclk) 990 aictrl_b |= DAC33_BCLKON; 991 else 992 aictrl_b &= ~DAC33_BCLKON; 993 break; 994 default: 995 /* 996 * For FIFO bypass mode: 997 * Enable the FIFO bypass (Disable the FIFO use) 998 * Set the BCLK as continuous 999 */ 1000 fifoctrl_a |= DAC33_FBYPAS; 1001 aictrl_b |= DAC33_BCLKON; 1002 break; 1003 } 1004 1005 dac33_write(component, DAC33_FIFO_CTRL_A, fifoctrl_a); 1006 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1007 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1008 1009 /* 1010 * BCLK divide ratio 1011 * 0: 1.5 1012 * 1: 1 1013 * 2: 2 1014 * ... 1015 * 254: 254 1016 * 255: 255 1017 */ 1018 if (dac33->fifo_mode) 1019 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 1020 dac33->burst_bclkdiv); 1021 else 1022 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 1023 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 32); 1024 else 1025 dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 16); 1026 1027 switch (dac33->fifo_mode) { 1028 case DAC33_FIFO_MODE1: 1029 dac33_write16(component, DAC33_ATHR_MSB, 1030 DAC33_THRREG(dac33->alarm_threshold)); 1031 break; 1032 case DAC33_FIFO_MODE7: 1033 /* 1034 * Configure the threshold levels, and leave 10 sample space 1035 * at the bottom, and also at the top of the FIFO 1036 */ 1037 dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); 1038 dac33_write16(component, DAC33_LTHR_MSB, 1039 DAC33_THRREG(DAC33_MODE7_MARGIN)); 1040 break; 1041 default: 1042 break; 1043 } 1044 1045 return 0; 1046 } 1047 1048 static void dac33_calculate_times(struct snd_pcm_substream *substream, 1049 struct snd_soc_component *component) 1050 { 1051 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1052 unsigned int period_size = substream->runtime->period_size; 1053 unsigned int rate = substream->runtime->rate; 1054 unsigned int nsample_limit; 1055 1056 /* In bypass mode we don't need to calculate */ 1057 if (!dac33->fifo_mode) 1058 return; 1059 1060 switch (dac33->fifo_mode) { 1061 case DAC33_FIFO_MODE1: 1062 /* Number of samples under i2c latency */ 1063 dac33->alarm_threshold = US_TO_SAMPLES(rate, 1064 dac33->mode1_latency); 1065 nsample_limit = dac33->fifo_size - dac33->alarm_threshold; 1066 1067 if (period_size <= dac33->alarm_threshold) 1068 /* 1069 * Configure nSamaple to number of periods, 1070 * which covers the latency requironment. 1071 */ 1072 dac33->nsample = period_size * 1073 ((dac33->alarm_threshold / period_size) + 1074 ((dac33->alarm_threshold % period_size) ? 1075 1 : 0)); 1076 else if (period_size > nsample_limit) 1077 dac33->nsample = nsample_limit; 1078 else 1079 dac33->nsample = period_size; 1080 1081 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, 1082 dac33->nsample); 1083 dac33->t_stamp1 = 0; 1084 dac33->t_stamp2 = 0; 1085 break; 1086 case DAC33_FIFO_MODE7: 1087 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, 1088 dac33->burst_rate) + 9; 1089 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) 1090 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; 1091 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) 1092 dac33->uthr = (DAC33_MODE7_MARGIN + 10); 1093 1094 dac33->mode7_us_to_lthr = 1095 SAMPLES_TO_US(substream->runtime->rate, 1096 dac33->uthr - DAC33_MODE7_MARGIN + 1); 1097 dac33->t_stamp1 = 0; 1098 break; 1099 default: 1100 break; 1101 } 1102 1103 } 1104 1105 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 1106 struct snd_soc_dai *dai) 1107 { 1108 struct snd_soc_component *component = dai->component; 1109 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1110 int ret = 0; 1111 1112 switch (cmd) { 1113 case SNDRV_PCM_TRIGGER_START: 1114 case SNDRV_PCM_TRIGGER_RESUME: 1115 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1116 if (dac33->fifo_mode) { 1117 dac33->state = DAC33_PREFILL; 1118 schedule_work(&dac33->work); 1119 } 1120 break; 1121 case SNDRV_PCM_TRIGGER_STOP: 1122 case SNDRV_PCM_TRIGGER_SUSPEND: 1123 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1124 if (dac33->fifo_mode) { 1125 dac33->state = DAC33_FLUSH; 1126 schedule_work(&dac33->work); 1127 } 1128 break; 1129 default: 1130 ret = -EINVAL; 1131 } 1132 1133 return ret; 1134 } 1135 1136 static snd_pcm_sframes_t dac33_dai_delay( 1137 struct snd_pcm_substream *substream, 1138 struct snd_soc_dai *dai) 1139 { 1140 struct snd_soc_component *component = dai->component; 1141 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1142 unsigned long long t0, t1, t_now; 1143 unsigned int time_delta, uthr; 1144 int samples_out, samples_in, samples; 1145 snd_pcm_sframes_t delay = 0; 1146 1147 switch (dac33->fifo_mode) { 1148 case DAC33_FIFO_BYPASS: 1149 break; 1150 case DAC33_FIFO_MODE1: 1151 scoped_guard(spinlock_irqsave, &dac33->lock) { 1152 t0 = dac33->t_stamp1; 1153 t1 = dac33->t_stamp2; 1154 } 1155 t_now = ktime_to_us(ktime_get()); 1156 1157 /* We have not started to fill the FIFO yet, delay is 0 */ 1158 if (!t1) 1159 return 0; 1160 1161 if (t0 > t1) { 1162 /* 1163 * Phase 1: 1164 * After Alarm threshold, and before nSample write 1165 */ 1166 time_delta = t_now - t0; 1167 samples_out = time_delta ? US_TO_SAMPLES( 1168 substream->runtime->rate, 1169 time_delta) : 0; 1170 1171 if (likely(dac33->alarm_threshold > samples_out)) 1172 delay = dac33->alarm_threshold - samples_out; 1173 else 1174 delay = 0; 1175 } else if ((t_now - t1) <= dac33->mode1_us_burst) { 1176 /* 1177 * Phase 2: 1178 * After nSample write (during burst operation) 1179 */ 1180 time_delta = t_now - t0; 1181 samples_out = time_delta ? US_TO_SAMPLES( 1182 substream->runtime->rate, 1183 time_delta) : 0; 1184 1185 time_delta = t_now - t1; 1186 samples_in = time_delta ? US_TO_SAMPLES( 1187 dac33->burst_rate, 1188 time_delta) : 0; 1189 1190 samples = dac33->alarm_threshold; 1191 samples += (samples_in - samples_out); 1192 1193 if (likely(samples > 0)) 1194 delay = samples; 1195 else 1196 delay = 0; 1197 } else { 1198 /* 1199 * Phase 3: 1200 * After burst operation, before next alarm threshold 1201 */ 1202 time_delta = t_now - t0; 1203 samples_out = time_delta ? US_TO_SAMPLES( 1204 substream->runtime->rate, 1205 time_delta) : 0; 1206 1207 samples_in = dac33->nsample; 1208 samples = dac33->alarm_threshold; 1209 samples += (samples_in - samples_out); 1210 1211 if (likely(samples > 0)) 1212 delay = samples > dac33->fifo_size ? 1213 dac33->fifo_size : samples; 1214 else 1215 delay = 0; 1216 } 1217 break; 1218 case DAC33_FIFO_MODE7: 1219 scoped_guard(spinlock_irqsave, &dac33->lock) { 1220 t0 = dac33->t_stamp1; 1221 uthr = dac33->uthr; 1222 } 1223 t_now = ktime_to_us(ktime_get()); 1224 1225 /* We have not started to fill the FIFO yet, delay is 0 */ 1226 if (!t0) 1227 return 0; 1228 1229 if (t_now <= t0) { 1230 /* 1231 * Either the timestamps are messed or equal. Report 1232 * maximum delay 1233 */ 1234 return uthr; 1235 } 1236 1237 time_delta = t_now - t0; 1238 if (time_delta <= dac33->mode7_us_to_lthr) { 1239 /* 1240 * Phase 1: 1241 * After burst (draining phase) 1242 */ 1243 samples_out = US_TO_SAMPLES( 1244 substream->runtime->rate, 1245 time_delta); 1246 1247 if (likely(uthr > samples_out)) 1248 delay = uthr - samples_out; 1249 else 1250 delay = 0; 1251 } else { 1252 /* 1253 * Phase 2: 1254 * During burst operation 1255 */ 1256 time_delta = time_delta - dac33->mode7_us_to_lthr; 1257 1258 samples_out = US_TO_SAMPLES( 1259 substream->runtime->rate, 1260 time_delta); 1261 samples_in = US_TO_SAMPLES( 1262 dac33->burst_rate, 1263 time_delta); 1264 delay = DAC33_MODE7_MARGIN + samples_in - samples_out; 1265 1266 if (unlikely(delay > uthr)) 1267 delay = uthr; 1268 } 1269 break; 1270 default: 1271 dev_warn(component->dev, "Unhandled FIFO mode: %d\n", 1272 dac33->fifo_mode); 1273 break; 1274 } 1275 1276 return delay; 1277 } 1278 1279 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1280 int clk_id, unsigned int freq, int dir) 1281 { 1282 struct snd_soc_component *component = codec_dai->component; 1283 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1284 u8 ioc_reg, asrcb_reg; 1285 1286 ioc_reg = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL); 1287 asrcb_reg = dac33_read_reg_cache(component, DAC33_ASRC_CTRL_B); 1288 switch (clk_id) { 1289 case TLV320DAC33_MCLK: 1290 ioc_reg |= DAC33_REFSEL; 1291 asrcb_reg |= DAC33_SRCREFSEL; 1292 break; 1293 case TLV320DAC33_SLEEPCLK: 1294 ioc_reg &= ~DAC33_REFSEL; 1295 asrcb_reg &= ~DAC33_SRCREFSEL; 1296 break; 1297 default: 1298 dev_err(component->dev, "Invalid clock ID (%d)\n", clk_id); 1299 break; 1300 } 1301 dac33->refclk = freq; 1302 1303 dac33_write_reg_cache(component, DAC33_INT_OSC_CTRL, ioc_reg); 1304 dac33_write_reg_cache(component, DAC33_ASRC_CTRL_B, asrcb_reg); 1305 1306 return 0; 1307 } 1308 1309 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, 1310 unsigned int fmt) 1311 { 1312 struct snd_soc_component *component = codec_dai->component; 1313 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1314 u8 aictrl_a, aictrl_b; 1315 1316 aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A); 1317 aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); 1318 1319 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1320 case SND_SOC_DAIFMT_CBP_CFP: 1321 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); 1322 break; 1323 case SND_SOC_DAIFMT_CBC_CFC: 1324 if (dac33->fifo_mode) { 1325 dev_err(component->dev, "FIFO mode requires provider mode\n"); 1326 return -EINVAL; 1327 } else 1328 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); 1329 break; 1330 default: 1331 return -EINVAL; 1332 } 1333 1334 aictrl_a &= ~DAC33_AFMT_MASK; 1335 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1336 case SND_SOC_DAIFMT_I2S: 1337 aictrl_a |= DAC33_AFMT_I2S; 1338 break; 1339 case SND_SOC_DAIFMT_DSP_A: 1340 aictrl_a |= DAC33_AFMT_DSP; 1341 aictrl_b &= ~DAC33_DATA_DELAY_MASK; 1342 aictrl_b |= DAC33_DATA_DELAY(0); 1343 break; 1344 case SND_SOC_DAIFMT_RIGHT_J: 1345 aictrl_a |= DAC33_AFMT_RIGHT_J; 1346 break; 1347 case SND_SOC_DAIFMT_LEFT_J: 1348 aictrl_a |= DAC33_AFMT_LEFT_J; 1349 break; 1350 default: 1351 dev_err(component->dev, "Unsupported format (%u)\n", 1352 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1353 return -EINVAL; 1354 } 1355 1356 dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1357 dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1358 1359 return 0; 1360 } 1361 1362 static int dac33_soc_probe(struct snd_soc_component *component) 1363 { 1364 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1365 int ret = 0; 1366 1367 dac33->component = component; 1368 1369 /* Read the tlv320dac33 ID registers */ 1370 ret = dac33_hard_power(component, 1); 1371 if (ret != 0) { 1372 dev_err(component->dev, "Failed to power up component: %d\n", ret); 1373 goto err_power; 1374 } 1375 ret = dac33_read_id(component); 1376 dac33_hard_power(component, 0); 1377 1378 if (ret < 0) { 1379 dev_err(component->dev, "Failed to read chip ID: %d\n", ret); 1380 ret = -ENODEV; 1381 goto err_power; 1382 } 1383 1384 /* Check if the IRQ number is valid and request it */ 1385 if (dac33->irq >= 0) { 1386 ret = request_irq(dac33->irq, dac33_interrupt_handler, 1387 IRQF_TRIGGER_RISING, 1388 component->name, component); 1389 if (ret < 0) { 1390 dev_err(component->dev, "Could not request IRQ%d (%d)\n", 1391 dac33->irq, ret); 1392 dac33->irq = -1; 1393 } 1394 if (dac33->irq != -1) { 1395 INIT_WORK(&dac33->work, dac33_work); 1396 } 1397 } 1398 1399 /* Only add the FIFO controls, if we have valid IRQ number */ 1400 if (dac33->irq >= 0) 1401 snd_soc_add_component_controls(component, dac33_mode_snd_controls, 1402 ARRAY_SIZE(dac33_mode_snd_controls)); 1403 1404 err_power: 1405 return ret; 1406 } 1407 1408 static void dac33_soc_remove(struct snd_soc_component *component) 1409 { 1410 struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component); 1411 1412 if (dac33->irq >= 0) { 1413 free_irq(dac33->irq, dac33->component); 1414 flush_work(&dac33->work); 1415 } 1416 } 1417 1418 static const struct snd_soc_component_driver soc_component_dev_tlv320dac33 = { 1419 .read = dac33_read_reg_cache, 1420 .write = dac33_write_locked, 1421 .set_bias_level = dac33_set_bias_level, 1422 .probe = dac33_soc_probe, 1423 .remove = dac33_soc_remove, 1424 .controls = dac33_snd_controls, 1425 .num_controls = ARRAY_SIZE(dac33_snd_controls), 1426 .dapm_widgets = dac33_dapm_widgets, 1427 .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets), 1428 .dapm_routes = audio_map, 1429 .num_dapm_routes = ARRAY_SIZE(audio_map), 1430 .use_pmdown_time = 1, 1431 .endianness = 1, 1432 }; 1433 1434 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ 1435 SNDRV_PCM_RATE_48000) 1436 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 1437 1438 static const struct snd_soc_dai_ops dac33_dai_ops = { 1439 .startup = dac33_startup, 1440 .shutdown = dac33_shutdown, 1441 .hw_params = dac33_hw_params, 1442 .trigger = dac33_pcm_trigger, 1443 .delay = dac33_dai_delay, 1444 .set_sysclk = dac33_set_dai_sysclk, 1445 .set_fmt = dac33_set_dai_fmt, 1446 }; 1447 1448 static struct snd_soc_dai_driver dac33_dai = { 1449 .name = "tlv320dac33-hifi", 1450 .playback = { 1451 .stream_name = "Playback", 1452 .channels_min = 2, 1453 .channels_max = 2, 1454 .rates = DAC33_RATES, 1455 .formats = DAC33_FORMATS, 1456 .sig_bits = 24, 1457 }, 1458 .ops = &dac33_dai_ops, 1459 }; 1460 1461 static int dac33_i2c_probe(struct i2c_client *client) 1462 { 1463 struct tlv320dac33_priv *dac33; 1464 int ret, i; 1465 1466 dac33 = devm_kzalloc(&client->dev, struct_size(dac33, reg_cache, ARRAY_SIZE(dac33_reg)), 1467 GFP_KERNEL); 1468 if (dac33 == NULL) 1469 return -ENOMEM; 1470 1471 memcpy(dac33->reg_cache, dac33_reg, ARRAY_SIZE(dac33_reg)); 1472 1473 dac33->i2c = client; 1474 mutex_init(&dac33->mutex); 1475 spin_lock_init(&dac33->lock); 1476 1477 i2c_set_clientdata(client, dac33); 1478 1479 if (!dac33->burst_bclkdiv) 1480 dac33->burst_bclkdiv = 8; 1481 if (!dac33->mode1_latency) 1482 dac33->mode1_latency = 10000; /* 10ms */ 1483 dac33->irq = client->irq; 1484 /* Disable FIFO use by default */ 1485 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1486 1487 /* request optional reset GPIO */ 1488 dac33->reset_gpiod = 1489 devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_LOW); 1490 if (IS_ERR(dac33->reset_gpiod)) { 1491 ret = PTR_ERR(dac33->reset_gpiod); 1492 dev_err_probe(&client->dev, ret, 1493 "Failed to get reset GPIO\n"); 1494 goto err; 1495 } 1496 1497 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) 1498 dac33->supplies[i].supply = dac33_supply_names[i]; 1499 1500 ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), 1501 dac33->supplies); 1502 1503 if (ret != 0) { 1504 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 1505 goto err; 1506 } 1507 1508 ret = devm_snd_soc_register_component(&client->dev, 1509 &soc_component_dev_tlv320dac33, &dac33_dai, 1); 1510 if (ret < 0) 1511 goto err; 1512 1513 return ret; 1514 1515 err: 1516 return ret; 1517 } 1518 1519 static void dac33_i2c_remove(struct i2c_client *client) 1520 { 1521 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); 1522 1523 if (unlikely(dac33->chip_power)) 1524 dac33_hard_power(dac33->component, 0); 1525 } 1526 1527 static const struct i2c_device_id tlv320dac33_i2c_id[] = { 1528 { 1529 .name = "tlv320dac33", 1530 .driver_data = 0, 1531 }, 1532 { }, 1533 }; 1534 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); 1535 1536 static struct i2c_driver tlv320dac33_i2c_driver = { 1537 .driver = { 1538 .name = "tlv320dac33-codec", 1539 }, 1540 .probe = dac33_i2c_probe, 1541 .remove = dac33_i2c_remove, 1542 .id_table = tlv320dac33_i2c_id, 1543 }; 1544 1545 module_i2c_driver(tlv320dac33_i2c_driver); 1546 1547 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); 1548 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1549 MODULE_LICENSE("GPL"); 1550