1 /* 2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver 3 * 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 * 6 * Copyright: (C) 2009 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/pm.h> 29 #include <linux/i2c.h> 30 #include <linux/interrupt.h> 31 #include <linux/gpio.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/slab.h> 34 #include <sound/core.h> 35 #include <sound/pcm.h> 36 #include <sound/pcm_params.h> 37 #include <sound/soc.h> 38 #include <sound/initval.h> 39 #include <sound/tlv.h> 40 41 #include <sound/tlv320dac33-plat.h> 42 #include "tlv320dac33.h" 43 44 /* 45 * The internal FIFO is 24576 bytes long 46 * It can be configured to hold 16bit or 24bit samples 47 * In 16bit configuration the FIFO can hold 6144 stereo samples 48 * In 24bit configuration the FIFO can hold 4096 stereo samples 49 */ 50 #define DAC33_FIFO_SIZE_16BIT 6144 51 #define DAC33_FIFO_SIZE_24BIT 4096 52 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ 53 54 #define BURST_BASEFREQ_HZ 49152000 55 56 #define SAMPLES_TO_US(rate, samples) \ 57 (1000000000 / (((rate) * 1000) / (samples))) 58 59 #define US_TO_SAMPLES(rate, us) \ 60 ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000))) 61 62 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ 63 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) 64 65 static void dac33_calculate_times(struct snd_pcm_substream *substream); 66 static int dac33_prepare_chip(struct snd_pcm_substream *substream); 67 68 enum dac33_state { 69 DAC33_IDLE = 0, 70 DAC33_PREFILL, 71 DAC33_PLAYBACK, 72 DAC33_FLUSH, 73 }; 74 75 enum dac33_fifo_modes { 76 DAC33_FIFO_BYPASS = 0, 77 DAC33_FIFO_MODE1, 78 DAC33_FIFO_MODE7, 79 DAC33_FIFO_LAST_MODE, 80 }; 81 82 #define DAC33_NUM_SUPPLIES 3 83 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { 84 "AVDD", 85 "DVDD", 86 "IOVDD", 87 }; 88 89 struct tlv320dac33_priv { 90 struct mutex mutex; 91 struct workqueue_struct *dac33_wq; 92 struct work_struct work; 93 struct snd_soc_codec *codec; 94 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; 95 struct snd_pcm_substream *substream; 96 int power_gpio; 97 int chip_power; 98 int irq; 99 unsigned int refclk; 100 101 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ 102 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 103 unsigned int fifo_size; /* Size of the FIFO in samples */ 104 unsigned int nsample; /* burst read amount from host */ 105 int mode1_latency; /* latency caused by the i2c writes in 106 * us */ 107 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 108 unsigned int burst_rate; /* Interface speed in Burst modes */ 109 110 int keep_bclk; /* Keep the BCLK continuously running 111 * in FIFO modes */ 112 spinlock_t lock; 113 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ 114 unsigned long long t_stamp2; /* calculate the FIFO caused delay */ 115 116 unsigned int mode1_us_burst; /* Time to burst read n number of 117 * samples */ 118 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ 119 120 unsigned int uthr; 121 122 enum dac33_state state; 123 enum snd_soc_control_type control_type; 124 void *control_data; 125 }; 126 127 static const u8 dac33_reg[DAC33_CACHEREGNUM] = { 128 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ 129 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ 130 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ 131 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ 132 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ 133 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ 134 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ 135 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ 136 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ 137 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ 138 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ 139 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ 140 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ 141 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ 142 0x00, 0x00, /* 0x38 - 0x39 */ 143 /* Registers 0x3a - 0x3f are reserved */ 144 0x00, 0x00, /* 0x3a - 0x3b */ 145 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ 146 147 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ 148 0x00, 0x80, /* 0x44 - 0x45 */ 149 /* Registers 0x46 - 0x47 are reserved */ 150 0x80, 0x80, /* 0x46 - 0x47 */ 151 152 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ 153 /* Registers 0x4b - 0x7c are reserved */ 154 0x00, /* 0x4b */ 155 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ 156 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ 157 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ 158 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ 159 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ 160 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ 161 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ 162 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ 163 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ 164 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ 165 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ 166 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ 167 0x00, /* 0x7c */ 168 169 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ 170 }; 171 172 /* Register read and write */ 173 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, 174 unsigned reg) 175 { 176 u8 *cache = codec->reg_cache; 177 if (reg >= DAC33_CACHEREGNUM) 178 return 0; 179 180 return cache[reg]; 181 } 182 183 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, 184 u8 reg, u8 value) 185 { 186 u8 *cache = codec->reg_cache; 187 if (reg >= DAC33_CACHEREGNUM) 188 return; 189 190 cache[reg] = value; 191 } 192 193 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, 194 u8 *value) 195 { 196 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 197 int val, ret = 0; 198 199 *value = reg & 0xff; 200 201 /* If powered off, return the cached value */ 202 if (dac33->chip_power) { 203 val = i2c_smbus_read_byte_data(codec->control_data, value[0]); 204 if (val < 0) { 205 dev_err(codec->dev, "Read failed (%d)\n", val); 206 value[0] = dac33_read_reg_cache(codec, reg); 207 ret = val; 208 } else { 209 value[0] = val; 210 dac33_write_reg_cache(codec, reg, val); 211 } 212 } else { 213 value[0] = dac33_read_reg_cache(codec, reg); 214 } 215 216 return ret; 217 } 218 219 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, 220 unsigned int value) 221 { 222 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 223 u8 data[2]; 224 int ret = 0; 225 226 /* 227 * data is 228 * D15..D8 dac33 register offset 229 * D7...D0 register data 230 */ 231 data[0] = reg & 0xff; 232 data[1] = value & 0xff; 233 234 dac33_write_reg_cache(codec, data[0], data[1]); 235 if (dac33->chip_power) { 236 ret = codec->hw_write(codec->control_data, data, 2); 237 if (ret != 2) 238 dev_err(codec->dev, "Write failed (%d)\n", ret); 239 else 240 ret = 0; 241 } 242 243 return ret; 244 } 245 246 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, 247 unsigned int value) 248 { 249 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 250 int ret; 251 252 mutex_lock(&dac33->mutex); 253 ret = dac33_write(codec, reg, value); 254 mutex_unlock(&dac33->mutex); 255 256 return ret; 257 } 258 259 #define DAC33_I2C_ADDR_AUTOINC 0x80 260 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, 261 unsigned int value) 262 { 263 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 264 u8 data[3]; 265 int ret = 0; 266 267 /* 268 * data is 269 * D23..D16 dac33 register offset 270 * D15..D8 register data MSB 271 * D7...D0 register data LSB 272 */ 273 data[0] = reg & 0xff; 274 data[1] = (value >> 8) & 0xff; 275 data[2] = value & 0xff; 276 277 dac33_write_reg_cache(codec, data[0], data[1]); 278 dac33_write_reg_cache(codec, data[0] + 1, data[2]); 279 280 if (dac33->chip_power) { 281 /* We need to set autoincrement mode for 16 bit writes */ 282 data[0] |= DAC33_I2C_ADDR_AUTOINC; 283 ret = codec->hw_write(codec->control_data, data, 3); 284 if (ret != 3) 285 dev_err(codec->dev, "Write failed (%d)\n", ret); 286 else 287 ret = 0; 288 } 289 290 return ret; 291 } 292 293 static void dac33_init_chip(struct snd_soc_codec *codec) 294 { 295 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 296 297 if (unlikely(!dac33->chip_power)) 298 return; 299 300 /* A : DAC sample rate Fsref/1.5 */ 301 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); 302 /* B : DAC src=normal, not muted */ 303 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | 304 DAC33_DACSRCL_LEFT); 305 /* C : (defaults) */ 306 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); 307 308 /* 73 : volume soft stepping control, 309 clock source = internal osc (?) */ 310 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); 311 312 /* Restore only selected registers (gains mostly) */ 313 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, 314 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); 315 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, 316 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); 317 318 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, 319 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); 320 dac33_write(codec, DAC33_LINER_TO_RLO_VOL, 321 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); 322 323 dac33_write(codec, DAC33_OUT_AMP_CTRL, 324 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL)); 325 326 dac33_write(codec, DAC33_LDAC_PWR_CTRL, 327 dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL)); 328 dac33_write(codec, DAC33_RDAC_PWR_CTRL, 329 dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL)); 330 } 331 332 static inline int dac33_read_id(struct snd_soc_codec *codec) 333 { 334 int i, ret = 0; 335 u8 reg; 336 337 for (i = 0; i < 3; i++) { 338 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, ®); 339 if (ret < 0) 340 break; 341 } 342 343 return ret; 344 } 345 346 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) 347 { 348 u8 reg; 349 350 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 351 if (power) 352 reg |= DAC33_PDNALLB; 353 else 354 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | 355 DAC33_DACRPDNB | DAC33_DACLPDNB); 356 dac33_write(codec, DAC33_PWR_CTRL, reg); 357 } 358 359 static inline void dac33_disable_digital(struct snd_soc_codec *codec) 360 { 361 u8 reg; 362 363 /* Stop the DAI clock */ 364 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 365 reg &= ~DAC33_BCLKON; 366 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg); 367 368 /* Power down the Oscillator, and DACs */ 369 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 370 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); 371 dac33_write(codec, DAC33_PWR_CTRL, reg); 372 } 373 374 static int dac33_hard_power(struct snd_soc_codec *codec, int power) 375 { 376 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 377 int ret = 0; 378 379 mutex_lock(&dac33->mutex); 380 381 /* Safety check */ 382 if (unlikely(power == dac33->chip_power)) { 383 dev_dbg(codec->dev, "Trying to set the same power state: %s\n", 384 power ? "ON" : "OFF"); 385 goto exit; 386 } 387 388 if (power) { 389 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), 390 dac33->supplies); 391 if (ret != 0) { 392 dev_err(codec->dev, 393 "Failed to enable supplies: %d\n", ret); 394 goto exit; 395 } 396 397 if (dac33->power_gpio >= 0) 398 gpio_set_value(dac33->power_gpio, 1); 399 400 dac33->chip_power = 1; 401 } else { 402 dac33_soft_power(codec, 0); 403 if (dac33->power_gpio >= 0) 404 gpio_set_value(dac33->power_gpio, 0); 405 406 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), 407 dac33->supplies); 408 if (ret != 0) { 409 dev_err(codec->dev, 410 "Failed to disable supplies: %d\n", ret); 411 goto exit; 412 } 413 414 dac33->chip_power = 0; 415 } 416 417 exit: 418 mutex_unlock(&dac33->mutex); 419 return ret; 420 } 421 422 static int dac33_playback_event(struct snd_soc_dapm_widget *w, 423 struct snd_kcontrol *kcontrol, int event) 424 { 425 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec); 426 427 switch (event) { 428 case SND_SOC_DAPM_PRE_PMU: 429 if (likely(dac33->substream)) { 430 dac33_calculate_times(dac33->substream); 431 dac33_prepare_chip(dac33->substream); 432 } 433 break; 434 case SND_SOC_DAPM_POST_PMD: 435 dac33_disable_digital(w->codec); 436 break; 437 } 438 return 0; 439 } 440 441 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 442 struct snd_ctl_elem_value *ucontrol) 443 { 444 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 445 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 446 447 ucontrol->value.integer.value[0] = dac33->fifo_mode; 448 449 return 0; 450 } 451 452 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, 453 struct snd_ctl_elem_value *ucontrol) 454 { 455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 456 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 457 int ret = 0; 458 459 if (dac33->fifo_mode == ucontrol->value.integer.value[0]) 460 return 0; 461 /* Do not allow changes while stream is running*/ 462 if (codec->active) 463 return -EPERM; 464 465 if (ucontrol->value.integer.value[0] < 0 || 466 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE) 467 ret = -EINVAL; 468 else 469 dac33->fifo_mode = ucontrol->value.integer.value[0]; 470 471 return ret; 472 } 473 474 /* Codec operation modes */ 475 static const char *dac33_fifo_mode_texts[] = { 476 "Bypass", "Mode 1", "Mode 7" 477 }; 478 479 static const struct soc_enum dac33_fifo_mode_enum = 480 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts), 481 dac33_fifo_mode_texts); 482 483 /* L/R Line Output Gain */ 484 static const char *lr_lineout_gain_texts[] = { 485 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", 486 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", 487 }; 488 489 static const struct soc_enum l_lineout_gain_enum = 490 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0, 491 ARRAY_SIZE(lr_lineout_gain_texts), 492 lr_lineout_gain_texts); 493 494 static const struct soc_enum r_lineout_gain_enum = 495 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0, 496 ARRAY_SIZE(lr_lineout_gain_texts), 497 lr_lineout_gain_texts); 498 499 /* 500 * DACL/R digital volume control: 501 * from 0 dB to -63.5 in 0.5 dB steps 502 * Need to be inverted later on: 503 * 0x00 == 0 dB 504 * 0x7f == -63.5 dB 505 */ 506 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); 507 508 static const struct snd_kcontrol_new dac33_snd_controls[] = { 509 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", 510 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 511 0, 0x7f, 1, dac_digivol_tlv), 512 SOC_DOUBLE_R("DAC Digital Playback Switch", 513 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), 514 SOC_DOUBLE_R("Line to Line Out Volume", 515 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), 516 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), 517 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), 518 }; 519 520 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { 521 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, 522 dac33_get_fifo_mode, dac33_set_fifo_mode), 523 }; 524 525 /* Analog bypass */ 526 static const struct snd_kcontrol_new dac33_dapm_abypassl_control = 527 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); 528 529 static const struct snd_kcontrol_new dac33_dapm_abypassr_control = 530 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); 531 532 /* LOP L/R invert selection */ 533 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; 534 535 static const struct soc_enum dac33_left_lom_enum = 536 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3, 537 ARRAY_SIZE(dac33_lr_lom_texts), 538 dac33_lr_lom_texts); 539 540 static const struct snd_kcontrol_new dac33_dapm_left_lom_control = 541 SOC_DAPM_ENUM("Route", dac33_left_lom_enum); 542 543 static const struct soc_enum dac33_right_lom_enum = 544 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2, 545 ARRAY_SIZE(dac33_lr_lom_texts), 546 dac33_lr_lom_texts); 547 548 static const struct snd_kcontrol_new dac33_dapm_right_lom_control = 549 SOC_DAPM_ENUM("Route", dac33_right_lom_enum); 550 551 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { 552 SND_SOC_DAPM_OUTPUT("LEFT_LO"), 553 SND_SOC_DAPM_OUTPUT("RIGHT_LO"), 554 555 SND_SOC_DAPM_INPUT("LINEL"), 556 SND_SOC_DAPM_INPUT("LINER"), 557 558 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), 559 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), 560 561 /* Analog bypass */ 562 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, 563 &dac33_dapm_abypassl_control), 564 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, 565 &dac33_dapm_abypassr_control), 566 567 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, 568 &dac33_dapm_left_lom_control), 569 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, 570 &dac33_dapm_right_lom_control), 571 /* 572 * For DAPM path, when only the anlog bypass path is enabled, and the 573 * LOP inverted from the corresponding DAC side. 574 * This is needed, so we can attach the DAC power supply in this case. 575 */ 576 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 577 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 578 579 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", 580 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), 581 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", 582 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), 583 584 SND_SOC_DAPM_SUPPLY("Left DAC Power", 585 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), 586 SND_SOC_DAPM_SUPPLY("Right DAC Power", 587 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), 588 589 SND_SOC_DAPM_SUPPLY("Codec Power", 590 DAC33_PWR_CTRL, 4, 0, NULL, 0), 591 592 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), 593 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), 594 }; 595 596 static const struct snd_soc_dapm_route audio_map[] = { 597 /* Analog bypass */ 598 {"Analog Left Bypass", "Switch", "LINEL"}, 599 {"Analog Right Bypass", "Switch", "LINER"}, 600 601 {"Output Left Amplifier", NULL, "DACL"}, 602 {"Output Right Amplifier", NULL, "DACR"}, 603 604 {"Left Bypass PGA", NULL, "Analog Left Bypass"}, 605 {"Right Bypass PGA", NULL, "Analog Right Bypass"}, 606 607 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, 608 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, 609 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, 610 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, 611 612 {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, 613 {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, 614 615 {"DACL", NULL, "Left DAC Power"}, 616 {"DACR", NULL, "Right DAC Power"}, 617 618 {"Left Bypass PGA", NULL, "Left DAC Power"}, 619 {"Right Bypass PGA", NULL, "Right DAC Power"}, 620 621 /* output */ 622 {"LEFT_LO", NULL, "Output Left Amplifier"}, 623 {"RIGHT_LO", NULL, "Output Right Amplifier"}, 624 625 {"LEFT_LO", NULL, "Codec Power"}, 626 {"RIGHT_LO", NULL, "Codec Power"}, 627 }; 628 629 static int dac33_set_bias_level(struct snd_soc_codec *codec, 630 enum snd_soc_bias_level level) 631 { 632 int ret; 633 634 switch (level) { 635 case SND_SOC_BIAS_ON: 636 break; 637 case SND_SOC_BIAS_PREPARE: 638 break; 639 case SND_SOC_BIAS_STANDBY: 640 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 641 /* Coming from OFF, switch on the codec */ 642 ret = dac33_hard_power(codec, 1); 643 if (ret != 0) 644 return ret; 645 646 dac33_init_chip(codec); 647 } 648 break; 649 case SND_SOC_BIAS_OFF: 650 /* Do not power off, when the codec is already off */ 651 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 652 return 0; 653 ret = dac33_hard_power(codec, 0); 654 if (ret != 0) 655 return ret; 656 break; 657 } 658 codec->dapm.bias_level = level; 659 660 return 0; 661 } 662 663 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) 664 { 665 struct snd_soc_codec *codec = dac33->codec; 666 unsigned int delay; 667 unsigned long flags; 668 669 switch (dac33->fifo_mode) { 670 case DAC33_FIFO_MODE1: 671 dac33_write16(codec, DAC33_NSAMPLE_MSB, 672 DAC33_THRREG(dac33->nsample)); 673 674 /* Take the timestamps */ 675 spin_lock_irqsave(&dac33->lock, flags); 676 dac33->t_stamp2 = ktime_to_us(ktime_get()); 677 dac33->t_stamp1 = dac33->t_stamp2; 678 spin_unlock_irqrestore(&dac33->lock, flags); 679 680 dac33_write16(codec, DAC33_PREFILL_MSB, 681 DAC33_THRREG(dac33->alarm_threshold)); 682 /* Enable Alarm Threshold IRQ with a delay */ 683 delay = SAMPLES_TO_US(dac33->burst_rate, 684 dac33->alarm_threshold) + 1000; 685 usleep_range(delay, delay + 500); 686 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); 687 break; 688 case DAC33_FIFO_MODE7: 689 /* Take the timestamp */ 690 spin_lock_irqsave(&dac33->lock, flags); 691 dac33->t_stamp1 = ktime_to_us(ktime_get()); 692 /* Move back the timestamp with drain time */ 693 dac33->t_stamp1 -= dac33->mode7_us_to_lthr; 694 spin_unlock_irqrestore(&dac33->lock, flags); 695 696 dac33_write16(codec, DAC33_PREFILL_MSB, 697 DAC33_THRREG(DAC33_MODE7_MARGIN)); 698 699 /* Enable Upper Threshold IRQ */ 700 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); 701 break; 702 default: 703 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 704 dac33->fifo_mode); 705 break; 706 } 707 } 708 709 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) 710 { 711 struct snd_soc_codec *codec = dac33->codec; 712 unsigned long flags; 713 714 switch (dac33->fifo_mode) { 715 case DAC33_FIFO_MODE1: 716 /* Take the timestamp */ 717 spin_lock_irqsave(&dac33->lock, flags); 718 dac33->t_stamp2 = ktime_to_us(ktime_get()); 719 spin_unlock_irqrestore(&dac33->lock, flags); 720 721 dac33_write16(codec, DAC33_NSAMPLE_MSB, 722 DAC33_THRREG(dac33->nsample)); 723 break; 724 case DAC33_FIFO_MODE7: 725 /* At the moment we are not using interrupts in mode7 */ 726 break; 727 default: 728 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 729 dac33->fifo_mode); 730 break; 731 } 732 } 733 734 static void dac33_work(struct work_struct *work) 735 { 736 struct snd_soc_codec *codec; 737 struct tlv320dac33_priv *dac33; 738 u8 reg; 739 740 dac33 = container_of(work, struct tlv320dac33_priv, work); 741 codec = dac33->codec; 742 743 mutex_lock(&dac33->mutex); 744 switch (dac33->state) { 745 case DAC33_PREFILL: 746 dac33->state = DAC33_PLAYBACK; 747 dac33_prefill_handler(dac33); 748 break; 749 case DAC33_PLAYBACK: 750 dac33_playback_handler(dac33); 751 break; 752 case DAC33_IDLE: 753 break; 754 case DAC33_FLUSH: 755 dac33->state = DAC33_IDLE; 756 /* Mask all interrupts from dac33 */ 757 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); 758 759 /* flush fifo */ 760 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 761 reg |= DAC33_FIFOFLUSH; 762 dac33_write(codec, DAC33_FIFO_CTRL_A, reg); 763 break; 764 } 765 mutex_unlock(&dac33->mutex); 766 } 767 768 static irqreturn_t dac33_interrupt_handler(int irq, void *dev) 769 { 770 struct snd_soc_codec *codec = dev; 771 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 772 unsigned long flags; 773 774 spin_lock_irqsave(&dac33->lock, flags); 775 dac33->t_stamp1 = ktime_to_us(ktime_get()); 776 spin_unlock_irqrestore(&dac33->lock, flags); 777 778 /* Do not schedule the workqueue in Mode7 */ 779 if (dac33->fifo_mode != DAC33_FIFO_MODE7) 780 queue_work(dac33->dac33_wq, &dac33->work); 781 782 return IRQ_HANDLED; 783 } 784 785 static void dac33_oscwait(struct snd_soc_codec *codec) 786 { 787 int timeout = 60; 788 u8 reg; 789 790 do { 791 usleep_range(1000, 2000); 792 dac33_read(codec, DAC33_INT_OSC_STATUS, ®); 793 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); 794 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) 795 dev_err(codec->dev, 796 "internal oscillator calibration failed\n"); 797 } 798 799 static int dac33_startup(struct snd_pcm_substream *substream, 800 struct snd_soc_dai *dai) 801 { 802 struct snd_soc_pcm_runtime *rtd = substream->private_data; 803 struct snd_soc_codec *codec = rtd->codec; 804 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 805 806 /* Stream started, save the substream pointer */ 807 dac33->substream = substream; 808 809 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24); 810 811 return 0; 812 } 813 814 static void dac33_shutdown(struct snd_pcm_substream *substream, 815 struct snd_soc_dai *dai) 816 { 817 struct snd_soc_pcm_runtime *rtd = substream->private_data; 818 struct snd_soc_codec *codec = rtd->codec; 819 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 820 821 dac33->substream = NULL; 822 } 823 824 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ 825 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) 826 static int dac33_hw_params(struct snd_pcm_substream *substream, 827 struct snd_pcm_hw_params *params, 828 struct snd_soc_dai *dai) 829 { 830 struct snd_soc_pcm_runtime *rtd = substream->private_data; 831 struct snd_soc_codec *codec = rtd->codec; 832 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 833 834 /* Check parameters for validity */ 835 switch (params_rate(params)) { 836 case 44100: 837 case 48000: 838 break; 839 default: 840 dev_err(codec->dev, "unsupported rate %d\n", 841 params_rate(params)); 842 return -EINVAL; 843 } 844 845 switch (params_format(params)) { 846 case SNDRV_PCM_FORMAT_S16_LE: 847 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; 848 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); 849 break; 850 case SNDRV_PCM_FORMAT_S32_LE: 851 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; 852 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); 853 break; 854 default: 855 dev_err(codec->dev, "unsupported format %d\n", 856 params_format(params)); 857 return -EINVAL; 858 } 859 860 return 0; 861 } 862 863 #define CALC_OSCSET(rate, refclk) ( \ 864 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) 865 #define CALC_RATIOSET(rate, refclk) ( \ 866 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) 867 868 /* 869 * tlv320dac33 is strict on the sequence of the register writes, if the register 870 * writes happens in different order, than dac33 might end up in unknown state. 871 * Use the known, working sequence of register writes to initialize the dac33. 872 */ 873 static int dac33_prepare_chip(struct snd_pcm_substream *substream) 874 { 875 struct snd_soc_pcm_runtime *rtd = substream->private_data; 876 struct snd_soc_codec *codec = rtd->codec; 877 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 878 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 879 u8 aictrl_a, aictrl_b, fifoctrl_a; 880 881 switch (substream->runtime->rate) { 882 case 44100: 883 case 48000: 884 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); 885 ratioset = CALC_RATIOSET(substream->runtime->rate, 886 dac33->refclk); 887 break; 888 default: 889 dev_err(codec->dev, "unsupported rate %d\n", 890 substream->runtime->rate); 891 return -EINVAL; 892 } 893 894 895 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 896 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); 897 /* Read FIFO control A, and clear FIFO flush bit */ 898 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 899 fifoctrl_a &= ~DAC33_FIFOFLUSH; 900 901 fifoctrl_a &= ~DAC33_WIDTH; 902 switch (substream->runtime->format) { 903 case SNDRV_PCM_FORMAT_S16_LE: 904 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); 905 fifoctrl_a |= DAC33_WIDTH; 906 break; 907 case SNDRV_PCM_FORMAT_S32_LE: 908 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); 909 break; 910 default: 911 dev_err(codec->dev, "unsupported format %d\n", 912 substream->runtime->format); 913 return -EINVAL; 914 } 915 916 mutex_lock(&dac33->mutex); 917 918 if (!dac33->chip_power) { 919 /* 920 * Chip is not powered yet. 921 * Do the init in the dac33_set_bias_level later. 922 */ 923 mutex_unlock(&dac33->mutex); 924 return 0; 925 } 926 927 dac33_soft_power(codec, 0); 928 dac33_soft_power(codec, 1); 929 930 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 931 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); 932 933 /* Write registers 0x08 and 0x09 (MSB, LSB) */ 934 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); 935 936 /* OSC calibration time */ 937 dac33_write(codec, DAC33_CALIB_TIME, 96); 938 939 /* adjustment treshold & step */ 940 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | 941 DAC33_ADJSTEP(1)); 942 943 /* div=4 / gain=1 / div */ 944 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); 945 946 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 947 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; 948 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); 949 950 dac33_oscwait(codec); 951 952 if (dac33->fifo_mode) { 953 /* Generic for all FIFO modes */ 954 /* 50-51 : ASRC Control registers */ 955 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); 956 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ 957 958 /* Write registers 0x34 and 0x35 (MSB, LSB) */ 959 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); 960 961 /* Set interrupts to high active */ 962 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); 963 } else { 964 /* FIFO bypass mode */ 965 /* 50-51 : ASRC Control registers */ 966 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); 967 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ 968 } 969 970 /* Interrupt behaviour configuration */ 971 switch (dac33->fifo_mode) { 972 case DAC33_FIFO_MODE1: 973 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, 974 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 975 break; 976 case DAC33_FIFO_MODE7: 977 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, 978 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); 979 break; 980 default: 981 /* in FIFO bypass mode, the interrupts are not used */ 982 break; 983 } 984 985 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 986 987 switch (dac33->fifo_mode) { 988 case DAC33_FIFO_MODE1: 989 /* 990 * For mode1: 991 * Disable the FIFO bypass (Enable the use of FIFO) 992 * Select nSample mode 993 * BCLK is only running when data is needed by DAC33 994 */ 995 fifoctrl_a &= ~DAC33_FBYPAS; 996 fifoctrl_a &= ~DAC33_FAUTO; 997 if (dac33->keep_bclk) 998 aictrl_b |= DAC33_BCLKON; 999 else 1000 aictrl_b &= ~DAC33_BCLKON; 1001 break; 1002 case DAC33_FIFO_MODE7: 1003 /* 1004 * For mode1: 1005 * Disable the FIFO bypass (Enable the use of FIFO) 1006 * Select Threshold mode 1007 * BCLK is only running when data is needed by DAC33 1008 */ 1009 fifoctrl_a &= ~DAC33_FBYPAS; 1010 fifoctrl_a |= DAC33_FAUTO; 1011 if (dac33->keep_bclk) 1012 aictrl_b |= DAC33_BCLKON; 1013 else 1014 aictrl_b &= ~DAC33_BCLKON; 1015 break; 1016 default: 1017 /* 1018 * For FIFO bypass mode: 1019 * Enable the FIFO bypass (Disable the FIFO use) 1020 * Set the BCLK as continuous 1021 */ 1022 fifoctrl_a |= DAC33_FBYPAS; 1023 aictrl_b |= DAC33_BCLKON; 1024 break; 1025 } 1026 1027 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); 1028 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1029 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1030 1031 /* 1032 * BCLK divide ratio 1033 * 0: 1.5 1034 * 1: 1 1035 * 2: 2 1036 * ... 1037 * 254: 254 1038 * 255: 255 1039 */ 1040 if (dac33->fifo_mode) 1041 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 1042 dac33->burst_bclkdiv); 1043 else 1044 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 1045 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); 1046 else 1047 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16); 1048 1049 switch (dac33->fifo_mode) { 1050 case DAC33_FIFO_MODE1: 1051 dac33_write16(codec, DAC33_ATHR_MSB, 1052 DAC33_THRREG(dac33->alarm_threshold)); 1053 break; 1054 case DAC33_FIFO_MODE7: 1055 /* 1056 * Configure the threshold levels, and leave 10 sample space 1057 * at the bottom, and also at the top of the FIFO 1058 */ 1059 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); 1060 dac33_write16(codec, DAC33_LTHR_MSB, 1061 DAC33_THRREG(DAC33_MODE7_MARGIN)); 1062 break; 1063 default: 1064 break; 1065 } 1066 1067 mutex_unlock(&dac33->mutex); 1068 1069 return 0; 1070 } 1071 1072 static void dac33_calculate_times(struct snd_pcm_substream *substream) 1073 { 1074 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1075 struct snd_soc_codec *codec = rtd->codec; 1076 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1077 unsigned int period_size = substream->runtime->period_size; 1078 unsigned int rate = substream->runtime->rate; 1079 unsigned int nsample_limit; 1080 1081 /* In bypass mode we don't need to calculate */ 1082 if (!dac33->fifo_mode) 1083 return; 1084 1085 switch (dac33->fifo_mode) { 1086 case DAC33_FIFO_MODE1: 1087 /* Number of samples under i2c latency */ 1088 dac33->alarm_threshold = US_TO_SAMPLES(rate, 1089 dac33->mode1_latency); 1090 nsample_limit = dac33->fifo_size - dac33->alarm_threshold; 1091 1092 if (period_size <= dac33->alarm_threshold) 1093 /* 1094 * Configure nSamaple to number of periods, 1095 * which covers the latency requironment. 1096 */ 1097 dac33->nsample = period_size * 1098 ((dac33->alarm_threshold / period_size) + 1099 (dac33->alarm_threshold % period_size ? 1100 1 : 0)); 1101 else if (period_size > nsample_limit) 1102 dac33->nsample = nsample_limit; 1103 else 1104 dac33->nsample = period_size; 1105 1106 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, 1107 dac33->nsample); 1108 dac33->t_stamp1 = 0; 1109 dac33->t_stamp2 = 0; 1110 break; 1111 case DAC33_FIFO_MODE7: 1112 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, 1113 dac33->burst_rate) + 9; 1114 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) 1115 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; 1116 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) 1117 dac33->uthr = (DAC33_MODE7_MARGIN + 10); 1118 1119 dac33->mode7_us_to_lthr = 1120 SAMPLES_TO_US(substream->runtime->rate, 1121 dac33->uthr - DAC33_MODE7_MARGIN + 1); 1122 dac33->t_stamp1 = 0; 1123 break; 1124 default: 1125 break; 1126 } 1127 1128 } 1129 1130 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 1131 struct snd_soc_dai *dai) 1132 { 1133 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1134 struct snd_soc_codec *codec = rtd->codec; 1135 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1136 int ret = 0; 1137 1138 switch (cmd) { 1139 case SNDRV_PCM_TRIGGER_START: 1140 case SNDRV_PCM_TRIGGER_RESUME: 1141 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1142 if (dac33->fifo_mode) { 1143 dac33->state = DAC33_PREFILL; 1144 queue_work(dac33->dac33_wq, &dac33->work); 1145 } 1146 break; 1147 case SNDRV_PCM_TRIGGER_STOP: 1148 case SNDRV_PCM_TRIGGER_SUSPEND: 1149 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1150 if (dac33->fifo_mode) { 1151 dac33->state = DAC33_FLUSH; 1152 queue_work(dac33->dac33_wq, &dac33->work); 1153 } 1154 break; 1155 default: 1156 ret = -EINVAL; 1157 } 1158 1159 return ret; 1160 } 1161 1162 static snd_pcm_sframes_t dac33_dai_delay( 1163 struct snd_pcm_substream *substream, 1164 struct snd_soc_dai *dai) 1165 { 1166 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1167 struct snd_soc_codec *codec = rtd->codec; 1168 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1169 unsigned long long t0, t1, t_now; 1170 unsigned int time_delta, uthr; 1171 int samples_out, samples_in, samples; 1172 snd_pcm_sframes_t delay = 0; 1173 unsigned long flags; 1174 1175 switch (dac33->fifo_mode) { 1176 case DAC33_FIFO_BYPASS: 1177 break; 1178 case DAC33_FIFO_MODE1: 1179 spin_lock_irqsave(&dac33->lock, flags); 1180 t0 = dac33->t_stamp1; 1181 t1 = dac33->t_stamp2; 1182 spin_unlock_irqrestore(&dac33->lock, flags); 1183 t_now = ktime_to_us(ktime_get()); 1184 1185 /* We have not started to fill the FIFO yet, delay is 0 */ 1186 if (!t1) 1187 goto out; 1188 1189 if (t0 > t1) { 1190 /* 1191 * Phase 1: 1192 * After Alarm threshold, and before nSample write 1193 */ 1194 time_delta = t_now - t0; 1195 samples_out = time_delta ? US_TO_SAMPLES( 1196 substream->runtime->rate, 1197 time_delta) : 0; 1198 1199 if (likely(dac33->alarm_threshold > samples_out)) 1200 delay = dac33->alarm_threshold - samples_out; 1201 else 1202 delay = 0; 1203 } else if ((t_now - t1) <= dac33->mode1_us_burst) { 1204 /* 1205 * Phase 2: 1206 * After nSample write (during burst operation) 1207 */ 1208 time_delta = t_now - t0; 1209 samples_out = time_delta ? US_TO_SAMPLES( 1210 substream->runtime->rate, 1211 time_delta) : 0; 1212 1213 time_delta = t_now - t1; 1214 samples_in = time_delta ? US_TO_SAMPLES( 1215 dac33->burst_rate, 1216 time_delta) : 0; 1217 1218 samples = dac33->alarm_threshold; 1219 samples += (samples_in - samples_out); 1220 1221 if (likely(samples > 0)) 1222 delay = samples; 1223 else 1224 delay = 0; 1225 } else { 1226 /* 1227 * Phase 3: 1228 * After burst operation, before next alarm threshold 1229 */ 1230 time_delta = t_now - t0; 1231 samples_out = time_delta ? US_TO_SAMPLES( 1232 substream->runtime->rate, 1233 time_delta) : 0; 1234 1235 samples_in = dac33->nsample; 1236 samples = dac33->alarm_threshold; 1237 samples += (samples_in - samples_out); 1238 1239 if (likely(samples > 0)) 1240 delay = samples > dac33->fifo_size ? 1241 dac33->fifo_size : samples; 1242 else 1243 delay = 0; 1244 } 1245 break; 1246 case DAC33_FIFO_MODE7: 1247 spin_lock_irqsave(&dac33->lock, flags); 1248 t0 = dac33->t_stamp1; 1249 uthr = dac33->uthr; 1250 spin_unlock_irqrestore(&dac33->lock, flags); 1251 t_now = ktime_to_us(ktime_get()); 1252 1253 /* We have not started to fill the FIFO yet, delay is 0 */ 1254 if (!t0) 1255 goto out; 1256 1257 if (t_now <= t0) { 1258 /* 1259 * Either the timestamps are messed or equal. Report 1260 * maximum delay 1261 */ 1262 delay = uthr; 1263 goto out; 1264 } 1265 1266 time_delta = t_now - t0; 1267 if (time_delta <= dac33->mode7_us_to_lthr) { 1268 /* 1269 * Phase 1: 1270 * After burst (draining phase) 1271 */ 1272 samples_out = US_TO_SAMPLES( 1273 substream->runtime->rate, 1274 time_delta); 1275 1276 if (likely(uthr > samples_out)) 1277 delay = uthr - samples_out; 1278 else 1279 delay = 0; 1280 } else { 1281 /* 1282 * Phase 2: 1283 * During burst operation 1284 */ 1285 time_delta = time_delta - dac33->mode7_us_to_lthr; 1286 1287 samples_out = US_TO_SAMPLES( 1288 substream->runtime->rate, 1289 time_delta); 1290 samples_in = US_TO_SAMPLES( 1291 dac33->burst_rate, 1292 time_delta); 1293 delay = DAC33_MODE7_MARGIN + samples_in - samples_out; 1294 1295 if (unlikely(delay > uthr)) 1296 delay = uthr; 1297 } 1298 break; 1299 default: 1300 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 1301 dac33->fifo_mode); 1302 break; 1303 } 1304 out: 1305 return delay; 1306 } 1307 1308 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1309 int clk_id, unsigned int freq, int dir) 1310 { 1311 struct snd_soc_codec *codec = codec_dai->codec; 1312 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1313 u8 ioc_reg, asrcb_reg; 1314 1315 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 1316 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); 1317 switch (clk_id) { 1318 case TLV320DAC33_MCLK: 1319 ioc_reg |= DAC33_REFSEL; 1320 asrcb_reg |= DAC33_SRCREFSEL; 1321 break; 1322 case TLV320DAC33_SLEEPCLK: 1323 ioc_reg &= ~DAC33_REFSEL; 1324 asrcb_reg &= ~DAC33_SRCREFSEL; 1325 break; 1326 default: 1327 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); 1328 break; 1329 } 1330 dac33->refclk = freq; 1331 1332 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); 1333 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); 1334 1335 return 0; 1336 } 1337 1338 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, 1339 unsigned int fmt) 1340 { 1341 struct snd_soc_codec *codec = codec_dai->codec; 1342 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1343 u8 aictrl_a, aictrl_b; 1344 1345 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 1346 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 1347 /* set master/slave audio interface */ 1348 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1349 case SND_SOC_DAIFMT_CBM_CFM: 1350 /* Codec Master */ 1351 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); 1352 break; 1353 case SND_SOC_DAIFMT_CBS_CFS: 1354 /* Codec Slave */ 1355 if (dac33->fifo_mode) { 1356 dev_err(codec->dev, "FIFO mode requires master mode\n"); 1357 return -EINVAL; 1358 } else 1359 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); 1360 break; 1361 default: 1362 return -EINVAL; 1363 } 1364 1365 aictrl_a &= ~DAC33_AFMT_MASK; 1366 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1367 case SND_SOC_DAIFMT_I2S: 1368 aictrl_a |= DAC33_AFMT_I2S; 1369 break; 1370 case SND_SOC_DAIFMT_DSP_A: 1371 aictrl_a |= DAC33_AFMT_DSP; 1372 aictrl_b &= ~DAC33_DATA_DELAY_MASK; 1373 aictrl_b |= DAC33_DATA_DELAY(0); 1374 break; 1375 case SND_SOC_DAIFMT_RIGHT_J: 1376 aictrl_a |= DAC33_AFMT_RIGHT_J; 1377 break; 1378 case SND_SOC_DAIFMT_LEFT_J: 1379 aictrl_a |= DAC33_AFMT_LEFT_J; 1380 break; 1381 default: 1382 dev_err(codec->dev, "Unsupported format (%u)\n", 1383 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1384 return -EINVAL; 1385 } 1386 1387 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1388 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1389 1390 return 0; 1391 } 1392 1393 static int dac33_soc_probe(struct snd_soc_codec *codec) 1394 { 1395 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1396 int ret = 0; 1397 1398 codec->control_data = dac33->control_data; 1399 codec->hw_write = (hw_write_t) i2c_master_send; 1400 codec->dapm.idle_bias_off = 1; 1401 dac33->codec = codec; 1402 1403 /* Read the tlv320dac33 ID registers */ 1404 ret = dac33_hard_power(codec, 1); 1405 if (ret != 0) { 1406 dev_err(codec->dev, "Failed to power up codec: %d\n", ret); 1407 goto err_power; 1408 } 1409 ret = dac33_read_id(codec); 1410 dac33_hard_power(codec, 0); 1411 1412 if (ret < 0) { 1413 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret); 1414 ret = -ENODEV; 1415 goto err_power; 1416 } 1417 1418 /* Check if the IRQ number is valid and request it */ 1419 if (dac33->irq >= 0) { 1420 ret = request_irq(dac33->irq, dac33_interrupt_handler, 1421 IRQF_TRIGGER_RISING, 1422 codec->name, codec); 1423 if (ret < 0) { 1424 dev_err(codec->dev, "Could not request IRQ%d (%d)\n", 1425 dac33->irq, ret); 1426 dac33->irq = -1; 1427 } 1428 if (dac33->irq != -1) { 1429 /* Setup work queue */ 1430 dac33->dac33_wq = 1431 create_singlethread_workqueue("tlv320dac33"); 1432 if (dac33->dac33_wq == NULL) { 1433 free_irq(dac33->irq, codec); 1434 return -ENOMEM; 1435 } 1436 1437 INIT_WORK(&dac33->work, dac33_work); 1438 } 1439 } 1440 1441 /* Only add the FIFO controls, if we have valid IRQ number */ 1442 if (dac33->irq >= 0) 1443 snd_soc_add_controls(codec, dac33_mode_snd_controls, 1444 ARRAY_SIZE(dac33_mode_snd_controls)); 1445 1446 err_power: 1447 return ret; 1448 } 1449 1450 static int dac33_soc_remove(struct snd_soc_codec *codec) 1451 { 1452 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1453 1454 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); 1455 1456 if (dac33->irq >= 0) { 1457 free_irq(dac33->irq, dac33->codec); 1458 destroy_workqueue(dac33->dac33_wq); 1459 } 1460 return 0; 1461 } 1462 1463 static int dac33_soc_suspend(struct snd_soc_codec *codec) 1464 { 1465 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); 1466 1467 return 0; 1468 } 1469 1470 static int dac33_soc_resume(struct snd_soc_codec *codec) 1471 { 1472 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1473 1474 return 0; 1475 } 1476 1477 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { 1478 .read = dac33_read_reg_cache, 1479 .write = dac33_write_locked, 1480 .set_bias_level = dac33_set_bias_level, 1481 .reg_cache_size = ARRAY_SIZE(dac33_reg), 1482 .reg_word_size = sizeof(u8), 1483 .reg_cache_default = dac33_reg, 1484 .probe = dac33_soc_probe, 1485 .remove = dac33_soc_remove, 1486 .suspend = dac33_soc_suspend, 1487 .resume = dac33_soc_resume, 1488 1489 .controls = dac33_snd_controls, 1490 .num_controls = ARRAY_SIZE(dac33_snd_controls), 1491 .dapm_widgets = dac33_dapm_widgets, 1492 .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets), 1493 .dapm_routes = audio_map, 1494 .num_dapm_routes = ARRAY_SIZE(audio_map), 1495 }; 1496 1497 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ 1498 SNDRV_PCM_RATE_48000) 1499 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 1500 1501 static const struct snd_soc_dai_ops dac33_dai_ops = { 1502 .startup = dac33_startup, 1503 .shutdown = dac33_shutdown, 1504 .hw_params = dac33_hw_params, 1505 .trigger = dac33_pcm_trigger, 1506 .delay = dac33_dai_delay, 1507 .set_sysclk = dac33_set_dai_sysclk, 1508 .set_fmt = dac33_set_dai_fmt, 1509 }; 1510 1511 static struct snd_soc_dai_driver dac33_dai = { 1512 .name = "tlv320dac33-hifi", 1513 .playback = { 1514 .stream_name = "Playback", 1515 .channels_min = 2, 1516 .channels_max = 2, 1517 .rates = DAC33_RATES, 1518 .formats = DAC33_FORMATS,}, 1519 .ops = &dac33_dai_ops, 1520 }; 1521 1522 static int __devinit dac33_i2c_probe(struct i2c_client *client, 1523 const struct i2c_device_id *id) 1524 { 1525 struct tlv320dac33_platform_data *pdata; 1526 struct tlv320dac33_priv *dac33; 1527 int ret, i; 1528 1529 if (client->dev.platform_data == NULL) { 1530 dev_err(&client->dev, "Platform data not set\n"); 1531 return -ENODEV; 1532 } 1533 pdata = client->dev.platform_data; 1534 1535 dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv), 1536 GFP_KERNEL); 1537 if (dac33 == NULL) 1538 return -ENOMEM; 1539 1540 dac33->control_data = client; 1541 mutex_init(&dac33->mutex); 1542 spin_lock_init(&dac33->lock); 1543 1544 i2c_set_clientdata(client, dac33); 1545 1546 dac33->power_gpio = pdata->power_gpio; 1547 dac33->burst_bclkdiv = pdata->burst_bclkdiv; 1548 dac33->keep_bclk = pdata->keep_bclk; 1549 dac33->mode1_latency = pdata->mode1_latency; 1550 if (!dac33->mode1_latency) 1551 dac33->mode1_latency = 10000; /* 10ms */ 1552 dac33->irq = client->irq; 1553 /* Disable FIFO use by default */ 1554 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1555 1556 /* Check if the reset GPIO number is valid and request it */ 1557 if (dac33->power_gpio >= 0) { 1558 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); 1559 if (ret < 0) { 1560 dev_err(&client->dev, 1561 "Failed to request reset GPIO (%d)\n", 1562 dac33->power_gpio); 1563 goto err_gpio; 1564 } 1565 gpio_direction_output(dac33->power_gpio, 0); 1566 } 1567 1568 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) 1569 dac33->supplies[i].supply = dac33_supply_names[i]; 1570 1571 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), 1572 dac33->supplies); 1573 1574 if (ret != 0) { 1575 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 1576 goto err_get; 1577 } 1578 1579 ret = snd_soc_register_codec(&client->dev, 1580 &soc_codec_dev_tlv320dac33, &dac33_dai, 1); 1581 if (ret < 0) 1582 goto err_register; 1583 1584 return ret; 1585 err_register: 1586 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); 1587 err_get: 1588 if (dac33->power_gpio >= 0) 1589 gpio_free(dac33->power_gpio); 1590 err_gpio: 1591 return ret; 1592 } 1593 1594 static int __devexit dac33_i2c_remove(struct i2c_client *client) 1595 { 1596 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); 1597 1598 if (unlikely(dac33->chip_power)) 1599 dac33_hard_power(dac33->codec, 0); 1600 1601 if (dac33->power_gpio >= 0) 1602 gpio_free(dac33->power_gpio); 1603 1604 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); 1605 1606 snd_soc_unregister_codec(&client->dev); 1607 return 0; 1608 } 1609 1610 static const struct i2c_device_id tlv320dac33_i2c_id[] = { 1611 { 1612 .name = "tlv320dac33", 1613 .driver_data = 0, 1614 }, 1615 { }, 1616 }; 1617 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); 1618 1619 static struct i2c_driver tlv320dac33_i2c_driver = { 1620 .driver = { 1621 .name = "tlv320dac33-codec", 1622 .owner = THIS_MODULE, 1623 }, 1624 .probe = dac33_i2c_probe, 1625 .remove = __devexit_p(dac33_i2c_remove), 1626 .id_table = tlv320dac33_i2c_id, 1627 }; 1628 1629 static int __init dac33_module_init(void) 1630 { 1631 int r; 1632 r = i2c_add_driver(&tlv320dac33_i2c_driver); 1633 if (r < 0) { 1634 printk(KERN_ERR "DAC33: driver registration failed\n"); 1635 return r; 1636 } 1637 return 0; 1638 } 1639 module_init(dac33_module_init); 1640 1641 static void __exit dac33_module_exit(void) 1642 { 1643 i2c_del_driver(&tlv320dac33_i2c_driver); 1644 } 1645 module_exit(dac33_module_exit); 1646 1647 1648 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); 1649 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1650 MODULE_LICENSE("GPL"); 1651