1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/slab.h> 44 #include <sound/core.h> 45 #include <sound/pcm.h> 46 #include <sound/pcm_params.h> 47 #include <sound/soc.h> 48 #include <sound/initval.h> 49 #include <sound/tlv.h> 50 #include <sound/tlv320aic3x.h> 51 52 #include "tlv320aic3x.h" 53 54 #define AIC3X_NUM_SUPPLIES 4 55 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 56 "IOVDD", /* I/O Voltage */ 57 "DVDD", /* Digital Core Voltage */ 58 "AVDD", /* Analog DAC Voltage */ 59 "DRVDD", /* ADC Analog and Output Driver Voltage */ 60 }; 61 62 static LIST_HEAD(reset_list); 63 64 struct aic3x_priv; 65 66 struct aic3x_disable_nb { 67 struct notifier_block nb; 68 struct aic3x_priv *aic3x; 69 }; 70 71 /* codec private data */ 72 struct aic3x_priv { 73 struct snd_soc_codec *codec; 74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 76 enum snd_soc_control_type control_type; 77 struct aic3x_setup_data *setup; 78 unsigned int sysclk; 79 struct list_head list; 80 int master; 81 int gpio_reset; 82 int power; 83 #define AIC3X_MODEL_3X 0 84 #define AIC3X_MODEL_33 1 85 #define AIC3X_MODEL_3007 2 86 u16 model; 87 }; 88 89 /* 90 * AIC3X register cache 91 * We can't read the AIC3X register space when we are 92 * using 2 wire for device control, so we cache them instead. 93 * There is no point in caching the reset register 94 */ 95 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 96 0x00, 0x00, 0x00, 0x10, /* 0 */ 97 0x04, 0x00, 0x00, 0x00, /* 4 */ 98 0x00, 0x00, 0x00, 0x01, /* 8 */ 99 0x00, 0x00, 0x00, 0x80, /* 12 */ 100 0x80, 0xff, 0xff, 0x78, /* 16 */ 101 0x78, 0x78, 0x78, 0x78, /* 20 */ 102 0x78, 0x00, 0x00, 0xfe, /* 24 */ 103 0x00, 0x00, 0xfe, 0x00, /* 28 */ 104 0x18, 0x18, 0x00, 0x00, /* 32 */ 105 0x00, 0x00, 0x00, 0x00, /* 36 */ 106 0x00, 0x00, 0x00, 0x80, /* 40 */ 107 0x80, 0x00, 0x00, 0x00, /* 44 */ 108 0x00, 0x00, 0x00, 0x04, /* 48 */ 109 0x00, 0x00, 0x00, 0x00, /* 52 */ 110 0x00, 0x00, 0x04, 0x00, /* 56 */ 111 0x00, 0x00, 0x00, 0x00, /* 60 */ 112 0x00, 0x04, 0x00, 0x00, /* 64 */ 113 0x00, 0x00, 0x00, 0x00, /* 68 */ 114 0x04, 0x00, 0x00, 0x00, /* 72 */ 115 0x00, 0x00, 0x00, 0x00, /* 76 */ 116 0x00, 0x00, 0x00, 0x00, /* 80 */ 117 0x00, 0x00, 0x00, 0x00, /* 84 */ 118 0x00, 0x00, 0x00, 0x00, /* 88 */ 119 0x00, 0x00, 0x00, 0x00, /* 92 */ 120 0x00, 0x00, 0x00, 0x00, /* 96 */ 121 0x00, 0x00, 0x02, /* 100 */ 122 }; 123 124 /* 125 * read from the aic3x register space. Only use for this function is if 126 * wanting to read volatile bits from those registers that has both read-only 127 * and read/write bits. All other cases should use snd_soc_read. 128 */ 129 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, 130 u8 *value) 131 { 132 u8 *cache = codec->reg_cache; 133 134 if (codec->cache_only) 135 return -EINVAL; 136 if (reg >= AIC3X_CACHEREGNUM) 137 return -1; 138 139 codec->cache_bypass = 1; 140 *value = snd_soc_read(codec, reg); 141 codec->cache_bypass = 0; 142 143 cache[reg] = *value; 144 145 return 0; 146 } 147 148 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 149 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 150 .info = snd_soc_info_volsw, \ 151 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ 152 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } 153 154 /* 155 * All input lines are connected when !0xf and disconnected with 0xf bit field, 156 * so we have to use specific dapm_put call for input mixer 157 */ 158 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 159 struct snd_ctl_elem_value *ucontrol) 160 { 161 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 162 struct snd_soc_dapm_widget *widget = wlist->widgets[0]; 163 struct soc_mixer_control *mc = 164 (struct soc_mixer_control *)kcontrol->private_value; 165 unsigned int reg = mc->reg; 166 unsigned int shift = mc->shift; 167 int max = mc->max; 168 unsigned int mask = (1 << fls(max)) - 1; 169 unsigned int invert = mc->invert; 170 unsigned short val, val_mask; 171 int ret; 172 struct snd_soc_dapm_path *path; 173 int found = 0; 174 175 val = (ucontrol->value.integer.value[0] & mask); 176 177 mask = 0xf; 178 if (val) 179 val = mask; 180 181 if (invert) 182 val = mask - val; 183 val_mask = mask << shift; 184 val = val << shift; 185 186 mutex_lock(&widget->codec->mutex); 187 188 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 189 /* find dapm widget path assoc with kcontrol */ 190 list_for_each_entry(path, &widget->dapm->card->paths, list) { 191 if (path->kcontrol != kcontrol) 192 continue; 193 194 /* found, now check type */ 195 found = 1; 196 if (val) 197 /* new connection */ 198 path->connect = invert ? 0 : 1; 199 else 200 /* old connection must be powered down */ 201 path->connect = invert ? 1 : 0; 202 203 dapm_mark_dirty(path->source, "tlv320aic3x source"); 204 dapm_mark_dirty(path->sink, "tlv320aic3x sink"); 205 206 break; 207 } 208 209 if (found) 210 snd_soc_dapm_sync(widget->dapm); 211 } 212 213 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); 214 215 mutex_unlock(&widget->codec->mutex); 216 return ret; 217 } 218 219 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 220 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 221 static const char *aic3x_left_hpcom_mux[] = 222 { "differential of HPLOUT", "constant VCM", "single-ended" }; 223 static const char *aic3x_right_hpcom_mux[] = 224 { "differential of HPROUT", "constant VCM", "single-ended", 225 "differential of HPLCOM", "external feedback" }; 226 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 227 static const char *aic3x_adc_hpf[] = 228 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 229 230 #define LDAC_ENUM 0 231 #define RDAC_ENUM 1 232 #define LHPCOM_ENUM 2 233 #define RHPCOM_ENUM 3 234 #define LINE1L_2_L_ENUM 4 235 #define LINE1L_2_R_ENUM 5 236 #define LINE1R_2_L_ENUM 6 237 #define LINE1R_2_R_ENUM 7 238 #define LINE2L_ENUM 8 239 #define LINE2R_ENUM 9 240 #define ADC_HPF_ENUM 10 241 242 static const struct soc_enum aic3x_enum[] = { 243 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 245 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 246 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 247 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 248 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 249 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 250 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 251 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 252 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 253 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 254 }; 255 256 /* 257 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 258 */ 259 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 260 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 261 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 262 /* 263 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 264 * Step size is approximately 0.5 dB over most of the scale but increasing 265 * near the very low levels. 266 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 267 * but having increasing dB difference below that (and where it doesn't count 268 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 269 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 270 */ 271 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 272 273 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 274 /* Output */ 275 SOC_DOUBLE_R_TLV("PCM Playback Volume", 276 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 277 278 /* 279 * Output controls that map to output mixer switches. Note these are 280 * only for swapped L-to-R and R-to-L routes. See below stereo controls 281 * for direct L-to-L and R-to-R routes. 282 */ 283 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 284 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 285 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 286 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 287 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 288 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 289 290 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 291 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 292 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 293 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 294 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 295 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 296 297 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 298 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 299 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 300 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 301 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 302 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 303 304 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 305 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 306 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 307 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 308 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 309 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 310 311 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 312 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 313 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 314 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 315 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 316 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 317 318 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 319 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 320 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 321 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 322 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 323 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 324 325 /* Stereo output controls for direct L-to-L and R-to-R routes */ 326 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 327 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 328 0, 118, 1, output_stage_tlv), 329 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 330 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 331 0, 118, 1, output_stage_tlv), 332 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 333 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 334 0, 118, 1, output_stage_tlv), 335 336 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 337 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 338 0, 118, 1, output_stage_tlv), 339 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 340 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 341 0, 118, 1, output_stage_tlv), 342 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 343 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 344 0, 118, 1, output_stage_tlv), 345 346 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 347 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 348 0, 118, 1, output_stage_tlv), 349 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 350 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 351 0, 118, 1, output_stage_tlv), 352 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 353 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 354 0, 118, 1, output_stage_tlv), 355 356 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 357 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 358 0, 118, 1, output_stage_tlv), 359 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 360 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 361 0, 118, 1, output_stage_tlv), 362 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 363 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 364 0, 118, 1, output_stage_tlv), 365 366 /* Output pin mute controls */ 367 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 368 0x01, 0), 369 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 370 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 371 0x01, 0), 372 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 373 0x01, 0), 374 375 /* 376 * Note: enable Automatic input Gain Controller with care. It can 377 * adjust PGA to max value when ADC is on and will never go back. 378 */ 379 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 380 381 /* Input */ 382 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 383 0, 119, 0, adc_tlv), 384 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 385 386 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 387 }; 388 389 /* 390 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 391 */ 392 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 393 394 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 395 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 396 397 /* Left DAC Mux */ 398 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 399 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 400 401 /* Right DAC Mux */ 402 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 403 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 404 405 /* Left HPCOM Mux */ 406 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 407 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 408 409 /* Right HPCOM Mux */ 410 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 411 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 412 413 /* Left Line Mixer */ 414 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 415 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 416 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 417 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 418 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 419 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 420 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 421 }; 422 423 /* Right Line Mixer */ 424 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 425 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 426 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 427 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 428 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 429 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 430 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 431 }; 432 433 /* Mono Mixer */ 434 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 435 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 436 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 437 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 438 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 439 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 440 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 441 }; 442 443 /* Left HP Mixer */ 444 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 445 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 446 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 447 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 448 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 449 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 450 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 451 }; 452 453 /* Right HP Mixer */ 454 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 455 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 456 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 457 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 458 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 459 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 460 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 461 }; 462 463 /* Left HPCOM Mixer */ 464 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 465 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 466 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 467 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 468 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 469 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 470 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 471 }; 472 473 /* Right HPCOM Mixer */ 474 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 475 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 476 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 477 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 478 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 479 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 480 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 481 }; 482 483 /* Left PGA Mixer */ 484 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 485 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 486 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 487 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 488 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 489 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 490 }; 491 492 /* Right PGA Mixer */ 493 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 494 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 495 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 496 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 497 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 498 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 499 }; 500 501 /* Left Line1 Mux */ 502 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 503 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]); 504 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 505 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]); 506 507 /* Right Line1 Mux */ 508 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 509 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]); 510 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 511 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]); 512 513 /* Left Line2 Mux */ 514 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 515 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 516 517 /* Right Line2 Mux */ 518 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 519 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 520 521 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 522 /* Left DAC to Left Outputs */ 523 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 524 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 525 &aic3x_left_dac_mux_controls), 526 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 527 &aic3x_left_hpcom_mux_controls), 528 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 529 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 530 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 531 532 /* Right DAC to Right Outputs */ 533 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 534 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 535 &aic3x_right_dac_mux_controls), 536 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 537 &aic3x_right_hpcom_mux_controls), 538 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 539 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 540 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 541 542 /* Mono Output */ 543 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 544 545 /* Inputs to Left ADC */ 546 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 547 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 548 &aic3x_left_pga_mixer_controls[0], 549 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 550 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 551 &aic3x_left_line1l_mux_controls), 552 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 553 &aic3x_left_line1r_mux_controls), 554 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 555 &aic3x_left_line2_mux_controls), 556 557 /* Inputs to Right ADC */ 558 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 559 LINE1R_2_RADC_CTRL, 2, 0), 560 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 561 &aic3x_right_pga_mixer_controls[0], 562 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 563 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 564 &aic3x_right_line1l_mux_controls), 565 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 566 &aic3x_right_line1r_mux_controls), 567 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 568 &aic3x_right_line2_mux_controls), 569 570 /* 571 * Not a real mic bias widget but similar function. This is for dynamic 572 * control of GPIO1 digital mic modulator clock output function when 573 * using digital mic. 574 */ 575 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 576 AIC3X_GPIO1_REG, 4, 0xf, 577 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 578 AIC3X_GPIO1_FUNC_DISABLED), 579 580 /* 581 * Also similar function like mic bias. Selects digital mic with 582 * configurable oversampling rate instead of ADC converter. 583 */ 584 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 585 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 586 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 587 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 588 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 589 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 590 591 /* Mic Bias */ 592 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", 593 MICBIAS_CTRL, 6, 3, 1, 0), 594 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", 595 MICBIAS_CTRL, 6, 3, 2, 0), 596 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", 597 MICBIAS_CTRL, 6, 3, 3, 0), 598 599 /* Output mixers */ 600 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 601 &aic3x_left_line_mixer_controls[0], 602 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 603 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 604 &aic3x_right_line_mixer_controls[0], 605 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 606 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 607 &aic3x_mono_mixer_controls[0], 608 ARRAY_SIZE(aic3x_mono_mixer_controls)), 609 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 610 &aic3x_left_hp_mixer_controls[0], 611 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 612 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 613 &aic3x_right_hp_mixer_controls[0], 614 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 615 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 616 &aic3x_left_hpcom_mixer_controls[0], 617 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 618 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 619 &aic3x_right_hpcom_mixer_controls[0], 620 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 621 622 SND_SOC_DAPM_OUTPUT("LLOUT"), 623 SND_SOC_DAPM_OUTPUT("RLOUT"), 624 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 625 SND_SOC_DAPM_OUTPUT("HPLOUT"), 626 SND_SOC_DAPM_OUTPUT("HPROUT"), 627 SND_SOC_DAPM_OUTPUT("HPLCOM"), 628 SND_SOC_DAPM_OUTPUT("HPRCOM"), 629 630 SND_SOC_DAPM_INPUT("MIC3L"), 631 SND_SOC_DAPM_INPUT("MIC3R"), 632 SND_SOC_DAPM_INPUT("LINE1L"), 633 SND_SOC_DAPM_INPUT("LINE1R"), 634 SND_SOC_DAPM_INPUT("LINE2L"), 635 SND_SOC_DAPM_INPUT("LINE2R"), 636 637 /* 638 * Virtual output pin to detection block inside codec. This can be 639 * used to keep codec bias on if gpio or detection features are needed. 640 * Force pin on or construct a path with an input jack and mic bias 641 * widgets. 642 */ 643 SND_SOC_DAPM_OUTPUT("Detection"), 644 }; 645 646 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 647 /* Class-D outputs */ 648 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 649 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 650 651 SND_SOC_DAPM_OUTPUT("SPOP"), 652 SND_SOC_DAPM_OUTPUT("SPOM"), 653 }; 654 655 static const struct snd_soc_dapm_route intercon[] = { 656 /* Left Input */ 657 {"Left Line1L Mux", "single-ended", "LINE1L"}, 658 {"Left Line1L Mux", "differential", "LINE1L"}, 659 660 {"Left Line2L Mux", "single-ended", "LINE2L"}, 661 {"Left Line2L Mux", "differential", "LINE2L"}, 662 663 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 664 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 665 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 666 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 667 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 668 669 {"Left ADC", NULL, "Left PGA Mixer"}, 670 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 671 672 /* Right Input */ 673 {"Right Line1R Mux", "single-ended", "LINE1R"}, 674 {"Right Line1R Mux", "differential", "LINE1R"}, 675 676 {"Right Line2R Mux", "single-ended", "LINE2R"}, 677 {"Right Line2R Mux", "differential", "LINE2R"}, 678 679 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 680 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 681 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 682 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 683 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 684 685 {"Right ADC", NULL, "Right PGA Mixer"}, 686 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 687 688 /* 689 * Logical path between digital mic enable and GPIO1 modulator clock 690 * output function 691 */ 692 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 693 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 694 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 695 696 /* Left DAC Output */ 697 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 698 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 699 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 700 701 /* Right DAC Output */ 702 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 703 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 704 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 705 706 /* Left Line Output */ 707 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 708 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 709 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 710 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 711 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 712 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 713 714 {"Left Line Out", NULL, "Left Line Mixer"}, 715 {"Left Line Out", NULL, "Left DAC Mux"}, 716 {"LLOUT", NULL, "Left Line Out"}, 717 718 /* Right Line Output */ 719 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 720 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 721 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 722 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 723 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 724 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 725 726 {"Right Line Out", NULL, "Right Line Mixer"}, 727 {"Right Line Out", NULL, "Right DAC Mux"}, 728 {"RLOUT", NULL, "Right Line Out"}, 729 730 /* Mono Output */ 731 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 732 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 733 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 734 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 735 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 736 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 737 738 {"Mono Out", NULL, "Mono Mixer"}, 739 {"MONO_LOUT", NULL, "Mono Out"}, 740 741 /* Left HP Output */ 742 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 743 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 744 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 745 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 746 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 747 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 748 749 {"Left HP Out", NULL, "Left HP Mixer"}, 750 {"Left HP Out", NULL, "Left DAC Mux"}, 751 {"HPLOUT", NULL, "Left HP Out"}, 752 753 /* Right HP Output */ 754 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 755 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 756 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 757 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 758 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 759 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 760 761 {"Right HP Out", NULL, "Right HP Mixer"}, 762 {"Right HP Out", NULL, "Right DAC Mux"}, 763 {"HPROUT", NULL, "Right HP Out"}, 764 765 /* Left HPCOM Output */ 766 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 767 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 768 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 769 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 770 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 771 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 772 773 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 774 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 775 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 776 {"Left HP Com", NULL, "Left HPCOM Mux"}, 777 {"HPLCOM", NULL, "Left HP Com"}, 778 779 /* Right HPCOM Output */ 780 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 781 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 782 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 783 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 784 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 785 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 786 787 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 788 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 789 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 790 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 791 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 792 {"Right HP Com", NULL, "Right HPCOM Mux"}, 793 {"HPRCOM", NULL, "Right HP Com"}, 794 }; 795 796 static const struct snd_soc_dapm_route intercon_3007[] = { 797 /* Class-D outputs */ 798 {"Left Class-D Out", NULL, "Left Line Out"}, 799 {"Right Class-D Out", NULL, "Left Line Out"}, 800 {"SPOP", NULL, "Left Class-D Out"}, 801 {"SPOM", NULL, "Right Class-D Out"}, 802 }; 803 804 static int aic3x_add_widgets(struct snd_soc_codec *codec) 805 { 806 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 807 struct snd_soc_dapm_context *dapm = &codec->dapm; 808 809 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, 810 ARRAY_SIZE(aic3x_dapm_widgets)); 811 812 /* set up audio path interconnects */ 813 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 814 815 if (aic3x->model == AIC3X_MODEL_3007) { 816 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 817 ARRAY_SIZE(aic3007_dapm_widgets)); 818 snd_soc_dapm_add_routes(dapm, intercon_3007, 819 ARRAY_SIZE(intercon_3007)); 820 } 821 822 return 0; 823 } 824 825 static int aic3x_hw_params(struct snd_pcm_substream *substream, 826 struct snd_pcm_hw_params *params, 827 struct snd_soc_dai *dai) 828 { 829 struct snd_soc_pcm_runtime *rtd = substream->private_data; 830 struct snd_soc_codec *codec =rtd->codec; 831 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 832 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 833 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 834 u16 d, pll_d = 1; 835 int clk; 836 837 /* select data word length */ 838 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 839 switch (params_format(params)) { 840 case SNDRV_PCM_FORMAT_S16_LE: 841 break; 842 case SNDRV_PCM_FORMAT_S20_3LE: 843 data |= (0x01 << 4); 844 break; 845 case SNDRV_PCM_FORMAT_S24_LE: 846 data |= (0x02 << 4); 847 break; 848 case SNDRV_PCM_FORMAT_S32_LE: 849 data |= (0x03 << 4); 850 break; 851 } 852 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 853 854 /* Fsref can be 44100 or 48000 */ 855 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 856 857 /* Try to find a value for Q which allows us to bypass the PLL and 858 * generate CODEC_CLK directly. */ 859 for (pll_q = 2; pll_q < 18; pll_q++) 860 if (aic3x->sysclk / (128 * pll_q) == fsref) { 861 bypass_pll = 1; 862 break; 863 } 864 865 if (bypass_pll) { 866 pll_q &= 0xf; 867 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 868 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 869 /* disable PLL if it is bypassed */ 870 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 871 872 } else { 873 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 874 /* enable PLL when it is used */ 875 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 876 PLL_ENABLE, PLL_ENABLE); 877 } 878 879 /* Route Left DAC to left channel input and 880 * right DAC to right channel input */ 881 data = (LDAC2LCH | RDAC2RCH); 882 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 883 if (params_rate(params) >= 64000) 884 data |= DUAL_RATE_MODE; 885 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 886 887 /* codec sample rate select */ 888 data = (fsref * 20) / params_rate(params); 889 if (params_rate(params) < 64000) 890 data /= 2; 891 data /= 5; 892 data -= 2; 893 data |= (data << 4); 894 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 895 896 if (bypass_pll) 897 return 0; 898 899 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 900 * one wins the game. Try with d==0 first, next with d!=0. 901 * Constraints for j are according to the datasheet. 902 * The sysclk is divided by 1000 to prevent integer overflows. 903 */ 904 905 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 906 907 for (r = 1; r <= 16; r++) 908 for (p = 1; p <= 8; p++) { 909 for (j = 4; j <= 55; j++) { 910 /* This is actually 1000*((j+(d/10000))*r)/p 911 * The term had to be converted to get 912 * rid of the division by 10000; d = 0 here 913 */ 914 int tmp_clk = (1000 * j * r) / p; 915 916 /* Check whether this values get closer than 917 * the best ones we had before 918 */ 919 if (abs(codec_clk - tmp_clk) < 920 abs(codec_clk - last_clk)) { 921 pll_j = j; pll_d = 0; 922 pll_r = r; pll_p = p; 923 last_clk = tmp_clk; 924 } 925 926 /* Early exit for exact matches */ 927 if (tmp_clk == codec_clk) 928 goto found; 929 } 930 } 931 932 /* try with d != 0 */ 933 for (p = 1; p <= 8; p++) { 934 j = codec_clk * p / 1000; 935 936 if (j < 4 || j > 11) 937 continue; 938 939 /* do not use codec_clk here since we'd loose precision */ 940 d = ((2048 * p * fsref) - j * aic3x->sysclk) 941 * 100 / (aic3x->sysclk/100); 942 943 clk = (10000 * j + d) / (10 * p); 944 945 /* check whether this values get closer than the best 946 * ones we had before */ 947 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 948 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 949 last_clk = clk; 950 } 951 952 /* Early exit for exact matches */ 953 if (clk == codec_clk) 954 goto found; 955 } 956 957 if (last_clk == 0) { 958 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 959 return -EINVAL; 960 } 961 962 found: 963 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 964 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, 965 data | (pll_p << PLLP_SHIFT)); 966 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 967 pll_r << PLLR_SHIFT); 968 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 969 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 970 (pll_d >> 6) << PLLD_MSB_SHIFT); 971 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 972 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 973 974 return 0; 975 } 976 977 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 978 { 979 struct snd_soc_codec *codec = dai->codec; 980 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 981 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 982 983 if (mute) { 984 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 985 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 986 } else { 987 snd_soc_write(codec, LDAC_VOL, ldac_reg); 988 snd_soc_write(codec, RDAC_VOL, rdac_reg); 989 } 990 991 return 0; 992 } 993 994 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 995 int clk_id, unsigned int freq, int dir) 996 { 997 struct snd_soc_codec *codec = codec_dai->codec; 998 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 999 1000 aic3x->sysclk = freq; 1001 return 0; 1002 } 1003 1004 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1005 unsigned int fmt) 1006 { 1007 struct snd_soc_codec *codec = codec_dai->codec; 1008 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1009 u8 iface_areg, iface_breg; 1010 int delay = 0; 1011 1012 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1013 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1014 1015 /* set master/slave audio interface */ 1016 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1017 case SND_SOC_DAIFMT_CBM_CFM: 1018 aic3x->master = 1; 1019 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1020 break; 1021 case SND_SOC_DAIFMT_CBS_CFS: 1022 aic3x->master = 0; 1023 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1024 break; 1025 default: 1026 return -EINVAL; 1027 } 1028 1029 /* 1030 * match both interface format and signal polarities since they 1031 * are fixed 1032 */ 1033 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1034 SND_SOC_DAIFMT_INV_MASK)) { 1035 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1036 break; 1037 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1038 delay = 1; 1039 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1040 iface_breg |= (0x01 << 6); 1041 break; 1042 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1043 iface_breg |= (0x02 << 6); 1044 break; 1045 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1046 iface_breg |= (0x03 << 6); 1047 break; 1048 default: 1049 return -EINVAL; 1050 } 1051 1052 /* set iface */ 1053 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1054 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1055 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1056 1057 return 0; 1058 } 1059 1060 static int aic3x_init_3007(struct snd_soc_codec *codec) 1061 { 1062 u8 tmp1, tmp2, *cache = codec->reg_cache; 1063 1064 /* 1065 * There is no need to cache writes to undocumented page 0xD but 1066 * respective page 0 register cache entries must be preserved 1067 */ 1068 tmp1 = cache[0xD]; 1069 tmp2 = cache[0x8]; 1070 /* Class-D speaker driver init; datasheet p. 46 */ 1071 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D); 1072 snd_soc_write(codec, 0xD, 0x0D); 1073 snd_soc_write(codec, 0x8, 0x5C); 1074 snd_soc_write(codec, 0x8, 0x5D); 1075 snd_soc_write(codec, 0x8, 0x5C); 1076 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00); 1077 cache[0xD] = tmp1; 1078 cache[0x8] = tmp2; 1079 1080 return 0; 1081 } 1082 1083 static int aic3x_regulator_event(struct notifier_block *nb, 1084 unsigned long event, void *data) 1085 { 1086 struct aic3x_disable_nb *disable_nb = 1087 container_of(nb, struct aic3x_disable_nb, nb); 1088 struct aic3x_priv *aic3x = disable_nb->aic3x; 1089 1090 if (event & REGULATOR_EVENT_DISABLE) { 1091 /* 1092 * Put codec to reset and require cache sync as at least one 1093 * of the supplies was disabled 1094 */ 1095 if (gpio_is_valid(aic3x->gpio_reset)) 1096 gpio_set_value(aic3x->gpio_reset, 0); 1097 aic3x->codec->cache_sync = 1; 1098 } 1099 1100 return 0; 1101 } 1102 1103 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1104 { 1105 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1106 int i, ret; 1107 u8 *cache = codec->reg_cache; 1108 1109 if (power) { 1110 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1111 aic3x->supplies); 1112 if (ret) 1113 goto out; 1114 aic3x->power = 1; 1115 /* 1116 * Reset release and cache sync is necessary only if some 1117 * supply was off or if there were cached writes 1118 */ 1119 if (!codec->cache_sync) 1120 goto out; 1121 1122 if (gpio_is_valid(aic3x->gpio_reset)) { 1123 udelay(1); 1124 gpio_set_value(aic3x->gpio_reset, 1); 1125 } 1126 1127 /* Sync reg_cache with the hardware */ 1128 codec->cache_only = 0; 1129 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) 1130 snd_soc_write(codec, i, cache[i]); 1131 if (aic3x->model == AIC3X_MODEL_3007) 1132 aic3x_init_3007(codec); 1133 codec->cache_sync = 0; 1134 } else { 1135 /* 1136 * Do soft reset to this codec instance in order to clear 1137 * possible VDD leakage currents in case the supply regulators 1138 * remain on 1139 */ 1140 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1141 codec->cache_sync = 1; 1142 aic3x->power = 0; 1143 /* HW writes are needless when bias is off */ 1144 codec->cache_only = 1; 1145 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1146 aic3x->supplies); 1147 } 1148 out: 1149 return ret; 1150 } 1151 1152 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1153 enum snd_soc_bias_level level) 1154 { 1155 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1156 1157 switch (level) { 1158 case SND_SOC_BIAS_ON: 1159 break; 1160 case SND_SOC_BIAS_PREPARE: 1161 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY && 1162 aic3x->master) { 1163 /* enable pll */ 1164 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1165 PLL_ENABLE, PLL_ENABLE); 1166 } 1167 break; 1168 case SND_SOC_BIAS_STANDBY: 1169 if (!aic3x->power) 1170 aic3x_set_power(codec, 1); 1171 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE && 1172 aic3x->master) { 1173 /* disable pll */ 1174 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1175 PLL_ENABLE, 0); 1176 } 1177 break; 1178 case SND_SOC_BIAS_OFF: 1179 if (aic3x->power) 1180 aic3x_set_power(codec, 0); 1181 break; 1182 } 1183 codec->dapm.bias_level = level; 1184 1185 return 0; 1186 } 1187 1188 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) 1189 { 1190 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1191 u8 bit = gpio ? 3: 0; 1192 u8 val = snd_soc_read(codec, reg) & ~(1 << bit); 1193 snd_soc_write(codec, reg, val | (!!state << bit)); 1194 } 1195 EXPORT_SYMBOL_GPL(aic3x_set_gpio); 1196 1197 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio) 1198 { 1199 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1200 u8 val = 0, bit = gpio ? 2 : 1; 1201 1202 aic3x_read(codec, reg, &val); 1203 return (val >> bit) & 1; 1204 } 1205 EXPORT_SYMBOL_GPL(aic3x_get_gpio); 1206 1207 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, 1208 int headset_debounce, int button_debounce) 1209 { 1210 u8 val; 1211 1212 val = ((detect & AIC3X_HEADSET_DETECT_MASK) 1213 << AIC3X_HEADSET_DETECT_SHIFT) | 1214 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK) 1215 << AIC3X_HEADSET_DEBOUNCE_SHIFT) | 1216 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK) 1217 << AIC3X_BUTTON_DEBOUNCE_SHIFT); 1218 1219 if (detect & AIC3X_HEADSET_DETECT_MASK) 1220 val |= AIC3X_HEADSET_DETECT_ENABLED; 1221 1222 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val); 1223 } 1224 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection); 1225 1226 int aic3x_headset_detected(struct snd_soc_codec *codec) 1227 { 1228 u8 val = 0; 1229 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1230 return (val >> 4) & 1; 1231 } 1232 EXPORT_SYMBOL_GPL(aic3x_headset_detected); 1233 1234 int aic3x_button_pressed(struct snd_soc_codec *codec) 1235 { 1236 u8 val = 0; 1237 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1238 return (val >> 5) & 1; 1239 } 1240 EXPORT_SYMBOL_GPL(aic3x_button_pressed); 1241 1242 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1243 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1244 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1245 1246 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1247 .hw_params = aic3x_hw_params, 1248 .digital_mute = aic3x_mute, 1249 .set_sysclk = aic3x_set_dai_sysclk, 1250 .set_fmt = aic3x_set_dai_fmt, 1251 }; 1252 1253 static struct snd_soc_dai_driver aic3x_dai = { 1254 .name = "tlv320aic3x-hifi", 1255 .playback = { 1256 .stream_name = "Playback", 1257 .channels_min = 1, 1258 .channels_max = 2, 1259 .rates = AIC3X_RATES, 1260 .formats = AIC3X_FORMATS,}, 1261 .capture = { 1262 .stream_name = "Capture", 1263 .channels_min = 1, 1264 .channels_max = 2, 1265 .rates = AIC3X_RATES, 1266 .formats = AIC3X_FORMATS,}, 1267 .ops = &aic3x_dai_ops, 1268 .symmetric_rates = 1, 1269 }; 1270 1271 static int aic3x_suspend(struct snd_soc_codec *codec) 1272 { 1273 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1274 1275 return 0; 1276 } 1277 1278 static int aic3x_resume(struct snd_soc_codec *codec) 1279 { 1280 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1281 1282 return 0; 1283 } 1284 1285 /* 1286 * initialise the AIC3X driver 1287 * register the mixer and dsp interfaces with the kernel 1288 */ 1289 static int aic3x_init(struct snd_soc_codec *codec) 1290 { 1291 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1292 1293 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1294 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1295 1296 /* DAC default volume and mute */ 1297 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1298 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1299 1300 /* DAC to HP default volume and route to Output mixer */ 1301 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1302 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1303 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1304 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1305 /* DAC to Line Out default volume and route to Output mixer */ 1306 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1307 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1308 /* DAC to Mono Line Out default volume and route to Output mixer */ 1309 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1310 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1311 1312 /* unmute all outputs */ 1313 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); 1314 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); 1315 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1316 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); 1317 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); 1318 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); 1319 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); 1320 1321 /* ADC default volume and unmute */ 1322 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1323 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1324 /* By default route Line1 to ADC PGA mixer */ 1325 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1326 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1327 1328 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1329 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1330 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1331 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1332 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1333 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1334 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1335 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1336 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1337 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1338 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1339 1340 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1341 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1342 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1343 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1344 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1345 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1346 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1347 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1348 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1349 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1350 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1351 1352 if (aic3x->model == AIC3X_MODEL_3007) { 1353 aic3x_init_3007(codec); 1354 snd_soc_write(codec, CLASSD_CTRL, 0); 1355 } 1356 1357 return 0; 1358 } 1359 1360 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1361 { 1362 struct aic3x_priv *a; 1363 1364 list_for_each_entry(a, &reset_list, list) { 1365 if (gpio_is_valid(aic3x->gpio_reset) && 1366 aic3x->gpio_reset == a->gpio_reset) 1367 return true; 1368 } 1369 1370 return false; 1371 } 1372 1373 static int aic3x_probe(struct snd_soc_codec *codec) 1374 { 1375 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1376 int ret, i; 1377 1378 INIT_LIST_HEAD(&aic3x->list); 1379 aic3x->codec = codec; 1380 codec->dapm.idle_bias_off = 1; 1381 1382 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); 1383 if (ret != 0) { 1384 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1385 return ret; 1386 } 1387 1388 if (gpio_is_valid(aic3x->gpio_reset) && 1389 !aic3x_is_shared_reset(aic3x)) { 1390 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1391 if (ret != 0) 1392 goto err_gpio; 1393 gpio_direction_output(aic3x->gpio_reset, 0); 1394 } 1395 1396 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1397 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1398 1399 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), 1400 aic3x->supplies); 1401 if (ret != 0) { 1402 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1403 goto err_get; 1404 } 1405 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1406 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1407 aic3x->disable_nb[i].aic3x = aic3x; 1408 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1409 &aic3x->disable_nb[i].nb); 1410 if (ret) { 1411 dev_err(codec->dev, 1412 "Failed to request regulator notifier: %d\n", 1413 ret); 1414 goto err_notif; 1415 } 1416 } 1417 1418 codec->cache_only = 1; 1419 aic3x_init(codec); 1420 1421 if (aic3x->setup) { 1422 /* setup GPIO functions */ 1423 snd_soc_write(codec, AIC3X_GPIO1_REG, 1424 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1425 snd_soc_write(codec, AIC3X_GPIO2_REG, 1426 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1427 } 1428 1429 snd_soc_add_controls(codec, aic3x_snd_controls, 1430 ARRAY_SIZE(aic3x_snd_controls)); 1431 if (aic3x->model == AIC3X_MODEL_3007) 1432 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1433 1434 aic3x_add_widgets(codec); 1435 list_add(&aic3x->list, &reset_list); 1436 1437 return 0; 1438 1439 err_notif: 1440 while (i--) 1441 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1442 &aic3x->disable_nb[i].nb); 1443 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1444 err_get: 1445 if (gpio_is_valid(aic3x->gpio_reset) && 1446 !aic3x_is_shared_reset(aic3x)) 1447 gpio_free(aic3x->gpio_reset); 1448 err_gpio: 1449 return ret; 1450 } 1451 1452 static int aic3x_remove(struct snd_soc_codec *codec) 1453 { 1454 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1455 int i; 1456 1457 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1458 list_del(&aic3x->list); 1459 if (gpio_is_valid(aic3x->gpio_reset) && 1460 !aic3x_is_shared_reset(aic3x)) { 1461 gpio_set_value(aic3x->gpio_reset, 0); 1462 gpio_free(aic3x->gpio_reset); 1463 } 1464 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1465 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1466 &aic3x->disable_nb[i].nb); 1467 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1468 1469 return 0; 1470 } 1471 1472 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1473 .set_bias_level = aic3x_set_bias_level, 1474 .reg_cache_size = ARRAY_SIZE(aic3x_reg), 1475 .reg_word_size = sizeof(u8), 1476 .reg_cache_default = aic3x_reg, 1477 .probe = aic3x_probe, 1478 .remove = aic3x_remove, 1479 .suspend = aic3x_suspend, 1480 .resume = aic3x_resume, 1481 }; 1482 1483 /* 1484 * AIC3X 2 wire address can be up to 4 devices with device addresses 1485 * 0x18, 0x19, 0x1A, 0x1B 1486 */ 1487 1488 static const struct i2c_device_id aic3x_i2c_id[] = { 1489 { "tlv320aic3x", AIC3X_MODEL_3X }, 1490 { "tlv320aic33", AIC3X_MODEL_33 }, 1491 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1492 { } 1493 }; 1494 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1495 1496 /* 1497 * If the i2c layer weren't so broken, we could pass this kind of data 1498 * around 1499 */ 1500 static int aic3x_i2c_probe(struct i2c_client *i2c, 1501 const struct i2c_device_id *id) 1502 { 1503 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1504 struct aic3x_priv *aic3x; 1505 int ret; 1506 1507 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1508 if (aic3x == NULL) { 1509 dev_err(&i2c->dev, "failed to create private data\n"); 1510 return -ENOMEM; 1511 } 1512 1513 aic3x->control_type = SND_SOC_I2C; 1514 1515 i2c_set_clientdata(i2c, aic3x); 1516 if (pdata) { 1517 aic3x->gpio_reset = pdata->gpio_reset; 1518 aic3x->setup = pdata->setup; 1519 } else { 1520 aic3x->gpio_reset = -1; 1521 } 1522 1523 aic3x->model = id->driver_data; 1524 1525 ret = snd_soc_register_codec(&i2c->dev, 1526 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1527 return ret; 1528 } 1529 1530 static int aic3x_i2c_remove(struct i2c_client *client) 1531 { 1532 snd_soc_unregister_codec(&client->dev); 1533 return 0; 1534 } 1535 1536 /* machine i2c codec control layer */ 1537 static struct i2c_driver aic3x_i2c_driver = { 1538 .driver = { 1539 .name = "tlv320aic3x-codec", 1540 .owner = THIS_MODULE, 1541 }, 1542 .probe = aic3x_i2c_probe, 1543 .remove = aic3x_i2c_remove, 1544 .id_table = aic3x_i2c_id, 1545 }; 1546 1547 static int __init aic3x_modinit(void) 1548 { 1549 int ret = 0; 1550 ret = i2c_add_driver(&aic3x_i2c_driver); 1551 if (ret != 0) { 1552 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n", 1553 ret); 1554 } 1555 return ret; 1556 } 1557 module_init(aic3x_modinit); 1558 1559 static void __exit aic3x_exit(void) 1560 { 1561 i2c_del_driver(&aic3x_i2c_driver); 1562 } 1563 module_exit(aic3x_exit); 1564 1565 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1566 MODULE_AUTHOR("Vladimir Barinov"); 1567 MODULE_LICENSE("GPL"); 1568