1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/of.h> 44 #include <linux/of_gpio.h> 45 #include <linux/slab.h> 46 #include <sound/core.h> 47 #include <sound/pcm.h> 48 #include <sound/pcm_params.h> 49 #include <sound/soc.h> 50 #include <sound/initval.h> 51 #include <sound/tlv.h> 52 #include <sound/tlv320aic3x.h> 53 54 #include "tlv320aic3x.h" 55 56 #define AIC3X_NUM_SUPPLIES 4 57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 58 "IOVDD", /* I/O Voltage */ 59 "DVDD", /* Digital Core Voltage */ 60 "AVDD", /* Analog DAC Voltage */ 61 "DRVDD", /* ADC Analog and Output Driver Voltage */ 62 }; 63 64 static LIST_HEAD(reset_list); 65 66 struct aic3x_priv; 67 68 struct aic3x_disable_nb { 69 struct notifier_block nb; 70 struct aic3x_priv *aic3x; 71 }; 72 73 /* codec private data */ 74 struct aic3x_priv { 75 struct snd_soc_component *component; 76 struct regmap *regmap; 77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 79 struct aic3x_setup_data *setup; 80 unsigned int sysclk; 81 unsigned int dai_fmt; 82 unsigned int tdm_delay; 83 unsigned int slot_width; 84 struct list_head list; 85 int master; 86 int gpio_reset; 87 int power; 88 #define AIC3X_MODEL_3X 0 89 #define AIC3X_MODEL_33 1 90 #define AIC3X_MODEL_3007 2 91 #define AIC3X_MODEL_3104 3 92 u16 model; 93 94 /* Selects the micbias voltage */ 95 enum aic3x_micbias_voltage micbias_vg; 96 /* Output Common-Mode Voltage */ 97 u8 ocmv; 98 }; 99 100 static const struct reg_default aic3x_reg[] = { 101 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 }, 102 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 }, 103 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 }, 104 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 }, 105 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 }, 106 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 }, 107 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe }, 108 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 }, 109 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 }, 110 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 }, 111 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 }, 112 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 113 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 }, 114 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 }, 115 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 }, 116 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 }, 117 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 }, 118 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 119 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 120 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 121 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 }, 122 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 123 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 124 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 125 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 126 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 }, 127 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 128 { 108, 0x00 }, { 109, 0x00 }, 129 }; 130 131 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg) 132 { 133 switch (reg) { 134 case AIC3X_RESET: 135 return true; 136 default: 137 return false; 138 } 139 } 140 141 static const struct regmap_config aic3x_regmap = { 142 .reg_bits = 8, 143 .val_bits = 8, 144 145 .max_register = DAC_ICC_ADJ, 146 .reg_defaults = aic3x_reg, 147 .num_reg_defaults = ARRAY_SIZE(aic3x_reg), 148 149 .volatile_reg = aic3x_volatile_reg, 150 151 .cache_type = REGCACHE_RBTREE, 152 }; 153 154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 155 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ 156 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x) 157 158 /* 159 * All input lines are connected when !0xf and disconnected with 0xf bit field, 160 * so we have to use specific dapm_put call for input mixer 161 */ 162 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 163 struct snd_ctl_elem_value *ucontrol) 164 { 165 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 166 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 167 struct soc_mixer_control *mc = 168 (struct soc_mixer_control *)kcontrol->private_value; 169 unsigned int reg = mc->reg; 170 unsigned int shift = mc->shift; 171 int max = mc->max; 172 unsigned int mask = (1 << fls(max)) - 1; 173 unsigned int invert = mc->invert; 174 unsigned short val; 175 struct snd_soc_dapm_update update = {}; 176 int connect, change; 177 178 val = (ucontrol->value.integer.value[0] & mask); 179 180 mask = 0xf; 181 if (val) 182 val = mask; 183 184 connect = !!val; 185 186 if (invert) 187 val = mask - val; 188 189 mask <<= shift; 190 val <<= shift; 191 192 change = snd_soc_component_test_bits(component, reg, mask, val); 193 if (change) { 194 update.kcontrol = kcontrol; 195 update.reg = reg; 196 update.mask = mask; 197 update.val = val; 198 199 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect, 200 &update); 201 } 202 203 return change; 204 } 205 206 /* 207 * mic bias power on/off share the same register bits with 208 * output voltage of mic bias. when power on mic bias, we 209 * need reclaim it to voltage value. 210 * 0x0 = Powered off 211 * 0x1 = MICBIAS output is powered to 2.0V, 212 * 0x2 = MICBIAS output is powered to 2.5V 213 * 0x3 = MICBIAS output is connected to AVDD 214 */ 215 static int mic_bias_event(struct snd_soc_dapm_widget *w, 216 struct snd_kcontrol *kcontrol, int event) 217 { 218 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 219 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 220 221 switch (event) { 222 case SND_SOC_DAPM_POST_PMU: 223 /* change mic bias voltage to user defined */ 224 snd_soc_component_update_bits(component, MICBIAS_CTRL, 225 MICBIAS_LEVEL_MASK, 226 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); 227 break; 228 229 case SND_SOC_DAPM_PRE_PMD: 230 snd_soc_component_update_bits(component, MICBIAS_CTRL, 231 MICBIAS_LEVEL_MASK, 0); 232 break; 233 } 234 return 0; 235 } 236 237 static const char * const aic3x_left_dac_mux[] = { 238 "DAC_L1", "DAC_L3", "DAC_L2" }; 239 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6, 240 aic3x_left_dac_mux); 241 242 static const char * const aic3x_right_dac_mux[] = { 243 "DAC_R1", "DAC_R3", "DAC_R2" }; 244 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4, 245 aic3x_right_dac_mux); 246 247 static const char * const aic3x_left_hpcom_mux[] = { 248 "differential of HPLOUT", "constant VCM", "single-ended" }; 249 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4, 250 aic3x_left_hpcom_mux); 251 252 static const char * const aic3x_right_hpcom_mux[] = { 253 "differential of HPROUT", "constant VCM", "single-ended", 254 "differential of HPLCOM", "external feedback" }; 255 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3, 256 aic3x_right_hpcom_mux); 257 258 static const char * const aic3x_linein_mode_mux[] = { 259 "single-ended", "differential" }; 260 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7, 261 aic3x_linein_mode_mux); 262 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7, 263 aic3x_linein_mode_mux); 264 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7, 265 aic3x_linein_mode_mux); 266 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7, 267 aic3x_linein_mode_mux); 268 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7, 269 aic3x_linein_mode_mux); 270 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7, 271 aic3x_linein_mode_mux); 272 273 static const char * const aic3x_adc_hpf[] = { 274 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 275 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4, 276 aic3x_adc_hpf); 277 278 static const char * const aic3x_agc_level[] = { 279 "-5.5dB", "-8dB", "-10dB", "-12dB", 280 "-14dB", "-17dB", "-20dB", "-24dB" }; 281 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4, 282 aic3x_agc_level); 283 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4, 284 aic3x_agc_level); 285 286 static const char * const aic3x_agc_attack[] = { 287 "8ms", "11ms", "16ms", "20ms" }; 288 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2, 289 aic3x_agc_attack); 290 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2, 291 aic3x_agc_attack); 292 293 static const char * const aic3x_agc_decay[] = { 294 "100ms", "200ms", "400ms", "500ms" }; 295 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0, 296 aic3x_agc_decay); 297 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0, 298 aic3x_agc_decay); 299 300 static const char * const aic3x_poweron_time[] = { 301 "0us", "10us", "100us", "1ms", "10ms", "50ms", 302 "100ms", "200ms", "400ms", "800ms", "2s", "4s" }; 303 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4, 304 aic3x_poweron_time); 305 306 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" }; 307 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2, 308 aic3x_rampup_step); 309 310 /* 311 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 312 */ 313 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 314 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 315 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 316 /* 317 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 318 * Step size is approximately 0.5 dB over most of the scale but increasing 319 * near the very low levels. 320 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 321 * but having increasing dB difference below that (and where it doesn't count 322 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 323 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 324 */ 325 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 326 327 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 328 /* Output */ 329 SOC_DOUBLE_R_TLV("PCM Playback Volume", 330 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 331 332 /* 333 * Output controls that map to output mixer switches. Note these are 334 * only for swapped L-to-R and R-to-L routes. See below stereo controls 335 * for direct L-to-L and R-to-R routes. 336 */ 337 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 338 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 339 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 340 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 341 342 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 343 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 344 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 345 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 346 347 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 348 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 349 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 350 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 351 352 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 353 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 354 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 355 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 356 357 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 358 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 359 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 360 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 361 362 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 363 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 364 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 365 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 366 367 /* Stereo output controls for direct L-to-L and R-to-R routes */ 368 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 369 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 370 0, 118, 1, output_stage_tlv), 371 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 372 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 373 0, 118, 1, output_stage_tlv), 374 375 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 376 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 377 0, 118, 1, output_stage_tlv), 378 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 379 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 380 0, 118, 1, output_stage_tlv), 381 382 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 383 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 384 0, 118, 1, output_stage_tlv), 385 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 386 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 387 0, 118, 1, output_stage_tlv), 388 389 /* Output pin mute controls */ 390 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 391 0x01, 0), 392 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 393 0x01, 0), 394 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 395 0x01, 0), 396 397 /* 398 * Note: enable Automatic input Gain Controller with care. It can 399 * adjust PGA to max value when ADC is on and will never go back. 400 */ 401 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 402 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum), 403 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum), 404 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum), 405 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum), 406 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum), 407 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum), 408 409 /* De-emphasis */ 410 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), 411 412 /* Input */ 413 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 414 0, 119, 0, adc_tlv), 415 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 416 417 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum), 418 419 /* Pop reduction */ 420 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum), 421 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum), 422 }; 423 424 /* For other than tlv320aic3104 */ 425 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = { 426 /* 427 * Output controls that map to output mixer switches. Note these are 428 * only for swapped L-to-R and R-to-L routes. See below stereo controls 429 * for direct L-to-L and R-to-R routes. 430 */ 431 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 432 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 433 434 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 435 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 436 437 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 438 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 439 440 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 441 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 442 443 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 444 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 445 446 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 447 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 448 449 /* Stereo output controls for direct L-to-L and R-to-R routes */ 450 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 451 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 452 0, 118, 1, output_stage_tlv), 453 454 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 455 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 456 0, 118, 1, output_stage_tlv), 457 458 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 459 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 460 0, 118, 1, output_stage_tlv), 461 }; 462 463 static const struct snd_kcontrol_new aic3x_mono_controls[] = { 464 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 465 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 466 0, 118, 1, output_stage_tlv), 467 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 468 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 469 0, 118, 1, output_stage_tlv), 470 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 471 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 472 0, 118, 1, output_stage_tlv), 473 474 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 475 }; 476 477 /* 478 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 479 */ 480 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 481 482 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 483 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 484 485 /* Left DAC Mux */ 486 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 487 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum); 488 489 /* Right DAC Mux */ 490 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 491 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum); 492 493 /* Left HPCOM Mux */ 494 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 495 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum); 496 497 /* Right HPCOM Mux */ 498 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 499 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum); 500 501 /* Left Line Mixer */ 502 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 503 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 504 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 505 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 506 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 507 /* Not on tlv320aic3104 */ 508 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 509 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 510 }; 511 512 /* Right Line Mixer */ 513 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 514 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 515 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 516 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 517 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 518 /* Not on tlv320aic3104 */ 519 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 520 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 521 }; 522 523 /* Mono Mixer */ 524 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 525 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 526 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 527 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 528 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 529 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 530 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 531 }; 532 533 /* Left HP Mixer */ 534 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 535 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 536 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 537 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 538 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 539 /* Not on tlv320aic3104 */ 540 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 541 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 542 }; 543 544 /* Right HP Mixer */ 545 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 546 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 547 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 548 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 549 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 550 /* Not on tlv320aic3104 */ 551 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 552 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 553 }; 554 555 /* Left HPCOM Mixer */ 556 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 557 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 558 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 559 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 560 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 561 /* Not on tlv320aic3104 */ 562 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 563 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 564 }; 565 566 /* Right HPCOM Mixer */ 567 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 568 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 569 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 570 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 571 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 572 /* Not on tlv320aic3104 */ 573 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 574 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 575 }; 576 577 /* Left PGA Mixer */ 578 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 579 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 580 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 581 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 582 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 583 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 584 }; 585 586 /* Right PGA Mixer */ 587 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 588 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 589 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 590 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 591 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 592 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 593 }; 594 595 /* Left PGA Mixer for tlv320aic3104 */ 596 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = { 597 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 598 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 599 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 600 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 601 }; 602 603 /* Right PGA Mixer for tlv320aic3104 */ 604 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = { 605 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 606 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 607 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 608 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 609 }; 610 611 /* Left Line1 Mux */ 612 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 613 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum); 614 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 615 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum); 616 617 /* Right Line1 Mux */ 618 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 619 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum); 620 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 621 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum); 622 623 /* Left Line2 Mux */ 624 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 625 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum); 626 627 /* Right Line2 Mux */ 628 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 629 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum); 630 631 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 632 /* Left DAC to Left Outputs */ 633 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 634 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 635 &aic3x_left_dac_mux_controls), 636 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 637 &aic3x_left_hpcom_mux_controls), 638 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 639 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 640 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 641 642 /* Right DAC to Right Outputs */ 643 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 644 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 645 &aic3x_right_dac_mux_controls), 646 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 647 &aic3x_right_hpcom_mux_controls), 648 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 649 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 650 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 651 652 /* Inputs to Left ADC */ 653 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 654 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 655 &aic3x_left_line1l_mux_controls), 656 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 657 &aic3x_left_line1r_mux_controls), 658 659 /* Inputs to Right ADC */ 660 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 661 LINE1R_2_RADC_CTRL, 2, 0), 662 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 663 &aic3x_right_line1l_mux_controls), 664 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 665 &aic3x_right_line1r_mux_controls), 666 667 /* Mic Bias */ 668 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, 669 mic_bias_event, 670 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 671 672 SND_SOC_DAPM_OUTPUT("LLOUT"), 673 SND_SOC_DAPM_OUTPUT("RLOUT"), 674 SND_SOC_DAPM_OUTPUT("HPLOUT"), 675 SND_SOC_DAPM_OUTPUT("HPROUT"), 676 SND_SOC_DAPM_OUTPUT("HPLCOM"), 677 SND_SOC_DAPM_OUTPUT("HPRCOM"), 678 679 SND_SOC_DAPM_INPUT("LINE1L"), 680 SND_SOC_DAPM_INPUT("LINE1R"), 681 682 /* 683 * Virtual output pin to detection block inside codec. This can be 684 * used to keep codec bias on if gpio or detection features are needed. 685 * Force pin on or construct a path with an input jack and mic bias 686 * widgets. 687 */ 688 SND_SOC_DAPM_OUTPUT("Detection"), 689 }; 690 691 /* For other than tlv320aic3104 */ 692 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = { 693 /* Inputs to Left ADC */ 694 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 695 &aic3x_left_pga_mixer_controls[0], 696 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 697 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 698 &aic3x_left_line2_mux_controls), 699 700 /* Inputs to Right ADC */ 701 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 702 &aic3x_right_pga_mixer_controls[0], 703 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 704 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 705 &aic3x_right_line2_mux_controls), 706 707 /* 708 * Not a real mic bias widget but similar function. This is for dynamic 709 * control of GPIO1 digital mic modulator clock output function when 710 * using digital mic. 711 */ 712 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 713 AIC3X_GPIO1_REG, 4, 0xf, 714 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 715 AIC3X_GPIO1_FUNC_DISABLED), 716 717 /* 718 * Also similar function like mic bias. Selects digital mic with 719 * configurable oversampling rate instead of ADC converter. 720 */ 721 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 722 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 723 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 724 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 725 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 726 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 727 728 /* Output mixers */ 729 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 730 &aic3x_left_line_mixer_controls[0], 731 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 732 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 733 &aic3x_right_line_mixer_controls[0], 734 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 735 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 736 &aic3x_left_hp_mixer_controls[0], 737 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 738 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 739 &aic3x_right_hp_mixer_controls[0], 740 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 741 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 742 &aic3x_left_hpcom_mixer_controls[0], 743 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 744 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 745 &aic3x_right_hpcom_mixer_controls[0], 746 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 747 748 SND_SOC_DAPM_INPUT("MIC3L"), 749 SND_SOC_DAPM_INPUT("MIC3R"), 750 SND_SOC_DAPM_INPUT("LINE2L"), 751 SND_SOC_DAPM_INPUT("LINE2R"), 752 }; 753 754 /* For tlv320aic3104 */ 755 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = { 756 /* Inputs to Left ADC */ 757 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 758 &aic3104_left_pga_mixer_controls[0], 759 ARRAY_SIZE(aic3104_left_pga_mixer_controls)), 760 761 /* Inputs to Right ADC */ 762 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 763 &aic3104_right_pga_mixer_controls[0], 764 ARRAY_SIZE(aic3104_right_pga_mixer_controls)), 765 766 /* Output mixers */ 767 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 768 &aic3x_left_line_mixer_controls[0], 769 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2), 770 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 771 &aic3x_right_line_mixer_controls[0], 772 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2), 773 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 774 &aic3x_left_hp_mixer_controls[0], 775 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2), 776 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 777 &aic3x_right_hp_mixer_controls[0], 778 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2), 779 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 780 &aic3x_left_hpcom_mixer_controls[0], 781 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2), 782 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 783 &aic3x_right_hpcom_mixer_controls[0], 784 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2), 785 786 SND_SOC_DAPM_INPUT("MIC2L"), 787 SND_SOC_DAPM_INPUT("MIC2R"), 788 }; 789 790 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = { 791 /* Mono Output */ 792 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 793 794 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 795 &aic3x_mono_mixer_controls[0], 796 ARRAY_SIZE(aic3x_mono_mixer_controls)), 797 798 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 799 }; 800 801 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 802 /* Class-D outputs */ 803 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 804 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 805 806 SND_SOC_DAPM_OUTPUT("SPOP"), 807 SND_SOC_DAPM_OUTPUT("SPOM"), 808 }; 809 810 static const struct snd_soc_dapm_route intercon[] = { 811 /* Left Input */ 812 {"Left Line1L Mux", "single-ended", "LINE1L"}, 813 {"Left Line1L Mux", "differential", "LINE1L"}, 814 {"Left Line1R Mux", "single-ended", "LINE1R"}, 815 {"Left Line1R Mux", "differential", "LINE1R"}, 816 817 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 818 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 819 820 {"Left ADC", NULL, "Left PGA Mixer"}, 821 822 /* Right Input */ 823 {"Right Line1R Mux", "single-ended", "LINE1R"}, 824 {"Right Line1R Mux", "differential", "LINE1R"}, 825 {"Right Line1L Mux", "single-ended", "LINE1L"}, 826 {"Right Line1L Mux", "differential", "LINE1L"}, 827 828 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 829 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 830 831 {"Right ADC", NULL, "Right PGA Mixer"}, 832 833 /* Left DAC Output */ 834 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 835 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 836 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 837 838 /* Right DAC Output */ 839 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 840 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 841 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 842 843 /* Left Line Output */ 844 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 845 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 846 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 847 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 848 849 {"Left Line Out", NULL, "Left Line Mixer"}, 850 {"Left Line Out", NULL, "Left DAC Mux"}, 851 {"LLOUT", NULL, "Left Line Out"}, 852 853 /* Right Line Output */ 854 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 855 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 856 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 857 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 858 859 {"Right Line Out", NULL, "Right Line Mixer"}, 860 {"Right Line Out", NULL, "Right DAC Mux"}, 861 {"RLOUT", NULL, "Right Line Out"}, 862 863 /* Left HP Output */ 864 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 865 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 866 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 867 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 868 869 {"Left HP Out", NULL, "Left HP Mixer"}, 870 {"Left HP Out", NULL, "Left DAC Mux"}, 871 {"HPLOUT", NULL, "Left HP Out"}, 872 873 /* Right HP Output */ 874 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 875 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 876 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 877 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 878 879 {"Right HP Out", NULL, "Right HP Mixer"}, 880 {"Right HP Out", NULL, "Right DAC Mux"}, 881 {"HPROUT", NULL, "Right HP Out"}, 882 883 /* Left HPCOM Output */ 884 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 885 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 886 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 887 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 888 889 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 890 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 891 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 892 {"Left HP Com", NULL, "Left HPCOM Mux"}, 893 {"HPLCOM", NULL, "Left HP Com"}, 894 895 /* Right HPCOM Output */ 896 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 897 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 898 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 899 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 900 901 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 902 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 903 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 904 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 905 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 906 {"Right HP Com", NULL, "Right HPCOM Mux"}, 907 {"HPRCOM", NULL, "Right HP Com"}, 908 }; 909 910 /* For other than tlv320aic3104 */ 911 static const struct snd_soc_dapm_route intercon_extra[] = { 912 /* Left Input */ 913 {"Left Line2L Mux", "single-ended", "LINE2L"}, 914 {"Left Line2L Mux", "differential", "LINE2L"}, 915 916 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 917 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 918 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 919 920 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 921 922 /* Right Input */ 923 {"Right Line2R Mux", "single-ended", "LINE2R"}, 924 {"Right Line2R Mux", "differential", "LINE2R"}, 925 926 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 927 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 928 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 929 930 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 931 932 /* 933 * Logical path between digital mic enable and GPIO1 modulator clock 934 * output function 935 */ 936 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 937 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 938 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 939 940 /* Left Line Output */ 941 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 942 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 943 944 /* Right Line Output */ 945 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 946 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 947 948 /* Left HP Output */ 949 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 950 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 951 952 /* Right HP Output */ 953 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 954 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 955 956 /* Left HPCOM Output */ 957 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 958 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 959 960 /* Right HPCOM Output */ 961 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 962 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 963 }; 964 965 /* For tlv320aic3104 */ 966 static const struct snd_soc_dapm_route intercon_extra_3104[] = { 967 /* Left Input */ 968 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"}, 969 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"}, 970 971 /* Right Input */ 972 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"}, 973 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"}, 974 }; 975 976 static const struct snd_soc_dapm_route intercon_mono[] = { 977 /* Mono Output */ 978 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 979 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 980 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 981 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 982 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 983 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 984 {"Mono Out", NULL, "Mono Mixer"}, 985 {"MONO_LOUT", NULL, "Mono Out"}, 986 }; 987 988 static const struct snd_soc_dapm_route intercon_3007[] = { 989 /* Class-D outputs */ 990 {"Left Class-D Out", NULL, "Left Line Out"}, 991 {"Right Class-D Out", NULL, "Left Line Out"}, 992 {"SPOP", NULL, "Left Class-D Out"}, 993 {"SPOM", NULL, "Right Class-D Out"}, 994 }; 995 996 static int aic3x_add_widgets(struct snd_soc_component *component) 997 { 998 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 999 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1000 1001 switch (aic3x->model) { 1002 case AIC3X_MODEL_3X: 1003 case AIC3X_MODEL_33: 1004 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 1005 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 1006 snd_soc_dapm_add_routes(dapm, intercon_extra, 1007 ARRAY_SIZE(intercon_extra)); 1008 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets, 1009 ARRAY_SIZE(aic3x_dapm_mono_widgets)); 1010 snd_soc_dapm_add_routes(dapm, intercon_mono, 1011 ARRAY_SIZE(intercon_mono)); 1012 break; 1013 case AIC3X_MODEL_3007: 1014 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 1015 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 1016 snd_soc_dapm_add_routes(dapm, intercon_extra, 1017 ARRAY_SIZE(intercon_extra)); 1018 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 1019 ARRAY_SIZE(aic3007_dapm_widgets)); 1020 snd_soc_dapm_add_routes(dapm, intercon_3007, 1021 ARRAY_SIZE(intercon_3007)); 1022 break; 1023 case AIC3X_MODEL_3104: 1024 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets, 1025 ARRAY_SIZE(aic3104_extra_dapm_widgets)); 1026 snd_soc_dapm_add_routes(dapm, intercon_extra_3104, 1027 ARRAY_SIZE(intercon_extra_3104)); 1028 break; 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int aic3x_hw_params(struct snd_pcm_substream *substream, 1035 struct snd_pcm_hw_params *params, 1036 struct snd_soc_dai *dai) 1037 { 1038 struct snd_soc_component *component = dai->component; 1039 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1040 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 1041 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 1042 u16 d, pll_d = 1; 1043 int clk; 1044 int width = aic3x->slot_width; 1045 1046 if (!width) 1047 width = params_width(params); 1048 1049 /* select data word length */ 1050 data = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 1051 switch (width) { 1052 case 16: 1053 break; 1054 case 20: 1055 data |= (0x01 << 4); 1056 break; 1057 case 24: 1058 data |= (0x02 << 4); 1059 break; 1060 case 32: 1061 data |= (0x03 << 4); 1062 break; 1063 } 1064 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data); 1065 1066 /* Fsref can be 44100 or 48000 */ 1067 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 1068 1069 /* Try to find a value for Q which allows us to bypass the PLL and 1070 * generate CODEC_CLK directly. */ 1071 for (pll_q = 2; pll_q < 18; pll_q++) 1072 if (aic3x->sysclk / (128 * pll_q) == fsref) { 1073 bypass_pll = 1; 1074 break; 1075 } 1076 1077 if (bypass_pll) { 1078 pll_q &= 0xf; 1079 snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 1080 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 1081 /* disable PLL if it is bypassed */ 1082 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 1083 1084 } else { 1085 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 1086 /* enable PLL when it is used */ 1087 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, 1088 PLL_ENABLE, PLL_ENABLE); 1089 } 1090 1091 /* Route Left DAC to left channel input and 1092 * right DAC to right channel input */ 1093 data = (LDAC2LCH | RDAC2RCH); 1094 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 1095 if (params_rate(params) >= 64000) 1096 data |= DUAL_RATE_MODE; 1097 snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data); 1098 1099 /* codec sample rate select */ 1100 data = (fsref * 20) / params_rate(params); 1101 if (params_rate(params) < 64000) 1102 data /= 2; 1103 data /= 5; 1104 data -= 2; 1105 data |= (data << 4); 1106 snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data); 1107 1108 if (bypass_pll) 1109 return 0; 1110 1111 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 1112 * one wins the game. Try with d==0 first, next with d!=0. 1113 * Constraints for j are according to the datasheet. 1114 * The sysclk is divided by 1000 to prevent integer overflows. 1115 */ 1116 1117 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 1118 1119 for (r = 1; r <= 16; r++) 1120 for (p = 1; p <= 8; p++) { 1121 for (j = 4; j <= 55; j++) { 1122 /* This is actually 1000*((j+(d/10000))*r)/p 1123 * The term had to be converted to get 1124 * rid of the division by 10000; d = 0 here 1125 */ 1126 int tmp_clk = (1000 * j * r) / p; 1127 1128 /* Check whether this values get closer than 1129 * the best ones we had before 1130 */ 1131 if (abs(codec_clk - tmp_clk) < 1132 abs(codec_clk - last_clk)) { 1133 pll_j = j; pll_d = 0; 1134 pll_r = r; pll_p = p; 1135 last_clk = tmp_clk; 1136 } 1137 1138 /* Early exit for exact matches */ 1139 if (tmp_clk == codec_clk) 1140 goto found; 1141 } 1142 } 1143 1144 /* try with d != 0 */ 1145 for (p = 1; p <= 8; p++) { 1146 j = codec_clk * p / 1000; 1147 1148 if (j < 4 || j > 11) 1149 continue; 1150 1151 /* do not use codec_clk here since we'd loose precision */ 1152 d = ((2048 * p * fsref) - j * aic3x->sysclk) 1153 * 100 / (aic3x->sysclk/100); 1154 1155 clk = (10000 * j + d) / (10 * p); 1156 1157 /* check whether this values get closer than the best 1158 * ones we had before */ 1159 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 1160 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 1161 last_clk = clk; 1162 } 1163 1164 /* Early exit for exact matches */ 1165 if (clk == codec_clk) 1166 goto found; 1167 } 1168 1169 if (last_clk == 0) { 1170 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 1171 return -EINVAL; 1172 } 1173 1174 found: 1175 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); 1176 snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG, 1177 pll_r << PLLR_SHIFT); 1178 snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 1179 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, 1180 (pll_d >> 6) << PLLD_MSB_SHIFT); 1181 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, 1182 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 1183 1184 return 0; 1185 } 1186 1187 static int aic3x_prepare(struct snd_pcm_substream *substream, 1188 struct snd_soc_dai *dai) 1189 { 1190 struct snd_soc_component *component = dai->component; 1191 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1192 int delay = 0; 1193 int width = aic3x->slot_width; 1194 1195 if (!width) 1196 width = substream->runtime->sample_bits; 1197 1198 /* TDM slot selection only valid in DSP_A/_B mode */ 1199 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A) 1200 delay += (aic3x->tdm_delay*width + 1); 1201 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B) 1202 delay += aic3x->tdm_delay*width; 1203 1204 /* Configure data delay */ 1205 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay); 1206 1207 return 0; 1208 } 1209 1210 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 1211 { 1212 struct snd_soc_component *component = dai->component; 1213 u8 ldac_reg = snd_soc_component_read32(component, LDAC_VOL) & ~MUTE_ON; 1214 u8 rdac_reg = snd_soc_component_read32(component, RDAC_VOL) & ~MUTE_ON; 1215 1216 if (mute) { 1217 snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON); 1218 snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON); 1219 } else { 1220 snd_soc_component_write(component, LDAC_VOL, ldac_reg); 1221 snd_soc_component_write(component, RDAC_VOL, rdac_reg); 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1228 int clk_id, unsigned int freq, int dir) 1229 { 1230 struct snd_soc_component *component = codec_dai->component; 1231 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1232 1233 /* set clock on MCLK or GPIO2 or BCLK */ 1234 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, 1235 clk_id << PLLCLK_IN_SHIFT); 1236 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, 1237 clk_id << CLKDIV_IN_SHIFT); 1238 1239 aic3x->sysclk = freq; 1240 return 0; 1241 } 1242 1243 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1244 unsigned int fmt) 1245 { 1246 struct snd_soc_component *component = codec_dai->component; 1247 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1248 u8 iface_areg, iface_breg; 1249 1250 iface_areg = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1251 iface_breg = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1252 1253 /* set master/slave audio interface */ 1254 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1255 case SND_SOC_DAIFMT_CBM_CFM: 1256 aic3x->master = 1; 1257 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1258 break; 1259 case SND_SOC_DAIFMT_CBS_CFS: 1260 aic3x->master = 0; 1261 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1262 break; 1263 case SND_SOC_DAIFMT_CBM_CFS: 1264 aic3x->master = 1; 1265 iface_areg |= BIT_CLK_MASTER; 1266 iface_areg &= ~WORD_CLK_MASTER; 1267 break; 1268 case SND_SOC_DAIFMT_CBS_CFM: 1269 aic3x->master = 1; 1270 iface_areg |= WORD_CLK_MASTER; 1271 iface_areg &= ~BIT_CLK_MASTER; 1272 break; 1273 default: 1274 return -EINVAL; 1275 } 1276 1277 /* 1278 * match both interface format and signal polarities since they 1279 * are fixed 1280 */ 1281 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1282 SND_SOC_DAIFMT_INV_MASK)) { 1283 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1284 break; 1285 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1286 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1287 iface_breg |= (0x01 << 6); 1288 break; 1289 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1290 iface_breg |= (0x02 << 6); 1291 break; 1292 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1293 iface_breg |= (0x03 << 6); 1294 break; 1295 default: 1296 return -EINVAL; 1297 } 1298 1299 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1300 1301 /* set iface */ 1302 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg); 1303 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg); 1304 1305 return 0; 1306 } 1307 1308 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 1309 unsigned int tx_mask, unsigned int rx_mask, 1310 int slots, int slot_width) 1311 { 1312 struct snd_soc_component *component = codec_dai->component; 1313 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1314 unsigned int lsb; 1315 1316 if (tx_mask != rx_mask) { 1317 dev_err(component->dev, "tx and rx masks must be symmetric\n"); 1318 return -EINVAL; 1319 } 1320 1321 if (unlikely(!tx_mask)) { 1322 dev_err(component->dev, "tx and rx masks need to be non 0\n"); 1323 return -EINVAL; 1324 } 1325 1326 /* TDM based on DSP mode requires slots to be adjacent */ 1327 lsb = __ffs(tx_mask); 1328 if ((lsb + 1) != __fls(tx_mask)) { 1329 dev_err(component->dev, "Invalid mask, slots must be adjacent\n"); 1330 return -EINVAL; 1331 } 1332 1333 switch (slot_width) { 1334 case 16: 1335 case 20: 1336 case 24: 1337 case 32: 1338 break; 1339 default: 1340 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); 1341 return -EINVAL; 1342 } 1343 1344 1345 aic3x->tdm_delay = lsb; 1346 aic3x->slot_width = slot_width; 1347 1348 /* DOUT in high-impedance on inactive bit clocks */ 1349 snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA, 1350 DOUT_TRISTATE, DOUT_TRISTATE); 1351 1352 return 0; 1353 } 1354 1355 static int aic3x_regulator_event(struct notifier_block *nb, 1356 unsigned long event, void *data) 1357 { 1358 struct aic3x_disable_nb *disable_nb = 1359 container_of(nb, struct aic3x_disable_nb, nb); 1360 struct aic3x_priv *aic3x = disable_nb->aic3x; 1361 1362 if (event & REGULATOR_EVENT_DISABLE) { 1363 /* 1364 * Put codec to reset and require cache sync as at least one 1365 * of the supplies was disabled 1366 */ 1367 if (gpio_is_valid(aic3x->gpio_reset)) 1368 gpio_set_value(aic3x->gpio_reset, 0); 1369 regcache_mark_dirty(aic3x->regmap); 1370 } 1371 1372 return 0; 1373 } 1374 1375 static int aic3x_set_power(struct snd_soc_component *component, int power) 1376 { 1377 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1378 unsigned int pll_c, pll_d; 1379 int ret; 1380 1381 if (power) { 1382 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1383 aic3x->supplies); 1384 if (ret) 1385 goto out; 1386 aic3x->power = 1; 1387 1388 if (gpio_is_valid(aic3x->gpio_reset)) { 1389 udelay(1); 1390 gpio_set_value(aic3x->gpio_reset, 1); 1391 } 1392 1393 /* Sync reg_cache with the hardware */ 1394 regcache_cache_only(aic3x->regmap, false); 1395 regcache_sync(aic3x->regmap); 1396 1397 /* Rewrite paired PLL D registers in case cached sync skipped 1398 * writing one of them and thus caused other one also not 1399 * being written 1400 */ 1401 pll_c = snd_soc_component_read32(component, AIC3X_PLL_PROGC_REG); 1402 pll_d = snd_soc_component_read32(component, AIC3X_PLL_PROGD_REG); 1403 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def || 1404 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) { 1405 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c); 1406 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d); 1407 } 1408 1409 /* 1410 * Delay is needed to reduce pop-noise after syncing back the 1411 * registers 1412 */ 1413 mdelay(50); 1414 } else { 1415 /* 1416 * Do soft reset to this codec instance in order to clear 1417 * possible VDD leakage currents in case the supply regulators 1418 * remain on 1419 */ 1420 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET); 1421 regcache_mark_dirty(aic3x->regmap); 1422 aic3x->power = 0; 1423 /* HW writes are needless when bias is off */ 1424 regcache_cache_only(aic3x->regmap, true); 1425 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1426 aic3x->supplies); 1427 } 1428 out: 1429 return ret; 1430 } 1431 1432 static int aic3x_set_bias_level(struct snd_soc_component *component, 1433 enum snd_soc_bias_level level) 1434 { 1435 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1436 1437 switch (level) { 1438 case SND_SOC_BIAS_ON: 1439 break; 1440 case SND_SOC_BIAS_PREPARE: 1441 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY && 1442 aic3x->master) { 1443 /* enable pll */ 1444 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, 1445 PLL_ENABLE, PLL_ENABLE); 1446 } 1447 break; 1448 case SND_SOC_BIAS_STANDBY: 1449 if (!aic3x->power) 1450 aic3x_set_power(component, 1); 1451 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE && 1452 aic3x->master) { 1453 /* disable pll */ 1454 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, 1455 PLL_ENABLE, 0); 1456 } 1457 break; 1458 case SND_SOC_BIAS_OFF: 1459 if (aic3x->power) 1460 aic3x_set_power(component, 0); 1461 break; 1462 } 1463 1464 return 0; 1465 } 1466 1467 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1468 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1469 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1470 SNDRV_PCM_FMTBIT_S32_LE) 1471 1472 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1473 .hw_params = aic3x_hw_params, 1474 .prepare = aic3x_prepare, 1475 .digital_mute = aic3x_mute, 1476 .set_sysclk = aic3x_set_dai_sysclk, 1477 .set_fmt = aic3x_set_dai_fmt, 1478 .set_tdm_slot = aic3x_set_dai_tdm_slot, 1479 }; 1480 1481 static struct snd_soc_dai_driver aic3x_dai = { 1482 .name = "tlv320aic3x-hifi", 1483 .playback = { 1484 .stream_name = "Playback", 1485 .channels_min = 2, 1486 .channels_max = 2, 1487 .rates = AIC3X_RATES, 1488 .formats = AIC3X_FORMATS,}, 1489 .capture = { 1490 .stream_name = "Capture", 1491 .channels_min = 2, 1492 .channels_max = 2, 1493 .rates = AIC3X_RATES, 1494 .formats = AIC3X_FORMATS,}, 1495 .ops = &aic3x_dai_ops, 1496 .symmetric_rates = 1, 1497 }; 1498 1499 static void aic3x_mono_init(struct snd_soc_component *component) 1500 { 1501 /* DAC to Mono Line Out default volume and route to Output mixer */ 1502 snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1503 snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1504 1505 /* unmute all outputs */ 1506 snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1507 1508 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1509 snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1510 snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1511 1512 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1513 snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1514 snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1515 } 1516 1517 /* 1518 * initialise the AIC3X driver 1519 * register the mixer and dsp interfaces with the kernel 1520 */ 1521 static int aic3x_init(struct snd_soc_component *component) 1522 { 1523 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1524 1525 snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1526 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET); 1527 1528 /* DAC default volume and mute */ 1529 snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1530 snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1531 1532 /* DAC to HP default volume and route to Output mixer */ 1533 snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1534 snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1535 snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1536 snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1537 /* DAC to Line Out default volume and route to Output mixer */ 1538 snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1539 snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1540 1541 /* unmute all outputs */ 1542 snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE); 1543 snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE); 1544 snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE); 1545 snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE); 1546 snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE); 1547 snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE); 1548 1549 /* ADC default volume and unmute */ 1550 snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN); 1551 snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN); 1552 /* By default route Line1 to ADC PGA mixer */ 1553 snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0); 1554 snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0); 1555 1556 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1557 snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1558 snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1559 snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1560 snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1561 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1562 snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1563 snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1564 1565 /* On tlv320aic3104, these registers are reserved and must not be written */ 1566 if (aic3x->model != AIC3X_MODEL_3104) { 1567 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1568 snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1569 snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1570 snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1571 snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1572 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1573 snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1574 snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1575 } 1576 1577 switch (aic3x->model) { 1578 case AIC3X_MODEL_3X: 1579 case AIC3X_MODEL_33: 1580 aic3x_mono_init(component); 1581 break; 1582 case AIC3X_MODEL_3007: 1583 snd_soc_component_write(component, CLASSD_CTRL, 0); 1584 break; 1585 } 1586 1587 /* Output common-mode voltage = 1.5 V */ 1588 snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK, 1589 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT); 1590 1591 return 0; 1592 } 1593 1594 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1595 { 1596 struct aic3x_priv *a; 1597 1598 list_for_each_entry(a, &reset_list, list) { 1599 if (gpio_is_valid(aic3x->gpio_reset) && 1600 aic3x->gpio_reset == a->gpio_reset) 1601 return true; 1602 } 1603 1604 return false; 1605 } 1606 1607 static int aic3x_probe(struct snd_soc_component *component) 1608 { 1609 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1610 int ret, i; 1611 1612 INIT_LIST_HEAD(&aic3x->list); 1613 aic3x->component = component; 1614 1615 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1616 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1617 aic3x->disable_nb[i].aic3x = aic3x; 1618 ret = devm_regulator_register_notifier( 1619 aic3x->supplies[i].consumer, 1620 &aic3x->disable_nb[i].nb); 1621 if (ret) { 1622 dev_err(component->dev, 1623 "Failed to request regulator notifier: %d\n", 1624 ret); 1625 return ret; 1626 } 1627 } 1628 1629 regcache_mark_dirty(aic3x->regmap); 1630 aic3x_init(component); 1631 1632 if (aic3x->setup) { 1633 if (aic3x->model != AIC3X_MODEL_3104) { 1634 /* setup GPIO functions */ 1635 snd_soc_component_write(component, AIC3X_GPIO1_REG, 1636 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1637 snd_soc_component_write(component, AIC3X_GPIO2_REG, 1638 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1639 } else { 1640 dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n"); 1641 } 1642 } 1643 1644 switch (aic3x->model) { 1645 case AIC3X_MODEL_3X: 1646 case AIC3X_MODEL_33: 1647 snd_soc_add_component_controls(component, aic3x_extra_snd_controls, 1648 ARRAY_SIZE(aic3x_extra_snd_controls)); 1649 snd_soc_add_component_controls(component, aic3x_mono_controls, 1650 ARRAY_SIZE(aic3x_mono_controls)); 1651 break; 1652 case AIC3X_MODEL_3007: 1653 snd_soc_add_component_controls(component, aic3x_extra_snd_controls, 1654 ARRAY_SIZE(aic3x_extra_snd_controls)); 1655 snd_soc_add_component_controls(component, 1656 &aic3x_classd_amp_gain_ctrl, 1); 1657 break; 1658 case AIC3X_MODEL_3104: 1659 break; 1660 } 1661 1662 /* set mic bias voltage */ 1663 switch (aic3x->micbias_vg) { 1664 case AIC3X_MICBIAS_2_0V: 1665 case AIC3X_MICBIAS_2_5V: 1666 case AIC3X_MICBIAS_AVDDV: 1667 snd_soc_component_update_bits(component, MICBIAS_CTRL, 1668 MICBIAS_LEVEL_MASK, 1669 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); 1670 break; 1671 case AIC3X_MICBIAS_OFF: 1672 /* 1673 * noting to do. target won't enter here. This is just to avoid 1674 * compile time warning "warning: enumeration value 1675 * 'AIC3X_MICBIAS_OFF' not handled in switch" 1676 */ 1677 break; 1678 } 1679 1680 aic3x_add_widgets(component); 1681 1682 return 0; 1683 } 1684 1685 static const struct snd_soc_component_driver soc_component_dev_aic3x = { 1686 .set_bias_level = aic3x_set_bias_level, 1687 .probe = aic3x_probe, 1688 .controls = aic3x_snd_controls, 1689 .num_controls = ARRAY_SIZE(aic3x_snd_controls), 1690 .dapm_widgets = aic3x_dapm_widgets, 1691 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets), 1692 .dapm_routes = intercon, 1693 .num_dapm_routes = ARRAY_SIZE(intercon), 1694 .use_pmdown_time = 1, 1695 .endianness = 1, 1696 .non_legacy_dai_naming = 1, 1697 }; 1698 1699 static void aic3x_configure_ocmv(struct i2c_client *client) 1700 { 1701 struct device_node *np = client->dev.of_node; 1702 struct aic3x_priv *aic3x = i2c_get_clientdata(client); 1703 u32 value; 1704 int dvdd, avdd; 1705 1706 if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) { 1707 /* OCMV setting is forced by DT */ 1708 if (value <= 3) { 1709 aic3x->ocmv = value; 1710 return; 1711 } 1712 } 1713 1714 dvdd = regulator_get_voltage(aic3x->supplies[1].consumer); 1715 avdd = regulator_get_voltage(aic3x->supplies[2].consumer); 1716 1717 if (avdd > 3600000 || dvdd > 1950000) { 1718 dev_warn(&client->dev, 1719 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n", 1720 avdd, dvdd); 1721 } else if (avdd == 3600000 && dvdd == 1950000) { 1722 aic3x->ocmv = HPOUT_SC_OCMV_1_8V; 1723 } else if (avdd > 3300000 && dvdd > 1800000) { 1724 aic3x->ocmv = HPOUT_SC_OCMV_1_65V; 1725 } else if (avdd > 3000000 && dvdd > 1650000) { 1726 aic3x->ocmv = HPOUT_SC_OCMV_1_5V; 1727 } else if (avdd >= 2700000 && dvdd >= 1525000) { 1728 aic3x->ocmv = HPOUT_SC_OCMV_1_35V; 1729 } else { 1730 dev_warn(&client->dev, 1731 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n", 1732 avdd, dvdd); 1733 } 1734 } 1735 1736 /* 1737 * AIC3X 2 wire address can be up to 4 devices with device addresses 1738 * 0x18, 0x19, 0x1A, 0x1B 1739 */ 1740 1741 static const struct i2c_device_id aic3x_i2c_id[] = { 1742 { "tlv320aic3x", AIC3X_MODEL_3X }, 1743 { "tlv320aic33", AIC3X_MODEL_33 }, 1744 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1745 { "tlv320aic3106", AIC3X_MODEL_3X }, 1746 { "tlv320aic3104", AIC3X_MODEL_3104 }, 1747 { } 1748 }; 1749 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1750 1751 static const struct reg_sequence aic3007_class_d[] = { 1752 /* Class-D speaker driver init; datasheet p. 46 */ 1753 { AIC3X_PAGE_SELECT, 0x0D }, 1754 { 0xD, 0x0D }, 1755 { 0x8, 0x5C }, 1756 { 0x8, 0x5D }, 1757 { 0x8, 0x5C }, 1758 { AIC3X_PAGE_SELECT, 0x00 }, 1759 }; 1760 1761 /* 1762 * If the i2c layer weren't so broken, we could pass this kind of data 1763 * around 1764 */ 1765 static int aic3x_i2c_probe(struct i2c_client *i2c, 1766 const struct i2c_device_id *id) 1767 { 1768 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1769 struct aic3x_priv *aic3x; 1770 struct aic3x_setup_data *ai3x_setup; 1771 struct device_node *np = i2c->dev.of_node; 1772 int ret, i; 1773 u32 value; 1774 1775 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1776 if (!aic3x) 1777 return -ENOMEM; 1778 1779 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap); 1780 if (IS_ERR(aic3x->regmap)) { 1781 ret = PTR_ERR(aic3x->regmap); 1782 return ret; 1783 } 1784 1785 regcache_cache_only(aic3x->regmap, true); 1786 1787 i2c_set_clientdata(i2c, aic3x); 1788 if (pdata) { 1789 aic3x->gpio_reset = pdata->gpio_reset; 1790 aic3x->setup = pdata->setup; 1791 aic3x->micbias_vg = pdata->micbias_vg; 1792 } else if (np) { 1793 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), 1794 GFP_KERNEL); 1795 if (!ai3x_setup) 1796 return -ENOMEM; 1797 1798 ret = of_get_named_gpio(np, "reset-gpios", 0); 1799 if (ret >= 0) { 1800 aic3x->gpio_reset = ret; 1801 } else { 1802 ret = of_get_named_gpio(np, "gpio-reset", 0); 1803 if (ret > 0) { 1804 dev_warn(&i2c->dev, "Using deprecated property \"gpio-reset\", please update your DT"); 1805 aic3x->gpio_reset = ret; 1806 } else { 1807 aic3x->gpio_reset = -1; 1808 } 1809 } 1810 1811 if (of_property_read_u32_array(np, "ai3x-gpio-func", 1812 ai3x_setup->gpio_func, 2) >= 0) { 1813 aic3x->setup = ai3x_setup; 1814 } 1815 1816 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { 1817 switch (value) { 1818 case 1 : 1819 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; 1820 break; 1821 case 2 : 1822 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; 1823 break; 1824 case 3 : 1825 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; 1826 break; 1827 default : 1828 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1829 dev_err(&i2c->dev, "Unsuitable MicBias voltage " 1830 "found in DT\n"); 1831 } 1832 } else { 1833 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1834 } 1835 1836 } else { 1837 aic3x->gpio_reset = -1; 1838 } 1839 1840 aic3x->model = id->driver_data; 1841 1842 if (gpio_is_valid(aic3x->gpio_reset) && 1843 !aic3x_is_shared_reset(aic3x)) { 1844 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1845 if (ret != 0) 1846 goto err; 1847 gpio_direction_output(aic3x->gpio_reset, 0); 1848 } 1849 1850 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1851 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1852 1853 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies), 1854 aic3x->supplies); 1855 if (ret != 0) { 1856 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 1857 goto err_gpio; 1858 } 1859 1860 aic3x_configure_ocmv(i2c); 1861 1862 if (aic3x->model == AIC3X_MODEL_3007) { 1863 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d, 1864 ARRAY_SIZE(aic3007_class_d)); 1865 if (ret != 0) 1866 dev_err(&i2c->dev, "Failed to init class D: %d\n", 1867 ret); 1868 } 1869 1870 ret = devm_snd_soc_register_component(&i2c->dev, 1871 &soc_component_dev_aic3x, &aic3x_dai, 1); 1872 1873 if (ret != 0) 1874 goto err_gpio; 1875 1876 list_add(&aic3x->list, &reset_list); 1877 1878 return 0; 1879 1880 err_gpio: 1881 if (gpio_is_valid(aic3x->gpio_reset) && 1882 !aic3x_is_shared_reset(aic3x)) 1883 gpio_free(aic3x->gpio_reset); 1884 err: 1885 return ret; 1886 } 1887 1888 static int aic3x_i2c_remove(struct i2c_client *client) 1889 { 1890 struct aic3x_priv *aic3x = i2c_get_clientdata(client); 1891 1892 if (gpio_is_valid(aic3x->gpio_reset) && 1893 !aic3x_is_shared_reset(aic3x)) { 1894 gpio_set_value(aic3x->gpio_reset, 0); 1895 gpio_free(aic3x->gpio_reset); 1896 } 1897 return 0; 1898 } 1899 1900 #if defined(CONFIG_OF) 1901 static const struct of_device_id tlv320aic3x_of_match[] = { 1902 { .compatible = "ti,tlv320aic3x", }, 1903 { .compatible = "ti,tlv320aic33" }, 1904 { .compatible = "ti,tlv320aic3007" }, 1905 { .compatible = "ti,tlv320aic3106" }, 1906 { .compatible = "ti,tlv320aic3104" }, 1907 {}, 1908 }; 1909 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match); 1910 #endif 1911 1912 /* machine i2c codec control layer */ 1913 static struct i2c_driver aic3x_i2c_driver = { 1914 .driver = { 1915 .name = "tlv320aic3x-codec", 1916 .of_match_table = of_match_ptr(tlv320aic3x_of_match), 1917 }, 1918 .probe = aic3x_i2c_probe, 1919 .remove = aic3x_i2c_remove, 1920 .id_table = aic3x_i2c_id, 1921 }; 1922 1923 module_i2c_driver(aic3x_i2c_driver); 1924 1925 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1926 MODULE_AUTHOR("Vladimir Barinov"); 1927 MODULE_LICENSE("GPL"); 1928