1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * linux/sound/soc/codecs/tlv320aic32x4.c 4 * 5 * Copyright 2011 Vista Silicon S.L. 6 * 7 * Author: Javier Martin <javier.martin@vista-silicon.com> 8 * 9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/gpio.h> 18 #include <linux/of_gpio.h> 19 #include <linux/cdev.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/of_clk.h> 23 #include <linux/regulator/consumer.h> 24 25 #include <sound/tlv320aic32x4.h> 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 34 #include "tlv320aic32x4.h" 35 36 struct aic32x4_priv { 37 struct regmap *regmap; 38 u32 power_cfg; 39 u32 micpga_routing; 40 bool swapdacs; 41 int rstn_gpio; 42 const char *mclk_name; 43 44 struct regulator *supply_ldo; 45 struct regulator *supply_iov; 46 struct regulator *supply_dv; 47 struct regulator *supply_av; 48 49 struct aic32x4_setup_data *setup; 50 struct device *dev; 51 }; 52 53 static int mic_bias_event(struct snd_soc_dapm_widget *w, 54 struct snd_kcontrol *kcontrol, int event) 55 { 56 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 57 58 switch (event) { 59 case SND_SOC_DAPM_POST_PMU: 60 /* Change Mic Bias Registor */ 61 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 62 AIC32x4_MICBIAS_MASK, 63 AIC32X4_MICBIAS_LDOIN | 64 AIC32X4_MICBIAS_2075V); 65 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 66 break; 67 case SND_SOC_DAPM_PRE_PMD: 68 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 69 AIC32x4_MICBIAS_MASK, 0); 70 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 71 __func__); 72 break; 73 } 74 75 return 0; 76 } 77 78 79 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 80 struct snd_ctl_elem_value *ucontrol) 81 { 82 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 83 u8 val; 84 85 val = snd_soc_component_read32(component, AIC32X4_DINCTL); 86 87 ucontrol->value.integer.value[0] = (val & 0x01); 88 89 return 0; 90 }; 91 92 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 93 struct snd_ctl_elem_value *ucontrol) 94 { 95 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 96 u8 val; 97 u8 gpio_check; 98 99 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 100 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 101 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 102 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 103 __func__); 104 return -EINVAL; 105 } 106 107 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 108 return 0; 109 110 if (ucontrol->value.integer.value[0]) 111 val |= ucontrol->value.integer.value[0]; 112 else 113 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 114 115 snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 116 117 return 0; 118 }; 119 120 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 121 struct snd_ctl_elem_value *ucontrol) 122 { 123 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 124 u8 val; 125 126 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 127 128 ucontrol->value.integer.value[0] = (val & 0x01); 129 130 return 0; 131 }; 132 133 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 134 struct snd_ctl_elem_value *ucontrol) 135 { 136 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 137 u8 val; 138 u8 gpio_check; 139 140 val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 141 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 142 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 143 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 144 __func__); 145 return -EINVAL; 146 } 147 148 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 149 return 0; 150 151 if (ucontrol->value.integer.value[0]) 152 val |= ucontrol->value.integer.value[0]; 153 else 154 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 155 156 snd_soc_component_write(component, AIC32X4_MISOCTL, val); 157 158 return 0; 159 }; 160 161 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 162 struct snd_ctl_elem_value *ucontrol) 163 { 164 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 165 u8 val; 166 167 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 168 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 169 170 return 0; 171 }; 172 173 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 174 struct snd_ctl_elem_value *ucontrol) 175 { 176 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 177 u8 val; 178 u8 gpio_check; 179 180 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 181 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 182 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 183 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 184 __func__); 185 return -EINVAL; 186 } 187 188 if (ucontrol->value.integer.value[0] == (val & 0x1)) 189 return 0; 190 191 if (ucontrol->value.integer.value[0]) 192 val |= ucontrol->value.integer.value[0]; 193 else 194 val &= 0xfe; 195 196 snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 197 198 return 0; 199 }; 200 201 static const struct snd_kcontrol_new aic32x4_mfp1[] = { 202 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 203 }; 204 205 static const struct snd_kcontrol_new aic32x4_mfp2[] = { 206 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 207 }; 208 209 static const struct snd_kcontrol_new aic32x4_mfp3[] = { 210 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 211 }; 212 213 static const struct snd_kcontrol_new aic32x4_mfp4[] = { 214 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 215 }; 216 217 static const struct snd_kcontrol_new aic32x4_mfp5[] = { 218 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 219 aic32x4_set_mfp5_gpio), 220 }; 221 222 /* 0dB min, 0.5dB steps */ 223 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 224 /* -63.5dB min, 0.5dB steps */ 225 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 226 /* -6dB min, 1dB steps */ 227 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 228 /* -12dB min, 0.5dB steps */ 229 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 230 231 static const char * const lo_cm_text[] = { 232 "Full Chip", "1.65V", 233 }; 234 235 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text); 236 237 static const char * const ptm_text[] = { 238 "P3", "P2", "P1", 239 }; 240 241 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text); 242 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text); 243 244 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 245 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 246 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 247 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum), 248 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum), 249 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 250 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 251 tlv_driver_gain), 252 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 253 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 254 tlv_driver_gain), 255 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 256 AIC32X4_HPRGAIN, 6, 0x01, 1), 257 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 258 AIC32X4_LORGAIN, 6, 0x01, 1), 259 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum), 260 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 261 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 262 263 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 264 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 265 266 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 267 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 268 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 269 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 270 271 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 272 273 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 274 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 275 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 276 4, 0x07, 0), 277 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 278 0, 0x03, 0), 279 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 280 6, 0x03, 0), 281 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 282 1, 0x1F, 0), 283 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 284 0, 0x7F, 0), 285 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 286 3, 0x1F, 0), 287 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 288 3, 0x1F, 0), 289 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 290 0, 0x1F, 0), 291 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 292 0, 0x0F, 0), 293 }; 294 295 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 296 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 297 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 298 }; 299 300 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 301 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 302 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 303 }; 304 305 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 306 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 307 }; 308 309 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 310 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 311 }; 312 313 static const char * const resistor_text[] = { 314 "Off", "10 kOhm", "20 kOhm", "40 kOhm", 315 }; 316 317 /* Left mixer pins */ 318 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 319 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 320 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 321 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 322 323 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 324 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 325 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 326 327 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 328 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 329 }; 330 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 331 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 332 }; 333 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 334 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 335 }; 336 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 337 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 338 }; 339 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 340 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 341 }; 342 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 343 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 344 }; 345 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 346 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 347 }; 348 349 /* Right mixer pins */ 350 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 351 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 352 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 353 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 354 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 355 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 356 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 357 358 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 359 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 360 }; 361 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 362 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 363 }; 364 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 365 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 366 }; 367 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 368 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 369 }; 370 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 371 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 372 }; 373 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 374 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 375 }; 376 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 377 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 378 }; 379 380 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 381 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 382 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 383 &hpl_output_mixer_controls[0], 384 ARRAY_SIZE(hpl_output_mixer_controls)), 385 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 386 387 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 388 &lol_output_mixer_controls[0], 389 ARRAY_SIZE(lol_output_mixer_controls)), 390 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 391 392 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 393 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 394 &hpr_output_mixer_controls[0], 395 ARRAY_SIZE(hpr_output_mixer_controls)), 396 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 397 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 398 &lor_output_mixer_controls[0], 399 ARRAY_SIZE(lor_output_mixer_controls)), 400 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 401 402 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 403 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 404 in1r_to_rmixer_controls), 405 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 406 in2r_to_rmixer_controls), 407 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 408 in3r_to_rmixer_controls), 409 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 410 in2l_to_rmixer_controls), 411 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 412 cmr_to_rmixer_controls), 413 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 414 in1l_to_rmixer_controls), 415 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 416 in3l_to_rmixer_controls), 417 418 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 419 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 420 in1l_to_lmixer_controls), 421 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 422 in2l_to_lmixer_controls), 423 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 424 in3l_to_lmixer_controls), 425 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 426 in1r_to_lmixer_controls), 427 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 428 cml_to_lmixer_controls), 429 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 430 in2r_to_lmixer_controls), 431 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 432 in3r_to_lmixer_controls), 433 434 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 435 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 436 437 438 SND_SOC_DAPM_OUTPUT("HPL"), 439 SND_SOC_DAPM_OUTPUT("HPR"), 440 SND_SOC_DAPM_OUTPUT("LOL"), 441 SND_SOC_DAPM_OUTPUT("LOR"), 442 SND_SOC_DAPM_INPUT("IN1_L"), 443 SND_SOC_DAPM_INPUT("IN1_R"), 444 SND_SOC_DAPM_INPUT("IN2_L"), 445 SND_SOC_DAPM_INPUT("IN2_R"), 446 SND_SOC_DAPM_INPUT("IN3_L"), 447 SND_SOC_DAPM_INPUT("IN3_R"), 448 SND_SOC_DAPM_INPUT("CM_L"), 449 SND_SOC_DAPM_INPUT("CM_R"), 450 }; 451 452 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 453 /* Left Output */ 454 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 455 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 456 457 {"HPL Power", NULL, "HPL Output Mixer"}, 458 {"HPL", NULL, "HPL Power"}, 459 460 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 461 462 {"LOL Power", NULL, "LOL Output Mixer"}, 463 {"LOL", NULL, "LOL Power"}, 464 465 /* Right Output */ 466 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 467 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 468 469 {"HPR Power", NULL, "HPR Output Mixer"}, 470 {"HPR", NULL, "HPR Power"}, 471 472 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 473 474 {"LOR Power", NULL, "LOR Output Mixer"}, 475 {"LOR", NULL, "LOR Power"}, 476 477 /* Right Input */ 478 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 479 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 480 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 481 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 482 483 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 484 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 485 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 486 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 487 488 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 489 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 490 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 491 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 492 493 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 494 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 495 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 496 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 497 498 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 499 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 500 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 501 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 502 503 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 504 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 505 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 506 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 507 508 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 509 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 510 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 511 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 512 513 /* Left Input */ 514 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 515 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 516 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 517 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 518 519 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 520 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 521 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 522 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 523 524 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 525 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 526 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 527 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 528 529 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 530 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 531 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 532 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 533 534 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 535 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 536 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 537 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 538 539 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 540 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 541 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 542 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 543 544 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 545 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 546 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 547 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 548 }; 549 550 static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 551 { 552 .selector_reg = 0, 553 .selector_mask = 0xff, 554 .window_start = 0, 555 .window_len = 128, 556 .range_min = 0, 557 .range_max = AIC32X4_RMICPGAVOL, 558 }, 559 }; 560 561 const struct regmap_config aic32x4_regmap_config = { 562 .max_register = AIC32X4_RMICPGAVOL, 563 .ranges = aic32x4_regmap_pages, 564 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 565 }; 566 EXPORT_SYMBOL(aic32x4_regmap_config); 567 568 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 569 int clk_id, unsigned int freq, int dir) 570 { 571 struct snd_soc_component *component = codec_dai->component; 572 struct clk *mclk; 573 struct clk *pll; 574 575 pll = devm_clk_get(component->dev, "pll"); 576 mclk = clk_get_parent(pll); 577 578 return clk_set_rate(mclk, freq); 579 } 580 581 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 582 { 583 struct snd_soc_component *component = codec_dai->component; 584 u8 iface_reg_1 = 0; 585 u8 iface_reg_2 = 0; 586 u8 iface_reg_3 = 0; 587 588 /* set master/slave audio interface */ 589 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 590 case SND_SOC_DAIFMT_CBM_CFM: 591 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 592 break; 593 case SND_SOC_DAIFMT_CBS_CFS: 594 break; 595 default: 596 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 597 return -EINVAL; 598 } 599 600 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 601 case SND_SOC_DAIFMT_I2S: 602 break; 603 case SND_SOC_DAIFMT_DSP_A: 604 iface_reg_1 |= (AIC32X4_DSP_MODE << 605 AIC32X4_IFACE1_DATATYPE_SHIFT); 606 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 607 iface_reg_2 = 0x01; /* add offset 1 */ 608 break; 609 case SND_SOC_DAIFMT_DSP_B: 610 iface_reg_1 |= (AIC32X4_DSP_MODE << 611 AIC32X4_IFACE1_DATATYPE_SHIFT); 612 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 613 break; 614 case SND_SOC_DAIFMT_RIGHT_J: 615 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 616 AIC32X4_IFACE1_DATATYPE_SHIFT); 617 break; 618 case SND_SOC_DAIFMT_LEFT_J: 619 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 620 AIC32X4_IFACE1_DATATYPE_SHIFT); 621 break; 622 default: 623 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 624 return -EINVAL; 625 } 626 627 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 628 AIC32X4_IFACE1_DATATYPE_MASK | 629 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 630 snd_soc_component_update_bits(component, AIC32X4_IFACE2, 631 AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 632 snd_soc_component_update_bits(component, AIC32X4_IFACE3, 633 AIC32X4_BCLKINV_MASK, iface_reg_3); 634 635 return 0; 636 } 637 638 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) 639 { 640 return snd_soc_component_write(component, AIC32X4_AOSR, aosr); 641 } 642 643 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) 644 { 645 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); 646 snd_soc_component_write(component, AIC32X4_DOSRLSB, 647 (dosr & 0xff)); 648 649 return 0; 650 } 651 652 static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 653 u8 r_block, u8 p_block) 654 { 655 if (r_block > 18 || p_block > 25) 656 return -EINVAL; 657 658 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 659 snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 660 661 return 0; 662 } 663 664 static int aic32x4_setup_clocks(struct snd_soc_component *component, 665 unsigned int sample_rate) 666 { 667 u8 aosr; 668 u16 dosr; 669 u8 adc_resource_class, dac_resource_class; 670 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; 671 u8 dosr_increment; 672 u16 max_dosr, min_dosr; 673 unsigned long adc_clock_rate, dac_clock_rate; 674 int ret; 675 676 struct clk_bulk_data clocks[] = { 677 { .id = "pll" }, 678 { .id = "nadc" }, 679 { .id = "madc" }, 680 { .id = "ndac" }, 681 { .id = "mdac" }, 682 { .id = "bdiv" }, 683 }; 684 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 685 if (ret) 686 return ret; 687 688 if (sample_rate <= 48000) { 689 aosr = 128; 690 adc_resource_class = 6; 691 dac_resource_class = 8; 692 dosr_increment = 8; 693 aic32x4_set_processing_blocks(component, 1, 1); 694 } else if (sample_rate <= 96000) { 695 aosr = 64; 696 adc_resource_class = 6; 697 dac_resource_class = 8; 698 dosr_increment = 4; 699 aic32x4_set_processing_blocks(component, 1, 9); 700 } else if (sample_rate == 192000) { 701 aosr = 32; 702 adc_resource_class = 3; 703 dac_resource_class = 4; 704 dosr_increment = 2; 705 aic32x4_set_processing_blocks(component, 13, 19); 706 } else { 707 dev_err(component->dev, "Sampling rate not supported\n"); 708 return -EINVAL; 709 } 710 711 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); 712 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * 713 dosr_increment; 714 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * 715 dosr_increment; 716 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); 717 718 for (nadc = max_nadc; nadc > 0; --nadc) { 719 adc_clock_rate = nadc * madc * aosr * sample_rate; 720 for (dosr = max_dosr; dosr >= min_dosr; 721 dosr -= dosr_increment) { 722 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); 723 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / 724 (min_mdac * dosr * sample_rate); 725 for (mdac = min_mdac; mdac <= 128; ++mdac) { 726 for (ndac = max_ndac; ndac > 0; --ndac) { 727 dac_clock_rate = ndac * mdac * dosr * 728 sample_rate; 729 if (dac_clock_rate == adc_clock_rate) { 730 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 731 continue; 732 733 clk_set_rate(clocks[0].clk, 734 dac_clock_rate); 735 736 clk_set_rate(clocks[1].clk, 737 sample_rate * aosr * 738 madc); 739 clk_set_rate(clocks[2].clk, 740 sample_rate * aosr); 741 aic32x4_set_aosr(component, 742 aosr); 743 744 clk_set_rate(clocks[3].clk, 745 sample_rate * dosr * 746 mdac); 747 clk_set_rate(clocks[4].clk, 748 sample_rate * dosr); 749 aic32x4_set_dosr(component, 750 dosr); 751 752 clk_set_rate(clocks[5].clk, 753 sample_rate * 32); 754 return 0; 755 } 756 } 757 } 758 } 759 } 760 761 dev_err(component->dev, 762 "Could not set clocks to support sample rate.\n"); 763 return -EINVAL; 764 } 765 766 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 767 struct snd_pcm_hw_params *params, 768 struct snd_soc_dai *dai) 769 { 770 struct snd_soc_component *component = dai->component; 771 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 772 u8 iface1_reg = 0; 773 u8 dacsetup_reg = 0; 774 775 aic32x4_setup_clocks(component, params_rate(params)); 776 777 switch (params_width(params)) { 778 case 16: 779 iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 780 AIC32X4_IFACE1_DATALEN_SHIFT); 781 break; 782 case 20: 783 iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 784 AIC32X4_IFACE1_DATALEN_SHIFT); 785 break; 786 case 24: 787 iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 788 AIC32X4_IFACE1_DATALEN_SHIFT); 789 break; 790 case 32: 791 iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 792 AIC32X4_IFACE1_DATALEN_SHIFT); 793 break; 794 } 795 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 796 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 797 798 if (params_channels(params) == 1) { 799 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 800 } else { 801 if (aic32x4->swapdacs) 802 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 803 else 804 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 805 } 806 snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 807 AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 808 809 return 0; 810 } 811 812 static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 813 { 814 struct snd_soc_component *component = dai->component; 815 816 snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 817 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 818 819 return 0; 820 } 821 822 static int aic32x4_set_bias_level(struct snd_soc_component *component, 823 enum snd_soc_bias_level level) 824 { 825 int ret; 826 827 struct clk_bulk_data clocks[] = { 828 { .id = "madc" }, 829 { .id = "mdac" }, 830 { .id = "bdiv" }, 831 }; 832 833 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 834 if (ret) 835 return ret; 836 837 switch (level) { 838 case SND_SOC_BIAS_ON: 839 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); 840 if (ret) { 841 dev_err(component->dev, "Failed to enable clocks\n"); 842 return ret; 843 } 844 break; 845 case SND_SOC_BIAS_PREPARE: 846 break; 847 case SND_SOC_BIAS_STANDBY: 848 /* Initial cold start */ 849 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 850 break; 851 852 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); 853 break; 854 case SND_SOC_BIAS_OFF: 855 break; 856 } 857 return 0; 858 } 859 860 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 861 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 862 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 863 864 static const struct snd_soc_dai_ops aic32x4_ops = { 865 .hw_params = aic32x4_hw_params, 866 .digital_mute = aic32x4_mute, 867 .set_fmt = aic32x4_set_dai_fmt, 868 .set_sysclk = aic32x4_set_dai_sysclk, 869 }; 870 871 static struct snd_soc_dai_driver aic32x4_dai = { 872 .name = "tlv320aic32x4-hifi", 873 .playback = { 874 .stream_name = "Playback", 875 .channels_min = 1, 876 .channels_max = 2, 877 .rates = AIC32X4_RATES, 878 .formats = AIC32X4_FORMATS,}, 879 .capture = { 880 .stream_name = "Capture", 881 .channels_min = 1, 882 .channels_max = 2, 883 .rates = AIC32X4_RATES, 884 .formats = AIC32X4_FORMATS,}, 885 .ops = &aic32x4_ops, 886 .symmetric_rates = 1, 887 }; 888 889 static void aic32x4_setup_gpios(struct snd_soc_component *component) 890 { 891 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 892 893 /* setup GPIO functions */ 894 /* MFP1 */ 895 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 896 snd_soc_component_write(component, AIC32X4_DINCTL, 897 aic32x4->setup->gpio_func[0]); 898 snd_soc_add_component_controls(component, aic32x4_mfp1, 899 ARRAY_SIZE(aic32x4_mfp1)); 900 } 901 902 /* MFP2 */ 903 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 904 snd_soc_component_write(component, AIC32X4_DOUTCTL, 905 aic32x4->setup->gpio_func[1]); 906 snd_soc_add_component_controls(component, aic32x4_mfp2, 907 ARRAY_SIZE(aic32x4_mfp2)); 908 } 909 910 /* MFP3 */ 911 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 912 snd_soc_component_write(component, AIC32X4_SCLKCTL, 913 aic32x4->setup->gpio_func[2]); 914 snd_soc_add_component_controls(component, aic32x4_mfp3, 915 ARRAY_SIZE(aic32x4_mfp3)); 916 } 917 918 /* MFP4 */ 919 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 920 snd_soc_component_write(component, AIC32X4_MISOCTL, 921 aic32x4->setup->gpio_func[3]); 922 snd_soc_add_component_controls(component, aic32x4_mfp4, 923 ARRAY_SIZE(aic32x4_mfp4)); 924 } 925 926 /* MFP5 */ 927 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 928 snd_soc_component_write(component, AIC32X4_GPIOCTL, 929 aic32x4->setup->gpio_func[4]); 930 snd_soc_add_component_controls(component, aic32x4_mfp5, 931 ARRAY_SIZE(aic32x4_mfp5)); 932 } 933 } 934 935 static int aic32x4_component_probe(struct snd_soc_component *component) 936 { 937 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 938 u32 tmp_reg; 939 int ret; 940 941 struct clk_bulk_data clocks[] = { 942 { .id = "codec_clkin" }, 943 { .id = "pll" }, 944 { .id = "bdiv" }, 945 { .id = "mdac" }, 946 }; 947 948 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 949 if (ret) 950 return ret; 951 952 if (gpio_is_valid(aic32x4->rstn_gpio)) { 953 ndelay(10); 954 gpio_set_value(aic32x4->rstn_gpio, 1); 955 mdelay(1); 956 } 957 958 snd_soc_component_write(component, AIC32X4_RESET, 0x01); 959 960 if (aic32x4->setup) 961 aic32x4_setup_gpios(component); 962 963 clk_set_parent(clocks[0].clk, clocks[1].clk); 964 clk_set_parent(clocks[2].clk, clocks[3].clk); 965 966 /* Power platform configuration */ 967 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 968 snd_soc_component_write(component, AIC32X4_MICBIAS, 969 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 970 } 971 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 972 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 973 974 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 975 AIC32X4_LDOCTLEN : 0; 976 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 977 978 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 979 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 980 tmp_reg |= AIC32X4_LDOIN_18_36; 981 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 982 tmp_reg |= AIC32X4_LDOIN2HP; 983 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 984 985 /* Mic PGA routing */ 986 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 987 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 988 AIC32X4_LMICPGANIN_IN2R_10K); 989 else 990 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 991 AIC32X4_LMICPGANIN_CM1L_10K); 992 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 993 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 994 AIC32X4_RMICPGANIN_IN1L_10K); 995 else 996 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 997 AIC32X4_RMICPGANIN_CM1R_10K); 998 999 /* 1000 * Workaround: for an unknown reason, the ADC needs to be powered up 1001 * and down for the first capture to work properly. It seems related to 1002 * a HW BUG or some kind of behavior not documented in the datasheet. 1003 */ 1004 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 1005 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1006 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1007 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1008 1009 return 0; 1010 } 1011 1012 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1013 .probe = aic32x4_component_probe, 1014 .set_bias_level = aic32x4_set_bias_level, 1015 .controls = aic32x4_snd_controls, 1016 .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1017 .dapm_widgets = aic32x4_dapm_widgets, 1018 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1019 .dapm_routes = aic32x4_dapm_routes, 1020 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1021 .suspend_bias_off = 1, 1022 .idle_bias_on = 1, 1023 .use_pmdown_time = 1, 1024 .endianness = 1, 1025 .non_legacy_dai_naming = 1, 1026 }; 1027 1028 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 1029 struct device_node *np) 1030 { 1031 struct aic32x4_setup_data *aic32x4_setup; 1032 int ret; 1033 1034 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1035 GFP_KERNEL); 1036 if (!aic32x4_setup) 1037 return -ENOMEM; 1038 1039 ret = of_property_match_string(np, "clock-names", "mclk"); 1040 if (ret < 0) 1041 return -EINVAL; 1042 aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1043 1044 aic32x4->swapdacs = false; 1045 aic32x4->micpga_routing = 0; 1046 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 1047 1048 if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1049 aic32x4_setup->gpio_func, 5) >= 0) 1050 aic32x4->setup = aic32x4_setup; 1051 return 0; 1052 } 1053 1054 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1055 { 1056 regulator_disable(aic32x4->supply_iov); 1057 1058 if (!IS_ERR(aic32x4->supply_ldo)) 1059 regulator_disable(aic32x4->supply_ldo); 1060 1061 if (!IS_ERR(aic32x4->supply_dv)) 1062 regulator_disable(aic32x4->supply_dv); 1063 1064 if (!IS_ERR(aic32x4->supply_av)) 1065 regulator_disable(aic32x4->supply_av); 1066 } 1067 1068 static int aic32x4_setup_regulators(struct device *dev, 1069 struct aic32x4_priv *aic32x4) 1070 { 1071 int ret = 0; 1072 1073 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1074 aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1075 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1076 aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1077 1078 /* Check if the regulator requirements are fulfilled */ 1079 1080 if (IS_ERR(aic32x4->supply_iov)) { 1081 dev_err(dev, "Missing supply 'iov'\n"); 1082 return PTR_ERR(aic32x4->supply_iov); 1083 } 1084 1085 if (IS_ERR(aic32x4->supply_ldo)) { 1086 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1087 return -EPROBE_DEFER; 1088 1089 if (IS_ERR(aic32x4->supply_dv)) { 1090 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1091 return PTR_ERR(aic32x4->supply_dv); 1092 } 1093 if (IS_ERR(aic32x4->supply_av)) { 1094 dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1095 return PTR_ERR(aic32x4->supply_av); 1096 } 1097 } else { 1098 if (IS_ERR(aic32x4->supply_dv) && 1099 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1100 return -EPROBE_DEFER; 1101 if (IS_ERR(aic32x4->supply_av) && 1102 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1103 return -EPROBE_DEFER; 1104 } 1105 1106 ret = regulator_enable(aic32x4->supply_iov); 1107 if (ret) { 1108 dev_err(dev, "Failed to enable regulator iov\n"); 1109 return ret; 1110 } 1111 1112 if (!IS_ERR(aic32x4->supply_ldo)) { 1113 ret = regulator_enable(aic32x4->supply_ldo); 1114 if (ret) { 1115 dev_err(dev, "Failed to enable regulator ldo\n"); 1116 goto error_ldo; 1117 } 1118 } 1119 1120 if (!IS_ERR(aic32x4->supply_dv)) { 1121 ret = regulator_enable(aic32x4->supply_dv); 1122 if (ret) { 1123 dev_err(dev, "Failed to enable regulator dv\n"); 1124 goto error_dv; 1125 } 1126 } 1127 1128 if (!IS_ERR(aic32x4->supply_av)) { 1129 ret = regulator_enable(aic32x4->supply_av); 1130 if (ret) { 1131 dev_err(dev, "Failed to enable regulator av\n"); 1132 goto error_av; 1133 } 1134 } 1135 1136 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1137 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1138 1139 return 0; 1140 1141 error_av: 1142 if (!IS_ERR(aic32x4->supply_dv)) 1143 regulator_disable(aic32x4->supply_dv); 1144 1145 error_dv: 1146 if (!IS_ERR(aic32x4->supply_ldo)) 1147 regulator_disable(aic32x4->supply_ldo); 1148 1149 error_ldo: 1150 regulator_disable(aic32x4->supply_iov); 1151 return ret; 1152 } 1153 1154 int aic32x4_probe(struct device *dev, struct regmap *regmap) 1155 { 1156 struct aic32x4_priv *aic32x4; 1157 struct aic32x4_pdata *pdata = dev->platform_data; 1158 struct device_node *np = dev->of_node; 1159 int ret; 1160 1161 if (IS_ERR(regmap)) 1162 return PTR_ERR(regmap); 1163 1164 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1165 GFP_KERNEL); 1166 if (aic32x4 == NULL) 1167 return -ENOMEM; 1168 1169 aic32x4->dev = dev; 1170 dev_set_drvdata(dev, aic32x4); 1171 1172 if (pdata) { 1173 aic32x4->power_cfg = pdata->power_cfg; 1174 aic32x4->swapdacs = pdata->swapdacs; 1175 aic32x4->micpga_routing = pdata->micpga_routing; 1176 aic32x4->rstn_gpio = pdata->rstn_gpio; 1177 aic32x4->mclk_name = "mclk"; 1178 } else if (np) { 1179 ret = aic32x4_parse_dt(aic32x4, np); 1180 if (ret) { 1181 dev_err(dev, "Failed to parse DT node\n"); 1182 return ret; 1183 } 1184 } else { 1185 aic32x4->power_cfg = 0; 1186 aic32x4->swapdacs = false; 1187 aic32x4->micpga_routing = 0; 1188 aic32x4->rstn_gpio = -1; 1189 aic32x4->mclk_name = "mclk"; 1190 } 1191 1192 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1193 if (ret) 1194 return ret; 1195 1196 if (gpio_is_valid(aic32x4->rstn_gpio)) { 1197 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1198 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1199 if (ret != 0) 1200 return ret; 1201 } 1202 1203 ret = aic32x4_setup_regulators(dev, aic32x4); 1204 if (ret) { 1205 dev_err(dev, "Failed to setup regulators\n"); 1206 return ret; 1207 } 1208 1209 ret = devm_snd_soc_register_component(dev, 1210 &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1211 if (ret) { 1212 dev_err(dev, "Failed to register component\n"); 1213 aic32x4_disable_regulators(aic32x4); 1214 return ret; 1215 } 1216 1217 return 0; 1218 } 1219 EXPORT_SYMBOL(aic32x4_probe); 1220 1221 int aic32x4_remove(struct device *dev) 1222 { 1223 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1224 1225 aic32x4_disable_regulators(aic32x4); 1226 1227 return 0; 1228 } 1229 EXPORT_SYMBOL(aic32x4_remove); 1230 1231 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 1232 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 1233 MODULE_LICENSE("GPL"); 1234