1 /* 2 * linux/sound/soc/codecs/tlv320aic32x4.c 3 * 4 * Copyright 2011 Vista Silicon S.L. 5 * 6 * Author: Javier Martin <javier.martin@vista-silicon.com> 7 * 8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23 * MA 02110-1301, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/init.h> 29 #include <linux/delay.h> 30 #include <linux/pm.h> 31 #include <linux/i2c.h> 32 #include <linux/cdev.h> 33 #include <linux/slab.h> 34 35 #include <sound/tlv320aic32x4.h> 36 #include <sound/core.h> 37 #include <sound/pcm.h> 38 #include <sound/pcm_params.h> 39 #include <sound/soc.h> 40 #include <sound/soc-dapm.h> 41 #include <sound/initval.h> 42 #include <sound/tlv.h> 43 44 #include "tlv320aic32x4.h" 45 46 struct aic32x4_rate_divs { 47 u32 mclk; 48 u32 rate; 49 u8 p_val; 50 u8 pll_j; 51 u16 pll_d; 52 u16 dosr; 53 u8 ndac; 54 u8 mdac; 55 u8 aosr; 56 u8 nadc; 57 u8 madc; 58 u8 blck_N; 59 }; 60 61 struct aic32x4_priv { 62 u32 sysclk; 63 s32 master; 64 u8 page_no; 65 void *control_data; 66 u32 power_cfg; 67 u32 micpga_routing; 68 bool swapdacs; 69 }; 70 71 /* 0dB min, 1dB steps */ 72 static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0); 73 /* 0dB min, 0.5dB steps */ 74 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 75 76 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 77 SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 78 AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5), 79 SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 80 AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1), 81 SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 82 AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1), 83 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 84 AIC32X4_HPRGAIN, 6, 0x01, 1), 85 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 86 AIC32X4_LORGAIN, 6, 0x01, 1), 87 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 88 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 89 90 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 91 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 92 93 SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL, 94 AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5), 95 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 96 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 97 98 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 99 100 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 101 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 102 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 103 4, 0x07, 0), 104 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 105 0, 0x03, 0), 106 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 107 6, 0x03, 0), 108 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 109 1, 0x1F, 0), 110 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 111 0, 0x7F, 0), 112 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 113 3, 0x1F, 0), 114 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 115 3, 0x1F, 0), 116 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 117 0, 0x1F, 0), 118 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 119 0, 0x0F, 0), 120 }; 121 122 static const struct aic32x4_rate_divs aic32x4_divs[] = { 123 /* 8k rate */ 124 {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24}, 125 {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24}, 126 {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24}, 127 /* 11.025k rate */ 128 {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16}, 129 {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16}, 130 /* 16k rate */ 131 {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12}, 132 {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12}, 133 {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12}, 134 /* 22.05k rate */ 135 {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8}, 136 {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8}, 137 {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8}, 138 /* 32k rate */ 139 {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6}, 140 {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6}, 141 /* 44.1k rate */ 142 {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4}, 143 {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4}, 144 {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4}, 145 /* 48k rate */ 146 {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4}, 147 {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4}, 148 {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4} 149 }; 150 151 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 152 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 153 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 154 }; 155 156 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 157 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 158 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 159 }; 160 161 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 162 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 163 }; 164 165 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 166 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 167 }; 168 169 static const struct snd_kcontrol_new left_input_mixer_controls[] = { 170 SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0), 171 SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0), 172 SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0), 173 }; 174 175 static const struct snd_kcontrol_new right_input_mixer_controls[] = { 176 SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0), 177 SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0), 178 SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0), 179 }; 180 181 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 182 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 183 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 184 &hpl_output_mixer_controls[0], 185 ARRAY_SIZE(hpl_output_mixer_controls)), 186 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 187 188 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 189 &lol_output_mixer_controls[0], 190 ARRAY_SIZE(lol_output_mixer_controls)), 191 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 192 193 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 194 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 195 &hpr_output_mixer_controls[0], 196 ARRAY_SIZE(hpr_output_mixer_controls)), 197 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 198 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 199 &lor_output_mixer_controls[0], 200 ARRAY_SIZE(lor_output_mixer_controls)), 201 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 202 SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0, 203 &left_input_mixer_controls[0], 204 ARRAY_SIZE(left_input_mixer_controls)), 205 SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0, 206 &right_input_mixer_controls[0], 207 ARRAY_SIZE(right_input_mixer_controls)), 208 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 209 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 210 SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0), 211 212 SND_SOC_DAPM_OUTPUT("HPL"), 213 SND_SOC_DAPM_OUTPUT("HPR"), 214 SND_SOC_DAPM_OUTPUT("LOL"), 215 SND_SOC_DAPM_OUTPUT("LOR"), 216 SND_SOC_DAPM_INPUT("IN1_L"), 217 SND_SOC_DAPM_INPUT("IN1_R"), 218 SND_SOC_DAPM_INPUT("IN2_L"), 219 SND_SOC_DAPM_INPUT("IN2_R"), 220 SND_SOC_DAPM_INPUT("IN3_L"), 221 SND_SOC_DAPM_INPUT("IN3_R"), 222 }; 223 224 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 225 /* Left Output */ 226 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 227 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 228 229 {"HPL Power", NULL, "HPL Output Mixer"}, 230 {"HPL", NULL, "HPL Power"}, 231 232 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 233 234 {"LOL Power", NULL, "LOL Output Mixer"}, 235 {"LOL", NULL, "LOL Power"}, 236 237 /* Right Output */ 238 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 239 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 240 241 {"HPR Power", NULL, "HPR Output Mixer"}, 242 {"HPR", NULL, "HPR Power"}, 243 244 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 245 246 {"LOR Power", NULL, "LOR Output Mixer"}, 247 {"LOR", NULL, "LOR Power"}, 248 249 /* Left input */ 250 {"Left Input Mixer", "IN1_L P Switch", "IN1_L"}, 251 {"Left Input Mixer", "IN2_L P Switch", "IN2_L"}, 252 {"Left Input Mixer", "IN3_L P Switch", "IN3_L"}, 253 254 {"Left ADC", NULL, "Left Input Mixer"}, 255 256 /* Right Input */ 257 {"Right Input Mixer", "IN1_R P Switch", "IN1_R"}, 258 {"Right Input Mixer", "IN2_R P Switch", "IN2_R"}, 259 {"Right Input Mixer", "IN3_R P Switch", "IN3_R"}, 260 261 {"Right ADC", NULL, "Right Input Mixer"}, 262 }; 263 264 static inline int aic32x4_change_page(struct snd_soc_codec *codec, 265 unsigned int new_page) 266 { 267 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 268 u8 data[2]; 269 int ret; 270 271 data[0] = 0x00; 272 data[1] = new_page & 0xff; 273 274 ret = codec->hw_write(codec->control_data, data, 2); 275 if (ret == 2) { 276 aic32x4->page_no = new_page; 277 return 0; 278 } else { 279 return ret; 280 } 281 } 282 283 static int aic32x4_write(struct snd_soc_codec *codec, unsigned int reg, 284 unsigned int val) 285 { 286 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 287 unsigned int page = reg / 128; 288 unsigned int fixed_reg = reg % 128; 289 u8 data[2]; 290 int ret; 291 292 /* A write to AIC32X4_PSEL is really a non-explicit page change */ 293 if (reg == AIC32X4_PSEL) 294 return aic32x4_change_page(codec, val); 295 296 if (aic32x4->page_no != page) { 297 ret = aic32x4_change_page(codec, page); 298 if (ret != 0) 299 return ret; 300 } 301 302 data[0] = fixed_reg & 0xff; 303 data[1] = val & 0xff; 304 305 if (codec->hw_write(codec->control_data, data, 2) == 2) 306 return 0; 307 else 308 return -EIO; 309 } 310 311 static unsigned int aic32x4_read(struct snd_soc_codec *codec, unsigned int reg) 312 { 313 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 314 unsigned int page = reg / 128; 315 unsigned int fixed_reg = reg % 128; 316 int ret; 317 318 if (aic32x4->page_no != page) { 319 ret = aic32x4_change_page(codec, page); 320 if (ret != 0) 321 return ret; 322 } 323 return i2c_smbus_read_byte_data(codec->control_data, fixed_reg & 0xff); 324 } 325 326 static inline int aic32x4_get_divs(int mclk, int rate) 327 { 328 int i; 329 330 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 331 if ((aic32x4_divs[i].rate == rate) 332 && (aic32x4_divs[i].mclk == mclk)) { 333 return i; 334 } 335 } 336 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 337 return -EINVAL; 338 } 339 340 static int aic32x4_add_widgets(struct snd_soc_codec *codec) 341 { 342 snd_soc_dapm_new_controls(&codec->dapm, aic32x4_dapm_widgets, 343 ARRAY_SIZE(aic32x4_dapm_widgets)); 344 345 snd_soc_dapm_add_routes(&codec->dapm, aic32x4_dapm_routes, 346 ARRAY_SIZE(aic32x4_dapm_routes)); 347 348 snd_soc_dapm_new_widgets(&codec->dapm); 349 return 0; 350 } 351 352 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 353 int clk_id, unsigned int freq, int dir) 354 { 355 struct snd_soc_codec *codec = codec_dai->codec; 356 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 357 358 switch (freq) { 359 case AIC32X4_FREQ_12000000: 360 case AIC32X4_FREQ_24000000: 361 case AIC32X4_FREQ_25000000: 362 aic32x4->sysclk = freq; 363 return 0; 364 } 365 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 366 return -EINVAL; 367 } 368 369 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 370 { 371 struct snd_soc_codec *codec = codec_dai->codec; 372 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 373 u8 iface_reg_1; 374 u8 iface_reg_2; 375 u8 iface_reg_3; 376 377 iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1); 378 iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2); 379 iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2); 380 iface_reg_2 = 0; 381 iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3); 382 iface_reg_3 = iface_reg_3 & ~(1 << 3); 383 384 /* set master/slave audio interface */ 385 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 386 case SND_SOC_DAIFMT_CBM_CFM: 387 aic32x4->master = 1; 388 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 389 break; 390 case SND_SOC_DAIFMT_CBS_CFS: 391 aic32x4->master = 0; 392 break; 393 default: 394 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 395 return -EINVAL; 396 } 397 398 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 399 case SND_SOC_DAIFMT_I2S: 400 break; 401 case SND_SOC_DAIFMT_DSP_A: 402 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 403 iface_reg_3 |= (1 << 3); /* invert bit clock */ 404 iface_reg_2 = 0x01; /* add offset 1 */ 405 break; 406 case SND_SOC_DAIFMT_DSP_B: 407 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 408 iface_reg_3 |= (1 << 3); /* invert bit clock */ 409 break; 410 case SND_SOC_DAIFMT_RIGHT_J: 411 iface_reg_1 |= 412 (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 413 break; 414 case SND_SOC_DAIFMT_LEFT_J: 415 iface_reg_1 |= 416 (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 417 break; 418 default: 419 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 420 return -EINVAL; 421 } 422 423 snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1); 424 snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2); 425 snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3); 426 return 0; 427 } 428 429 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 430 struct snd_pcm_hw_params *params, 431 struct snd_soc_dai *dai) 432 { 433 struct snd_soc_codec *codec = dai->codec; 434 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 435 u8 data; 436 int i; 437 438 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params)); 439 if (i < 0) { 440 printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 441 return i; 442 } 443 444 /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */ 445 snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN); 446 snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK); 447 448 /* We will fix R value to 1 and will make P & J=K.D as varialble */ 449 data = snd_soc_read(codec, AIC32X4_PLLPR); 450 data &= ~(7 << 4); 451 snd_soc_write(codec, AIC32X4_PLLPR, 452 (data | (aic32x4_divs[i].p_val << 4) | 0x01)); 453 454 snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j); 455 456 snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8)); 457 snd_soc_write(codec, AIC32X4_PLLDLSB, 458 (aic32x4_divs[i].pll_d & 0xff)); 459 460 /* NDAC divider value */ 461 data = snd_soc_read(codec, AIC32X4_NDAC); 462 data &= ~(0x7f); 463 snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac); 464 465 /* MDAC divider value */ 466 data = snd_soc_read(codec, AIC32X4_MDAC); 467 data &= ~(0x7f); 468 snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac); 469 470 /* DOSR MSB & LSB values */ 471 snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 472 snd_soc_write(codec, AIC32X4_DOSRLSB, 473 (aic32x4_divs[i].dosr & 0xff)); 474 475 /* NADC divider value */ 476 data = snd_soc_read(codec, AIC32X4_NADC); 477 data &= ~(0x7f); 478 snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc); 479 480 /* MADC divider value */ 481 data = snd_soc_read(codec, AIC32X4_MADC); 482 data &= ~(0x7f); 483 snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc); 484 485 /* AOSR value */ 486 snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr); 487 488 /* BCLK N divider */ 489 data = snd_soc_read(codec, AIC32X4_BCLKN); 490 data &= ~(0x7f); 491 snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N); 492 493 data = snd_soc_read(codec, AIC32X4_IFACE1); 494 data = data & ~(3 << 4); 495 switch (params_format(params)) { 496 case SNDRV_PCM_FORMAT_S16_LE: 497 break; 498 case SNDRV_PCM_FORMAT_S20_3LE: 499 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT); 500 break; 501 case SNDRV_PCM_FORMAT_S24_LE: 502 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT); 503 break; 504 case SNDRV_PCM_FORMAT_S32_LE: 505 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT); 506 break; 507 } 508 snd_soc_write(codec, AIC32X4_IFACE1, data); 509 510 return 0; 511 } 512 513 static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 514 { 515 struct snd_soc_codec *codec = dai->codec; 516 u8 dac_reg; 517 518 dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON; 519 if (mute) 520 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON); 521 else 522 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg); 523 return 0; 524 } 525 526 static int aic32x4_set_bias_level(struct snd_soc_codec *codec, 527 enum snd_soc_bias_level level) 528 { 529 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 530 531 switch (level) { 532 case SND_SOC_BIAS_ON: 533 if (aic32x4->master) { 534 /* Switch on PLL */ 535 snd_soc_update_bits(codec, AIC32X4_PLLPR, 536 AIC32X4_PLLEN, AIC32X4_PLLEN); 537 538 /* Switch on NDAC Divider */ 539 snd_soc_update_bits(codec, AIC32X4_NDAC, 540 AIC32X4_NDACEN, AIC32X4_NDACEN); 541 542 /* Switch on MDAC Divider */ 543 snd_soc_update_bits(codec, AIC32X4_MDAC, 544 AIC32X4_MDACEN, AIC32X4_MDACEN); 545 546 /* Switch on NADC Divider */ 547 snd_soc_update_bits(codec, AIC32X4_NADC, 548 AIC32X4_NADCEN, AIC32X4_NADCEN); 549 550 /* Switch on MADC Divider */ 551 snd_soc_update_bits(codec, AIC32X4_MADC, 552 AIC32X4_MADCEN, AIC32X4_MADCEN); 553 554 /* Switch on BCLK_N Divider */ 555 snd_soc_update_bits(codec, AIC32X4_BCLKN, 556 AIC32X4_BCLKEN, AIC32X4_BCLKEN); 557 } 558 break; 559 case SND_SOC_BIAS_PREPARE: 560 break; 561 case SND_SOC_BIAS_STANDBY: 562 if (aic32x4->master) { 563 /* Switch off PLL */ 564 snd_soc_update_bits(codec, AIC32X4_PLLPR, 565 AIC32X4_PLLEN, 0); 566 567 /* Switch off NDAC Divider */ 568 snd_soc_update_bits(codec, AIC32X4_NDAC, 569 AIC32X4_NDACEN, 0); 570 571 /* Switch off MDAC Divider */ 572 snd_soc_update_bits(codec, AIC32X4_MDAC, 573 AIC32X4_MDACEN, 0); 574 575 /* Switch off NADC Divider */ 576 snd_soc_update_bits(codec, AIC32X4_NADC, 577 AIC32X4_NADCEN, 0); 578 579 /* Switch off MADC Divider */ 580 snd_soc_update_bits(codec, AIC32X4_MADC, 581 AIC32X4_MADCEN, 0); 582 583 /* Switch off BCLK_N Divider */ 584 snd_soc_update_bits(codec, AIC32X4_BCLKN, 585 AIC32X4_BCLKEN, 0); 586 } 587 break; 588 case SND_SOC_BIAS_OFF: 589 break; 590 } 591 codec->dapm.bias_level = level; 592 return 0; 593 } 594 595 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000 596 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 597 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 598 599 static const struct snd_soc_dai_ops aic32x4_ops = { 600 .hw_params = aic32x4_hw_params, 601 .digital_mute = aic32x4_mute, 602 .set_fmt = aic32x4_set_dai_fmt, 603 .set_sysclk = aic32x4_set_dai_sysclk, 604 }; 605 606 static struct snd_soc_dai_driver aic32x4_dai = { 607 .name = "tlv320aic32x4-hifi", 608 .playback = { 609 .stream_name = "Playback", 610 .channels_min = 1, 611 .channels_max = 2, 612 .rates = AIC32X4_RATES, 613 .formats = AIC32X4_FORMATS,}, 614 .capture = { 615 .stream_name = "Capture", 616 .channels_min = 1, 617 .channels_max = 2, 618 .rates = AIC32X4_RATES, 619 .formats = AIC32X4_FORMATS,}, 620 .ops = &aic32x4_ops, 621 .symmetric_rates = 1, 622 }; 623 624 static int aic32x4_suspend(struct snd_soc_codec *codec) 625 { 626 aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 627 return 0; 628 } 629 630 static int aic32x4_resume(struct snd_soc_codec *codec) 631 { 632 aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 633 return 0; 634 } 635 636 static int aic32x4_probe(struct snd_soc_codec *codec) 637 { 638 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 639 u32 tmp_reg; 640 641 codec->hw_write = (hw_write_t) i2c_master_send; 642 codec->control_data = aic32x4->control_data; 643 644 snd_soc_write(codec, AIC32X4_RESET, 0x01); 645 646 /* Power platform configuration */ 647 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 648 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN | 649 AIC32X4_MICBIAS_2075V); 650 } 651 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) { 652 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 653 } 654 if (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) { 655 snd_soc_write(codec, AIC32X4_LDOCTL, AIC32X4_LDOCTLEN); 656 } 657 tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE); 658 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) { 659 tmp_reg |= AIC32X4_LDOIN_18_36; 660 } 661 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) { 662 tmp_reg |= AIC32X4_LDOIN2HP; 663 } 664 snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg); 665 666 /* Do DACs need to be swapped? */ 667 if (aic32x4->swapdacs) { 668 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2RCHN | AIC32X4_RDAC2LCHN); 669 } else { 670 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN); 671 } 672 673 /* Mic PGA routing */ 674 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) { 675 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K); 676 } 677 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) { 678 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K); 679 } 680 681 aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 682 snd_soc_add_controls(codec, aic32x4_snd_controls, 683 ARRAY_SIZE(aic32x4_snd_controls)); 684 aic32x4_add_widgets(codec); 685 686 return 0; 687 } 688 689 static int aic32x4_remove(struct snd_soc_codec *codec) 690 { 691 aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 692 return 0; 693 } 694 695 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = { 696 .read = aic32x4_read, 697 .write = aic32x4_write, 698 .probe = aic32x4_probe, 699 .remove = aic32x4_remove, 700 .suspend = aic32x4_suspend, 701 .resume = aic32x4_resume, 702 .set_bias_level = aic32x4_set_bias_level, 703 }; 704 705 static __devinit int aic32x4_i2c_probe(struct i2c_client *i2c, 706 const struct i2c_device_id *id) 707 { 708 struct aic32x4_pdata *pdata = i2c->dev.platform_data; 709 struct aic32x4_priv *aic32x4; 710 int ret; 711 712 aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv), 713 GFP_KERNEL); 714 if (aic32x4 == NULL) 715 return -ENOMEM; 716 717 aic32x4->control_data = i2c; 718 i2c_set_clientdata(i2c, aic32x4); 719 720 if (pdata) { 721 aic32x4->power_cfg = pdata->power_cfg; 722 aic32x4->swapdacs = pdata->swapdacs; 723 aic32x4->micpga_routing = pdata->micpga_routing; 724 } else { 725 aic32x4->power_cfg = 0; 726 aic32x4->swapdacs = false; 727 aic32x4->micpga_routing = 0; 728 } 729 730 ret = snd_soc_register_codec(&i2c->dev, 731 &soc_codec_dev_aic32x4, &aic32x4_dai, 1); 732 return ret; 733 } 734 735 static __devexit int aic32x4_i2c_remove(struct i2c_client *client) 736 { 737 snd_soc_unregister_codec(&client->dev); 738 return 0; 739 } 740 741 static const struct i2c_device_id aic32x4_i2c_id[] = { 742 { "tlv320aic32x4", 0 }, 743 { } 744 }; 745 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id); 746 747 static struct i2c_driver aic32x4_i2c_driver = { 748 .driver = { 749 .name = "tlv320aic32x4", 750 .owner = THIS_MODULE, 751 }, 752 .probe = aic32x4_i2c_probe, 753 .remove = __devexit_p(aic32x4_i2c_remove), 754 .id_table = aic32x4_i2c_id, 755 }; 756 757 static int __init aic32x4_modinit(void) 758 { 759 int ret = 0; 760 761 ret = i2c_add_driver(&aic32x4_i2c_driver); 762 if (ret != 0) { 763 printk(KERN_ERR "Failed to register aic32x4 I2C driver: %d\n", 764 ret); 765 } 766 return ret; 767 } 768 module_init(aic32x4_modinit); 769 770 static void __exit aic32x4_exit(void) 771 { 772 i2c_del_driver(&aic32x4_i2c_driver); 773 } 774 module_exit(aic32x4_exit); 775 776 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 777 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 778 MODULE_LICENSE("GPL"); 779