11d471cd1SJavier Martin /* 21d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c 31d471cd1SJavier Martin * 41d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L. 51d471cd1SJavier Martin * 61d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com> 71d471cd1SJavier Martin * 81d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 91d471cd1SJavier Martin * 101d471cd1SJavier Martin * This program is free software; you can redistribute it and/or modify 111d471cd1SJavier Martin * it under the terms of the GNU General Public License as published by 121d471cd1SJavier Martin * the Free Software Foundation; either version 2 of the License, or 131d471cd1SJavier Martin * (at your option) any later version. 141d471cd1SJavier Martin * 151d471cd1SJavier Martin * This program is distributed in the hope that it will be useful, 161d471cd1SJavier Martin * but WITHOUT ANY WARRANTY; without even the implied warranty of 171d471cd1SJavier Martin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 181d471cd1SJavier Martin * GNU General Public License for more details. 191d471cd1SJavier Martin * 201d471cd1SJavier Martin * You should have received a copy of the GNU General Public License 211d471cd1SJavier Martin * along with this program; if not, write to the Free Software 221d471cd1SJavier Martin * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 231d471cd1SJavier Martin * MA 02110-1301, USA. 241d471cd1SJavier Martin */ 251d471cd1SJavier Martin 261d471cd1SJavier Martin #include <linux/module.h> 271d471cd1SJavier Martin #include <linux/moduleparam.h> 281d471cd1SJavier Martin #include <linux/init.h> 291d471cd1SJavier Martin #include <linux/delay.h> 301d471cd1SJavier Martin #include <linux/pm.h> 311858fe97SJavier Martin #include <linux/gpio.h> 324d16700dSMarkus Pargmann #include <linux/of_gpio.h> 331d471cd1SJavier Martin #include <linux/cdev.h> 341d471cd1SJavier Martin #include <linux/slab.h> 3598b664e2SMarkus Pargmann #include <linux/clk.h> 36514b044cSAnnaliese McDermond #include <linux/of_clk.h> 37239b669bSMarkus Pargmann #include <linux/regulator/consumer.h> 381d471cd1SJavier Martin 391d471cd1SJavier Martin #include <sound/tlv320aic32x4.h> 401d471cd1SJavier Martin #include <sound/core.h> 411d471cd1SJavier Martin #include <sound/pcm.h> 421d471cd1SJavier Martin #include <sound/pcm_params.h> 431d471cd1SJavier Martin #include <sound/soc.h> 441d471cd1SJavier Martin #include <sound/soc-dapm.h> 451d471cd1SJavier Martin #include <sound/initval.h> 461d471cd1SJavier Martin #include <sound/tlv.h> 471d471cd1SJavier Martin 481d471cd1SJavier Martin #include "tlv320aic32x4.h" 491d471cd1SJavier Martin 501d471cd1SJavier Martin struct aic32x4_priv { 514d208ca4SMark Brown struct regmap *regmap; 521d471cd1SJavier Martin u32 power_cfg; 531d471cd1SJavier Martin u32 micpga_routing; 541d471cd1SJavier Martin bool swapdacs; 551858fe97SJavier Martin int rstn_gpio; 56514b044cSAnnaliese McDermond const char *mclk_name; 57239b669bSMarkus Pargmann 58239b669bSMarkus Pargmann struct regulator *supply_ldo; 59239b669bSMarkus Pargmann struct regulator *supply_iov; 60239b669bSMarkus Pargmann struct regulator *supply_dv; 61239b669bSMarkus Pargmann struct regulator *supply_av; 62b9045b9cSDan Murphy 63b9045b9cSDan Murphy struct aic32x4_setup_data *setup; 64b9045b9cSDan Murphy struct device *dev; 65b9045b9cSDan Murphy }; 66b9045b9cSDan Murphy 6704d979d7Sb-ak static int mic_bias_event(struct snd_soc_dapm_widget *w, 6804d979d7Sb-ak struct snd_kcontrol *kcontrol, int event) 6904d979d7Sb-ak { 7004d979d7Sb-ak struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 7104d979d7Sb-ak 7204d979d7Sb-ak switch (event) { 7304d979d7Sb-ak case SND_SOC_DAPM_POST_PMU: 7404d979d7Sb-ak /* Change Mic Bias Registor */ 7504d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 7604d979d7Sb-ak AIC32x4_MICBIAS_MASK, 7704d979d7Sb-ak AIC32X4_MICBIAS_LDOIN | 7804d979d7Sb-ak AIC32X4_MICBIAS_2075V); 7904d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 8004d979d7Sb-ak break; 8104d979d7Sb-ak case SND_SOC_DAPM_PRE_PMD: 8204d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 8304d979d7Sb-ak AIC32x4_MICBIAS_MASK, 0); 8404d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 8504d979d7Sb-ak __func__); 8604d979d7Sb-ak break; 8704d979d7Sb-ak } 8804d979d7Sb-ak 8904d979d7Sb-ak return 0; 9004d979d7Sb-ak } 9104d979d7Sb-ak 9204d979d7Sb-ak 93b9045b9cSDan Murphy static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 94b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 95b9045b9cSDan Murphy { 96b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 97b9045b9cSDan Murphy u8 val; 98b9045b9cSDan Murphy 99b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_DINCTL); 100b9045b9cSDan Murphy 101b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 102b9045b9cSDan Murphy 103b9045b9cSDan Murphy return 0; 104b9045b9cSDan Murphy }; 105b9045b9cSDan Murphy 106b9045b9cSDan Murphy static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 107b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 108b9045b9cSDan Murphy { 109b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 110b9045b9cSDan Murphy u8 val; 111b9045b9cSDan Murphy u8 gpio_check; 112b9045b9cSDan Murphy 113b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 114b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 115b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 116b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 117b9045b9cSDan Murphy __func__); 118b9045b9cSDan Murphy return -EINVAL; 119b9045b9cSDan Murphy } 120b9045b9cSDan Murphy 121b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 122b9045b9cSDan Murphy return 0; 123b9045b9cSDan Murphy 124b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 125b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 126b9045b9cSDan Murphy else 127b9045b9cSDan Murphy val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 128b9045b9cSDan Murphy 129b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 130b9045b9cSDan Murphy 131b9045b9cSDan Murphy return 0; 132b9045b9cSDan Murphy }; 133b9045b9cSDan Murphy 134b9045b9cSDan Murphy static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 135b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 136b9045b9cSDan Murphy { 137b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 138b9045b9cSDan Murphy u8 val; 139b9045b9cSDan Murphy 140b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 141b9045b9cSDan Murphy 142b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 143b9045b9cSDan Murphy 144b9045b9cSDan Murphy return 0; 145b9045b9cSDan Murphy }; 146b9045b9cSDan Murphy 147b9045b9cSDan Murphy static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 148b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 149b9045b9cSDan Murphy { 150b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 151b9045b9cSDan Murphy u8 val; 152b9045b9cSDan Murphy u8 gpio_check; 153b9045b9cSDan Murphy 154b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 155b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 156b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 157b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 158b9045b9cSDan Murphy __func__); 159b9045b9cSDan Murphy return -EINVAL; 160b9045b9cSDan Murphy } 161b9045b9cSDan Murphy 162b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 163b9045b9cSDan Murphy return 0; 164b9045b9cSDan Murphy 165b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 166b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 167b9045b9cSDan Murphy else 168b9045b9cSDan Murphy val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 169b9045b9cSDan Murphy 170b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, val); 171b9045b9cSDan Murphy 172b9045b9cSDan Murphy return 0; 173b9045b9cSDan Murphy }; 174b9045b9cSDan Murphy 175b9045b9cSDan Murphy static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 176b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 177b9045b9cSDan Murphy { 178b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 179b9045b9cSDan Murphy u8 val; 180b9045b9cSDan Murphy 181b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 182b9045b9cSDan Murphy ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 183b9045b9cSDan Murphy 184b9045b9cSDan Murphy return 0; 185b9045b9cSDan Murphy }; 186b9045b9cSDan Murphy 187b9045b9cSDan Murphy static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 188b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 189b9045b9cSDan Murphy { 190b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 191b9045b9cSDan Murphy u8 val; 192b9045b9cSDan Murphy u8 gpio_check; 193b9045b9cSDan Murphy 194b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 195b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 196b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 197b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 198b9045b9cSDan Murphy __func__); 199b9045b9cSDan Murphy return -EINVAL; 200b9045b9cSDan Murphy } 201b9045b9cSDan Murphy 202b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & 0x1)) 203b9045b9cSDan Murphy return 0; 204b9045b9cSDan Murphy 205b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 206b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 207b9045b9cSDan Murphy else 208b9045b9cSDan Murphy val &= 0xfe; 209b9045b9cSDan Murphy 210b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 211b9045b9cSDan Murphy 212b9045b9cSDan Murphy return 0; 213b9045b9cSDan Murphy }; 214b9045b9cSDan Murphy 215b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp1[] = { 216b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 217b9045b9cSDan Murphy }; 218b9045b9cSDan Murphy 219b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp2[] = { 220b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 221b9045b9cSDan Murphy }; 222b9045b9cSDan Murphy 223b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp3[] = { 224b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 225b9045b9cSDan Murphy }; 226b9045b9cSDan Murphy 227b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp4[] = { 228b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 229b9045b9cSDan Murphy }; 230b9045b9cSDan Murphy 231b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp5[] = { 232b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 233b9045b9cSDan Murphy aic32x4_set_mfp5_gpio), 2341d471cd1SJavier Martin }; 2351d471cd1SJavier Martin 2361d471cd1SJavier Martin /* 0dB min, 0.5dB steps */ 2371d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 238c671e79dSMarkus Pargmann /* -63.5dB min, 0.5dB steps */ 239c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 240c671e79dSMarkus Pargmann /* -6dB min, 1dB steps */ 241c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 242c671e79dSMarkus Pargmann /* -12dB min, 0.5dB steps */ 243c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 2441d471cd1SJavier Martin 24544ceee84SAnnaliese McDermond static const char * const lo_cm_text[] = { 24644ceee84SAnnaliese McDermond "Full Chip", "1.65V", 24744ceee84SAnnaliese McDermond }; 24844ceee84SAnnaliese McDermond 24944ceee84SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text); 25044ceee84SAnnaliese McDermond 251*d3e6e374SAnnaliese McDermond static const char * const ptm_text[] = { 252*d3e6e374SAnnaliese McDermond "P3", "P2", "P1", 253*d3e6e374SAnnaliese McDermond }; 254*d3e6e374SAnnaliese McDermond 255*d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text); 256*d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text); 257*d3e6e374SAnnaliese McDermond 2581d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 259c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 260c671e79dSMarkus Pargmann AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 261*d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum), 262*d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum), 263c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 264c671e79dSMarkus Pargmann AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 265c671e79dSMarkus Pargmann tlv_driver_gain), 266c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 267c671e79dSMarkus Pargmann AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 268c671e79dSMarkus Pargmann tlv_driver_gain), 2691d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 2701d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1), 2711d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 2721d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1), 27344ceee84SAnnaliese McDermond SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum), 2741d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 2751d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1), 2761d471cd1SJavier Martin 2771d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 2781d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 2791d471cd1SJavier Martin 280c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 281c671e79dSMarkus Pargmann AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 2821d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 2831d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 2841d471cd1SJavier Martin 2851d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 2861d471cd1SJavier Martin 2871d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 2881d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 2891d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 2901d471cd1SJavier Martin 4, 0x07, 0), 2911d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 2921d471cd1SJavier Martin 0, 0x03, 0), 2931d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 2941d471cd1SJavier Martin 6, 0x03, 0), 2951d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 2961d471cd1SJavier Martin 1, 0x1F, 0), 2971d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 2981d471cd1SJavier Martin 0, 0x7F, 0), 2991d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 3001d471cd1SJavier Martin 3, 0x1F, 0), 3011d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 3021d471cd1SJavier Martin 3, 0x1F, 0), 3031d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 3041d471cd1SJavier Martin 0, 0x1F, 0), 3051d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 3061d471cd1SJavier Martin 0, 0x0F, 0), 3071d471cd1SJavier Martin }; 3081d471cd1SJavier Martin 3091d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 3101d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 3111d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 3121d471cd1SJavier Martin }; 3131d471cd1SJavier Martin 3141d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 3151d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 3161d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 3171d471cd1SJavier Martin }; 3181d471cd1SJavier Martin 3191d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 3201d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 3211d471cd1SJavier Martin }; 3221d471cd1SJavier Martin 3231d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 3241d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 3251d471cd1SJavier Martin }; 3261d471cd1SJavier Martin 32720d2cecbSJeremy McDermond static const char * const resistor_text[] = { 32820d2cecbSJeremy McDermond "Off", "10 kOhm", "20 kOhm", "40 kOhm", 3291d471cd1SJavier Martin }; 3301d471cd1SJavier Martin 3312213fc35SJeremy McDermond /* Left mixer pins */ 3322213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 3332213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 3342213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 3352213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 33620d2cecbSJeremy McDermond 3372213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 3382213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 3392213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 3402213fc35SJeremy McDermond 3412213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 3422213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 3432213fc35SJeremy McDermond }; 3442213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 3452213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 3462213fc35SJeremy McDermond }; 3472213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 3482213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 3492213fc35SJeremy McDermond }; 3502213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 3512213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 3522213fc35SJeremy McDermond }; 3532213fc35SJeremy McDermond static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 3542213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 3552213fc35SJeremy McDermond }; 3562213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 3572213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 3582213fc35SJeremy McDermond }; 3592213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 3602213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 36120d2cecbSJeremy McDermond }; 36220d2cecbSJeremy McDermond 3632213fc35SJeremy McDermond /* Right mixer pins */ 3642213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 3652213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 3662213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 3672213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 3682213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 3692213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 3702213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 37120d2cecbSJeremy McDermond 3722213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 3732213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 3742213fc35SJeremy McDermond }; 3752213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 3762213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 3772213fc35SJeremy McDermond }; 3782213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 3792213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 3802213fc35SJeremy McDermond }; 3812213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 3822213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 3832213fc35SJeremy McDermond }; 3842213fc35SJeremy McDermond static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 3852213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 3862213fc35SJeremy McDermond }; 3872213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 3882213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 3892213fc35SJeremy McDermond }; 3902213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 3912213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 3921d471cd1SJavier Martin }; 3931d471cd1SJavier Martin 3941d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 3951d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 3961d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 3971d471cd1SJavier Martin &hpl_output_mixer_controls[0], 3981d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)), 3991d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 4001d471cd1SJavier Martin 4011d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 4021d471cd1SJavier Martin &lol_output_mixer_controls[0], 4031d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)), 4041d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 4051d471cd1SJavier Martin 4061d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 4071d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 4081d471cd1SJavier Martin &hpr_output_mixer_controls[0], 4091d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)), 4101d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 4111d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 4121d471cd1SJavier Martin &lor_output_mixer_controls[0], 4131d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)), 4141d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 4152213fc35SJeremy McDermond 4161d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 4172213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4182213fc35SJeremy McDermond in1r_to_rmixer_controls), 4192213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4202213fc35SJeremy McDermond in2r_to_rmixer_controls), 4212213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4222213fc35SJeremy McDermond in3r_to_rmixer_controls), 4232213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4242213fc35SJeremy McDermond in2l_to_rmixer_controls), 4252213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4262213fc35SJeremy McDermond cmr_to_rmixer_controls), 4272213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4282213fc35SJeremy McDermond in1l_to_rmixer_controls), 4292213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4302213fc35SJeremy McDermond in3l_to_rmixer_controls), 4312213fc35SJeremy McDermond 4322213fc35SJeremy McDermond SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 4332213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4342213fc35SJeremy McDermond in1l_to_lmixer_controls), 4352213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4362213fc35SJeremy McDermond in2l_to_lmixer_controls), 4372213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4382213fc35SJeremy McDermond in3l_to_lmixer_controls), 4392213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4402213fc35SJeremy McDermond in1r_to_lmixer_controls), 4412213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4422213fc35SJeremy McDermond cml_to_lmixer_controls), 4432213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4442213fc35SJeremy McDermond in2r_to_lmixer_controls), 4452213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4462213fc35SJeremy McDermond in3r_to_lmixer_controls), 4472213fc35SJeremy McDermond 44804d979d7Sb-ak SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 44904d979d7Sb-ak SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 45004d979d7Sb-ak 4511d471cd1SJavier Martin 4521d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"), 4531d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"), 4541d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"), 4551d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"), 4561d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"), 4571d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"), 4581d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"), 4591d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"), 4601d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"), 4611d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"), 462c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_L"), 463c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_R"), 4641d471cd1SJavier Martin }; 4651d471cd1SJavier Martin 4661d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 4671d471cd1SJavier Martin /* Left Output */ 4681d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 4691d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 4701d471cd1SJavier Martin 4711d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"}, 4721d471cd1SJavier Martin {"HPL", NULL, "HPL Power"}, 4731d471cd1SJavier Martin 4741d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 4751d471cd1SJavier Martin 4761d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"}, 4771d471cd1SJavier Martin {"LOL", NULL, "LOL Power"}, 4781d471cd1SJavier Martin 4791d471cd1SJavier Martin /* Right Output */ 4801d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 4811d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 4821d471cd1SJavier Martin 4831d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"}, 4841d471cd1SJavier Martin {"HPR", NULL, "HPR Power"}, 4851d471cd1SJavier Martin 4861d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 4871d471cd1SJavier Martin 4881d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"}, 4891d471cd1SJavier Martin {"LOR", NULL, "LOR Power"}, 4901d471cd1SJavier Martin 4911d471cd1SJavier Martin /* Right Input */ 4922213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 4932213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 4942213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 4952213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 4961d471cd1SJavier Martin 4972213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 4982213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 4992213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 5002213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 5012213fc35SJeremy McDermond 5022213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 5032213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 5042213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 5052213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 5062213fc35SJeremy McDermond 5072213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 5082213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5092213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5102213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5112213fc35SJeremy McDermond 5122213fc35SJeremy McDermond {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 5132213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 5142213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 5152213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 5162213fc35SJeremy McDermond 5172213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 5182213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 5192213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 5202213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 5212213fc35SJeremy McDermond 5222213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 5232213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 5242213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 5252213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 5262213fc35SJeremy McDermond 5272213fc35SJeremy McDermond /* Left Input */ 5282213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 5292213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 5302213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 5312213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 5322213fc35SJeremy McDermond 5332213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 5342213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5352213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5362213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5372213fc35SJeremy McDermond 5382213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 5392213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 5402213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 5412213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 5422213fc35SJeremy McDermond 5432213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 5442213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 5452213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 5462213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 5472213fc35SJeremy McDermond 5482213fc35SJeremy McDermond {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 5492213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 5502213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 5512213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 5522213fc35SJeremy McDermond 5532213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 5542213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 5552213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 5562213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 5572213fc35SJeremy McDermond 5582213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 5592213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 5602213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 5612213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 5621d471cd1SJavier Martin }; 5631d471cd1SJavier Martin 5644d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 5651d471cd1SJavier Martin { 5664d208ca4SMark Brown .selector_reg = 0, 5674d208ca4SMark Brown .selector_mask = 0xff, 5684d208ca4SMark Brown .window_start = 0, 5694d208ca4SMark Brown .window_len = 128, 570e8e08c52SMarkus Pargmann .range_min = 0, 5716d0d5103SMarkus Pargmann .range_max = AIC32X4_RMICPGAVOL, 5724d208ca4SMark Brown }, 5734d208ca4SMark Brown }; 5741d471cd1SJavier Martin 5753bcfd222SJeremy McDermond const struct regmap_config aic32x4_regmap_config = { 5764d208ca4SMark Brown .max_register = AIC32X4_RMICPGAVOL, 5774d208ca4SMark Brown .ranges = aic32x4_regmap_pages, 5784d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 5794d208ca4SMark Brown }; 5803bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_regmap_config); 5811d471cd1SJavier Martin 5821d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 5831d471cd1SJavier Martin int clk_id, unsigned int freq, int dir) 5841d471cd1SJavier Martin { 585b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 586aa6a60f7SAnnaliese McDermond struct clk *mclk; 587aa6a60f7SAnnaliese McDermond struct clk *pll; 5881d471cd1SJavier Martin 589aa6a60f7SAnnaliese McDermond pll = devm_clk_get(component->dev, "pll"); 590aa6a60f7SAnnaliese McDermond mclk = clk_get_parent(pll); 591aa6a60f7SAnnaliese McDermond 592aa6a60f7SAnnaliese McDermond return clk_set_rate(mclk, freq); 5931d471cd1SJavier Martin } 5941d471cd1SJavier Martin 5951d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 5961d471cd1SJavier Martin { 597b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 59860fb4be5SAndrew F. Davis u8 iface_reg_1 = 0; 59960fb4be5SAndrew F. Davis u8 iface_reg_2 = 0; 60060fb4be5SAndrew F. Davis u8 iface_reg_3 = 0; 6011d471cd1SJavier Martin 6021d471cd1SJavier Martin /* set master/slave audio interface */ 6031d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 6041d471cd1SJavier Martin case SND_SOC_DAIFMT_CBM_CFM: 6051d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 6061d471cd1SJavier Martin break; 6071d471cd1SJavier Martin case SND_SOC_DAIFMT_CBS_CFS: 6081d471cd1SJavier Martin break; 6091d471cd1SJavier Martin default: 6101d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 6111d471cd1SJavier Martin return -EINVAL; 6121d471cd1SJavier Martin } 6131d471cd1SJavier Martin 6141d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 6151d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S: 6161d471cd1SJavier Martin break; 6171d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A: 6184483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6194483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 62060fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6211d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */ 6221d471cd1SJavier Martin break; 6231d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B: 6244483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6254483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 62660fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6271d471cd1SJavier Martin break; 6281d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J: 6294483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 6304483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6311d471cd1SJavier Martin break; 6321d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J: 6334483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 6344483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6351d471cd1SJavier Martin break; 6361d471cd1SJavier Martin default: 6371d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 6381d471cd1SJavier Martin return -EINVAL; 6391d471cd1SJavier Martin } 6401d471cd1SJavier Martin 641b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 64260fb4be5SAndrew F. Davis AIC32X4_IFACE1_DATATYPE_MASK | 64360fb4be5SAndrew F. Davis AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 644b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE2, 64560fb4be5SAndrew F. Davis AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 646b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE3, 64760fb4be5SAndrew F. Davis AIC32X4_BCLKINV_MASK, iface_reg_3); 64860fb4be5SAndrew F. Davis 6491d471cd1SJavier Martin return 0; 6501d471cd1SJavier Martin } 6511d471cd1SJavier Martin 652fbafbf65SAnnaliese McDermond static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) 653fbafbf65SAnnaliese McDermond { 654fbafbf65SAnnaliese McDermond return snd_soc_component_write(component, AIC32X4_AOSR, aosr); 655fbafbf65SAnnaliese McDermond } 656fbafbf65SAnnaliese McDermond 657fbafbf65SAnnaliese McDermond static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) 658fbafbf65SAnnaliese McDermond { 659fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); 660fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRLSB, 661fbafbf65SAnnaliese McDermond (dosr & 0xff)); 662fbafbf65SAnnaliese McDermond 663fbafbf65SAnnaliese McDermond return 0; 664fbafbf65SAnnaliese McDermond } 665fbafbf65SAnnaliese McDermond 666c95e3a4bSAnnaliese McDermond static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 667c95e3a4bSAnnaliese McDermond u8 r_block, u8 p_block) 668c95e3a4bSAnnaliese McDermond { 669c95e3a4bSAnnaliese McDermond if (r_block > 18 || p_block > 25) 670c95e3a4bSAnnaliese McDermond return -EINVAL; 671c95e3a4bSAnnaliese McDermond 672c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 673c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 674c95e3a4bSAnnaliese McDermond 675c95e3a4bSAnnaliese McDermond return 0; 676c95e3a4bSAnnaliese McDermond } 677c95e3a4bSAnnaliese McDermond 678bf31cbfbSAnnaliese McDermond static int aic32x4_setup_clocks(struct snd_soc_component *component, 67996c3bb00SAnnaliese McDermond unsigned int sample_rate) 6801d471cd1SJavier Martin { 68196c3bb00SAnnaliese McDermond u8 aosr; 68296c3bb00SAnnaliese McDermond u16 dosr; 68396c3bb00SAnnaliese McDermond u8 adc_resource_class, dac_resource_class; 68496c3bb00SAnnaliese McDermond u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; 68596c3bb00SAnnaliese McDermond u8 dosr_increment; 68696c3bb00SAnnaliese McDermond u16 max_dosr, min_dosr; 68796c3bb00SAnnaliese McDermond unsigned long mclk_rate, adc_clock_rate, dac_clock_rate; 688514b044cSAnnaliese McDermond int ret; 68996c3bb00SAnnaliese McDermond struct clk *mclk; 690514b044cSAnnaliese McDermond 691514b044cSAnnaliese McDermond struct clk_bulk_data clocks[] = { 692514b044cSAnnaliese McDermond { .id = "pll" }, 693a51b5006SAnnaliese McDermond { .id = "nadc" }, 694a51b5006SAnnaliese McDermond { .id = "madc" }, 695a51b5006SAnnaliese McDermond { .id = "ndac" }, 696a51b5006SAnnaliese McDermond { .id = "mdac" }, 6979b484124SAnnaliese McDermond { .id = "bdiv" }, 698514b044cSAnnaliese McDermond }; 699514b044cSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 700514b044cSAnnaliese McDermond if (ret) 701514b044cSAnnaliese McDermond return ret; 702514b044cSAnnaliese McDermond 70396c3bb00SAnnaliese McDermond mclk = clk_get_parent(clocks[1].clk); 70496c3bb00SAnnaliese McDermond mclk_rate = clk_get_rate(mclk); 705514b044cSAnnaliese McDermond 70696c3bb00SAnnaliese McDermond if (sample_rate <= 48000) { 70796c3bb00SAnnaliese McDermond aosr = 128; 70896c3bb00SAnnaliese McDermond adc_resource_class = 6; 70996c3bb00SAnnaliese McDermond dac_resource_class = 8; 71096c3bb00SAnnaliese McDermond dosr_increment = 8; 71196c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 1); 71296c3bb00SAnnaliese McDermond } else if (sample_rate <= 96000) { 71396c3bb00SAnnaliese McDermond aosr = 64; 71496c3bb00SAnnaliese McDermond adc_resource_class = 6; 71596c3bb00SAnnaliese McDermond dac_resource_class = 8; 71696c3bb00SAnnaliese McDermond dosr_increment = 4; 71796c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 9); 71896c3bb00SAnnaliese McDermond } else if (sample_rate == 192000) { 71996c3bb00SAnnaliese McDermond aosr = 32; 72096c3bb00SAnnaliese McDermond adc_resource_class = 3; 72196c3bb00SAnnaliese McDermond dac_resource_class = 4; 72296c3bb00SAnnaliese McDermond dosr_increment = 2; 72396c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 13, 19); 72496c3bb00SAnnaliese McDermond } else { 72596c3bb00SAnnaliese McDermond dev_err(component->dev, "Sampling rate not supported\n"); 72696c3bb00SAnnaliese McDermond return -EINVAL; 72796c3bb00SAnnaliese McDermond } 728fbafbf65SAnnaliese McDermond 72996c3bb00SAnnaliese McDermond madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); 73096c3bb00SAnnaliese McDermond max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * 73196c3bb00SAnnaliese McDermond dosr_increment; 73296c3bb00SAnnaliese McDermond min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * 73396c3bb00SAnnaliese McDermond dosr_increment; 73496c3bb00SAnnaliese McDermond max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); 735c95e3a4bSAnnaliese McDermond 73696c3bb00SAnnaliese McDermond for (nadc = max_nadc; nadc > 0; --nadc) { 73796c3bb00SAnnaliese McDermond adc_clock_rate = nadc * madc * aosr * sample_rate; 73896c3bb00SAnnaliese McDermond for (dosr = max_dosr; dosr >= min_dosr; 73996c3bb00SAnnaliese McDermond dosr -= dosr_increment) { 74096c3bb00SAnnaliese McDermond min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); 74196c3bb00SAnnaliese McDermond max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / 74296c3bb00SAnnaliese McDermond (min_mdac * dosr * sample_rate); 74396c3bb00SAnnaliese McDermond for (mdac = min_mdac; mdac <= 128; ++mdac) { 74496c3bb00SAnnaliese McDermond for (ndac = max_ndac; ndac > 0; --ndac) { 74596c3bb00SAnnaliese McDermond dac_clock_rate = ndac * mdac * dosr * 74696c3bb00SAnnaliese McDermond sample_rate; 74796c3bb00SAnnaliese McDermond if (dac_clock_rate == adc_clock_rate) { 74896c3bb00SAnnaliese McDermond if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 74996c3bb00SAnnaliese McDermond continue; 75096c3bb00SAnnaliese McDermond 75196c3bb00SAnnaliese McDermond clk_set_rate(clocks[0].clk, 75296c3bb00SAnnaliese McDermond dac_clock_rate); 75396c3bb00SAnnaliese McDermond 75496c3bb00SAnnaliese McDermond clk_set_rate(clocks[1].clk, 75596c3bb00SAnnaliese McDermond sample_rate * aosr * 75696c3bb00SAnnaliese McDermond madc); 75796c3bb00SAnnaliese McDermond clk_set_rate(clocks[2].clk, 75896c3bb00SAnnaliese McDermond sample_rate * aosr); 75996c3bb00SAnnaliese McDermond aic32x4_set_aosr(component, 76096c3bb00SAnnaliese McDermond aosr); 76196c3bb00SAnnaliese McDermond 76296c3bb00SAnnaliese McDermond clk_set_rate(clocks[3].clk, 76396c3bb00SAnnaliese McDermond sample_rate * dosr * 76496c3bb00SAnnaliese McDermond mdac); 76596c3bb00SAnnaliese McDermond clk_set_rate(clocks[4].clk, 76696c3bb00SAnnaliese McDermond sample_rate * dosr); 76796c3bb00SAnnaliese McDermond aic32x4_set_dosr(component, 76896c3bb00SAnnaliese McDermond dosr); 76996c3bb00SAnnaliese McDermond 77096c3bb00SAnnaliese McDermond clk_set_rate(clocks[5].clk, 77196c3bb00SAnnaliese McDermond sample_rate * 32); 772bf31cbfbSAnnaliese McDermond return 0; 773bf31cbfbSAnnaliese McDermond } 77496c3bb00SAnnaliese McDermond } 77596c3bb00SAnnaliese McDermond } 77696c3bb00SAnnaliese McDermond } 77796c3bb00SAnnaliese McDermond } 77896c3bb00SAnnaliese McDermond 77996c3bb00SAnnaliese McDermond dev_err(component->dev, 78096c3bb00SAnnaliese McDermond "Could not set clocks to support sample rate.\n"); 78196c3bb00SAnnaliese McDermond return -EINVAL; 78296c3bb00SAnnaliese McDermond } 783bf31cbfbSAnnaliese McDermond 784bf31cbfbSAnnaliese McDermond static int aic32x4_hw_params(struct snd_pcm_substream *substream, 785bf31cbfbSAnnaliese McDermond struct snd_pcm_hw_params *params, 786bf31cbfbSAnnaliese McDermond struct snd_soc_dai *dai) 787bf31cbfbSAnnaliese McDermond { 788bf31cbfbSAnnaliese McDermond struct snd_soc_component *component = dai->component; 789bf31cbfbSAnnaliese McDermond struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 790bf31cbfbSAnnaliese McDermond u8 iface1_reg = 0; 791bf31cbfbSAnnaliese McDermond u8 dacsetup_reg = 0; 792bf31cbfbSAnnaliese McDermond 79396c3bb00SAnnaliese McDermond aic32x4_setup_clocks(component, params_rate(params)); 794bf31cbfbSAnnaliese McDermond 795bd8a5711SMark Brown switch (params_width(params)) { 796bd8a5711SMark Brown case 16: 79764aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 79877bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7991d471cd1SJavier Martin break; 800bd8a5711SMark Brown case 20: 80164aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 80277bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8031d471cd1SJavier Martin break; 804bd8a5711SMark Brown case 24: 80564aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 80677bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8071d471cd1SJavier Martin break; 808bd8a5711SMark Brown case 32: 80964aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 81077bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8111d471cd1SJavier Martin break; 8121d471cd1SJavier Martin } 813b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 81464aab899SAndrew F. Davis AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 8151d471cd1SJavier Martin 816b44aa40fSMarkus Pargmann if (params_channels(params) == 1) { 81764aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 818b44aa40fSMarkus Pargmann } else { 819b44aa40fSMarkus Pargmann if (aic32x4->swapdacs) 82064aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 821b44aa40fSMarkus Pargmann else 82264aab899SAndrew F. Davis dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 823b44aa40fSMarkus Pargmann } 824b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 82564aab899SAndrew F. Davis AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 826b44aa40fSMarkus Pargmann 8271d471cd1SJavier Martin return 0; 8281d471cd1SJavier Martin } 8291d471cd1SJavier Martin 8301d471cd1SJavier Martin static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 8311d471cd1SJavier Martin { 832b154dc5dSKuninori Morimoto struct snd_soc_component *component = dai->component; 8331d471cd1SJavier Martin 834b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 835b7ddd9caSAndrew F. Davis AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 836b7ddd9caSAndrew F. Davis 8371d471cd1SJavier Martin return 0; 8381d471cd1SJavier Martin } 8391d471cd1SJavier Martin 840b154dc5dSKuninori Morimoto static int aic32x4_set_bias_level(struct snd_soc_component *component, 8411d471cd1SJavier Martin enum snd_soc_bias_level level) 8421d471cd1SJavier Martin { 84398b664e2SMarkus Pargmann int ret; 84498b664e2SMarkus Pargmann 845d25970b5SAnnaliese McDermond struct clk_bulk_data clocks[] = { 846d25970b5SAnnaliese McDermond { .id = "madc" }, 847d25970b5SAnnaliese McDermond { .id = "mdac" }, 848d25970b5SAnnaliese McDermond { .id = "bdiv" }, 849d25970b5SAnnaliese McDermond }; 850d25970b5SAnnaliese McDermond 851d25970b5SAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 852d25970b5SAnnaliese McDermond if (ret) 853d25970b5SAnnaliese McDermond return ret; 854d25970b5SAnnaliese McDermond 8551d471cd1SJavier Martin switch (level) { 8561d471cd1SJavier Martin case SND_SOC_BIAS_ON: 857d25970b5SAnnaliese McDermond ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); 85898b664e2SMarkus Pargmann if (ret) { 859d25970b5SAnnaliese McDermond dev_err(component->dev, "Failed to enable clocks\n"); 86098b664e2SMarkus Pargmann return ret; 86198b664e2SMarkus Pargmann } 8621d471cd1SJavier Martin break; 8631d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE: 8641d471cd1SJavier Martin break; 8651d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY: 866667e9334Sb-ak /* Initial cold start */ 867667e9334Sb-ak if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 868667e9334Sb-ak break; 869667e9334Sb-ak 870d25970b5SAnnaliese McDermond clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); 8711d471cd1SJavier Martin break; 8721d471cd1SJavier Martin case SND_SOC_BIAS_OFF: 8731d471cd1SJavier Martin break; 8741d471cd1SJavier Martin } 8751d471cd1SJavier Martin return 0; 8761d471cd1SJavier Martin } 8771d471cd1SJavier Martin 8786d56ee15SAnnaliese McDermond #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 8791d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 8801d471cd1SJavier Martin | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 8811d471cd1SJavier Martin 88285e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = { 8831d471cd1SJavier Martin .hw_params = aic32x4_hw_params, 8841d471cd1SJavier Martin .digital_mute = aic32x4_mute, 8851d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt, 8861d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk, 8871d471cd1SJavier Martin }; 8881d471cd1SJavier Martin 8891d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = { 8901d471cd1SJavier Martin .name = "tlv320aic32x4-hifi", 8911d471cd1SJavier Martin .playback = { 8921d471cd1SJavier Martin .stream_name = "Playback", 8931d471cd1SJavier Martin .channels_min = 1, 8941d471cd1SJavier Martin .channels_max = 2, 8951d471cd1SJavier Martin .rates = AIC32X4_RATES, 8961d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 8971d471cd1SJavier Martin .capture = { 8981d471cd1SJavier Martin .stream_name = "Capture", 8991d471cd1SJavier Martin .channels_min = 1, 9001d471cd1SJavier Martin .channels_max = 2, 9011d471cd1SJavier Martin .rates = AIC32X4_RATES, 9021d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 9031d471cd1SJavier Martin .ops = &aic32x4_ops, 9041d471cd1SJavier Martin .symmetric_rates = 1, 9051d471cd1SJavier Martin }; 9061d471cd1SJavier Martin 907b154dc5dSKuninori Morimoto static void aic32x4_setup_gpios(struct snd_soc_component *component) 908b9045b9cSDan Murphy { 909b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 910b9045b9cSDan Murphy 911b9045b9cSDan Murphy /* setup GPIO functions */ 912b9045b9cSDan Murphy /* MFP1 */ 913b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 914b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DINCTL, 915b9045b9cSDan Murphy aic32x4->setup->gpio_func[0]); 916b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp1, 917b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp1)); 918b9045b9cSDan Murphy } 919b9045b9cSDan Murphy 920b9045b9cSDan Murphy /* MFP2 */ 921b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 922b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, 923b9045b9cSDan Murphy aic32x4->setup->gpio_func[1]); 924b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp2, 925b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp2)); 926b9045b9cSDan Murphy } 927b9045b9cSDan Murphy 928b9045b9cSDan Murphy /* MFP3 */ 929b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 930b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_SCLKCTL, 931b9045b9cSDan Murphy aic32x4->setup->gpio_func[2]); 932b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp3, 933b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp3)); 934b9045b9cSDan Murphy } 935b9045b9cSDan Murphy 936b9045b9cSDan Murphy /* MFP4 */ 937b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 938b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, 939b9045b9cSDan Murphy aic32x4->setup->gpio_func[3]); 940b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp4, 941b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp4)); 942b9045b9cSDan Murphy } 943b9045b9cSDan Murphy 944b9045b9cSDan Murphy /* MFP5 */ 945b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 946b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, 947b9045b9cSDan Murphy aic32x4->setup->gpio_func[4]); 948b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp5, 949b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp5)); 950b9045b9cSDan Murphy } 951b9045b9cSDan Murphy } 952b9045b9cSDan Murphy 953b154dc5dSKuninori Morimoto static int aic32x4_component_probe(struct snd_soc_component *component) 9541d471cd1SJavier Martin { 955b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 9561d471cd1SJavier Martin u32 tmp_reg; 957fd2df3aeSAnnaliese McDermond int ret; 958fd2df3aeSAnnaliese McDermond 959fd2df3aeSAnnaliese McDermond struct clk_bulk_data clocks[] = { 960fd2df3aeSAnnaliese McDermond { .id = "codec_clkin" }, 961a51b5006SAnnaliese McDermond { .id = "pll" }, 9629b484124SAnnaliese McDermond { .id = "bdiv" }, 9639b484124SAnnaliese McDermond { .id = "mdac" }, 964fd2df3aeSAnnaliese McDermond }; 965fd2df3aeSAnnaliese McDermond 966fd2df3aeSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 967fd2df3aeSAnnaliese McDermond if (ret) 968fd2df3aeSAnnaliese McDermond return ret; 9691d471cd1SJavier Martin 970a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 9711858fe97SJavier Martin ndelay(10); 9721858fe97SJavier Martin gpio_set_value(aic32x4->rstn_gpio, 1); 973674f9abdSPeter Seiderer mdelay(1); 9741858fe97SJavier Martin } 9751858fe97SJavier Martin 976b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RESET, 0x01); 9771d471cd1SJavier Martin 978b9045b9cSDan Murphy if (aic32x4->setup) 979b154dc5dSKuninori Morimoto aic32x4_setup_gpios(component); 980b9045b9cSDan Murphy 981fd2df3aeSAnnaliese McDermond clk_set_parent(clocks[0].clk, clocks[1].clk); 9829b484124SAnnaliese McDermond clk_set_parent(clocks[2].clk, clocks[3].clk); 983fd2df3aeSAnnaliese McDermond 9841d471cd1SJavier Martin /* Power platform configuration */ 9851d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 986514b044cSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_MICBIAS, 987514b044cSAnnaliese McDermond AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 9881d471cd1SJavier Martin } 989eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 990b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 9910c93a167SWolfram Sang 9920c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 9930c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0; 994b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 9950c93a167SWolfram Sang 996b154dc5dSKuninori Morimoto tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 997eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 9981d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36; 999eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 10001d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP; 1001b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 10021d471cd1SJavier Martin 10031d471cd1SJavier Martin /* Mic PGA routing */ 1004609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 1005b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 100643bf38baSShahina Shaik AIC32X4_LMICPGANIN_IN2R_10K); 1007609e6025SMarkus Pargmann else 1008b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 100943bf38baSShahina Shaik AIC32X4_LMICPGANIN_CM1L_10K); 1010609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 1011b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 101243bf38baSShahina Shaik AIC32X4_RMICPGANIN_IN1L_10K); 1013609e6025SMarkus Pargmann else 1014b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 101543bf38baSShahina Shaik AIC32X4_RMICPGANIN_CM1R_10K); 10161d471cd1SJavier Martin 1017a405387cSJavier Martin /* 1018a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up 1019a405387cSJavier Martin * and down for the first capture to work properly. It seems related to 1020a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet. 1021a405387cSJavier Martin */ 1022b154dc5dSKuninori Morimoto tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 1023b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1024a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1025b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1026a405387cSJavier Martin 10271d471cd1SJavier Martin return 0; 10281d471cd1SJavier Martin } 10291d471cd1SJavier Martin 1030b154dc5dSKuninori Morimoto static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1031b154dc5dSKuninori Morimoto .probe = aic32x4_component_probe, 10321d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level, 1033aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls, 1034aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1035aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets, 1036aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1037aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes, 1038aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1039b154dc5dSKuninori Morimoto .suspend_bias_off = 1, 1040b154dc5dSKuninori Morimoto .idle_bias_on = 1, 1041b154dc5dSKuninori Morimoto .use_pmdown_time = 1, 1042b154dc5dSKuninori Morimoto .endianness = 1, 1043b154dc5dSKuninori Morimoto .non_legacy_dai_naming = 1, 10441d471cd1SJavier Martin }; 10451d471cd1SJavier Martin 10464d16700dSMarkus Pargmann static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 10474d16700dSMarkus Pargmann struct device_node *np) 10484d16700dSMarkus Pargmann { 1049b9045b9cSDan Murphy struct aic32x4_setup_data *aic32x4_setup; 1050514b044cSAnnaliese McDermond int ret; 1051b9045b9cSDan Murphy 1052b9045b9cSDan Murphy aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1053b9045b9cSDan Murphy GFP_KERNEL); 1054b9045b9cSDan Murphy if (!aic32x4_setup) 1055b9045b9cSDan Murphy return -ENOMEM; 1056b9045b9cSDan Murphy 1057514b044cSAnnaliese McDermond ret = of_property_match_string(np, "clock-names", "mclk"); 1058514b044cSAnnaliese McDermond if (ret < 0) 1059514b044cSAnnaliese McDermond return -EINVAL; 1060514b044cSAnnaliese McDermond aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1061514b044cSAnnaliese McDermond 10624d16700dSMarkus Pargmann aic32x4->swapdacs = false; 10634d16700dSMarkus Pargmann aic32x4->micpga_routing = 0; 10644d16700dSMarkus Pargmann aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 10654d16700dSMarkus Pargmann 1066b9045b9cSDan Murphy if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1067b9045b9cSDan Murphy aic32x4_setup->gpio_func, 5) >= 0) 1068b9045b9cSDan Murphy aic32x4->setup = aic32x4_setup; 10694d16700dSMarkus Pargmann return 0; 10704d16700dSMarkus Pargmann } 10714d16700dSMarkus Pargmann 1072239b669bSMarkus Pargmann static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1073239b669bSMarkus Pargmann { 1074239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1075239b669bSMarkus Pargmann 1076239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1077239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1078239b669bSMarkus Pargmann 1079239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1080239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1081239b669bSMarkus Pargmann 1082239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) 1083239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_av); 1084239b669bSMarkus Pargmann } 1085239b669bSMarkus Pargmann 1086239b669bSMarkus Pargmann static int aic32x4_setup_regulators(struct device *dev, 1087239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4) 1088239b669bSMarkus Pargmann { 1089239b669bSMarkus Pargmann int ret = 0; 1090239b669bSMarkus Pargmann 1091239b669bSMarkus Pargmann aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1092239b669bSMarkus Pargmann aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1093239b669bSMarkus Pargmann aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1094239b669bSMarkus Pargmann aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1095239b669bSMarkus Pargmann 1096239b669bSMarkus Pargmann /* Check if the regulator requirements are fulfilled */ 1097239b669bSMarkus Pargmann 1098239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_iov)) { 1099239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'iov'\n"); 1100239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_iov); 1101239b669bSMarkus Pargmann } 1102239b669bSMarkus Pargmann 1103239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_ldo)) { 1104239b669bSMarkus Pargmann if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1105239b669bSMarkus Pargmann return -EPROBE_DEFER; 1106239b669bSMarkus Pargmann 1107239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv)) { 1108239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1109239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_dv); 1110239b669bSMarkus Pargmann } 1111239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av)) { 1112239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1113239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_av); 1114239b669bSMarkus Pargmann } 1115239b669bSMarkus Pargmann } else { 1116239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv) && 1117239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1118239b669bSMarkus Pargmann return -EPROBE_DEFER; 1119239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av) && 1120239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1121239b669bSMarkus Pargmann return -EPROBE_DEFER; 1122239b669bSMarkus Pargmann } 1123239b669bSMarkus Pargmann 1124239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_iov); 1125239b669bSMarkus Pargmann if (ret) { 1126239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator iov\n"); 1127239b669bSMarkus Pargmann return ret; 1128239b669bSMarkus Pargmann } 1129239b669bSMarkus Pargmann 1130239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) { 1131239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_ldo); 1132239b669bSMarkus Pargmann if (ret) { 1133239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator ldo\n"); 1134239b669bSMarkus Pargmann goto error_ldo; 1135239b669bSMarkus Pargmann } 1136239b669bSMarkus Pargmann } 1137239b669bSMarkus Pargmann 1138239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) { 1139239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_dv); 1140239b669bSMarkus Pargmann if (ret) { 1141239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator dv\n"); 1142239b669bSMarkus Pargmann goto error_dv; 1143239b669bSMarkus Pargmann } 1144239b669bSMarkus Pargmann } 1145239b669bSMarkus Pargmann 1146239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) { 1147239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_av); 1148239b669bSMarkus Pargmann if (ret) { 1149239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator av\n"); 1150239b669bSMarkus Pargmann goto error_av; 1151239b669bSMarkus Pargmann } 1152239b669bSMarkus Pargmann } 1153239b669bSMarkus Pargmann 1154239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1155239b669bSMarkus Pargmann aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1156239b669bSMarkus Pargmann 1157239b669bSMarkus Pargmann return 0; 1158239b669bSMarkus Pargmann 1159239b669bSMarkus Pargmann error_av: 1160239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1161239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1162239b669bSMarkus Pargmann 1163239b669bSMarkus Pargmann error_dv: 1164239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1165239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1166239b669bSMarkus Pargmann 1167239b669bSMarkus Pargmann error_ldo: 1168239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1169239b669bSMarkus Pargmann return ret; 1170239b669bSMarkus Pargmann } 1171239b669bSMarkus Pargmann 11723bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap) 11731d471cd1SJavier Martin { 11741d471cd1SJavier Martin struct aic32x4_priv *aic32x4; 11753bcfd222SJeremy McDermond struct aic32x4_pdata *pdata = dev->platform_data; 11763bcfd222SJeremy McDermond struct device_node *np = dev->of_node; 11771d471cd1SJavier Martin int ret; 11781d471cd1SJavier Martin 11793bcfd222SJeremy McDermond if (IS_ERR(regmap)) 11803bcfd222SJeremy McDermond return PTR_ERR(regmap); 11813bcfd222SJeremy McDermond 11823bcfd222SJeremy McDermond aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1183658ecf77SAxel Lin GFP_KERNEL); 11841d471cd1SJavier Martin if (aic32x4 == NULL) 11851d471cd1SJavier Martin return -ENOMEM; 11861d471cd1SJavier Martin 1187b9045b9cSDan Murphy aic32x4->dev = dev; 11883bcfd222SJeremy McDermond dev_set_drvdata(dev, aic32x4); 11891d471cd1SJavier Martin 11901d471cd1SJavier Martin if (pdata) { 11911d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg; 11921d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs; 11931d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing; 11941858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio; 1195514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 11964d16700dSMarkus Pargmann } else if (np) { 11974d16700dSMarkus Pargmann ret = aic32x4_parse_dt(aic32x4, np); 11984d16700dSMarkus Pargmann if (ret) { 11993bcfd222SJeremy McDermond dev_err(dev, "Failed to parse DT node\n"); 12004d16700dSMarkus Pargmann return ret; 12014d16700dSMarkus Pargmann } 12021d471cd1SJavier Martin } else { 12031d471cd1SJavier Martin aic32x4->power_cfg = 0; 12041d471cd1SJavier Martin aic32x4->swapdacs = false; 12051d471cd1SJavier Martin aic32x4->micpga_routing = 0; 12061858fe97SJavier Martin aic32x4->rstn_gpio = -1; 1207514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 12081d471cd1SJavier Martin } 12091d471cd1SJavier Martin 1210514b044cSAnnaliese McDermond ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1211514b044cSAnnaliese McDermond if (ret) 1212514b044cSAnnaliese McDermond return ret; 1213514b044cSAnnaliese McDermond 1214a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 12153bcfd222SJeremy McDermond ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1216752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1217752b7764SMark Brown if (ret != 0) 1218752b7764SMark Brown return ret; 1219752b7764SMark Brown } 1220752b7764SMark Brown 12213bcfd222SJeremy McDermond ret = aic32x4_setup_regulators(dev, aic32x4); 1222239b669bSMarkus Pargmann if (ret) { 12233bcfd222SJeremy McDermond dev_err(dev, "Failed to setup regulators\n"); 1224239b669bSMarkus Pargmann return ret; 1225239b669bSMarkus Pargmann } 1226239b669bSMarkus Pargmann 1227b154dc5dSKuninori Morimoto ret = devm_snd_soc_register_component(dev, 1228b154dc5dSKuninori Morimoto &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1229239b669bSMarkus Pargmann if (ret) { 1230b154dc5dSKuninori Morimoto dev_err(dev, "Failed to register component\n"); 1231239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 12321d471cd1SJavier Martin return ret; 12331d471cd1SJavier Martin } 12341d471cd1SJavier Martin 1235239b669bSMarkus Pargmann return 0; 1236239b669bSMarkus Pargmann } 12373bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_probe); 1238239b669bSMarkus Pargmann 12393bcfd222SJeremy McDermond int aic32x4_remove(struct device *dev) 12401d471cd1SJavier Martin { 12413bcfd222SJeremy McDermond struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1242239b669bSMarkus Pargmann 1243239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 1244239b669bSMarkus Pargmann 12451d471cd1SJavier Martin return 0; 12461d471cd1SJavier Martin } 12473bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_remove); 12481d471cd1SJavier Martin 12491d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 12501d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 12511d471cd1SJavier Martin MODULE_LICENSE("GPL"); 1252