11d471cd1SJavier Martin /* 21d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c 31d471cd1SJavier Martin * 41d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L. 51d471cd1SJavier Martin * 61d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com> 71d471cd1SJavier Martin * 81d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 91d471cd1SJavier Martin * 101d471cd1SJavier Martin * This program is free software; you can redistribute it and/or modify 111d471cd1SJavier Martin * it under the terms of the GNU General Public License as published by 121d471cd1SJavier Martin * the Free Software Foundation; either version 2 of the License, or 131d471cd1SJavier Martin * (at your option) any later version. 141d471cd1SJavier Martin * 151d471cd1SJavier Martin * This program is distributed in the hope that it will be useful, 161d471cd1SJavier Martin * but WITHOUT ANY WARRANTY; without even the implied warranty of 171d471cd1SJavier Martin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 181d471cd1SJavier Martin * GNU General Public License for more details. 191d471cd1SJavier Martin * 201d471cd1SJavier Martin * You should have received a copy of the GNU General Public License 211d471cd1SJavier Martin * along with this program; if not, write to the Free Software 221d471cd1SJavier Martin * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 231d471cd1SJavier Martin * MA 02110-1301, USA. 241d471cd1SJavier Martin */ 251d471cd1SJavier Martin 261d471cd1SJavier Martin #include <linux/module.h> 271d471cd1SJavier Martin #include <linux/moduleparam.h> 281d471cd1SJavier Martin #include <linux/init.h> 291d471cd1SJavier Martin #include <linux/delay.h> 301d471cd1SJavier Martin #include <linux/pm.h> 311858fe97SJavier Martin #include <linux/gpio.h> 324d16700dSMarkus Pargmann #include <linux/of_gpio.h> 331d471cd1SJavier Martin #include <linux/i2c.h> 341d471cd1SJavier Martin #include <linux/cdev.h> 351d471cd1SJavier Martin #include <linux/slab.h> 3698b664e2SMarkus Pargmann #include <linux/clk.h> 37239b669bSMarkus Pargmann #include <linux/regulator/consumer.h> 381d471cd1SJavier Martin 391d471cd1SJavier Martin #include <sound/tlv320aic32x4.h> 401d471cd1SJavier Martin #include <sound/core.h> 411d471cd1SJavier Martin #include <sound/pcm.h> 421d471cd1SJavier Martin #include <sound/pcm_params.h> 431d471cd1SJavier Martin #include <sound/soc.h> 441d471cd1SJavier Martin #include <sound/soc-dapm.h> 451d471cd1SJavier Martin #include <sound/initval.h> 461d471cd1SJavier Martin #include <sound/tlv.h> 471d471cd1SJavier Martin 481d471cd1SJavier Martin #include "tlv320aic32x4.h" 491d471cd1SJavier Martin 501d471cd1SJavier Martin struct aic32x4_rate_divs { 511d471cd1SJavier Martin u32 mclk; 521d471cd1SJavier Martin u32 rate; 531d471cd1SJavier Martin u8 p_val; 541d471cd1SJavier Martin u8 pll_j; 551d471cd1SJavier Martin u16 pll_d; 561d471cd1SJavier Martin u16 dosr; 571d471cd1SJavier Martin u8 ndac; 581d471cd1SJavier Martin u8 mdac; 591d471cd1SJavier Martin u8 aosr; 601d471cd1SJavier Martin u8 nadc; 611d471cd1SJavier Martin u8 madc; 621d471cd1SJavier Martin u8 blck_N; 631d471cd1SJavier Martin }; 641d471cd1SJavier Martin 651d471cd1SJavier Martin struct aic32x4_priv { 664d208ca4SMark Brown struct regmap *regmap; 671d471cd1SJavier Martin u32 sysclk; 681d471cd1SJavier Martin u32 power_cfg; 691d471cd1SJavier Martin u32 micpga_routing; 701d471cd1SJavier Martin bool swapdacs; 711858fe97SJavier Martin int rstn_gpio; 7298b664e2SMarkus Pargmann struct clk *mclk; 73239b669bSMarkus Pargmann 74239b669bSMarkus Pargmann struct regulator *supply_ldo; 75239b669bSMarkus Pargmann struct regulator *supply_iov; 76239b669bSMarkus Pargmann struct regulator *supply_dv; 77239b669bSMarkus Pargmann struct regulator *supply_av; 781d471cd1SJavier Martin }; 791d471cd1SJavier Martin 801d471cd1SJavier Martin /* 0dB min, 0.5dB steps */ 811d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 82c671e79dSMarkus Pargmann /* -63.5dB min, 0.5dB steps */ 83c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 84c671e79dSMarkus Pargmann /* -6dB min, 1dB steps */ 85c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 86c671e79dSMarkus Pargmann /* -12dB min, 0.5dB steps */ 87c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 881d471cd1SJavier Martin 891d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 90c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 91c671e79dSMarkus Pargmann AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 92c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 93c671e79dSMarkus Pargmann AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 94c671e79dSMarkus Pargmann tlv_driver_gain), 95c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 96c671e79dSMarkus Pargmann AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 97c671e79dSMarkus Pargmann tlv_driver_gain), 981d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 991d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1), 1001d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 1011d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1), 1021d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 1031d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1), 1041d471cd1SJavier Martin 1051d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 1061d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 1071d471cd1SJavier Martin 108c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 109c671e79dSMarkus Pargmann AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 1101d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 1111d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 1121d471cd1SJavier Martin 1131d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 1141d471cd1SJavier Martin 1151d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 1161d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 1171d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 1181d471cd1SJavier Martin 4, 0x07, 0), 1191d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 1201d471cd1SJavier Martin 0, 0x03, 0), 1211d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 1221d471cd1SJavier Martin 6, 0x03, 0), 1231d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 1241d471cd1SJavier Martin 1, 0x1F, 0), 1251d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 1261d471cd1SJavier Martin 0, 0x7F, 0), 1271d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 1281d471cd1SJavier Martin 3, 0x1F, 0), 1291d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 1301d471cd1SJavier Martin 3, 0x1F, 0), 1311d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 1321d471cd1SJavier Martin 0, 0x1F, 0), 1331d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 1341d471cd1SJavier Martin 0, 0x0F, 0), 1351d471cd1SJavier Martin }; 1361d471cd1SJavier Martin 1371d471cd1SJavier Martin static const struct aic32x4_rate_divs aic32x4_divs[] = { 1381d471cd1SJavier Martin /* 8k rate */ 1391d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24}, 1401d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24}, 1411d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24}, 1421d471cd1SJavier Martin /* 11.025k rate */ 1431d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16}, 1441d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16}, 1451d471cd1SJavier Martin /* 16k rate */ 1461d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12}, 1471d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12}, 1481d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12}, 1491d471cd1SJavier Martin /* 22.05k rate */ 1501d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8}, 1511d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8}, 1521d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8}, 1531d471cd1SJavier Martin /* 32k rate */ 1541d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6}, 1551d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6}, 1561d471cd1SJavier Martin /* 44.1k rate */ 1571d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4}, 1581d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4}, 1591d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4}, 1601d471cd1SJavier Martin /* 48k rate */ 1611d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4}, 1621d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4}, 1631d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4} 1641d471cd1SJavier Martin }; 1651d471cd1SJavier Martin 1661d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 1671d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 1681d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 1691d471cd1SJavier Martin }; 1701d471cd1SJavier Martin 1711d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 1721d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 1731d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 1741d471cd1SJavier Martin }; 1751d471cd1SJavier Martin 1761d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 1771d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 1781d471cd1SJavier Martin }; 1791d471cd1SJavier Martin 1801d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 1811d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 1821d471cd1SJavier Martin }; 1831d471cd1SJavier Martin 1841d471cd1SJavier Martin static const struct snd_kcontrol_new left_input_mixer_controls[] = { 1851d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0), 1861d471cd1SJavier Martin SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0), 1871d471cd1SJavier Martin SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0), 1881d471cd1SJavier Martin }; 1891d471cd1SJavier Martin 1901d471cd1SJavier Martin static const struct snd_kcontrol_new right_input_mixer_controls[] = { 1911d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0), 1921d471cd1SJavier Martin SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0), 1931d471cd1SJavier Martin SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0), 1941d471cd1SJavier Martin }; 1951d471cd1SJavier Martin 1961d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 1971d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 1981d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 1991d471cd1SJavier Martin &hpl_output_mixer_controls[0], 2001d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)), 2011d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 2021d471cd1SJavier Martin 2031d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 2041d471cd1SJavier Martin &lol_output_mixer_controls[0], 2051d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)), 2061d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 2071d471cd1SJavier Martin 2081d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 2091d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 2101d471cd1SJavier Martin &hpr_output_mixer_controls[0], 2111d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)), 2121d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 2131d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 2141d471cd1SJavier Martin &lor_output_mixer_controls[0], 2151d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)), 2161d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 2171d471cd1SJavier Martin SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0, 2181d471cd1SJavier Martin &left_input_mixer_controls[0], 2191d471cd1SJavier Martin ARRAY_SIZE(left_input_mixer_controls)), 2201d471cd1SJavier Martin SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0, 2211d471cd1SJavier Martin &right_input_mixer_controls[0], 2221d471cd1SJavier Martin ARRAY_SIZE(right_input_mixer_controls)), 2231d471cd1SJavier Martin SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 2241d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 2251d471cd1SJavier Martin SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0), 2261d471cd1SJavier Martin 2271d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"), 2281d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"), 2291d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"), 2301d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"), 2311d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"), 2321d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"), 2331d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"), 2341d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"), 2351d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"), 2361d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"), 2371d471cd1SJavier Martin }; 2381d471cd1SJavier Martin 2391d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 2401d471cd1SJavier Martin /* Left Output */ 2411d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 2421d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 2431d471cd1SJavier Martin 2441d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"}, 2451d471cd1SJavier Martin {"HPL", NULL, "HPL Power"}, 2461d471cd1SJavier Martin 2471d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 2481d471cd1SJavier Martin 2491d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"}, 2501d471cd1SJavier Martin {"LOL", NULL, "LOL Power"}, 2511d471cd1SJavier Martin 2521d471cd1SJavier Martin /* Right Output */ 2531d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 2541d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 2551d471cd1SJavier Martin 2561d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"}, 2571d471cd1SJavier Martin {"HPR", NULL, "HPR Power"}, 2581d471cd1SJavier Martin 2591d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 2601d471cd1SJavier Martin 2611d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"}, 2621d471cd1SJavier Martin {"LOR", NULL, "LOR Power"}, 2631d471cd1SJavier Martin 2641d471cd1SJavier Martin /* Left input */ 2651d471cd1SJavier Martin {"Left Input Mixer", "IN1_L P Switch", "IN1_L"}, 2661d471cd1SJavier Martin {"Left Input Mixer", "IN2_L P Switch", "IN2_L"}, 2671d471cd1SJavier Martin {"Left Input Mixer", "IN3_L P Switch", "IN3_L"}, 2681d471cd1SJavier Martin 2691d471cd1SJavier Martin {"Left ADC", NULL, "Left Input Mixer"}, 2701d471cd1SJavier Martin 2711d471cd1SJavier Martin /* Right Input */ 2721d471cd1SJavier Martin {"Right Input Mixer", "IN1_R P Switch", "IN1_R"}, 2731d471cd1SJavier Martin {"Right Input Mixer", "IN2_R P Switch", "IN2_R"}, 2741d471cd1SJavier Martin {"Right Input Mixer", "IN3_R P Switch", "IN3_R"}, 2751d471cd1SJavier Martin 2761d471cd1SJavier Martin {"Right ADC", NULL, "Right Input Mixer"}, 2771d471cd1SJavier Martin }; 2781d471cd1SJavier Martin 2794d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 2801d471cd1SJavier Martin { 2814d208ca4SMark Brown .selector_reg = 0, 2824d208ca4SMark Brown .selector_mask = 0xff, 2834d208ca4SMark Brown .window_start = 0, 2844d208ca4SMark Brown .window_len = 128, 285e8e08c52SMarkus Pargmann .range_min = 0, 2866d0d5103SMarkus Pargmann .range_max = AIC32X4_RMICPGAVOL, 2874d208ca4SMark Brown }, 2884d208ca4SMark Brown }; 2891d471cd1SJavier Martin 2904d208ca4SMark Brown static const struct regmap_config aic32x4_regmap = { 2914d208ca4SMark Brown .reg_bits = 8, 2924d208ca4SMark Brown .val_bits = 8, 2931d471cd1SJavier Martin 2944d208ca4SMark Brown .max_register = AIC32X4_RMICPGAVOL, 2954d208ca4SMark Brown .ranges = aic32x4_regmap_pages, 2964d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 2974d208ca4SMark Brown }; 2981d471cd1SJavier Martin 2991d471cd1SJavier Martin static inline int aic32x4_get_divs(int mclk, int rate) 3001d471cd1SJavier Martin { 3011d471cd1SJavier Martin int i; 3021d471cd1SJavier Martin 3031d471cd1SJavier Martin for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 3041d471cd1SJavier Martin if ((aic32x4_divs[i].rate == rate) 3051d471cd1SJavier Martin && (aic32x4_divs[i].mclk == mclk)) { 3061d471cd1SJavier Martin return i; 3071d471cd1SJavier Martin } 3081d471cd1SJavier Martin } 3091d471cd1SJavier Martin printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 3101d471cd1SJavier Martin return -EINVAL; 3111d471cd1SJavier Martin } 3121d471cd1SJavier Martin 3131d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 3141d471cd1SJavier Martin int clk_id, unsigned int freq, int dir) 3151d471cd1SJavier Martin { 3161d471cd1SJavier Martin struct snd_soc_codec *codec = codec_dai->codec; 3171d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 3181d471cd1SJavier Martin 3191d471cd1SJavier Martin switch (freq) { 3201d471cd1SJavier Martin case AIC32X4_FREQ_12000000: 3211d471cd1SJavier Martin case AIC32X4_FREQ_24000000: 3221d471cd1SJavier Martin case AIC32X4_FREQ_25000000: 3231d471cd1SJavier Martin aic32x4->sysclk = freq; 3241d471cd1SJavier Martin return 0; 3251d471cd1SJavier Martin } 3261d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 3271d471cd1SJavier Martin return -EINVAL; 3281d471cd1SJavier Martin } 3291d471cd1SJavier Martin 3301d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 3311d471cd1SJavier Martin { 3321d471cd1SJavier Martin struct snd_soc_codec *codec = codec_dai->codec; 3331d471cd1SJavier Martin u8 iface_reg_1; 3341d471cd1SJavier Martin u8 iface_reg_2; 3351d471cd1SJavier Martin u8 iface_reg_3; 3361d471cd1SJavier Martin 3371d471cd1SJavier Martin iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1); 3381d471cd1SJavier Martin iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2); 3391d471cd1SJavier Martin iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2); 3401d471cd1SJavier Martin iface_reg_2 = 0; 3411d471cd1SJavier Martin iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3); 3421d471cd1SJavier Martin iface_reg_3 = iface_reg_3 & ~(1 << 3); 3431d471cd1SJavier Martin 3441d471cd1SJavier Martin /* set master/slave audio interface */ 3451d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3461d471cd1SJavier Martin case SND_SOC_DAIFMT_CBM_CFM: 3471d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 3481d471cd1SJavier Martin break; 3491d471cd1SJavier Martin case SND_SOC_DAIFMT_CBS_CFS: 3501d471cd1SJavier Martin break; 3511d471cd1SJavier Martin default: 3521d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 3531d471cd1SJavier Martin return -EINVAL; 3541d471cd1SJavier Martin } 3551d471cd1SJavier Martin 3561d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3571d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S: 3581d471cd1SJavier Martin break; 3591d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A: 3601d471cd1SJavier Martin iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 3611d471cd1SJavier Martin iface_reg_3 |= (1 << 3); /* invert bit clock */ 3621d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */ 3631d471cd1SJavier Martin break; 3641d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B: 3651d471cd1SJavier Martin iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 3661d471cd1SJavier Martin iface_reg_3 |= (1 << 3); /* invert bit clock */ 3671d471cd1SJavier Martin break; 3681d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J: 3691d471cd1SJavier Martin iface_reg_1 |= 3701d471cd1SJavier Martin (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 3711d471cd1SJavier Martin break; 3721d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J: 3731d471cd1SJavier Martin iface_reg_1 |= 3741d471cd1SJavier Martin (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 3751d471cd1SJavier Martin break; 3761d471cd1SJavier Martin default: 3771d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 3781d471cd1SJavier Martin return -EINVAL; 3791d471cd1SJavier Martin } 3801d471cd1SJavier Martin 3811d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1); 3821d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2); 3831d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3); 3841d471cd1SJavier Martin return 0; 3851d471cd1SJavier Martin } 3861d471cd1SJavier Martin 3871d471cd1SJavier Martin static int aic32x4_hw_params(struct snd_pcm_substream *substream, 3881d471cd1SJavier Martin struct snd_pcm_hw_params *params, 3891d471cd1SJavier Martin struct snd_soc_dai *dai) 3901d471cd1SJavier Martin { 3911d471cd1SJavier Martin struct snd_soc_codec *codec = dai->codec; 3921d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 3931d471cd1SJavier Martin u8 data; 3941d471cd1SJavier Martin int i; 3951d471cd1SJavier Martin 3961d471cd1SJavier Martin i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params)); 3971d471cd1SJavier Martin if (i < 0) { 3981d471cd1SJavier Martin printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 3991d471cd1SJavier Martin return i; 4001d471cd1SJavier Martin } 4011d471cd1SJavier Martin 4021d471cd1SJavier Martin /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */ 4031d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN); 4041d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK); 4051d471cd1SJavier Martin 4061d471cd1SJavier Martin /* We will fix R value to 1 and will make P & J=K.D as varialble */ 4071d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_PLLPR); 4081d471cd1SJavier Martin data &= ~(7 << 4); 4091d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLPR, 4101d471cd1SJavier Martin (data | (aic32x4_divs[i].p_val << 4) | 0x01)); 4111d471cd1SJavier Martin 4121d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j); 4131d471cd1SJavier Martin 4141d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8)); 4151d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLDLSB, 4161d471cd1SJavier Martin (aic32x4_divs[i].pll_d & 0xff)); 4171d471cd1SJavier Martin 4181d471cd1SJavier Martin /* NDAC divider value */ 4191d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_NDAC); 4201d471cd1SJavier Martin data &= ~(0x7f); 4211d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac); 4221d471cd1SJavier Martin 4231d471cd1SJavier Martin /* MDAC divider value */ 4241d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_MDAC); 4251d471cd1SJavier Martin data &= ~(0x7f); 4261d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac); 4271d471cd1SJavier Martin 4281d471cd1SJavier Martin /* DOSR MSB & LSB values */ 4291d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 4301d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DOSRLSB, 4311d471cd1SJavier Martin (aic32x4_divs[i].dosr & 0xff)); 4321d471cd1SJavier Martin 4331d471cd1SJavier Martin /* NADC divider value */ 4341d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_NADC); 4351d471cd1SJavier Martin data &= ~(0x7f); 4361d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc); 4371d471cd1SJavier Martin 4381d471cd1SJavier Martin /* MADC divider value */ 4391d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_MADC); 4401d471cd1SJavier Martin data &= ~(0x7f); 4411d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc); 4421d471cd1SJavier Martin 4431d471cd1SJavier Martin /* AOSR value */ 4441d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr); 4451d471cd1SJavier Martin 4461d471cd1SJavier Martin /* BCLK N divider */ 4471d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_BCLKN); 4481d471cd1SJavier Martin data &= ~(0x7f); 4491d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N); 4501d471cd1SJavier Martin 4511d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_IFACE1); 4521d471cd1SJavier Martin data = data & ~(3 << 4); 453*bd8a5711SMark Brown switch (params_width(params)) { 454*bd8a5711SMark Brown case 16: 4551d471cd1SJavier Martin break; 456*bd8a5711SMark Brown case 20: 4571d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT); 4581d471cd1SJavier Martin break; 459*bd8a5711SMark Brown case 24: 4601d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT); 4611d471cd1SJavier Martin break; 462*bd8a5711SMark Brown case 32: 4631d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT); 4641d471cd1SJavier Martin break; 4651d471cd1SJavier Martin } 4661d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE1, data); 4671d471cd1SJavier Martin 468b44aa40fSMarkus Pargmann if (params_channels(params) == 1) { 469b44aa40fSMarkus Pargmann data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 470b44aa40fSMarkus Pargmann } else { 471b44aa40fSMarkus Pargmann if (aic32x4->swapdacs) 472b44aa40fSMarkus Pargmann data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 473b44aa40fSMarkus Pargmann else 474b44aa40fSMarkus Pargmann data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 475b44aa40fSMarkus Pargmann } 476b44aa40fSMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK, 477b44aa40fSMarkus Pargmann data); 478b44aa40fSMarkus Pargmann 4791d471cd1SJavier Martin return 0; 4801d471cd1SJavier Martin } 4811d471cd1SJavier Martin 4821d471cd1SJavier Martin static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 4831d471cd1SJavier Martin { 4841d471cd1SJavier Martin struct snd_soc_codec *codec = dai->codec; 4851d471cd1SJavier Martin u8 dac_reg; 4861d471cd1SJavier Martin 4871d471cd1SJavier Martin dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON; 4881d471cd1SJavier Martin if (mute) 4891d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON); 4901d471cd1SJavier Martin else 4911d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg); 4921d471cd1SJavier Martin return 0; 4931d471cd1SJavier Martin } 4941d471cd1SJavier Martin 4951d471cd1SJavier Martin static int aic32x4_set_bias_level(struct snd_soc_codec *codec, 4961d471cd1SJavier Martin enum snd_soc_bias_level level) 4971d471cd1SJavier Martin { 49898b664e2SMarkus Pargmann struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 49998b664e2SMarkus Pargmann int ret; 50098b664e2SMarkus Pargmann 5011d471cd1SJavier Martin switch (level) { 5021d471cd1SJavier Martin case SND_SOC_BIAS_ON: 50398b664e2SMarkus Pargmann /* Switch on master clock */ 50498b664e2SMarkus Pargmann ret = clk_prepare_enable(aic32x4->mclk); 50598b664e2SMarkus Pargmann if (ret) { 50698b664e2SMarkus Pargmann dev_err(codec->dev, "Failed to enable master clock\n"); 50798b664e2SMarkus Pargmann return ret; 50898b664e2SMarkus Pargmann } 50998b664e2SMarkus Pargmann 5101d471cd1SJavier Martin /* Switch on PLL */ 511bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_PLLPR, 512bc6ae96aSAxel Lin AIC32X4_PLLEN, AIC32X4_PLLEN); 5131d471cd1SJavier Martin 5141d471cd1SJavier Martin /* Switch on NDAC Divider */ 515bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NDAC, 516bc6ae96aSAxel Lin AIC32X4_NDACEN, AIC32X4_NDACEN); 5171d471cd1SJavier Martin 5181d471cd1SJavier Martin /* Switch on MDAC Divider */ 519bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MDAC, 520bc6ae96aSAxel Lin AIC32X4_MDACEN, AIC32X4_MDACEN); 5211d471cd1SJavier Martin 5221d471cd1SJavier Martin /* Switch on NADC Divider */ 523bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NADC, 524bc6ae96aSAxel Lin AIC32X4_NADCEN, AIC32X4_NADCEN); 5251d471cd1SJavier Martin 5261d471cd1SJavier Martin /* Switch on MADC Divider */ 527bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MADC, 528bc6ae96aSAxel Lin AIC32X4_MADCEN, AIC32X4_MADCEN); 5291d471cd1SJavier Martin 5301d471cd1SJavier Martin /* Switch on BCLK_N Divider */ 531bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_BCLKN, 532bc6ae96aSAxel Lin AIC32X4_BCLKEN, AIC32X4_BCLKEN); 5331d471cd1SJavier Martin break; 5341d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE: 5351d471cd1SJavier Martin break; 5361d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY: 5373154cc74SMarkus Pargmann /* Switch off BCLK_N Divider */ 5383154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_BCLKN, 5393154cc74SMarkus Pargmann AIC32X4_BCLKEN, 0); 5401d471cd1SJavier Martin 5411d471cd1SJavier Martin /* Switch off MADC Divider */ 542bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MADC, 543bc6ae96aSAxel Lin AIC32X4_MADCEN, 0); 5441d471cd1SJavier Martin 5453154cc74SMarkus Pargmann /* Switch off NADC Divider */ 5463154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_NADC, 5473154cc74SMarkus Pargmann AIC32X4_NADCEN, 0); 5483154cc74SMarkus Pargmann 5493154cc74SMarkus Pargmann /* Switch off MDAC Divider */ 5503154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_MDAC, 5513154cc74SMarkus Pargmann AIC32X4_MDACEN, 0); 5523154cc74SMarkus Pargmann 5533154cc74SMarkus Pargmann /* Switch off NDAC Divider */ 5543154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_NDAC, 5553154cc74SMarkus Pargmann AIC32X4_NDACEN, 0); 5563154cc74SMarkus Pargmann 5573154cc74SMarkus Pargmann /* Switch off PLL */ 5583154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_PLLPR, 5593154cc74SMarkus Pargmann AIC32X4_PLLEN, 0); 56098b664e2SMarkus Pargmann 56198b664e2SMarkus Pargmann /* Switch off master clock */ 56298b664e2SMarkus Pargmann clk_disable_unprepare(aic32x4->mclk); 5631d471cd1SJavier Martin break; 5641d471cd1SJavier Martin case SND_SOC_BIAS_OFF: 5651d471cd1SJavier Martin break; 5661d471cd1SJavier Martin } 56720d66065SMark Brown codec->dapm.bias_level = level; 5681d471cd1SJavier Martin return 0; 5691d471cd1SJavier Martin } 5701d471cd1SJavier Martin 5711d471cd1SJavier Martin #define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000 5721d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 5731d471cd1SJavier Martin | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 5741d471cd1SJavier Martin 57585e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = { 5761d471cd1SJavier Martin .hw_params = aic32x4_hw_params, 5771d471cd1SJavier Martin .digital_mute = aic32x4_mute, 5781d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt, 5791d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk, 5801d471cd1SJavier Martin }; 5811d471cd1SJavier Martin 5821d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = { 5831d471cd1SJavier Martin .name = "tlv320aic32x4-hifi", 5841d471cd1SJavier Martin .playback = { 5851d471cd1SJavier Martin .stream_name = "Playback", 5861d471cd1SJavier Martin .channels_min = 1, 5871d471cd1SJavier Martin .channels_max = 2, 5881d471cd1SJavier Martin .rates = AIC32X4_RATES, 5891d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 5901d471cd1SJavier Martin .capture = { 5911d471cd1SJavier Martin .stream_name = "Capture", 5921d471cd1SJavier Martin .channels_min = 1, 5931d471cd1SJavier Martin .channels_max = 2, 5941d471cd1SJavier Martin .rates = AIC32X4_RATES, 5951d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 5961d471cd1SJavier Martin .ops = &aic32x4_ops, 5971d471cd1SJavier Martin .symmetric_rates = 1, 5981d471cd1SJavier Martin }; 5991d471cd1SJavier Martin 60084b315eeSLars-Peter Clausen static int aic32x4_suspend(struct snd_soc_codec *codec) 6011d471cd1SJavier Martin { 6021d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 6031d471cd1SJavier Martin return 0; 6041d471cd1SJavier Martin } 6051d471cd1SJavier Martin 6061d471cd1SJavier Martin static int aic32x4_resume(struct snd_soc_codec *codec) 6071d471cd1SJavier Martin { 6081d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 6091d471cd1SJavier Martin return 0; 6101d471cd1SJavier Martin } 6111d471cd1SJavier Martin 6121d471cd1SJavier Martin static int aic32x4_probe(struct snd_soc_codec *codec) 6131d471cd1SJavier Martin { 6141d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 6151d471cd1SJavier Martin u32 tmp_reg; 6161d471cd1SJavier Martin 617a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 6181858fe97SJavier Martin ndelay(10); 6191858fe97SJavier Martin gpio_set_value(aic32x4->rstn_gpio, 1); 6201858fe97SJavier Martin } 6211858fe97SJavier Martin 6221d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_RESET, 0x01); 6231d471cd1SJavier Martin 6241d471cd1SJavier Martin /* Power platform configuration */ 6251d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 6261d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN | 6271d471cd1SJavier Martin AIC32X4_MICBIAS_2075V); 6281d471cd1SJavier Martin } 6291d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) { 6301d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 6311d471cd1SJavier Martin } 6320c93a167SWolfram Sang 6330c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 6340c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0; 6350c93a167SWolfram Sang snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg); 6360c93a167SWolfram Sang 6371d471cd1SJavier Martin tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE); 6381d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) { 6391d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36; 6401d471cd1SJavier Martin } 6411d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) { 6421d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP; 6431d471cd1SJavier Martin } 6441d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg); 6451d471cd1SJavier Martin 6461d471cd1SJavier Martin /* Mic PGA routing */ 647609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 6481d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K); 649609e6025SMarkus Pargmann else 650609e6025SMarkus Pargmann snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_CM1L_10K); 651609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 6521d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K); 653609e6025SMarkus Pargmann else 654609e6025SMarkus Pargmann snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_CM1R_10K); 6551d471cd1SJavier Martin 6561d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 6571d471cd1SJavier Martin 658a405387cSJavier Martin /* 659a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up 660a405387cSJavier Martin * and down for the first capture to work properly. It seems related to 661a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet. 662a405387cSJavier Martin */ 663a405387cSJavier Martin tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP); 664a405387cSJavier Martin snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg | 665a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN); 666a405387cSJavier Martin snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg); 667a405387cSJavier Martin 6681d471cd1SJavier Martin return 0; 6691d471cd1SJavier Martin } 6701d471cd1SJavier Martin 6711d471cd1SJavier Martin static int aic32x4_remove(struct snd_soc_codec *codec) 6721d471cd1SJavier Martin { 6731d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 6741d471cd1SJavier Martin return 0; 6751d471cd1SJavier Martin } 6761d471cd1SJavier Martin 6771d471cd1SJavier Martin static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = { 6781d471cd1SJavier Martin .probe = aic32x4_probe, 6791d471cd1SJavier Martin .remove = aic32x4_remove, 6801d471cd1SJavier Martin .suspend = aic32x4_suspend, 6811d471cd1SJavier Martin .resume = aic32x4_resume, 6821d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level, 683aac97b5fSLars-Peter Clausen 684aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls, 685aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 686aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets, 687aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 688aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes, 689aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 6901d471cd1SJavier Martin }; 6911d471cd1SJavier Martin 6924d16700dSMarkus Pargmann static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 6934d16700dSMarkus Pargmann struct device_node *np) 6944d16700dSMarkus Pargmann { 6954d16700dSMarkus Pargmann aic32x4->swapdacs = false; 6964d16700dSMarkus Pargmann aic32x4->micpga_routing = 0; 6974d16700dSMarkus Pargmann aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 6984d16700dSMarkus Pargmann 6994d16700dSMarkus Pargmann return 0; 7004d16700dSMarkus Pargmann } 7014d16700dSMarkus Pargmann 702239b669bSMarkus Pargmann static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 703239b669bSMarkus Pargmann { 704239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 705239b669bSMarkus Pargmann 706239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 707239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 708239b669bSMarkus Pargmann 709239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 710239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 711239b669bSMarkus Pargmann 712239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) 713239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_av); 714239b669bSMarkus Pargmann } 715239b669bSMarkus Pargmann 716239b669bSMarkus Pargmann static int aic32x4_setup_regulators(struct device *dev, 717239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4) 718239b669bSMarkus Pargmann { 719239b669bSMarkus Pargmann int ret = 0; 720239b669bSMarkus Pargmann 721239b669bSMarkus Pargmann aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 722239b669bSMarkus Pargmann aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 723239b669bSMarkus Pargmann aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 724239b669bSMarkus Pargmann aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 725239b669bSMarkus Pargmann 726239b669bSMarkus Pargmann /* Check if the regulator requirements are fulfilled */ 727239b669bSMarkus Pargmann 728239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_iov)) { 729239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'iov'\n"); 730239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_iov); 731239b669bSMarkus Pargmann } 732239b669bSMarkus Pargmann 733239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_ldo)) { 734239b669bSMarkus Pargmann if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 735239b669bSMarkus Pargmann return -EPROBE_DEFER; 736239b669bSMarkus Pargmann 737239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv)) { 738239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 739239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_dv); 740239b669bSMarkus Pargmann } 741239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av)) { 742239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 743239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_av); 744239b669bSMarkus Pargmann } 745239b669bSMarkus Pargmann } else { 746239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv) && 747239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 748239b669bSMarkus Pargmann return -EPROBE_DEFER; 749239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av) && 750239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 751239b669bSMarkus Pargmann return -EPROBE_DEFER; 752239b669bSMarkus Pargmann } 753239b669bSMarkus Pargmann 754239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_iov); 755239b669bSMarkus Pargmann if (ret) { 756239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator iov\n"); 757239b669bSMarkus Pargmann return ret; 758239b669bSMarkus Pargmann } 759239b669bSMarkus Pargmann 760239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) { 761239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_ldo); 762239b669bSMarkus Pargmann if (ret) { 763239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator ldo\n"); 764239b669bSMarkus Pargmann goto error_ldo; 765239b669bSMarkus Pargmann } 766239b669bSMarkus Pargmann } 767239b669bSMarkus Pargmann 768239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) { 769239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_dv); 770239b669bSMarkus Pargmann if (ret) { 771239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator dv\n"); 772239b669bSMarkus Pargmann goto error_dv; 773239b669bSMarkus Pargmann } 774239b669bSMarkus Pargmann } 775239b669bSMarkus Pargmann 776239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) { 777239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_av); 778239b669bSMarkus Pargmann if (ret) { 779239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator av\n"); 780239b669bSMarkus Pargmann goto error_av; 781239b669bSMarkus Pargmann } 782239b669bSMarkus Pargmann } 783239b669bSMarkus Pargmann 784239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 785239b669bSMarkus Pargmann aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 786239b669bSMarkus Pargmann 787239b669bSMarkus Pargmann return 0; 788239b669bSMarkus Pargmann 789239b669bSMarkus Pargmann error_av: 790239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 791239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 792239b669bSMarkus Pargmann 793239b669bSMarkus Pargmann error_dv: 794239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 795239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 796239b669bSMarkus Pargmann 797239b669bSMarkus Pargmann error_ldo: 798239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 799239b669bSMarkus Pargmann return ret; 800239b669bSMarkus Pargmann } 801239b669bSMarkus Pargmann 8027a79e94eSBill Pemberton static int aic32x4_i2c_probe(struct i2c_client *i2c, 8031d471cd1SJavier Martin const struct i2c_device_id *id) 8041d471cd1SJavier Martin { 8051d471cd1SJavier Martin struct aic32x4_pdata *pdata = i2c->dev.platform_data; 8061d471cd1SJavier Martin struct aic32x4_priv *aic32x4; 8074d16700dSMarkus Pargmann struct device_node *np = i2c->dev.of_node; 8081d471cd1SJavier Martin int ret; 8091d471cd1SJavier Martin 810658ecf77SAxel Lin aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv), 811658ecf77SAxel Lin GFP_KERNEL); 8121d471cd1SJavier Martin if (aic32x4 == NULL) 8131d471cd1SJavier Martin return -ENOMEM; 8141d471cd1SJavier Martin 8154d208ca4SMark Brown aic32x4->regmap = devm_regmap_init_i2c(i2c, &aic32x4_regmap); 8164d208ca4SMark Brown if (IS_ERR(aic32x4->regmap)) 8174d208ca4SMark Brown return PTR_ERR(aic32x4->regmap); 8184d208ca4SMark Brown 8191d471cd1SJavier Martin i2c_set_clientdata(i2c, aic32x4); 8201d471cd1SJavier Martin 8211d471cd1SJavier Martin if (pdata) { 8221d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg; 8231d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs; 8241d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing; 8251858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio; 8264d16700dSMarkus Pargmann } else if (np) { 8274d16700dSMarkus Pargmann ret = aic32x4_parse_dt(aic32x4, np); 8284d16700dSMarkus Pargmann if (ret) { 8294d16700dSMarkus Pargmann dev_err(&i2c->dev, "Failed to parse DT node\n"); 8304d16700dSMarkus Pargmann return ret; 8314d16700dSMarkus Pargmann } 8321d471cd1SJavier Martin } else { 8331d471cd1SJavier Martin aic32x4->power_cfg = 0; 8341d471cd1SJavier Martin aic32x4->swapdacs = false; 8351d471cd1SJavier Martin aic32x4->micpga_routing = 0; 8361858fe97SJavier Martin aic32x4->rstn_gpio = -1; 8371d471cd1SJavier Martin } 8381d471cd1SJavier Martin 83998b664e2SMarkus Pargmann aic32x4->mclk = devm_clk_get(&i2c->dev, "mclk"); 84098b664e2SMarkus Pargmann if (IS_ERR(aic32x4->mclk)) { 84198b664e2SMarkus Pargmann dev_err(&i2c->dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n"); 84298b664e2SMarkus Pargmann return PTR_ERR(aic32x4->mclk); 84398b664e2SMarkus Pargmann } 84498b664e2SMarkus Pargmann 845a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 846752b7764SMark Brown ret = devm_gpio_request_one(&i2c->dev, aic32x4->rstn_gpio, 847752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 848752b7764SMark Brown if (ret != 0) 849752b7764SMark Brown return ret; 850752b7764SMark Brown } 851752b7764SMark Brown 852239b669bSMarkus Pargmann ret = aic32x4_setup_regulators(&i2c->dev, aic32x4); 853239b669bSMarkus Pargmann if (ret) { 854239b669bSMarkus Pargmann dev_err(&i2c->dev, "Failed to setup regulators\n"); 855239b669bSMarkus Pargmann return ret; 856239b669bSMarkus Pargmann } 857239b669bSMarkus Pargmann 8581d471cd1SJavier Martin ret = snd_soc_register_codec(&i2c->dev, 8591d471cd1SJavier Martin &soc_codec_dev_aic32x4, &aic32x4_dai, 1); 860239b669bSMarkus Pargmann if (ret) { 861239b669bSMarkus Pargmann dev_err(&i2c->dev, "Failed to register codec\n"); 862239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 8631d471cd1SJavier Martin return ret; 8641d471cd1SJavier Martin } 8651d471cd1SJavier Martin 866239b669bSMarkus Pargmann i2c_set_clientdata(i2c, aic32x4); 867239b669bSMarkus Pargmann 868239b669bSMarkus Pargmann return 0; 869239b669bSMarkus Pargmann } 870239b669bSMarkus Pargmann 8717a79e94eSBill Pemberton static int aic32x4_i2c_remove(struct i2c_client *client) 8721d471cd1SJavier Martin { 873239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4 = i2c_get_clientdata(client); 874239b669bSMarkus Pargmann 875239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 876239b669bSMarkus Pargmann 8771d471cd1SJavier Martin snd_soc_unregister_codec(&client->dev); 8781d471cd1SJavier Martin return 0; 8791d471cd1SJavier Martin } 8801d471cd1SJavier Martin 8811d471cd1SJavier Martin static const struct i2c_device_id aic32x4_i2c_id[] = { 8821d471cd1SJavier Martin { "tlv320aic32x4", 0 }, 8831d471cd1SJavier Martin { } 8841d471cd1SJavier Martin }; 8851d471cd1SJavier Martin MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id); 8861d471cd1SJavier Martin 8874d16700dSMarkus Pargmann static const struct of_device_id aic32x4_of_id[] = { 8884d16700dSMarkus Pargmann { .compatible = "ti,tlv320aic32x4", }, 8894d16700dSMarkus Pargmann { /* senitel */ } 8904d16700dSMarkus Pargmann }; 8914d16700dSMarkus Pargmann MODULE_DEVICE_TABLE(of, aic32x4_of_id); 8924d16700dSMarkus Pargmann 8931d471cd1SJavier Martin static struct i2c_driver aic32x4_i2c_driver = { 8941d471cd1SJavier Martin .driver = { 8951d471cd1SJavier Martin .name = "tlv320aic32x4", 8961d471cd1SJavier Martin .owner = THIS_MODULE, 8974d16700dSMarkus Pargmann .of_match_table = aic32x4_of_id, 8981d471cd1SJavier Martin }, 8991d471cd1SJavier Martin .probe = aic32x4_i2c_probe, 9007a79e94eSBill Pemberton .remove = aic32x4_i2c_remove, 9011d471cd1SJavier Martin .id_table = aic32x4_i2c_id, 9021d471cd1SJavier Martin }; 9031d471cd1SJavier Martin 9043b09efd1SSachin Kamat module_i2c_driver(aic32x4_i2c_driver); 9051d471cd1SJavier Martin 9061d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 9071d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 9081d471cd1SJavier Martin MODULE_LICENSE("GPL"); 909