11d471cd1SJavier Martin /* 21d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c 31d471cd1SJavier Martin * 41d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L. 51d471cd1SJavier Martin * 61d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com> 71d471cd1SJavier Martin * 81d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 91d471cd1SJavier Martin * 101d471cd1SJavier Martin * This program is free software; you can redistribute it and/or modify 111d471cd1SJavier Martin * it under the terms of the GNU General Public License as published by 121d471cd1SJavier Martin * the Free Software Foundation; either version 2 of the License, or 131d471cd1SJavier Martin * (at your option) any later version. 141d471cd1SJavier Martin * 151d471cd1SJavier Martin * This program is distributed in the hope that it will be useful, 161d471cd1SJavier Martin * but WITHOUT ANY WARRANTY; without even the implied warranty of 171d471cd1SJavier Martin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 181d471cd1SJavier Martin * GNU General Public License for more details. 191d471cd1SJavier Martin * 201d471cd1SJavier Martin * You should have received a copy of the GNU General Public License 211d471cd1SJavier Martin * along with this program; if not, write to the Free Software 221d471cd1SJavier Martin * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 231d471cd1SJavier Martin * MA 02110-1301, USA. 241d471cd1SJavier Martin */ 251d471cd1SJavier Martin 261d471cd1SJavier Martin #include <linux/module.h> 271d471cd1SJavier Martin #include <linux/moduleparam.h> 281d471cd1SJavier Martin #include <linux/init.h> 291d471cd1SJavier Martin #include <linux/delay.h> 301d471cd1SJavier Martin #include <linux/pm.h> 311858fe97SJavier Martin #include <linux/gpio.h> 321d471cd1SJavier Martin #include <linux/i2c.h> 331d471cd1SJavier Martin #include <linux/cdev.h> 341d471cd1SJavier Martin #include <linux/slab.h> 351d471cd1SJavier Martin 361d471cd1SJavier Martin #include <sound/tlv320aic32x4.h> 371d471cd1SJavier Martin #include <sound/core.h> 381d471cd1SJavier Martin #include <sound/pcm.h> 391d471cd1SJavier Martin #include <sound/pcm_params.h> 401d471cd1SJavier Martin #include <sound/soc.h> 411d471cd1SJavier Martin #include <sound/soc-dapm.h> 421d471cd1SJavier Martin #include <sound/initval.h> 431d471cd1SJavier Martin #include <sound/tlv.h> 441d471cd1SJavier Martin 451d471cd1SJavier Martin #include "tlv320aic32x4.h" 461d471cd1SJavier Martin 471d471cd1SJavier Martin struct aic32x4_rate_divs { 481d471cd1SJavier Martin u32 mclk; 491d471cd1SJavier Martin u32 rate; 501d471cd1SJavier Martin u8 p_val; 511d471cd1SJavier Martin u8 pll_j; 521d471cd1SJavier Martin u16 pll_d; 531d471cd1SJavier Martin u16 dosr; 541d471cd1SJavier Martin u8 ndac; 551d471cd1SJavier Martin u8 mdac; 561d471cd1SJavier Martin u8 aosr; 571d471cd1SJavier Martin u8 nadc; 581d471cd1SJavier Martin u8 madc; 591d471cd1SJavier Martin u8 blck_N; 601d471cd1SJavier Martin }; 611d471cd1SJavier Martin 621d471cd1SJavier Martin struct aic32x4_priv { 634d208ca4SMark Brown struct regmap *regmap; 641d471cd1SJavier Martin u32 sysclk; 651d471cd1SJavier Martin u32 power_cfg; 661d471cd1SJavier Martin u32 micpga_routing; 671d471cd1SJavier Martin bool swapdacs; 681858fe97SJavier Martin int rstn_gpio; 691d471cd1SJavier Martin }; 701d471cd1SJavier Martin 711d471cd1SJavier Martin /* 0dB min, 1dB steps */ 721d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0); 731d471cd1SJavier Martin /* 0dB min, 0.5dB steps */ 741d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 751d471cd1SJavier Martin 761d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 771d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 781d471cd1SJavier Martin AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5), 791d471cd1SJavier Martin SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 801d471cd1SJavier Martin AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1), 811d471cd1SJavier Martin SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 821d471cd1SJavier Martin AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1), 831d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 841d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1), 851d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 861d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1), 871d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 881d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1), 891d471cd1SJavier Martin 901d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 911d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 921d471cd1SJavier Martin 931d471cd1SJavier Martin SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL, 941d471cd1SJavier Martin AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5), 951d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 961d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 971d471cd1SJavier Martin 981d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 991d471cd1SJavier Martin 1001d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 1011d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 1021d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 1031d471cd1SJavier Martin 4, 0x07, 0), 1041d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 1051d471cd1SJavier Martin 0, 0x03, 0), 1061d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 1071d471cd1SJavier Martin 6, 0x03, 0), 1081d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 1091d471cd1SJavier Martin 1, 0x1F, 0), 1101d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 1111d471cd1SJavier Martin 0, 0x7F, 0), 1121d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 1131d471cd1SJavier Martin 3, 0x1F, 0), 1141d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 1151d471cd1SJavier Martin 3, 0x1F, 0), 1161d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 1171d471cd1SJavier Martin 0, 0x1F, 0), 1181d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 1191d471cd1SJavier Martin 0, 0x0F, 0), 1201d471cd1SJavier Martin }; 1211d471cd1SJavier Martin 1221d471cd1SJavier Martin static const struct aic32x4_rate_divs aic32x4_divs[] = { 1231d471cd1SJavier Martin /* 8k rate */ 1241d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24}, 1251d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24}, 1261d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24}, 1271d471cd1SJavier Martin /* 11.025k rate */ 1281d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16}, 1291d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16}, 1301d471cd1SJavier Martin /* 16k rate */ 1311d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12}, 1321d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12}, 1331d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12}, 1341d471cd1SJavier Martin /* 22.05k rate */ 1351d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8}, 1361d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8}, 1371d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8}, 1381d471cd1SJavier Martin /* 32k rate */ 1391d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6}, 1401d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6}, 1411d471cd1SJavier Martin /* 44.1k rate */ 1421d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4}, 1431d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4}, 1441d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4}, 1451d471cd1SJavier Martin /* 48k rate */ 1461d471cd1SJavier Martin {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4}, 1471d471cd1SJavier Martin {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4}, 1481d471cd1SJavier Martin {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4} 1491d471cd1SJavier Martin }; 1501d471cd1SJavier Martin 1511d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 1521d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 1531d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 1541d471cd1SJavier Martin }; 1551d471cd1SJavier Martin 1561d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 1571d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 1581d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 1591d471cd1SJavier Martin }; 1601d471cd1SJavier Martin 1611d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 1621d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 1631d471cd1SJavier Martin }; 1641d471cd1SJavier Martin 1651d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 1661d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 1671d471cd1SJavier Martin }; 1681d471cd1SJavier Martin 1691d471cd1SJavier Martin static const struct snd_kcontrol_new left_input_mixer_controls[] = { 1701d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0), 1711d471cd1SJavier Martin SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0), 1721d471cd1SJavier Martin SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0), 1731d471cd1SJavier Martin }; 1741d471cd1SJavier Martin 1751d471cd1SJavier Martin static const struct snd_kcontrol_new right_input_mixer_controls[] = { 1761d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0), 1771d471cd1SJavier Martin SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0), 1781d471cd1SJavier Martin SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0), 1791d471cd1SJavier Martin }; 1801d471cd1SJavier Martin 1811d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 1821d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 1831d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 1841d471cd1SJavier Martin &hpl_output_mixer_controls[0], 1851d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)), 1861d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 1871d471cd1SJavier Martin 1881d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 1891d471cd1SJavier Martin &lol_output_mixer_controls[0], 1901d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)), 1911d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 1921d471cd1SJavier Martin 1931d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 1941d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 1951d471cd1SJavier Martin &hpr_output_mixer_controls[0], 1961d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)), 1971d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 1981d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 1991d471cd1SJavier Martin &lor_output_mixer_controls[0], 2001d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)), 2011d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 2021d471cd1SJavier Martin SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0, 2031d471cd1SJavier Martin &left_input_mixer_controls[0], 2041d471cd1SJavier Martin ARRAY_SIZE(left_input_mixer_controls)), 2051d471cd1SJavier Martin SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0, 2061d471cd1SJavier Martin &right_input_mixer_controls[0], 2071d471cd1SJavier Martin ARRAY_SIZE(right_input_mixer_controls)), 2081d471cd1SJavier Martin SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 2091d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 2101d471cd1SJavier Martin SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0), 2111d471cd1SJavier Martin 2121d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"), 2131d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"), 2141d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"), 2151d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"), 2161d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"), 2171d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"), 2181d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"), 2191d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"), 2201d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"), 2211d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"), 2221d471cd1SJavier Martin }; 2231d471cd1SJavier Martin 2241d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 2251d471cd1SJavier Martin /* Left Output */ 2261d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 2271d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 2281d471cd1SJavier Martin 2291d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"}, 2301d471cd1SJavier Martin {"HPL", NULL, "HPL Power"}, 2311d471cd1SJavier Martin 2321d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 2331d471cd1SJavier Martin 2341d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"}, 2351d471cd1SJavier Martin {"LOL", NULL, "LOL Power"}, 2361d471cd1SJavier Martin 2371d471cd1SJavier Martin /* Right Output */ 2381d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 2391d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 2401d471cd1SJavier Martin 2411d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"}, 2421d471cd1SJavier Martin {"HPR", NULL, "HPR Power"}, 2431d471cd1SJavier Martin 2441d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 2451d471cd1SJavier Martin 2461d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"}, 2471d471cd1SJavier Martin {"LOR", NULL, "LOR Power"}, 2481d471cd1SJavier Martin 2491d471cd1SJavier Martin /* Left input */ 2501d471cd1SJavier Martin {"Left Input Mixer", "IN1_L P Switch", "IN1_L"}, 2511d471cd1SJavier Martin {"Left Input Mixer", "IN2_L P Switch", "IN2_L"}, 2521d471cd1SJavier Martin {"Left Input Mixer", "IN3_L P Switch", "IN3_L"}, 2531d471cd1SJavier Martin 2541d471cd1SJavier Martin {"Left ADC", NULL, "Left Input Mixer"}, 2551d471cd1SJavier Martin 2561d471cd1SJavier Martin /* Right Input */ 2571d471cd1SJavier Martin {"Right Input Mixer", "IN1_R P Switch", "IN1_R"}, 2581d471cd1SJavier Martin {"Right Input Mixer", "IN2_R P Switch", "IN2_R"}, 2591d471cd1SJavier Martin {"Right Input Mixer", "IN3_R P Switch", "IN3_R"}, 2601d471cd1SJavier Martin 2611d471cd1SJavier Martin {"Right ADC", NULL, "Right Input Mixer"}, 2621d471cd1SJavier Martin }; 2631d471cd1SJavier Martin 2644d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 2651d471cd1SJavier Martin { 2664d208ca4SMark Brown .selector_reg = 0, 2674d208ca4SMark Brown .selector_mask = 0xff, 2684d208ca4SMark Brown .window_start = 0, 2694d208ca4SMark Brown .window_len = 128, 270e8e08c52SMarkus Pargmann .range_min = 0, 2716d0d5103SMarkus Pargmann .range_max = AIC32X4_RMICPGAVOL, 2724d208ca4SMark Brown }, 2734d208ca4SMark Brown }; 2741d471cd1SJavier Martin 2754d208ca4SMark Brown static const struct regmap_config aic32x4_regmap = { 2764d208ca4SMark Brown .reg_bits = 8, 2774d208ca4SMark Brown .val_bits = 8, 2781d471cd1SJavier Martin 2794d208ca4SMark Brown .max_register = AIC32X4_RMICPGAVOL, 2804d208ca4SMark Brown .ranges = aic32x4_regmap_pages, 2814d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 2824d208ca4SMark Brown }; 2831d471cd1SJavier Martin 2841d471cd1SJavier Martin static inline int aic32x4_get_divs(int mclk, int rate) 2851d471cd1SJavier Martin { 2861d471cd1SJavier Martin int i; 2871d471cd1SJavier Martin 2881d471cd1SJavier Martin for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 2891d471cd1SJavier Martin if ((aic32x4_divs[i].rate == rate) 2901d471cd1SJavier Martin && (aic32x4_divs[i].mclk == mclk)) { 2911d471cd1SJavier Martin return i; 2921d471cd1SJavier Martin } 2931d471cd1SJavier Martin } 2941d471cd1SJavier Martin printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 2951d471cd1SJavier Martin return -EINVAL; 2961d471cd1SJavier Martin } 2971d471cd1SJavier Martin 2981d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 2991d471cd1SJavier Martin int clk_id, unsigned int freq, int dir) 3001d471cd1SJavier Martin { 3011d471cd1SJavier Martin struct snd_soc_codec *codec = codec_dai->codec; 3021d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 3031d471cd1SJavier Martin 3041d471cd1SJavier Martin switch (freq) { 3051d471cd1SJavier Martin case AIC32X4_FREQ_12000000: 3061d471cd1SJavier Martin case AIC32X4_FREQ_24000000: 3071d471cd1SJavier Martin case AIC32X4_FREQ_25000000: 3081d471cd1SJavier Martin aic32x4->sysclk = freq; 3091d471cd1SJavier Martin return 0; 3101d471cd1SJavier Martin } 3111d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 3121d471cd1SJavier Martin return -EINVAL; 3131d471cd1SJavier Martin } 3141d471cd1SJavier Martin 3151d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 3161d471cd1SJavier Martin { 3171d471cd1SJavier Martin struct snd_soc_codec *codec = codec_dai->codec; 3181d471cd1SJavier Martin u8 iface_reg_1; 3191d471cd1SJavier Martin u8 iface_reg_2; 3201d471cd1SJavier Martin u8 iface_reg_3; 3211d471cd1SJavier Martin 3221d471cd1SJavier Martin iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1); 3231d471cd1SJavier Martin iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2); 3241d471cd1SJavier Martin iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2); 3251d471cd1SJavier Martin iface_reg_2 = 0; 3261d471cd1SJavier Martin iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3); 3271d471cd1SJavier Martin iface_reg_3 = iface_reg_3 & ~(1 << 3); 3281d471cd1SJavier Martin 3291d471cd1SJavier Martin /* set master/slave audio interface */ 3301d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3311d471cd1SJavier Martin case SND_SOC_DAIFMT_CBM_CFM: 3321d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 3331d471cd1SJavier Martin break; 3341d471cd1SJavier Martin case SND_SOC_DAIFMT_CBS_CFS: 3351d471cd1SJavier Martin break; 3361d471cd1SJavier Martin default: 3371d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 3381d471cd1SJavier Martin return -EINVAL; 3391d471cd1SJavier Martin } 3401d471cd1SJavier Martin 3411d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3421d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S: 3431d471cd1SJavier Martin break; 3441d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A: 3451d471cd1SJavier Martin iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 3461d471cd1SJavier Martin iface_reg_3 |= (1 << 3); /* invert bit clock */ 3471d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */ 3481d471cd1SJavier Martin break; 3491d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B: 3501d471cd1SJavier Martin iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 3511d471cd1SJavier Martin iface_reg_3 |= (1 << 3); /* invert bit clock */ 3521d471cd1SJavier Martin break; 3531d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J: 3541d471cd1SJavier Martin iface_reg_1 |= 3551d471cd1SJavier Martin (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 3561d471cd1SJavier Martin break; 3571d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J: 3581d471cd1SJavier Martin iface_reg_1 |= 3591d471cd1SJavier Martin (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 3601d471cd1SJavier Martin break; 3611d471cd1SJavier Martin default: 3621d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 3631d471cd1SJavier Martin return -EINVAL; 3641d471cd1SJavier Martin } 3651d471cd1SJavier Martin 3661d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1); 3671d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2); 3681d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3); 3691d471cd1SJavier Martin return 0; 3701d471cd1SJavier Martin } 3711d471cd1SJavier Martin 3721d471cd1SJavier Martin static int aic32x4_hw_params(struct snd_pcm_substream *substream, 3731d471cd1SJavier Martin struct snd_pcm_hw_params *params, 3741d471cd1SJavier Martin struct snd_soc_dai *dai) 3751d471cd1SJavier Martin { 3761d471cd1SJavier Martin struct snd_soc_codec *codec = dai->codec; 3771d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 3781d471cd1SJavier Martin u8 data; 3791d471cd1SJavier Martin int i; 3801d471cd1SJavier Martin 3811d471cd1SJavier Martin i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params)); 3821d471cd1SJavier Martin if (i < 0) { 3831d471cd1SJavier Martin printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 3841d471cd1SJavier Martin return i; 3851d471cd1SJavier Martin } 3861d471cd1SJavier Martin 3871d471cd1SJavier Martin /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */ 3881d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN); 3891d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK); 3901d471cd1SJavier Martin 3911d471cd1SJavier Martin /* We will fix R value to 1 and will make P & J=K.D as varialble */ 3921d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_PLLPR); 3931d471cd1SJavier Martin data &= ~(7 << 4); 3941d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLPR, 3951d471cd1SJavier Martin (data | (aic32x4_divs[i].p_val << 4) | 0x01)); 3961d471cd1SJavier Martin 3971d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j); 3981d471cd1SJavier Martin 3991d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8)); 4001d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLDLSB, 4011d471cd1SJavier Martin (aic32x4_divs[i].pll_d & 0xff)); 4021d471cd1SJavier Martin 4031d471cd1SJavier Martin /* NDAC divider value */ 4041d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_NDAC); 4051d471cd1SJavier Martin data &= ~(0x7f); 4061d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac); 4071d471cd1SJavier Martin 4081d471cd1SJavier Martin /* MDAC divider value */ 4091d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_MDAC); 4101d471cd1SJavier Martin data &= ~(0x7f); 4111d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac); 4121d471cd1SJavier Martin 4131d471cd1SJavier Martin /* DOSR MSB & LSB values */ 4141d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 4151d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DOSRLSB, 4161d471cd1SJavier Martin (aic32x4_divs[i].dosr & 0xff)); 4171d471cd1SJavier Martin 4181d471cd1SJavier Martin /* NADC divider value */ 4191d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_NADC); 4201d471cd1SJavier Martin data &= ~(0x7f); 4211d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc); 4221d471cd1SJavier Martin 4231d471cd1SJavier Martin /* MADC divider value */ 4241d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_MADC); 4251d471cd1SJavier Martin data &= ~(0x7f); 4261d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc); 4271d471cd1SJavier Martin 4281d471cd1SJavier Martin /* AOSR value */ 4291d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr); 4301d471cd1SJavier Martin 4311d471cd1SJavier Martin /* BCLK N divider */ 4321d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_BCLKN); 4331d471cd1SJavier Martin data &= ~(0x7f); 4341d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N); 4351d471cd1SJavier Martin 4361d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_IFACE1); 4371d471cd1SJavier Martin data = data & ~(3 << 4); 4381d471cd1SJavier Martin switch (params_format(params)) { 4391d471cd1SJavier Martin case SNDRV_PCM_FORMAT_S16_LE: 4401d471cd1SJavier Martin break; 4411d471cd1SJavier Martin case SNDRV_PCM_FORMAT_S20_3LE: 4421d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT); 4431d471cd1SJavier Martin break; 4441d471cd1SJavier Martin case SNDRV_PCM_FORMAT_S24_LE: 4451d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT); 4461d471cd1SJavier Martin break; 4471d471cd1SJavier Martin case SNDRV_PCM_FORMAT_S32_LE: 4481d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT); 4491d471cd1SJavier Martin break; 4501d471cd1SJavier Martin } 4511d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE1, data); 4521d471cd1SJavier Martin 453*b44aa40fSMarkus Pargmann if (params_channels(params) == 1) { 454*b44aa40fSMarkus Pargmann data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 455*b44aa40fSMarkus Pargmann } else { 456*b44aa40fSMarkus Pargmann if (aic32x4->swapdacs) 457*b44aa40fSMarkus Pargmann data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 458*b44aa40fSMarkus Pargmann else 459*b44aa40fSMarkus Pargmann data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 460*b44aa40fSMarkus Pargmann } 461*b44aa40fSMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK, 462*b44aa40fSMarkus Pargmann data); 463*b44aa40fSMarkus Pargmann 4641d471cd1SJavier Martin return 0; 4651d471cd1SJavier Martin } 4661d471cd1SJavier Martin 4671d471cd1SJavier Martin static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 4681d471cd1SJavier Martin { 4691d471cd1SJavier Martin struct snd_soc_codec *codec = dai->codec; 4701d471cd1SJavier Martin u8 dac_reg; 4711d471cd1SJavier Martin 4721d471cd1SJavier Martin dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON; 4731d471cd1SJavier Martin if (mute) 4741d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON); 4751d471cd1SJavier Martin else 4761d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg); 4771d471cd1SJavier Martin return 0; 4781d471cd1SJavier Martin } 4791d471cd1SJavier Martin 4801d471cd1SJavier Martin static int aic32x4_set_bias_level(struct snd_soc_codec *codec, 4811d471cd1SJavier Martin enum snd_soc_bias_level level) 4821d471cd1SJavier Martin { 4831d471cd1SJavier Martin switch (level) { 4841d471cd1SJavier Martin case SND_SOC_BIAS_ON: 4851d471cd1SJavier Martin /* Switch on PLL */ 486bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_PLLPR, 487bc6ae96aSAxel Lin AIC32X4_PLLEN, AIC32X4_PLLEN); 4881d471cd1SJavier Martin 4891d471cd1SJavier Martin /* Switch on NDAC Divider */ 490bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NDAC, 491bc6ae96aSAxel Lin AIC32X4_NDACEN, AIC32X4_NDACEN); 4921d471cd1SJavier Martin 4931d471cd1SJavier Martin /* Switch on MDAC Divider */ 494bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MDAC, 495bc6ae96aSAxel Lin AIC32X4_MDACEN, AIC32X4_MDACEN); 4961d471cd1SJavier Martin 4971d471cd1SJavier Martin /* Switch on NADC Divider */ 498bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NADC, 499bc6ae96aSAxel Lin AIC32X4_NADCEN, AIC32X4_NADCEN); 5001d471cd1SJavier Martin 5011d471cd1SJavier Martin /* Switch on MADC Divider */ 502bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MADC, 503bc6ae96aSAxel Lin AIC32X4_MADCEN, AIC32X4_MADCEN); 5041d471cd1SJavier Martin 5051d471cd1SJavier Martin /* Switch on BCLK_N Divider */ 506bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_BCLKN, 507bc6ae96aSAxel Lin AIC32X4_BCLKEN, AIC32X4_BCLKEN); 5081d471cd1SJavier Martin break; 5091d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE: 5101d471cd1SJavier Martin break; 5111d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY: 5121d471cd1SJavier Martin /* Switch off PLL */ 513bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_PLLPR, 514bc6ae96aSAxel Lin AIC32X4_PLLEN, 0); 5151d471cd1SJavier Martin 5161d471cd1SJavier Martin /* Switch off NDAC Divider */ 517bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NDAC, 518bc6ae96aSAxel Lin AIC32X4_NDACEN, 0); 5191d471cd1SJavier Martin 5201d471cd1SJavier Martin /* Switch off MDAC Divider */ 521bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MDAC, 522bc6ae96aSAxel Lin AIC32X4_MDACEN, 0); 5231d471cd1SJavier Martin 5241d471cd1SJavier Martin /* Switch off NADC Divider */ 525bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NADC, 526bc6ae96aSAxel Lin AIC32X4_NADCEN, 0); 5271d471cd1SJavier Martin 5281d471cd1SJavier Martin /* Switch off MADC Divider */ 529bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MADC, 530bc6ae96aSAxel Lin AIC32X4_MADCEN, 0); 5311d471cd1SJavier Martin 5321d471cd1SJavier Martin /* Switch off BCLK_N Divider */ 533bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_BCLKN, 534bc6ae96aSAxel Lin AIC32X4_BCLKEN, 0); 5351d471cd1SJavier Martin break; 5361d471cd1SJavier Martin case SND_SOC_BIAS_OFF: 5371d471cd1SJavier Martin break; 5381d471cd1SJavier Martin } 53920d66065SMark Brown codec->dapm.bias_level = level; 5401d471cd1SJavier Martin return 0; 5411d471cd1SJavier Martin } 5421d471cd1SJavier Martin 5431d471cd1SJavier Martin #define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000 5441d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 5451d471cd1SJavier Martin | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 5461d471cd1SJavier Martin 54785e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = { 5481d471cd1SJavier Martin .hw_params = aic32x4_hw_params, 5491d471cd1SJavier Martin .digital_mute = aic32x4_mute, 5501d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt, 5511d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk, 5521d471cd1SJavier Martin }; 5531d471cd1SJavier Martin 5541d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = { 5551d471cd1SJavier Martin .name = "tlv320aic32x4-hifi", 5561d471cd1SJavier Martin .playback = { 5571d471cd1SJavier Martin .stream_name = "Playback", 5581d471cd1SJavier Martin .channels_min = 1, 5591d471cd1SJavier Martin .channels_max = 2, 5601d471cd1SJavier Martin .rates = AIC32X4_RATES, 5611d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 5621d471cd1SJavier Martin .capture = { 5631d471cd1SJavier Martin .stream_name = "Capture", 5641d471cd1SJavier Martin .channels_min = 1, 5651d471cd1SJavier Martin .channels_max = 2, 5661d471cd1SJavier Martin .rates = AIC32X4_RATES, 5671d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 5681d471cd1SJavier Martin .ops = &aic32x4_ops, 5691d471cd1SJavier Martin .symmetric_rates = 1, 5701d471cd1SJavier Martin }; 5711d471cd1SJavier Martin 57284b315eeSLars-Peter Clausen static int aic32x4_suspend(struct snd_soc_codec *codec) 5731d471cd1SJavier Martin { 5741d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 5751d471cd1SJavier Martin return 0; 5761d471cd1SJavier Martin } 5771d471cd1SJavier Martin 5781d471cd1SJavier Martin static int aic32x4_resume(struct snd_soc_codec *codec) 5791d471cd1SJavier Martin { 5801d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 5811d471cd1SJavier Martin return 0; 5821d471cd1SJavier Martin } 5831d471cd1SJavier Martin 5841d471cd1SJavier Martin static int aic32x4_probe(struct snd_soc_codec *codec) 5851d471cd1SJavier Martin { 5861d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 5871d471cd1SJavier Martin u32 tmp_reg; 5881d471cd1SJavier Martin 5894d208ca4SMark Brown snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); 5901d471cd1SJavier Martin 5911858fe97SJavier Martin if (aic32x4->rstn_gpio >= 0) { 5921858fe97SJavier Martin ndelay(10); 5931858fe97SJavier Martin gpio_set_value(aic32x4->rstn_gpio, 1); 5941858fe97SJavier Martin } 5951858fe97SJavier Martin 5961d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_RESET, 0x01); 5971d471cd1SJavier Martin 5981d471cd1SJavier Martin /* Power platform configuration */ 5991d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 6001d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN | 6011d471cd1SJavier Martin AIC32X4_MICBIAS_2075V); 6021d471cd1SJavier Martin } 6031d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) { 6041d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 6051d471cd1SJavier Martin } 6060c93a167SWolfram Sang 6070c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 6080c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0; 6090c93a167SWolfram Sang snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg); 6100c93a167SWolfram Sang 6111d471cd1SJavier Martin tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE); 6121d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) { 6131d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36; 6141d471cd1SJavier Martin } 6151d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) { 6161d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP; 6171d471cd1SJavier Martin } 6181d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg); 6191d471cd1SJavier Martin 6201d471cd1SJavier Martin /* Mic PGA routing */ 62123524eb1SWolfram Sang if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) { 6221d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K); 6231d471cd1SJavier Martin } 62423524eb1SWolfram Sang if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) { 6251d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K); 6261d471cd1SJavier Martin } 6271d471cd1SJavier Martin 6281d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 6291d471cd1SJavier Martin 630a405387cSJavier Martin /* 631a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up 632a405387cSJavier Martin * and down for the first capture to work properly. It seems related to 633a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet. 634a405387cSJavier Martin */ 635a405387cSJavier Martin tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP); 636a405387cSJavier Martin snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg | 637a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN); 638a405387cSJavier Martin snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg); 639a405387cSJavier Martin 6401d471cd1SJavier Martin return 0; 6411d471cd1SJavier Martin } 6421d471cd1SJavier Martin 6431d471cd1SJavier Martin static int aic32x4_remove(struct snd_soc_codec *codec) 6441d471cd1SJavier Martin { 6451d471cd1SJavier Martin aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 6461d471cd1SJavier Martin return 0; 6471d471cd1SJavier Martin } 6481d471cd1SJavier Martin 6491d471cd1SJavier Martin static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = { 6501d471cd1SJavier Martin .probe = aic32x4_probe, 6511d471cd1SJavier Martin .remove = aic32x4_remove, 6521d471cd1SJavier Martin .suspend = aic32x4_suspend, 6531d471cd1SJavier Martin .resume = aic32x4_resume, 6541d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level, 655aac97b5fSLars-Peter Clausen 656aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls, 657aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 658aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets, 659aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 660aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes, 661aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 6621d471cd1SJavier Martin }; 6631d471cd1SJavier Martin 6647a79e94eSBill Pemberton static int aic32x4_i2c_probe(struct i2c_client *i2c, 6651d471cd1SJavier Martin const struct i2c_device_id *id) 6661d471cd1SJavier Martin { 6671d471cd1SJavier Martin struct aic32x4_pdata *pdata = i2c->dev.platform_data; 6681d471cd1SJavier Martin struct aic32x4_priv *aic32x4; 6691d471cd1SJavier Martin int ret; 6701d471cd1SJavier Martin 671658ecf77SAxel Lin aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv), 672658ecf77SAxel Lin GFP_KERNEL); 6731d471cd1SJavier Martin if (aic32x4 == NULL) 6741d471cd1SJavier Martin return -ENOMEM; 6751d471cd1SJavier Martin 6764d208ca4SMark Brown aic32x4->regmap = devm_regmap_init_i2c(i2c, &aic32x4_regmap); 6774d208ca4SMark Brown if (IS_ERR(aic32x4->regmap)) 6784d208ca4SMark Brown return PTR_ERR(aic32x4->regmap); 6794d208ca4SMark Brown 6801d471cd1SJavier Martin i2c_set_clientdata(i2c, aic32x4); 6811d471cd1SJavier Martin 6821d471cd1SJavier Martin if (pdata) { 6831d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg; 6841d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs; 6851d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing; 6861858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio; 6871d471cd1SJavier Martin } else { 6881d471cd1SJavier Martin aic32x4->power_cfg = 0; 6891d471cd1SJavier Martin aic32x4->swapdacs = false; 6901d471cd1SJavier Martin aic32x4->micpga_routing = 0; 6911858fe97SJavier Martin aic32x4->rstn_gpio = -1; 6921d471cd1SJavier Martin } 6931d471cd1SJavier Martin 694752b7764SMark Brown if (aic32x4->rstn_gpio >= 0) { 695752b7764SMark Brown ret = devm_gpio_request_one(&i2c->dev, aic32x4->rstn_gpio, 696752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 697752b7764SMark Brown if (ret != 0) 698752b7764SMark Brown return ret; 699752b7764SMark Brown } 700752b7764SMark Brown 7011d471cd1SJavier Martin ret = snd_soc_register_codec(&i2c->dev, 7021d471cd1SJavier Martin &soc_codec_dev_aic32x4, &aic32x4_dai, 1); 7031d471cd1SJavier Martin return ret; 7041d471cd1SJavier Martin } 7051d471cd1SJavier Martin 7067a79e94eSBill Pemberton static int aic32x4_i2c_remove(struct i2c_client *client) 7071d471cd1SJavier Martin { 7081d471cd1SJavier Martin snd_soc_unregister_codec(&client->dev); 7091d471cd1SJavier Martin return 0; 7101d471cd1SJavier Martin } 7111d471cd1SJavier Martin 7121d471cd1SJavier Martin static const struct i2c_device_id aic32x4_i2c_id[] = { 7131d471cd1SJavier Martin { "tlv320aic32x4", 0 }, 7141d471cd1SJavier Martin { } 7151d471cd1SJavier Martin }; 7161d471cd1SJavier Martin MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id); 7171d471cd1SJavier Martin 7181d471cd1SJavier Martin static struct i2c_driver aic32x4_i2c_driver = { 7191d471cd1SJavier Martin .driver = { 7201d471cd1SJavier Martin .name = "tlv320aic32x4", 7211d471cd1SJavier Martin .owner = THIS_MODULE, 7221d471cd1SJavier Martin }, 7231d471cd1SJavier Martin .probe = aic32x4_i2c_probe, 7247a79e94eSBill Pemberton .remove = aic32x4_i2c_remove, 7251d471cd1SJavier Martin .id_table = aic32x4_i2c_id, 7261d471cd1SJavier Martin }; 7271d471cd1SJavier Martin 7283b09efd1SSachin Kamat module_i2c_driver(aic32x4_i2c_driver); 7291d471cd1SJavier Martin 7301d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 7311d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 7321d471cd1SJavier Martin MODULE_LICENSE("GPL"); 733