116216333SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 21d471cd1SJavier Martin /* 31d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c 41d471cd1SJavier Martin * 51d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L. 61d471cd1SJavier Martin * 71d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com> 81d471cd1SJavier Martin * 91d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 101d471cd1SJavier Martin */ 111d471cd1SJavier Martin 121d471cd1SJavier Martin #include <linux/module.h> 131d471cd1SJavier Martin #include <linux/moduleparam.h> 141d471cd1SJavier Martin #include <linux/init.h> 151d471cd1SJavier Martin #include <linux/delay.h> 161d471cd1SJavier Martin #include <linux/pm.h> 171858fe97SJavier Martin #include <linux/gpio.h> 184d16700dSMarkus Pargmann #include <linux/of_gpio.h> 191d471cd1SJavier Martin #include <linux/cdev.h> 201d471cd1SJavier Martin #include <linux/slab.h> 2198b664e2SMarkus Pargmann #include <linux/clk.h> 22514b044cSAnnaliese McDermond #include <linux/of_clk.h> 23239b669bSMarkus Pargmann #include <linux/regulator/consumer.h> 241d471cd1SJavier Martin 251d471cd1SJavier Martin #include <sound/tlv320aic32x4.h> 261d471cd1SJavier Martin #include <sound/core.h> 271d471cd1SJavier Martin #include <sound/pcm.h> 281d471cd1SJavier Martin #include <sound/pcm_params.h> 291d471cd1SJavier Martin #include <sound/soc.h> 301d471cd1SJavier Martin #include <sound/soc-dapm.h> 311d471cd1SJavier Martin #include <sound/initval.h> 321d471cd1SJavier Martin #include <sound/tlv.h> 331d471cd1SJavier Martin 341d471cd1SJavier Martin #include "tlv320aic32x4.h" 351d471cd1SJavier Martin 361d471cd1SJavier Martin struct aic32x4_priv { 374d208ca4SMark Brown struct regmap *regmap; 381d471cd1SJavier Martin u32 power_cfg; 391d471cd1SJavier Martin u32 micpga_routing; 401d471cd1SJavier Martin bool swapdacs; 411858fe97SJavier Martin int rstn_gpio; 42514b044cSAnnaliese McDermond const char *mclk_name; 43239b669bSMarkus Pargmann 44239b669bSMarkus Pargmann struct regulator *supply_ldo; 45239b669bSMarkus Pargmann struct regulator *supply_iov; 46239b669bSMarkus Pargmann struct regulator *supply_dv; 47239b669bSMarkus Pargmann struct regulator *supply_av; 48b9045b9cSDan Murphy 49b9045b9cSDan Murphy struct aic32x4_setup_data *setup; 50b9045b9cSDan Murphy struct device *dev; 51*688d47cdSClaudius Heine enum aic32x4_type type; 52b9045b9cSDan Murphy }; 53b9045b9cSDan Murphy 549d4befffSMichael Sit Wei Hong static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w, 559d4befffSMichael Sit Wei Hong struct snd_kcontrol *kcontrol, int event) 569d4befffSMichael Sit Wei Hong { 579d4befffSMichael Sit Wei Hong struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 589d4befffSMichael Sit Wei Hong u32 adc_reg; 599d4befffSMichael Sit Wei Hong 609d4befffSMichael Sit Wei Hong /* 619d4befffSMichael Sit Wei Hong * Workaround: the datasheet does not mention a required programming 629d4befffSMichael Sit Wei Hong * sequence but experiments show the ADC needs to be reset after each 639d4befffSMichael Sit Wei Hong * capture to avoid audible artifacts. 649d4befffSMichael Sit Wei Hong */ 659d4befffSMichael Sit Wei Hong switch (event) { 669d4befffSMichael Sit Wei Hong case SND_SOC_DAPM_POST_PMD: 679d4befffSMichael Sit Wei Hong adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP); 689d4befffSMichael Sit Wei Hong snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg | 699d4befffSMichael Sit Wei Hong AIC32X4_LADC_EN | AIC32X4_RADC_EN); 709d4befffSMichael Sit Wei Hong snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg); 719d4befffSMichael Sit Wei Hong break; 729d4befffSMichael Sit Wei Hong } 739d4befffSMichael Sit Wei Hong return 0; 749d4befffSMichael Sit Wei Hong }; 759d4befffSMichael Sit Wei Hong 7604d979d7Sb-ak static int mic_bias_event(struct snd_soc_dapm_widget *w, 7704d979d7Sb-ak struct snd_kcontrol *kcontrol, int event) 7804d979d7Sb-ak { 7904d979d7Sb-ak struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 8004d979d7Sb-ak 8104d979d7Sb-ak switch (event) { 8204d979d7Sb-ak case SND_SOC_DAPM_POST_PMU: 8304d979d7Sb-ak /* Change Mic Bias Registor */ 8404d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 8504d979d7Sb-ak AIC32x4_MICBIAS_MASK, 8604d979d7Sb-ak AIC32X4_MICBIAS_LDOIN | 8704d979d7Sb-ak AIC32X4_MICBIAS_2075V); 8804d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 8904d979d7Sb-ak break; 9004d979d7Sb-ak case SND_SOC_DAPM_PRE_PMD: 9104d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 9204d979d7Sb-ak AIC32x4_MICBIAS_MASK, 0); 9304d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 9404d979d7Sb-ak __func__); 9504d979d7Sb-ak break; 9604d979d7Sb-ak } 9704d979d7Sb-ak 9804d979d7Sb-ak return 0; 9904d979d7Sb-ak } 10004d979d7Sb-ak 10104d979d7Sb-ak 102b9045b9cSDan Murphy static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 103b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 104b9045b9cSDan Murphy { 105b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 106b9045b9cSDan Murphy u8 val; 107b9045b9cSDan Murphy 108e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_DINCTL); 109b9045b9cSDan Murphy 110b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 111b9045b9cSDan Murphy 112b9045b9cSDan Murphy return 0; 113b9045b9cSDan Murphy }; 114b9045b9cSDan Murphy 115b9045b9cSDan Murphy static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 116b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 117b9045b9cSDan Murphy { 118b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 119b9045b9cSDan Murphy u8 val; 120b9045b9cSDan Murphy u8 gpio_check; 121b9045b9cSDan Murphy 122e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_DOUTCTL); 123b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 124b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 125b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 126b9045b9cSDan Murphy __func__); 127b9045b9cSDan Murphy return -EINVAL; 128b9045b9cSDan Murphy } 129b9045b9cSDan Murphy 130b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 131b9045b9cSDan Murphy return 0; 132b9045b9cSDan Murphy 133b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 134b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 135b9045b9cSDan Murphy else 136b9045b9cSDan Murphy val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 137b9045b9cSDan Murphy 138b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 139b9045b9cSDan Murphy 140b9045b9cSDan Murphy return 0; 141b9045b9cSDan Murphy }; 142b9045b9cSDan Murphy 143b9045b9cSDan Murphy static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 144b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 145b9045b9cSDan Murphy { 146b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 147b9045b9cSDan Murphy u8 val; 148b9045b9cSDan Murphy 149e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_SCLKCTL); 150b9045b9cSDan Murphy 151b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 152b9045b9cSDan Murphy 153b9045b9cSDan Murphy return 0; 154b9045b9cSDan Murphy }; 155b9045b9cSDan Murphy 156b9045b9cSDan Murphy static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 157b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 158b9045b9cSDan Murphy { 159b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 160b9045b9cSDan Murphy u8 val; 161b9045b9cSDan Murphy u8 gpio_check; 162b9045b9cSDan Murphy 163e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_MISOCTL); 164b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 165b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 166b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 167b9045b9cSDan Murphy __func__); 168b9045b9cSDan Murphy return -EINVAL; 169b9045b9cSDan Murphy } 170b9045b9cSDan Murphy 171b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 172b9045b9cSDan Murphy return 0; 173b9045b9cSDan Murphy 174b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 175b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 176b9045b9cSDan Murphy else 177b9045b9cSDan Murphy val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 178b9045b9cSDan Murphy 179b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, val); 180b9045b9cSDan Murphy 181b9045b9cSDan Murphy return 0; 182b9045b9cSDan Murphy }; 183b9045b9cSDan Murphy 184b9045b9cSDan Murphy static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 185b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 186b9045b9cSDan Murphy { 187b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 188b9045b9cSDan Murphy u8 val; 189b9045b9cSDan Murphy 190e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_GPIOCTL); 191b9045b9cSDan Murphy ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 192b9045b9cSDan Murphy 193b9045b9cSDan Murphy return 0; 194b9045b9cSDan Murphy }; 195b9045b9cSDan Murphy 196b9045b9cSDan Murphy static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 197b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 198b9045b9cSDan Murphy { 199b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 200b9045b9cSDan Murphy u8 val; 201b9045b9cSDan Murphy u8 gpio_check; 202b9045b9cSDan Murphy 203e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_GPIOCTL); 204b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 205b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 206b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 207b9045b9cSDan Murphy __func__); 208b9045b9cSDan Murphy return -EINVAL; 209b9045b9cSDan Murphy } 210b9045b9cSDan Murphy 211b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & 0x1)) 212b9045b9cSDan Murphy return 0; 213b9045b9cSDan Murphy 214b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 215b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 216b9045b9cSDan Murphy else 217b9045b9cSDan Murphy val &= 0xfe; 218b9045b9cSDan Murphy 219b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 220b9045b9cSDan Murphy 221b9045b9cSDan Murphy return 0; 222b9045b9cSDan Murphy }; 223b9045b9cSDan Murphy 224b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp1[] = { 225b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 226b9045b9cSDan Murphy }; 227b9045b9cSDan Murphy 228b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp2[] = { 229b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 230b9045b9cSDan Murphy }; 231b9045b9cSDan Murphy 232b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp3[] = { 233b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 234b9045b9cSDan Murphy }; 235b9045b9cSDan Murphy 236b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp4[] = { 237b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 238b9045b9cSDan Murphy }; 239b9045b9cSDan Murphy 240b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp5[] = { 241b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 242b9045b9cSDan Murphy aic32x4_set_mfp5_gpio), 2431d471cd1SJavier Martin }; 2441d471cd1SJavier Martin 2451d471cd1SJavier Martin /* 0dB min, 0.5dB steps */ 2461d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 247c671e79dSMarkus Pargmann /* -63.5dB min, 0.5dB steps */ 248c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 249c671e79dSMarkus Pargmann /* -6dB min, 1dB steps */ 250c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 251c671e79dSMarkus Pargmann /* -12dB min, 0.5dB steps */ 252c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 2531d471cd1SJavier Martin 25444ceee84SAnnaliese McDermond static const char * const lo_cm_text[] = { 25544ceee84SAnnaliese McDermond "Full Chip", "1.65V", 25644ceee84SAnnaliese McDermond }; 25744ceee84SAnnaliese McDermond 25844ceee84SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text); 25944ceee84SAnnaliese McDermond 260d3e6e374SAnnaliese McDermond static const char * const ptm_text[] = { 261d3e6e374SAnnaliese McDermond "P3", "P2", "P1", 262d3e6e374SAnnaliese McDermond }; 263d3e6e374SAnnaliese McDermond 264d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text); 265d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text); 266d3e6e374SAnnaliese McDermond 2671d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 268c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 269c671e79dSMarkus Pargmann AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 270d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum), 271d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum), 272c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 273c671e79dSMarkus Pargmann AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 274c671e79dSMarkus Pargmann tlv_driver_gain), 275c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 276c671e79dSMarkus Pargmann AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 277c671e79dSMarkus Pargmann tlv_driver_gain), 2781d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 2791d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1), 2801d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 2811d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1), 28244ceee84SAnnaliese McDermond SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum), 2831d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 2841d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1), 2851d471cd1SJavier Martin 2861d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 2871d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 2881d471cd1SJavier Martin 289c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 290c671e79dSMarkus Pargmann AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 2911d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 2921d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 2931d471cd1SJavier Martin 2941d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 2951d471cd1SJavier Martin 2961d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 2971d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 2981d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 2991d471cd1SJavier Martin 4, 0x07, 0), 3001d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 3011d471cd1SJavier Martin 0, 0x03, 0), 3021d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 3031d471cd1SJavier Martin 6, 0x03, 0), 3041d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 3051d471cd1SJavier Martin 1, 0x1F, 0), 3061d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 3071d471cd1SJavier Martin 0, 0x7F, 0), 3081d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 3091d471cd1SJavier Martin 3, 0x1F, 0), 3101d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 3111d471cd1SJavier Martin 3, 0x1F, 0), 3121d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 3131d471cd1SJavier Martin 0, 0x1F, 0), 3141d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 3151d471cd1SJavier Martin 0, 0x0F, 0), 3161d471cd1SJavier Martin }; 3171d471cd1SJavier Martin 3181d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 3191d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 3201d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 3211d471cd1SJavier Martin }; 3221d471cd1SJavier Martin 3231d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 3241d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 3251d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 3261d471cd1SJavier Martin }; 3271d471cd1SJavier Martin 3281d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 3291d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 3301d471cd1SJavier Martin }; 3311d471cd1SJavier Martin 3321d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 3331d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 3341d471cd1SJavier Martin }; 3351d471cd1SJavier Martin 33620d2cecbSJeremy McDermond static const char * const resistor_text[] = { 33720d2cecbSJeremy McDermond "Off", "10 kOhm", "20 kOhm", "40 kOhm", 3381d471cd1SJavier Martin }; 3391d471cd1SJavier Martin 3402213fc35SJeremy McDermond /* Left mixer pins */ 3412213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 3422213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 3432213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 3442213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 34520d2cecbSJeremy McDermond 3462213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 3472213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 3482213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 3492213fc35SJeremy McDermond 3502213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 3512213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 3522213fc35SJeremy McDermond }; 3532213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 3542213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 3552213fc35SJeremy McDermond }; 3562213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 3572213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 3582213fc35SJeremy McDermond }; 3592213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 3602213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 3612213fc35SJeremy McDermond }; 3622213fc35SJeremy McDermond static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 3632213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 3642213fc35SJeremy McDermond }; 3652213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 3662213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 3672213fc35SJeremy McDermond }; 3682213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 3692213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 37020d2cecbSJeremy McDermond }; 37120d2cecbSJeremy McDermond 3722213fc35SJeremy McDermond /* Right mixer pins */ 3732213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 3742213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 3752213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 3762213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 3772213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 3782213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 3792213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 38020d2cecbSJeremy McDermond 3812213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 3822213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 3832213fc35SJeremy McDermond }; 3842213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 3852213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 3862213fc35SJeremy McDermond }; 3872213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 3882213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 3892213fc35SJeremy McDermond }; 3902213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 3912213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 3922213fc35SJeremy McDermond }; 3932213fc35SJeremy McDermond static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 3942213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 3952213fc35SJeremy McDermond }; 3962213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 3972213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 3982213fc35SJeremy McDermond }; 3992213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 4002213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 4011d471cd1SJavier Martin }; 4021d471cd1SJavier Martin 4031d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 4041d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 4051d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 4061d471cd1SJavier Martin &hpl_output_mixer_controls[0], 4071d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)), 4081d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 4091d471cd1SJavier Martin 4101d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 4111d471cd1SJavier Martin &lol_output_mixer_controls[0], 4121d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)), 4131d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 4141d471cd1SJavier Martin 4151d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 4161d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 4171d471cd1SJavier Martin &hpr_output_mixer_controls[0], 4181d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)), 4191d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 4201d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 4211d471cd1SJavier Martin &lor_output_mixer_controls[0], 4221d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)), 4231d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 4242213fc35SJeremy McDermond 4251d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 4262213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4272213fc35SJeremy McDermond in1r_to_rmixer_controls), 4282213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4292213fc35SJeremy McDermond in2r_to_rmixer_controls), 4302213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4312213fc35SJeremy McDermond in3r_to_rmixer_controls), 4322213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4332213fc35SJeremy McDermond in2l_to_rmixer_controls), 4342213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4352213fc35SJeremy McDermond cmr_to_rmixer_controls), 4362213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4372213fc35SJeremy McDermond in1l_to_rmixer_controls), 4382213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4392213fc35SJeremy McDermond in3l_to_rmixer_controls), 4402213fc35SJeremy McDermond 4412213fc35SJeremy McDermond SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 4422213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4432213fc35SJeremy McDermond in1l_to_lmixer_controls), 4442213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4452213fc35SJeremy McDermond in2l_to_lmixer_controls), 4462213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4472213fc35SJeremy McDermond in3l_to_lmixer_controls), 4482213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4492213fc35SJeremy McDermond in1r_to_lmixer_controls), 4502213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4512213fc35SJeremy McDermond cml_to_lmixer_controls), 4522213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4532213fc35SJeremy McDermond in2r_to_lmixer_controls), 4542213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4552213fc35SJeremy McDermond in3r_to_lmixer_controls), 4562213fc35SJeremy McDermond 45704d979d7Sb-ak SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 45804d979d7Sb-ak SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 45904d979d7Sb-ak 4609d4befffSMichael Sit Wei Hong SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc), 4611d471cd1SJavier Martin 4621d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"), 4631d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"), 4641d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"), 4651d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"), 4661d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"), 4671d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"), 4681d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"), 4691d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"), 4701d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"), 4711d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"), 472c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_L"), 473c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_R"), 4741d471cd1SJavier Martin }; 4751d471cd1SJavier Martin 4761d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 4771d471cd1SJavier Martin /* Left Output */ 4781d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 4791d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 4801d471cd1SJavier Martin 4811d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"}, 4821d471cd1SJavier Martin {"HPL", NULL, "HPL Power"}, 4831d471cd1SJavier Martin 4841d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 4851d471cd1SJavier Martin 4861d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"}, 4871d471cd1SJavier Martin {"LOL", NULL, "LOL Power"}, 4881d471cd1SJavier Martin 4891d471cd1SJavier Martin /* Right Output */ 4901d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 4911d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 4921d471cd1SJavier Martin 4931d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"}, 4941d471cd1SJavier Martin {"HPR", NULL, "HPR Power"}, 4951d471cd1SJavier Martin 4961d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 4971d471cd1SJavier Martin 4981d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"}, 4991d471cd1SJavier Martin {"LOR", NULL, "LOR Power"}, 5001d471cd1SJavier Martin 5011d471cd1SJavier Martin /* Right Input */ 5022213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 5032213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 5042213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 5052213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 5061d471cd1SJavier Martin 5072213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 5082213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 5092213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 5102213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 5112213fc35SJeremy McDermond 5122213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 5132213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 5142213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 5152213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 5162213fc35SJeremy McDermond 5172213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 5182213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5192213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5202213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5212213fc35SJeremy McDermond 5222213fc35SJeremy McDermond {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 5232213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 5242213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 5252213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 5262213fc35SJeremy McDermond 5272213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 5282213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 5292213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 5302213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 5312213fc35SJeremy McDermond 5322213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 5332213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 5342213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 5352213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 5362213fc35SJeremy McDermond 5372213fc35SJeremy McDermond /* Left Input */ 5382213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 5392213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 5402213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 5412213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 5422213fc35SJeremy McDermond 5432213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 5442213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5452213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5462213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5472213fc35SJeremy McDermond 5482213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 5492213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 5502213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 5512213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 5522213fc35SJeremy McDermond 5532213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 5542213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 5552213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 5562213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 5572213fc35SJeremy McDermond 5582213fc35SJeremy McDermond {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 5592213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 5602213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 5612213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 5622213fc35SJeremy McDermond 5632213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 5642213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 5652213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 5662213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 5672213fc35SJeremy McDermond 5682213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 5692213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 5702213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 5712213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 5721d471cd1SJavier Martin }; 5731d471cd1SJavier Martin 5744d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 5751d471cd1SJavier Martin { 5764d208ca4SMark Brown .selector_reg = 0, 5774d208ca4SMark Brown .selector_mask = 0xff, 5784d208ca4SMark Brown .window_start = 0, 5794d208ca4SMark Brown .window_len = 128, 580e8e08c52SMarkus Pargmann .range_min = 0, 58129654ed8SAnnaliese McDermond .range_max = AIC32X4_REFPOWERUP, 5824d208ca4SMark Brown }, 5834d208ca4SMark Brown }; 5841d471cd1SJavier Martin 5853bcfd222SJeremy McDermond const struct regmap_config aic32x4_regmap_config = { 58629654ed8SAnnaliese McDermond .max_register = AIC32X4_REFPOWERUP, 5874d208ca4SMark Brown .ranges = aic32x4_regmap_pages, 5884d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 5894d208ca4SMark Brown }; 5903bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_regmap_config); 5911d471cd1SJavier Martin 5921d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 5931d471cd1SJavier Martin int clk_id, unsigned int freq, int dir) 5941d471cd1SJavier Martin { 595b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 596aa6a60f7SAnnaliese McDermond struct clk *mclk; 597aa6a60f7SAnnaliese McDermond struct clk *pll; 5981d471cd1SJavier Martin 599aa6a60f7SAnnaliese McDermond pll = devm_clk_get(component->dev, "pll"); 6001092b097SChuhong Yuan if (IS_ERR(pll)) 6011092b097SChuhong Yuan return PTR_ERR(pll); 6021092b097SChuhong Yuan 603aa6a60f7SAnnaliese McDermond mclk = clk_get_parent(pll); 604aa6a60f7SAnnaliese McDermond 605aa6a60f7SAnnaliese McDermond return clk_set_rate(mclk, freq); 6061d471cd1SJavier Martin } 6071d471cd1SJavier Martin 6081d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 6091d471cd1SJavier Martin { 610b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 61160fb4be5SAndrew F. Davis u8 iface_reg_1 = 0; 61260fb4be5SAndrew F. Davis u8 iface_reg_2 = 0; 61360fb4be5SAndrew F. Davis u8 iface_reg_3 = 0; 6141d471cd1SJavier Martin 6151d471cd1SJavier Martin /* set master/slave audio interface */ 6161d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 6171d471cd1SJavier Martin case SND_SOC_DAIFMT_CBM_CFM: 6181d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 6191d471cd1SJavier Martin break; 6201d471cd1SJavier Martin case SND_SOC_DAIFMT_CBS_CFS: 6211d471cd1SJavier Martin break; 6221d471cd1SJavier Martin default: 6231d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 6241d471cd1SJavier Martin return -EINVAL; 6251d471cd1SJavier Martin } 6261d471cd1SJavier Martin 6271d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 6281d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S: 6291d471cd1SJavier Martin break; 6301d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A: 6314483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6324483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 63360fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6341d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */ 6351d471cd1SJavier Martin break; 6361d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B: 6374483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6384483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 63960fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6401d471cd1SJavier Martin break; 6411d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J: 6424483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 6434483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6441d471cd1SJavier Martin break; 6451d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J: 6464483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 6474483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6481d471cd1SJavier Martin break; 6491d471cd1SJavier Martin default: 6501d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 6511d471cd1SJavier Martin return -EINVAL; 6521d471cd1SJavier Martin } 6531d471cd1SJavier Martin 654b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 65560fb4be5SAndrew F. Davis AIC32X4_IFACE1_DATATYPE_MASK | 65660fb4be5SAndrew F. Davis AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 657b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE2, 65860fb4be5SAndrew F. Davis AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 659b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE3, 66060fb4be5SAndrew F. Davis AIC32X4_BCLKINV_MASK, iface_reg_3); 66160fb4be5SAndrew F. Davis 6621d471cd1SJavier Martin return 0; 6631d471cd1SJavier Martin } 6641d471cd1SJavier Martin 665fbafbf65SAnnaliese McDermond static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) 666fbafbf65SAnnaliese McDermond { 667fbafbf65SAnnaliese McDermond return snd_soc_component_write(component, AIC32X4_AOSR, aosr); 668fbafbf65SAnnaliese McDermond } 669fbafbf65SAnnaliese McDermond 670fbafbf65SAnnaliese McDermond static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) 671fbafbf65SAnnaliese McDermond { 672fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); 673fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRLSB, 674fbafbf65SAnnaliese McDermond (dosr & 0xff)); 675fbafbf65SAnnaliese McDermond 676fbafbf65SAnnaliese McDermond return 0; 677fbafbf65SAnnaliese McDermond } 678fbafbf65SAnnaliese McDermond 679c95e3a4bSAnnaliese McDermond static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 680c95e3a4bSAnnaliese McDermond u8 r_block, u8 p_block) 681c95e3a4bSAnnaliese McDermond { 682c95e3a4bSAnnaliese McDermond if (r_block > 18 || p_block > 25) 683c95e3a4bSAnnaliese McDermond return -EINVAL; 684c95e3a4bSAnnaliese McDermond 685c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 686c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 687c95e3a4bSAnnaliese McDermond 688c95e3a4bSAnnaliese McDermond return 0; 689c95e3a4bSAnnaliese McDermond } 690c95e3a4bSAnnaliese McDermond 691bf31cbfbSAnnaliese McDermond static int aic32x4_setup_clocks(struct snd_soc_component *component, 69297ee967eSMark Brown unsigned int sample_rate, unsigned int channels, 693dcd79364SMichael Sit Wei Hong unsigned int bit_depth) 6941d471cd1SJavier Martin { 69596c3bb00SAnnaliese McDermond u8 aosr; 69696c3bb00SAnnaliese McDermond u16 dosr; 69796c3bb00SAnnaliese McDermond u8 adc_resource_class, dac_resource_class; 69896c3bb00SAnnaliese McDermond u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; 69996c3bb00SAnnaliese McDermond u8 dosr_increment; 70096c3bb00SAnnaliese McDermond u16 max_dosr, min_dosr; 70183b4f50cSYueHaibing unsigned long adc_clock_rate, dac_clock_rate; 702514b044cSAnnaliese McDermond int ret; 703514b044cSAnnaliese McDermond 704514b044cSAnnaliese McDermond struct clk_bulk_data clocks[] = { 705514b044cSAnnaliese McDermond { .id = "pll" }, 706a51b5006SAnnaliese McDermond { .id = "nadc" }, 707a51b5006SAnnaliese McDermond { .id = "madc" }, 708a51b5006SAnnaliese McDermond { .id = "ndac" }, 709a51b5006SAnnaliese McDermond { .id = "mdac" }, 7109b484124SAnnaliese McDermond { .id = "bdiv" }, 711514b044cSAnnaliese McDermond }; 712514b044cSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 713514b044cSAnnaliese McDermond if (ret) 714514b044cSAnnaliese McDermond return ret; 715514b044cSAnnaliese McDermond 71696c3bb00SAnnaliese McDermond if (sample_rate <= 48000) { 71796c3bb00SAnnaliese McDermond aosr = 128; 71896c3bb00SAnnaliese McDermond adc_resource_class = 6; 71996c3bb00SAnnaliese McDermond dac_resource_class = 8; 72096c3bb00SAnnaliese McDermond dosr_increment = 8; 72196c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 1); 72296c3bb00SAnnaliese McDermond } else if (sample_rate <= 96000) { 72396c3bb00SAnnaliese McDermond aosr = 64; 72496c3bb00SAnnaliese McDermond adc_resource_class = 6; 72596c3bb00SAnnaliese McDermond dac_resource_class = 8; 72696c3bb00SAnnaliese McDermond dosr_increment = 4; 72796c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 9); 72896c3bb00SAnnaliese McDermond } else if (sample_rate == 192000) { 72996c3bb00SAnnaliese McDermond aosr = 32; 73096c3bb00SAnnaliese McDermond adc_resource_class = 3; 73196c3bb00SAnnaliese McDermond dac_resource_class = 4; 73296c3bb00SAnnaliese McDermond dosr_increment = 2; 73396c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 13, 19); 73496c3bb00SAnnaliese McDermond } else { 73596c3bb00SAnnaliese McDermond dev_err(component->dev, "Sampling rate not supported\n"); 73696c3bb00SAnnaliese McDermond return -EINVAL; 73796c3bb00SAnnaliese McDermond } 738fbafbf65SAnnaliese McDermond 73996c3bb00SAnnaliese McDermond madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); 74096c3bb00SAnnaliese McDermond max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * 74196c3bb00SAnnaliese McDermond dosr_increment; 74296c3bb00SAnnaliese McDermond min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * 74396c3bb00SAnnaliese McDermond dosr_increment; 74496c3bb00SAnnaliese McDermond max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); 745c95e3a4bSAnnaliese McDermond 74696c3bb00SAnnaliese McDermond for (nadc = max_nadc; nadc > 0; --nadc) { 74796c3bb00SAnnaliese McDermond adc_clock_rate = nadc * madc * aosr * sample_rate; 74896c3bb00SAnnaliese McDermond for (dosr = max_dosr; dosr >= min_dosr; 74996c3bb00SAnnaliese McDermond dosr -= dosr_increment) { 75096c3bb00SAnnaliese McDermond min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); 75196c3bb00SAnnaliese McDermond max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / 75296c3bb00SAnnaliese McDermond (min_mdac * dosr * sample_rate); 75396c3bb00SAnnaliese McDermond for (mdac = min_mdac; mdac <= 128; ++mdac) { 75496c3bb00SAnnaliese McDermond for (ndac = max_ndac; ndac > 0; --ndac) { 75596c3bb00SAnnaliese McDermond dac_clock_rate = ndac * mdac * dosr * 75696c3bb00SAnnaliese McDermond sample_rate; 75796c3bb00SAnnaliese McDermond if (dac_clock_rate == adc_clock_rate) { 75896c3bb00SAnnaliese McDermond if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 75996c3bb00SAnnaliese McDermond continue; 76096c3bb00SAnnaliese McDermond 76196c3bb00SAnnaliese McDermond clk_set_rate(clocks[0].clk, 76296c3bb00SAnnaliese McDermond dac_clock_rate); 76396c3bb00SAnnaliese McDermond 76496c3bb00SAnnaliese McDermond clk_set_rate(clocks[1].clk, 76596c3bb00SAnnaliese McDermond sample_rate * aosr * 76696c3bb00SAnnaliese McDermond madc); 76796c3bb00SAnnaliese McDermond clk_set_rate(clocks[2].clk, 76896c3bb00SAnnaliese McDermond sample_rate * aosr); 76996c3bb00SAnnaliese McDermond aic32x4_set_aosr(component, 77096c3bb00SAnnaliese McDermond aosr); 77196c3bb00SAnnaliese McDermond 77296c3bb00SAnnaliese McDermond clk_set_rate(clocks[3].clk, 77396c3bb00SAnnaliese McDermond sample_rate * dosr * 77496c3bb00SAnnaliese McDermond mdac); 77596c3bb00SAnnaliese McDermond clk_set_rate(clocks[4].clk, 77696c3bb00SAnnaliese McDermond sample_rate * dosr); 77796c3bb00SAnnaliese McDermond aic32x4_set_dosr(component, 77896c3bb00SAnnaliese McDermond dosr); 77996c3bb00SAnnaliese McDermond 78096c3bb00SAnnaliese McDermond clk_set_rate(clocks[5].clk, 78197ee967eSMark Brown sample_rate * channels * 782dcd79364SMichael Sit Wei Hong bit_depth); 78340b37136SMiquel Raynal 784bf31cbfbSAnnaliese McDermond return 0; 785bf31cbfbSAnnaliese McDermond } 78696c3bb00SAnnaliese McDermond } 78796c3bb00SAnnaliese McDermond } 78896c3bb00SAnnaliese McDermond } 78996c3bb00SAnnaliese McDermond } 79096c3bb00SAnnaliese McDermond 79196c3bb00SAnnaliese McDermond dev_err(component->dev, 79296c3bb00SAnnaliese McDermond "Could not set clocks to support sample rate.\n"); 79396c3bb00SAnnaliese McDermond return -EINVAL; 79496c3bb00SAnnaliese McDermond } 795bf31cbfbSAnnaliese McDermond 796bf31cbfbSAnnaliese McDermond static int aic32x4_hw_params(struct snd_pcm_substream *substream, 797bf31cbfbSAnnaliese McDermond struct snd_pcm_hw_params *params, 798bf31cbfbSAnnaliese McDermond struct snd_soc_dai *dai) 799bf31cbfbSAnnaliese McDermond { 800bf31cbfbSAnnaliese McDermond struct snd_soc_component *component = dai->component; 801bf31cbfbSAnnaliese McDermond struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 802bf31cbfbSAnnaliese McDermond u8 iface1_reg = 0; 803bf31cbfbSAnnaliese McDermond u8 dacsetup_reg = 0; 804bf31cbfbSAnnaliese McDermond 805dcd79364SMichael Sit Wei Hong aic32x4_setup_clocks(component, params_rate(params), 806dcd79364SMichael Sit Wei Hong params_channels(params), 807dcd79364SMichael Sit Wei Hong params_physical_width(params)); 808bf31cbfbSAnnaliese McDermond 809dcd79364SMichael Sit Wei Hong switch (params_physical_width(params)) { 810bd8a5711SMark Brown case 16: 81164aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 81277bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8131d471cd1SJavier Martin break; 814bd8a5711SMark Brown case 20: 81564aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 81677bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8171d471cd1SJavier Martin break; 818bd8a5711SMark Brown case 24: 81964aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 82077bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8211d471cd1SJavier Martin break; 822bd8a5711SMark Brown case 32: 82364aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 82477bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8251d471cd1SJavier Martin break; 8261d471cd1SJavier Martin } 827b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 82864aab899SAndrew F. Davis AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 8291d471cd1SJavier Martin 830b44aa40fSMarkus Pargmann if (params_channels(params) == 1) { 83164aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 832b44aa40fSMarkus Pargmann } else { 833b44aa40fSMarkus Pargmann if (aic32x4->swapdacs) 83464aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 835b44aa40fSMarkus Pargmann else 83664aab899SAndrew F. Davis dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 837b44aa40fSMarkus Pargmann } 838b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 83964aab899SAndrew F. Davis AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 840b44aa40fSMarkus Pargmann 8411d471cd1SJavier Martin return 0; 8421d471cd1SJavier Martin } 8431d471cd1SJavier Martin 844960af79dSKuninori Morimoto static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction) 8451d471cd1SJavier Martin { 846b154dc5dSKuninori Morimoto struct snd_soc_component *component = dai->component; 8471d471cd1SJavier Martin 848b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 849b7ddd9caSAndrew F. Davis AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 850b7ddd9caSAndrew F. Davis 8511d471cd1SJavier Martin return 0; 8521d471cd1SJavier Martin } 8531d471cd1SJavier Martin 854b154dc5dSKuninori Morimoto static int aic32x4_set_bias_level(struct snd_soc_component *component, 8551d471cd1SJavier Martin enum snd_soc_bias_level level) 8561d471cd1SJavier Martin { 85798b664e2SMarkus Pargmann int ret; 85898b664e2SMarkus Pargmann 859d25970b5SAnnaliese McDermond struct clk_bulk_data clocks[] = { 860d25970b5SAnnaliese McDermond { .id = "madc" }, 861d25970b5SAnnaliese McDermond { .id = "mdac" }, 862d25970b5SAnnaliese McDermond { .id = "bdiv" }, 863d25970b5SAnnaliese McDermond }; 864d25970b5SAnnaliese McDermond 865d25970b5SAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 866d25970b5SAnnaliese McDermond if (ret) 867d25970b5SAnnaliese McDermond return ret; 868d25970b5SAnnaliese McDermond 8691d471cd1SJavier Martin switch (level) { 8701d471cd1SJavier Martin case SND_SOC_BIAS_ON: 871d25970b5SAnnaliese McDermond ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); 87298b664e2SMarkus Pargmann if (ret) { 873d25970b5SAnnaliese McDermond dev_err(component->dev, "Failed to enable clocks\n"); 87498b664e2SMarkus Pargmann return ret; 87598b664e2SMarkus Pargmann } 8761d471cd1SJavier Martin break; 8771d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE: 8781d471cd1SJavier Martin break; 8791d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY: 880667e9334Sb-ak /* Initial cold start */ 881667e9334Sb-ak if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 882667e9334Sb-ak break; 883667e9334Sb-ak 884d25970b5SAnnaliese McDermond clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); 8851d471cd1SJavier Martin break; 8861d471cd1SJavier Martin case SND_SOC_BIAS_OFF: 8871d471cd1SJavier Martin break; 8881d471cd1SJavier Martin } 8891d471cd1SJavier Martin return 0; 8901d471cd1SJavier Martin } 8911d471cd1SJavier Martin 8926d56ee15SAnnaliese McDermond #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 8931d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 894dcd79364SMichael Sit Wei Hong | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \ 895dcd79364SMichael Sit Wei Hong | SNDRV_PCM_FMTBIT_S32_LE) 8961d471cd1SJavier Martin 89785e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = { 8981d471cd1SJavier Martin .hw_params = aic32x4_hw_params, 899960af79dSKuninori Morimoto .mute_stream = aic32x4_mute, 9001d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt, 9011d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk, 902960af79dSKuninori Morimoto .no_capture_mute = 1, 9031d471cd1SJavier Martin }; 9041d471cd1SJavier Martin 9051d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = { 9061d471cd1SJavier Martin .name = "tlv320aic32x4-hifi", 9071d471cd1SJavier Martin .playback = { 9081d471cd1SJavier Martin .stream_name = "Playback", 9091d471cd1SJavier Martin .channels_min = 1, 9101d471cd1SJavier Martin .channels_max = 2, 9111d471cd1SJavier Martin .rates = AIC32X4_RATES, 9121d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 9131d471cd1SJavier Martin .capture = { 9141d471cd1SJavier Martin .stream_name = "Capture", 9151d471cd1SJavier Martin .channels_min = 1, 916d1c859d3SMichael Sit Wei Hong .channels_max = 8, 9171d471cd1SJavier Martin .rates = AIC32X4_RATES, 9181d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 9191d471cd1SJavier Martin .ops = &aic32x4_ops, 920a9aef184SKuninori Morimoto .symmetric_rate = 1, 9211d471cd1SJavier Martin }; 9221d471cd1SJavier Martin 923b154dc5dSKuninori Morimoto static void aic32x4_setup_gpios(struct snd_soc_component *component) 924b9045b9cSDan Murphy { 925b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 926b9045b9cSDan Murphy 927b9045b9cSDan Murphy /* setup GPIO functions */ 928b9045b9cSDan Murphy /* MFP1 */ 929b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 930b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DINCTL, 931b9045b9cSDan Murphy aic32x4->setup->gpio_func[0]); 932b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp1, 933b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp1)); 934b9045b9cSDan Murphy } 935b9045b9cSDan Murphy 936b9045b9cSDan Murphy /* MFP2 */ 937b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 938b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, 939b9045b9cSDan Murphy aic32x4->setup->gpio_func[1]); 940b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp2, 941b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp2)); 942b9045b9cSDan Murphy } 943b9045b9cSDan Murphy 944b9045b9cSDan Murphy /* MFP3 */ 945b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 946b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_SCLKCTL, 947b9045b9cSDan Murphy aic32x4->setup->gpio_func[2]); 948b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp3, 949b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp3)); 950b9045b9cSDan Murphy } 951b9045b9cSDan Murphy 952b9045b9cSDan Murphy /* MFP4 */ 953b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 954b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, 955b9045b9cSDan Murphy aic32x4->setup->gpio_func[3]); 956b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp4, 957b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp4)); 958b9045b9cSDan Murphy } 959b9045b9cSDan Murphy 960b9045b9cSDan Murphy /* MFP5 */ 961b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 962b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, 963b9045b9cSDan Murphy aic32x4->setup->gpio_func[4]); 964b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp5, 965b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp5)); 966b9045b9cSDan Murphy } 967b9045b9cSDan Murphy } 968b9045b9cSDan Murphy 969b154dc5dSKuninori Morimoto static int aic32x4_component_probe(struct snd_soc_component *component) 9701d471cd1SJavier Martin { 971b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 9721d471cd1SJavier Martin u32 tmp_reg; 973fd2df3aeSAnnaliese McDermond int ret; 974fd2df3aeSAnnaliese McDermond 975fd2df3aeSAnnaliese McDermond struct clk_bulk_data clocks[] = { 976fd2df3aeSAnnaliese McDermond { .id = "codec_clkin" }, 977a51b5006SAnnaliese McDermond { .id = "pll" }, 9789b484124SAnnaliese McDermond { .id = "bdiv" }, 9799b484124SAnnaliese McDermond { .id = "mdac" }, 980fd2df3aeSAnnaliese McDermond }; 981fd2df3aeSAnnaliese McDermond 982fd2df3aeSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 983fd2df3aeSAnnaliese McDermond if (ret) 984fd2df3aeSAnnaliese McDermond return ret; 9851d471cd1SJavier Martin 986b9045b9cSDan Murphy if (aic32x4->setup) 987b154dc5dSKuninori Morimoto aic32x4_setup_gpios(component); 988b9045b9cSDan Murphy 989fd2df3aeSAnnaliese McDermond clk_set_parent(clocks[0].clk, clocks[1].clk); 9909b484124SAnnaliese McDermond clk_set_parent(clocks[2].clk, clocks[3].clk); 991fd2df3aeSAnnaliese McDermond 9921d471cd1SJavier Martin /* Power platform configuration */ 9931d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 994514b044cSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_MICBIAS, 995514b044cSAnnaliese McDermond AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 9961d471cd1SJavier Martin } 997eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 998b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 9990c93a167SWolfram Sang 10000c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 10010c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0; 1002b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 10030c93a167SWolfram Sang 1004e348cf54SKuninori Morimoto tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE); 1005eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 10061d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36; 1007eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 10081d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP; 1009b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 10101d471cd1SJavier Martin 10111d471cd1SJavier Martin /* Mic PGA routing */ 1012609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 1013b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 101443bf38baSShahina Shaik AIC32X4_LMICPGANIN_IN2R_10K); 1015609e6025SMarkus Pargmann else 1016b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 101743bf38baSShahina Shaik AIC32X4_LMICPGANIN_CM1L_10K); 1018609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 1019b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 102043bf38baSShahina Shaik AIC32X4_RMICPGANIN_IN1L_10K); 1021609e6025SMarkus Pargmann else 1022b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 102343bf38baSShahina Shaik AIC32X4_RMICPGANIN_CM1R_10K); 10241d471cd1SJavier Martin 1025a405387cSJavier Martin /* 1026a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up 1027a405387cSJavier Martin * and down for the first capture to work properly. It seems related to 1028a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet. 1029a405387cSJavier Martin */ 1030e348cf54SKuninori Morimoto tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP); 1031b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1032a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1033b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1034a405387cSJavier Martin 1035ec96690dSMiquel Raynal /* 1036ec96690dSMiquel Raynal * Enable the fast charging feature and ensure the needed 40ms ellapsed 1037ec96690dSMiquel Raynal * before using the analog circuits. 1038ec96690dSMiquel Raynal */ 1039ec96690dSMiquel Raynal snd_soc_component_write(component, AIC32X4_REFPOWERUP, 1040ec96690dSMiquel Raynal AIC32X4_REFPOWERUP_40MS); 1041ec96690dSMiquel Raynal msleep(40); 1042ec96690dSMiquel Raynal 10431d471cd1SJavier Martin return 0; 10441d471cd1SJavier Martin } 10451d471cd1SJavier Martin 1046b154dc5dSKuninori Morimoto static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1047b154dc5dSKuninori Morimoto .probe = aic32x4_component_probe, 10481d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level, 1049aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls, 1050aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1051aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets, 1052aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1053aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes, 1054aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1055b154dc5dSKuninori Morimoto .suspend_bias_off = 1, 1056b154dc5dSKuninori Morimoto .idle_bias_on = 1, 1057b154dc5dSKuninori Morimoto .use_pmdown_time = 1, 1058b154dc5dSKuninori Morimoto .endianness = 1, 1059b154dc5dSKuninori Morimoto .non_legacy_dai_naming = 1, 10601d471cd1SJavier Martin }; 10611d471cd1SJavier Martin 10624d16700dSMarkus Pargmann static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 10634d16700dSMarkus Pargmann struct device_node *np) 10644d16700dSMarkus Pargmann { 1065b9045b9cSDan Murphy struct aic32x4_setup_data *aic32x4_setup; 1066514b044cSAnnaliese McDermond int ret; 1067b9045b9cSDan Murphy 1068b9045b9cSDan Murphy aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1069b9045b9cSDan Murphy GFP_KERNEL); 1070b9045b9cSDan Murphy if (!aic32x4_setup) 1071b9045b9cSDan Murphy return -ENOMEM; 1072b9045b9cSDan Murphy 1073514b044cSAnnaliese McDermond ret = of_property_match_string(np, "clock-names", "mclk"); 1074514b044cSAnnaliese McDermond if (ret < 0) 1075514b044cSAnnaliese McDermond return -EINVAL; 1076514b044cSAnnaliese McDermond aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1077514b044cSAnnaliese McDermond 10784d16700dSMarkus Pargmann aic32x4->swapdacs = false; 10794d16700dSMarkus Pargmann aic32x4->micpga_routing = 0; 10804d16700dSMarkus Pargmann aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 10814d16700dSMarkus Pargmann 1082b9045b9cSDan Murphy if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1083b9045b9cSDan Murphy aic32x4_setup->gpio_func, 5) >= 0) 1084b9045b9cSDan Murphy aic32x4->setup = aic32x4_setup; 10854d16700dSMarkus Pargmann return 0; 10864d16700dSMarkus Pargmann } 10874d16700dSMarkus Pargmann 1088239b669bSMarkus Pargmann static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1089239b669bSMarkus Pargmann { 1090239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1091239b669bSMarkus Pargmann 1092239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1093239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1094239b669bSMarkus Pargmann 1095239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1096239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1097239b669bSMarkus Pargmann 1098239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) 1099239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_av); 1100239b669bSMarkus Pargmann } 1101239b669bSMarkus Pargmann 1102239b669bSMarkus Pargmann static int aic32x4_setup_regulators(struct device *dev, 1103239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4) 1104239b669bSMarkus Pargmann { 1105239b669bSMarkus Pargmann int ret = 0; 1106239b669bSMarkus Pargmann 1107239b669bSMarkus Pargmann aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1108239b669bSMarkus Pargmann aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1109239b669bSMarkus Pargmann aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1110239b669bSMarkus Pargmann aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1111239b669bSMarkus Pargmann 1112239b669bSMarkus Pargmann /* Check if the regulator requirements are fulfilled */ 1113239b669bSMarkus Pargmann 1114239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_iov)) { 1115239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'iov'\n"); 1116239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_iov); 1117239b669bSMarkus Pargmann } 1118239b669bSMarkus Pargmann 1119239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_ldo)) { 1120239b669bSMarkus Pargmann if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1121239b669bSMarkus Pargmann return -EPROBE_DEFER; 1122239b669bSMarkus Pargmann 1123239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv)) { 1124239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1125239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_dv); 1126239b669bSMarkus Pargmann } 1127239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av)) { 1128239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1129239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_av); 1130239b669bSMarkus Pargmann } 1131239b669bSMarkus Pargmann } else { 113245586c70SMasahiro Yamada if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1133239b669bSMarkus Pargmann return -EPROBE_DEFER; 113445586c70SMasahiro Yamada if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1135239b669bSMarkus Pargmann return -EPROBE_DEFER; 1136239b669bSMarkus Pargmann } 1137239b669bSMarkus Pargmann 1138239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_iov); 1139239b669bSMarkus Pargmann if (ret) { 1140239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator iov\n"); 1141239b669bSMarkus Pargmann return ret; 1142239b669bSMarkus Pargmann } 1143239b669bSMarkus Pargmann 1144239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) { 1145239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_ldo); 1146239b669bSMarkus Pargmann if (ret) { 1147239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator ldo\n"); 1148239b669bSMarkus Pargmann goto error_ldo; 1149239b669bSMarkus Pargmann } 1150239b669bSMarkus Pargmann } 1151239b669bSMarkus Pargmann 1152239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) { 1153239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_dv); 1154239b669bSMarkus Pargmann if (ret) { 1155239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator dv\n"); 1156239b669bSMarkus Pargmann goto error_dv; 1157239b669bSMarkus Pargmann } 1158239b669bSMarkus Pargmann } 1159239b669bSMarkus Pargmann 1160239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) { 1161239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_av); 1162239b669bSMarkus Pargmann if (ret) { 1163239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator av\n"); 1164239b669bSMarkus Pargmann goto error_av; 1165239b669bSMarkus Pargmann } 1166239b669bSMarkus Pargmann } 1167239b669bSMarkus Pargmann 1168239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1169239b669bSMarkus Pargmann aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1170239b669bSMarkus Pargmann 1171239b669bSMarkus Pargmann return 0; 1172239b669bSMarkus Pargmann 1173239b669bSMarkus Pargmann error_av: 1174239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1175239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1176239b669bSMarkus Pargmann 1177239b669bSMarkus Pargmann error_dv: 1178239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1179239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1180239b669bSMarkus Pargmann 1181239b669bSMarkus Pargmann error_ldo: 1182239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1183239b669bSMarkus Pargmann return ret; 1184239b669bSMarkus Pargmann } 1185239b669bSMarkus Pargmann 11863bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap) 11871d471cd1SJavier Martin { 11881d471cd1SJavier Martin struct aic32x4_priv *aic32x4; 11893bcfd222SJeremy McDermond struct aic32x4_pdata *pdata = dev->platform_data; 11903bcfd222SJeremy McDermond struct device_node *np = dev->of_node; 11911d471cd1SJavier Martin int ret; 11921d471cd1SJavier Martin 11933bcfd222SJeremy McDermond if (IS_ERR(regmap)) 11943bcfd222SJeremy McDermond return PTR_ERR(regmap); 11953bcfd222SJeremy McDermond 11963bcfd222SJeremy McDermond aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1197658ecf77SAxel Lin GFP_KERNEL); 11981d471cd1SJavier Martin if (aic32x4 == NULL) 11991d471cd1SJavier Martin return -ENOMEM; 12001d471cd1SJavier Martin 1201b9045b9cSDan Murphy aic32x4->dev = dev; 1202*688d47cdSClaudius Heine aic32x4->type = (enum aic32x4_type)dev_get_drvdata(dev); 1203*688d47cdSClaudius Heine 12043bcfd222SJeremy McDermond dev_set_drvdata(dev, aic32x4); 12051d471cd1SJavier Martin 12061d471cd1SJavier Martin if (pdata) { 12071d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg; 12081d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs; 12091d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing; 12101858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio; 1211514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 12124d16700dSMarkus Pargmann } else if (np) { 12134d16700dSMarkus Pargmann ret = aic32x4_parse_dt(aic32x4, np); 12144d16700dSMarkus Pargmann if (ret) { 12153bcfd222SJeremy McDermond dev_err(dev, "Failed to parse DT node\n"); 12164d16700dSMarkus Pargmann return ret; 12174d16700dSMarkus Pargmann } 12181d471cd1SJavier Martin } else { 12191d471cd1SJavier Martin aic32x4->power_cfg = 0; 12201d471cd1SJavier Martin aic32x4->swapdacs = false; 12211d471cd1SJavier Martin aic32x4->micpga_routing = 0; 12221858fe97SJavier Martin aic32x4->rstn_gpio = -1; 1223514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 12241d471cd1SJavier Martin } 12251d471cd1SJavier Martin 1226a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 12273bcfd222SJeremy McDermond ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1228752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1229752b7764SMark Brown if (ret != 0) 1230752b7764SMark Brown return ret; 1231752b7764SMark Brown } 1232752b7764SMark Brown 12333bcfd222SJeremy McDermond ret = aic32x4_setup_regulators(dev, aic32x4); 1234239b669bSMarkus Pargmann if (ret) { 12353bcfd222SJeremy McDermond dev_err(dev, "Failed to setup regulators\n"); 1236239b669bSMarkus Pargmann return ret; 1237239b669bSMarkus Pargmann } 1238239b669bSMarkus Pargmann 1239df44bc16SMatthias Schiffer if (gpio_is_valid(aic32x4->rstn_gpio)) { 1240df44bc16SMatthias Schiffer ndelay(10); 1241df44bc16SMatthias Schiffer gpio_set_value_cansleep(aic32x4->rstn_gpio, 1); 1242df44bc16SMatthias Schiffer mdelay(1); 1243df44bc16SMatthias Schiffer } 1244df44bc16SMatthias Schiffer 1245df44bc16SMatthias Schiffer ret = regmap_write(regmap, AIC32X4_RESET, 0x01); 1246df44bc16SMatthias Schiffer if (ret) 1247df44bc16SMatthias Schiffer goto err_disable_regulators; 1248df44bc16SMatthias Schiffer 12491ca1156cSAnnaliese McDermond ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 12501ca1156cSAnnaliese McDermond if (ret) 12511ca1156cSAnnaliese McDermond goto err_disable_regulators; 12521ca1156cSAnnaliese McDermond 1253b154dc5dSKuninori Morimoto ret = devm_snd_soc_register_component(dev, 1254b154dc5dSKuninori Morimoto &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1255239b669bSMarkus Pargmann if (ret) { 1256b154dc5dSKuninori Morimoto dev_err(dev, "Failed to register component\n"); 1257251e5c86SMatthias Schiffer goto err_disable_regulators; 12581d471cd1SJavier Martin } 12591d471cd1SJavier Martin 1260239b669bSMarkus Pargmann return 0; 1261251e5c86SMatthias Schiffer 1262251e5c86SMatthias Schiffer err_disable_regulators: 1263251e5c86SMatthias Schiffer aic32x4_disable_regulators(aic32x4); 1264251e5c86SMatthias Schiffer 1265251e5c86SMatthias Schiffer return ret; 1266239b669bSMarkus Pargmann } 12673bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_probe); 1268239b669bSMarkus Pargmann 12693bcfd222SJeremy McDermond int aic32x4_remove(struct device *dev) 12701d471cd1SJavier Martin { 12713bcfd222SJeremy McDermond struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1272239b669bSMarkus Pargmann 1273239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 1274239b669bSMarkus Pargmann 12751d471cd1SJavier Martin return 0; 12761d471cd1SJavier Martin } 12773bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_remove); 12781d471cd1SJavier Martin 12791d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 12801d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 12811d471cd1SJavier Martin MODULE_LICENSE("GPL"); 1282