11d471cd1SJavier Martin /* 21d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c 31d471cd1SJavier Martin * 41d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L. 51d471cd1SJavier Martin * 61d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com> 71d471cd1SJavier Martin * 81d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 91d471cd1SJavier Martin * 101d471cd1SJavier Martin * This program is free software; you can redistribute it and/or modify 111d471cd1SJavier Martin * it under the terms of the GNU General Public License as published by 121d471cd1SJavier Martin * the Free Software Foundation; either version 2 of the License, or 131d471cd1SJavier Martin * (at your option) any later version. 141d471cd1SJavier Martin * 151d471cd1SJavier Martin * This program is distributed in the hope that it will be useful, 161d471cd1SJavier Martin * but WITHOUT ANY WARRANTY; without even the implied warranty of 171d471cd1SJavier Martin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 181d471cd1SJavier Martin * GNU General Public License for more details. 191d471cd1SJavier Martin * 201d471cd1SJavier Martin * You should have received a copy of the GNU General Public License 211d471cd1SJavier Martin * along with this program; if not, write to the Free Software 221d471cd1SJavier Martin * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 231d471cd1SJavier Martin * MA 02110-1301, USA. 241d471cd1SJavier Martin */ 251d471cd1SJavier Martin 261d471cd1SJavier Martin #include <linux/module.h> 271d471cd1SJavier Martin #include <linux/moduleparam.h> 281d471cd1SJavier Martin #include <linux/init.h> 291d471cd1SJavier Martin #include <linux/delay.h> 301d471cd1SJavier Martin #include <linux/pm.h> 311858fe97SJavier Martin #include <linux/gpio.h> 324d16700dSMarkus Pargmann #include <linux/of_gpio.h> 331d471cd1SJavier Martin #include <linux/cdev.h> 341d471cd1SJavier Martin #include <linux/slab.h> 3598b664e2SMarkus Pargmann #include <linux/clk.h> 36*514b044cSAnnaliese McDermond #include <linux/of_clk.h> 37239b669bSMarkus Pargmann #include <linux/regulator/consumer.h> 381d471cd1SJavier Martin 391d471cd1SJavier Martin #include <sound/tlv320aic32x4.h> 401d471cd1SJavier Martin #include <sound/core.h> 411d471cd1SJavier Martin #include <sound/pcm.h> 421d471cd1SJavier Martin #include <sound/pcm_params.h> 431d471cd1SJavier Martin #include <sound/soc.h> 441d471cd1SJavier Martin #include <sound/soc-dapm.h> 451d471cd1SJavier Martin #include <sound/initval.h> 461d471cd1SJavier Martin #include <sound/tlv.h> 471d471cd1SJavier Martin 481d471cd1SJavier Martin #include "tlv320aic32x4.h" 491d471cd1SJavier Martin 501d471cd1SJavier Martin struct aic32x4_rate_divs { 511d471cd1SJavier Martin u32 mclk; 521d471cd1SJavier Martin u32 rate; 53*514b044cSAnnaliese McDermond unsigned long pll_rate; 541d471cd1SJavier Martin u16 dosr; 551d471cd1SJavier Martin u8 ndac; 561d471cd1SJavier Martin u8 mdac; 571d471cd1SJavier Martin u8 aosr; 581d471cd1SJavier Martin u8 nadc; 591d471cd1SJavier Martin u8 madc; 601d471cd1SJavier Martin u8 blck_N; 61c95e3a4bSAnnaliese McDermond u8 r_block; 62c95e3a4bSAnnaliese McDermond u8 p_block; 631d471cd1SJavier Martin }; 641d471cd1SJavier Martin 651d471cd1SJavier Martin struct aic32x4_priv { 664d208ca4SMark Brown struct regmap *regmap; 671d471cd1SJavier Martin u32 sysclk; 681d471cd1SJavier Martin u32 power_cfg; 691d471cd1SJavier Martin u32 micpga_routing; 701d471cd1SJavier Martin bool swapdacs; 711858fe97SJavier Martin int rstn_gpio; 7298b664e2SMarkus Pargmann struct clk *mclk; 73*514b044cSAnnaliese McDermond const char *mclk_name; 74239b669bSMarkus Pargmann 75239b669bSMarkus Pargmann struct regulator *supply_ldo; 76239b669bSMarkus Pargmann struct regulator *supply_iov; 77239b669bSMarkus Pargmann struct regulator *supply_dv; 78239b669bSMarkus Pargmann struct regulator *supply_av; 79b9045b9cSDan Murphy 80b9045b9cSDan Murphy struct aic32x4_setup_data *setup; 81b9045b9cSDan Murphy struct device *dev; 82b9045b9cSDan Murphy }; 83b9045b9cSDan Murphy 8404d979d7Sb-ak static int mic_bias_event(struct snd_soc_dapm_widget *w, 8504d979d7Sb-ak struct snd_kcontrol *kcontrol, int event) 8604d979d7Sb-ak { 8704d979d7Sb-ak struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 8804d979d7Sb-ak 8904d979d7Sb-ak switch (event) { 9004d979d7Sb-ak case SND_SOC_DAPM_POST_PMU: 9104d979d7Sb-ak /* Change Mic Bias Registor */ 9204d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 9304d979d7Sb-ak AIC32x4_MICBIAS_MASK, 9404d979d7Sb-ak AIC32X4_MICBIAS_LDOIN | 9504d979d7Sb-ak AIC32X4_MICBIAS_2075V); 9604d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 9704d979d7Sb-ak break; 9804d979d7Sb-ak case SND_SOC_DAPM_PRE_PMD: 9904d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 10004d979d7Sb-ak AIC32x4_MICBIAS_MASK, 0); 10104d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 10204d979d7Sb-ak __func__); 10304d979d7Sb-ak break; 10404d979d7Sb-ak } 10504d979d7Sb-ak 10604d979d7Sb-ak return 0; 10704d979d7Sb-ak } 10804d979d7Sb-ak 10904d979d7Sb-ak 110b9045b9cSDan Murphy static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 111b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 112b9045b9cSDan Murphy { 113b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 114b9045b9cSDan Murphy u8 val; 115b9045b9cSDan Murphy 116b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_DINCTL); 117b9045b9cSDan Murphy 118b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 119b9045b9cSDan Murphy 120b9045b9cSDan Murphy return 0; 121b9045b9cSDan Murphy }; 122b9045b9cSDan Murphy 123b9045b9cSDan Murphy static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 124b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 125b9045b9cSDan Murphy { 126b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 127b9045b9cSDan Murphy u8 val; 128b9045b9cSDan Murphy u8 gpio_check; 129b9045b9cSDan Murphy 130b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 131b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 132b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 133b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 134b9045b9cSDan Murphy __func__); 135b9045b9cSDan Murphy return -EINVAL; 136b9045b9cSDan Murphy } 137b9045b9cSDan Murphy 138b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 139b9045b9cSDan Murphy return 0; 140b9045b9cSDan Murphy 141b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 142b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 143b9045b9cSDan Murphy else 144b9045b9cSDan Murphy val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 145b9045b9cSDan Murphy 146b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 147b9045b9cSDan Murphy 148b9045b9cSDan Murphy return 0; 149b9045b9cSDan Murphy }; 150b9045b9cSDan Murphy 151b9045b9cSDan Murphy static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 152b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 153b9045b9cSDan Murphy { 154b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 155b9045b9cSDan Murphy u8 val; 156b9045b9cSDan Murphy 157b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 158b9045b9cSDan Murphy 159b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 160b9045b9cSDan Murphy 161b9045b9cSDan Murphy return 0; 162b9045b9cSDan Murphy }; 163b9045b9cSDan Murphy 164b9045b9cSDan Murphy static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 165b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 166b9045b9cSDan Murphy { 167b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 168b9045b9cSDan Murphy u8 val; 169b9045b9cSDan Murphy u8 gpio_check; 170b9045b9cSDan Murphy 171b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 172b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 173b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 174b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 175b9045b9cSDan Murphy __func__); 176b9045b9cSDan Murphy return -EINVAL; 177b9045b9cSDan Murphy } 178b9045b9cSDan Murphy 179b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 180b9045b9cSDan Murphy return 0; 181b9045b9cSDan Murphy 182b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 183b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 184b9045b9cSDan Murphy else 185b9045b9cSDan Murphy val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 186b9045b9cSDan Murphy 187b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, val); 188b9045b9cSDan Murphy 189b9045b9cSDan Murphy return 0; 190b9045b9cSDan Murphy }; 191b9045b9cSDan Murphy 192b9045b9cSDan Murphy static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 193b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 194b9045b9cSDan Murphy { 195b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 196b9045b9cSDan Murphy u8 val; 197b9045b9cSDan Murphy 198b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 199b9045b9cSDan Murphy ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 200b9045b9cSDan Murphy 201b9045b9cSDan Murphy return 0; 202b9045b9cSDan Murphy }; 203b9045b9cSDan Murphy 204b9045b9cSDan Murphy static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 205b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 206b9045b9cSDan Murphy { 207b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 208b9045b9cSDan Murphy u8 val; 209b9045b9cSDan Murphy u8 gpio_check; 210b9045b9cSDan Murphy 211b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 212b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 213b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 214b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 215b9045b9cSDan Murphy __func__); 216b9045b9cSDan Murphy return -EINVAL; 217b9045b9cSDan Murphy } 218b9045b9cSDan Murphy 219b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & 0x1)) 220b9045b9cSDan Murphy return 0; 221b9045b9cSDan Murphy 222b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 223b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 224b9045b9cSDan Murphy else 225b9045b9cSDan Murphy val &= 0xfe; 226b9045b9cSDan Murphy 227b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 228b9045b9cSDan Murphy 229b9045b9cSDan Murphy return 0; 230b9045b9cSDan Murphy }; 231b9045b9cSDan Murphy 232b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp1[] = { 233b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 234b9045b9cSDan Murphy }; 235b9045b9cSDan Murphy 236b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp2[] = { 237b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 238b9045b9cSDan Murphy }; 239b9045b9cSDan Murphy 240b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp3[] = { 241b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 242b9045b9cSDan Murphy }; 243b9045b9cSDan Murphy 244b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp4[] = { 245b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 246b9045b9cSDan Murphy }; 247b9045b9cSDan Murphy 248b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp5[] = { 249b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 250b9045b9cSDan Murphy aic32x4_set_mfp5_gpio), 2511d471cd1SJavier Martin }; 2521d471cd1SJavier Martin 2531d471cd1SJavier Martin /* 0dB min, 0.5dB steps */ 2541d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 255c671e79dSMarkus Pargmann /* -63.5dB min, 0.5dB steps */ 256c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 257c671e79dSMarkus Pargmann /* -6dB min, 1dB steps */ 258c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 259c671e79dSMarkus Pargmann /* -12dB min, 0.5dB steps */ 260c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 2611d471cd1SJavier Martin 2621d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 263c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 264c671e79dSMarkus Pargmann AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 265c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 266c671e79dSMarkus Pargmann AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 267c671e79dSMarkus Pargmann tlv_driver_gain), 268c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 269c671e79dSMarkus Pargmann AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 270c671e79dSMarkus Pargmann tlv_driver_gain), 2711d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 2721d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1), 2731d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 2741d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1), 2751d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 2761d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1), 2771d471cd1SJavier Martin 2781d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 2791d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 2801d471cd1SJavier Martin 281c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 282c671e79dSMarkus Pargmann AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 2831d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 2841d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 2851d471cd1SJavier Martin 2861d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 2871d471cd1SJavier Martin 2881d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 2891d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 2901d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 2911d471cd1SJavier Martin 4, 0x07, 0), 2921d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 2931d471cd1SJavier Martin 0, 0x03, 0), 2941d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 2951d471cd1SJavier Martin 6, 0x03, 0), 2961d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 2971d471cd1SJavier Martin 1, 0x1F, 0), 2981d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 2991d471cd1SJavier Martin 0, 0x7F, 0), 3001d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 3011d471cd1SJavier Martin 3, 0x1F, 0), 3021d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 3031d471cd1SJavier Martin 3, 0x1F, 0), 3041d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 3051d471cd1SJavier Martin 0, 0x1F, 0), 3061d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 3071d471cd1SJavier Martin 0, 0x0F, 0), 3081d471cd1SJavier Martin }; 3091d471cd1SJavier Martin 3101d471cd1SJavier Martin static const struct aic32x4_rate_divs aic32x4_divs[] = { 3111d471cd1SJavier Martin /* 8k rate */ 312*514b044cSAnnaliese McDermond { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 }, 313*514b044cSAnnaliese McDermond { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, 314*514b044cSAnnaliese McDermond { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 }, 3151d471cd1SJavier Martin /* 11.025k rate */ 316*514b044cSAnnaliese McDermond { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 }, 317*514b044cSAnnaliese McDermond { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 }, 3181d471cd1SJavier Martin /* 16k rate */ 319*514b044cSAnnaliese McDermond { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 }, 320*514b044cSAnnaliese McDermond { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, 321*514b044cSAnnaliese McDermond { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 }, 3221d471cd1SJavier Martin /* 22.05k rate */ 323*514b044cSAnnaliese McDermond { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 }, 324*514b044cSAnnaliese McDermond { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, 325*514b044cSAnnaliese McDermond { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 }, 3261d471cd1SJavier Martin /* 32k rate */ 327*514b044cSAnnaliese McDermond { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 }, 328*514b044cSAnnaliese McDermond { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 }, 3291d471cd1SJavier Martin /* 44.1k rate */ 330*514b044cSAnnaliese McDermond { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, 331*514b044cSAnnaliese McDermond { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 332*514b044cSAnnaliese McDermond { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 3331d471cd1SJavier Martin /* 48k rate */ 334*514b044cSAnnaliese McDermond { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 }, 335*514b044cSAnnaliese McDermond { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 336*514b044cSAnnaliese McDermond { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 }, 337041f9d33SJeremy McDermond 338041f9d33SJeremy McDermond /* 96k rate */ 339*514b044cSAnnaliese McDermond { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 }, 3401d471cd1SJavier Martin }; 3411d471cd1SJavier Martin 3421d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 3431d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 3441d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 3451d471cd1SJavier Martin }; 3461d471cd1SJavier Martin 3471d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 3481d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 3491d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 3501d471cd1SJavier Martin }; 3511d471cd1SJavier Martin 3521d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 3531d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 3541d471cd1SJavier Martin }; 3551d471cd1SJavier Martin 3561d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 3571d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 3581d471cd1SJavier Martin }; 3591d471cd1SJavier Martin 36020d2cecbSJeremy McDermond static const char * const resistor_text[] = { 36120d2cecbSJeremy McDermond "Off", "10 kOhm", "20 kOhm", "40 kOhm", 3621d471cd1SJavier Martin }; 3631d471cd1SJavier Martin 3642213fc35SJeremy McDermond /* Left mixer pins */ 3652213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 3662213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 3672213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 3682213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 36920d2cecbSJeremy McDermond 3702213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 3712213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 3722213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 3732213fc35SJeremy McDermond 3742213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 3752213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 3762213fc35SJeremy McDermond }; 3772213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 3782213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 3792213fc35SJeremy McDermond }; 3802213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 3812213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 3822213fc35SJeremy McDermond }; 3832213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 3842213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 3852213fc35SJeremy McDermond }; 3862213fc35SJeremy McDermond static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 3872213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 3882213fc35SJeremy McDermond }; 3892213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 3902213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 3912213fc35SJeremy McDermond }; 3922213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 3932213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 39420d2cecbSJeremy McDermond }; 39520d2cecbSJeremy McDermond 3962213fc35SJeremy McDermond /* Right mixer pins */ 3972213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 3982213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 3992213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 4002213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 4012213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 4022213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 4032213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 40420d2cecbSJeremy McDermond 4052213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 4062213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 4072213fc35SJeremy McDermond }; 4082213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 4092213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 4102213fc35SJeremy McDermond }; 4112213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 4122213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 4132213fc35SJeremy McDermond }; 4142213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 4152213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 4162213fc35SJeremy McDermond }; 4172213fc35SJeremy McDermond static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 4182213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 4192213fc35SJeremy McDermond }; 4202213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 4212213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 4222213fc35SJeremy McDermond }; 4232213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 4242213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 4251d471cd1SJavier Martin }; 4261d471cd1SJavier Martin 4271d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 4281d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 4291d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 4301d471cd1SJavier Martin &hpl_output_mixer_controls[0], 4311d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)), 4321d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 4331d471cd1SJavier Martin 4341d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 4351d471cd1SJavier Martin &lol_output_mixer_controls[0], 4361d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)), 4371d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 4381d471cd1SJavier Martin 4391d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 4401d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 4411d471cd1SJavier Martin &hpr_output_mixer_controls[0], 4421d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)), 4431d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 4441d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 4451d471cd1SJavier Martin &lor_output_mixer_controls[0], 4461d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)), 4471d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 4482213fc35SJeremy McDermond 4491d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 4502213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4512213fc35SJeremy McDermond in1r_to_rmixer_controls), 4522213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4532213fc35SJeremy McDermond in2r_to_rmixer_controls), 4542213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4552213fc35SJeremy McDermond in3r_to_rmixer_controls), 4562213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4572213fc35SJeremy McDermond in2l_to_rmixer_controls), 4582213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4592213fc35SJeremy McDermond cmr_to_rmixer_controls), 4602213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4612213fc35SJeremy McDermond in1l_to_rmixer_controls), 4622213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4632213fc35SJeremy McDermond in3l_to_rmixer_controls), 4642213fc35SJeremy McDermond 4652213fc35SJeremy McDermond SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 4662213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4672213fc35SJeremy McDermond in1l_to_lmixer_controls), 4682213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4692213fc35SJeremy McDermond in2l_to_lmixer_controls), 4702213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4712213fc35SJeremy McDermond in3l_to_lmixer_controls), 4722213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4732213fc35SJeremy McDermond in1r_to_lmixer_controls), 4742213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4752213fc35SJeremy McDermond cml_to_lmixer_controls), 4762213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4772213fc35SJeremy McDermond in2r_to_lmixer_controls), 4782213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4792213fc35SJeremy McDermond in3r_to_lmixer_controls), 4802213fc35SJeremy McDermond 48104d979d7Sb-ak SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 48204d979d7Sb-ak SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 48304d979d7Sb-ak 4841d471cd1SJavier Martin 4851d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"), 4861d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"), 4871d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"), 4881d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"), 4891d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"), 4901d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"), 4911d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"), 4921d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"), 4931d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"), 4941d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"), 4951d471cd1SJavier Martin }; 4961d471cd1SJavier Martin 4971d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 4981d471cd1SJavier Martin /* Left Output */ 4991d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 5001d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 5011d471cd1SJavier Martin 5021d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"}, 5031d471cd1SJavier Martin {"HPL", NULL, "HPL Power"}, 5041d471cd1SJavier Martin 5051d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 5061d471cd1SJavier Martin 5071d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"}, 5081d471cd1SJavier Martin {"LOL", NULL, "LOL Power"}, 5091d471cd1SJavier Martin 5101d471cd1SJavier Martin /* Right Output */ 5111d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 5121d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 5131d471cd1SJavier Martin 5141d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"}, 5151d471cd1SJavier Martin {"HPR", NULL, "HPR Power"}, 5161d471cd1SJavier Martin 5171d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 5181d471cd1SJavier Martin 5191d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"}, 5201d471cd1SJavier Martin {"LOR", NULL, "LOR Power"}, 5211d471cd1SJavier Martin 5221d471cd1SJavier Martin /* Right Input */ 5232213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 5242213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 5252213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 5262213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 5271d471cd1SJavier Martin 5282213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 5292213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 5302213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 5312213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 5322213fc35SJeremy McDermond 5332213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 5342213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 5352213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 5362213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 5372213fc35SJeremy McDermond 5382213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 5392213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5402213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5412213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5422213fc35SJeremy McDermond 5432213fc35SJeremy McDermond {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 5442213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 5452213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 5462213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 5472213fc35SJeremy McDermond 5482213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 5492213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 5502213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 5512213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 5522213fc35SJeremy McDermond 5532213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 5542213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 5552213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 5562213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 5572213fc35SJeremy McDermond 5582213fc35SJeremy McDermond /* Left Input */ 5592213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 5602213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 5612213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 5622213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 5632213fc35SJeremy McDermond 5642213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 5652213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5662213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5672213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5682213fc35SJeremy McDermond 5692213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 5702213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 5712213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 5722213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 5732213fc35SJeremy McDermond 5742213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 5752213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 5762213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 5772213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 5782213fc35SJeremy McDermond 5792213fc35SJeremy McDermond {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 5802213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 5812213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 5822213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 5832213fc35SJeremy McDermond 5842213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 5852213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 5862213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 5872213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 5882213fc35SJeremy McDermond 5892213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 5902213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 5912213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 5922213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 5931d471cd1SJavier Martin }; 5941d471cd1SJavier Martin 5954d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 5961d471cd1SJavier Martin { 5974d208ca4SMark Brown .selector_reg = 0, 5984d208ca4SMark Brown .selector_mask = 0xff, 5994d208ca4SMark Brown .window_start = 0, 6004d208ca4SMark Brown .window_len = 128, 601e8e08c52SMarkus Pargmann .range_min = 0, 6026d0d5103SMarkus Pargmann .range_max = AIC32X4_RMICPGAVOL, 6034d208ca4SMark Brown }, 6044d208ca4SMark Brown }; 6051d471cd1SJavier Martin 6063bcfd222SJeremy McDermond const struct regmap_config aic32x4_regmap_config = { 6074d208ca4SMark Brown .max_register = AIC32X4_RMICPGAVOL, 6084d208ca4SMark Brown .ranges = aic32x4_regmap_pages, 6094d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 6104d208ca4SMark Brown }; 6113bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_regmap_config); 6121d471cd1SJavier Martin 6131d471cd1SJavier Martin static inline int aic32x4_get_divs(int mclk, int rate) 6141d471cd1SJavier Martin { 6151d471cd1SJavier Martin int i; 6161d471cd1SJavier Martin 6171d471cd1SJavier Martin for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 6181d471cd1SJavier Martin if ((aic32x4_divs[i].rate == rate) 6191d471cd1SJavier Martin && (aic32x4_divs[i].mclk == mclk)) { 6201d471cd1SJavier Martin return i; 6211d471cd1SJavier Martin } 6221d471cd1SJavier Martin } 6231d471cd1SJavier Martin printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 6241d471cd1SJavier Martin return -EINVAL; 6251d471cd1SJavier Martin } 6261d471cd1SJavier Martin 6271d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 6281d471cd1SJavier Martin int clk_id, unsigned int freq, int dir) 6291d471cd1SJavier Martin { 630b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 631b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 6321d471cd1SJavier Martin 6331d471cd1SJavier Martin switch (freq) { 6347e2a4dc5SAndrew F. Davis case 12000000: 6357e2a4dc5SAndrew F. Davis case 24000000: 6367e2a4dc5SAndrew F. Davis case 25000000: 6371d471cd1SJavier Martin aic32x4->sysclk = freq; 6381d471cd1SJavier Martin return 0; 6391d471cd1SJavier Martin } 6401d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 6411d471cd1SJavier Martin return -EINVAL; 6421d471cd1SJavier Martin } 6431d471cd1SJavier Martin 6441d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 6451d471cd1SJavier Martin { 646b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 64760fb4be5SAndrew F. Davis u8 iface_reg_1 = 0; 64860fb4be5SAndrew F. Davis u8 iface_reg_2 = 0; 64960fb4be5SAndrew F. Davis u8 iface_reg_3 = 0; 6501d471cd1SJavier Martin 6511d471cd1SJavier Martin /* set master/slave audio interface */ 6521d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 6531d471cd1SJavier Martin case SND_SOC_DAIFMT_CBM_CFM: 6541d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 6551d471cd1SJavier Martin break; 6561d471cd1SJavier Martin case SND_SOC_DAIFMT_CBS_CFS: 6571d471cd1SJavier Martin break; 6581d471cd1SJavier Martin default: 6591d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 6601d471cd1SJavier Martin return -EINVAL; 6611d471cd1SJavier Martin } 6621d471cd1SJavier Martin 6631d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 6641d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S: 6651d471cd1SJavier Martin break; 6661d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A: 6674483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6684483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 66960fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6701d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */ 6711d471cd1SJavier Martin break; 6721d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B: 6734483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6744483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 67560fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6761d471cd1SJavier Martin break; 6771d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J: 6784483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 6794483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6801d471cd1SJavier Martin break; 6811d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J: 6824483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 6834483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6841d471cd1SJavier Martin break; 6851d471cd1SJavier Martin default: 6861d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 6871d471cd1SJavier Martin return -EINVAL; 6881d471cd1SJavier Martin } 6891d471cd1SJavier Martin 690b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 69160fb4be5SAndrew F. Davis AIC32X4_IFACE1_DATATYPE_MASK | 69260fb4be5SAndrew F. Davis AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 693b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE2, 69460fb4be5SAndrew F. Davis AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 695b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE3, 69660fb4be5SAndrew F. Davis AIC32X4_BCLKINV_MASK, iface_reg_3); 69760fb4be5SAndrew F. Davis 6981d471cd1SJavier Martin return 0; 6991d471cd1SJavier Martin } 7001d471cd1SJavier Martin 701c95e3a4bSAnnaliese McDermond static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 702c95e3a4bSAnnaliese McDermond u8 r_block, u8 p_block) 703c95e3a4bSAnnaliese McDermond { 704c95e3a4bSAnnaliese McDermond if (r_block > 18 || p_block > 25) 705c95e3a4bSAnnaliese McDermond return -EINVAL; 706c95e3a4bSAnnaliese McDermond 707c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 708c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 709c95e3a4bSAnnaliese McDermond 710c95e3a4bSAnnaliese McDermond return 0; 711c95e3a4bSAnnaliese McDermond } 712c95e3a4bSAnnaliese McDermond 713bf31cbfbSAnnaliese McDermond static int aic32x4_setup_clocks(struct snd_soc_component *component, 714bf31cbfbSAnnaliese McDermond unsigned int sample_rate, 715bf31cbfbSAnnaliese McDermond unsigned int parent_rate) 7161d471cd1SJavier Martin { 7171d471cd1SJavier Martin int i; 718*514b044cSAnnaliese McDermond int ret; 719*514b044cSAnnaliese McDermond 720*514b044cSAnnaliese McDermond struct clk_bulk_data clocks[] = { 721*514b044cSAnnaliese McDermond { .id = "pll" }, 722*514b044cSAnnaliese McDermond }; 7231d471cd1SJavier Martin 724bf31cbfbSAnnaliese McDermond i = aic32x4_get_divs(parent_rate, sample_rate); 7251d471cd1SJavier Martin if (i < 0) { 7261d471cd1SJavier Martin printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 7271d471cd1SJavier Martin return i; 7281d471cd1SJavier Martin } 7291d471cd1SJavier Martin 730*514b044cSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 731*514b044cSAnnaliese McDermond if (ret) 732*514b044cSAnnaliese McDermond return ret; 733*514b044cSAnnaliese McDermond 734*514b044cSAnnaliese McDermond clk_set_rate(clocks[0].clk, sample_rate); 735*514b044cSAnnaliese McDermond 736c95e3a4bSAnnaliese McDermond aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); 737c95e3a4bSAnnaliese McDermond 73864aab899SAndrew F. Davis /* PLL as CODEC_CLKIN */ 739*514b044cSAnnaliese McDermond snd_soc_component_update_bits(component, AIC32X4_CLKMUX, 740*514b044cSAnnaliese McDermond AIC32X4_CODEC_CLKIN_MASK, 74164aab899SAndrew F. Davis AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT); 74264aab899SAndrew F. Davis /* DAC_MOD_CLK as BDIV_CLKIN */ 743b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK, 74464aab899SAndrew F. Davis AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); 7451d471cd1SJavier Martin 7461d471cd1SJavier Martin /* NDAC divider value */ 747b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_NDAC, 74864aab899SAndrew F. Davis AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac); 7491d471cd1SJavier Martin 7501d471cd1SJavier Martin /* MDAC divider value */ 751b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_MDAC, 75264aab899SAndrew F. Davis AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac); 7531d471cd1SJavier Martin 7541d471cd1SJavier Martin /* DOSR MSB & LSB values */ 755b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 756b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff)); 7571d471cd1SJavier Martin 7581d471cd1SJavier Martin /* NADC divider value */ 759b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_NADC, 76064aab899SAndrew F. Davis AIC32X4_NADC_MASK, aic32x4_divs[i].nadc); 7611d471cd1SJavier Martin 7621d471cd1SJavier Martin /* MADC divider value */ 763b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_MADC, 76464aab899SAndrew F. Davis AIC32X4_MADC_MASK, aic32x4_divs[i].madc); 7651d471cd1SJavier Martin 7661d471cd1SJavier Martin /* AOSR value */ 767b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); 7681d471cd1SJavier Martin 7691d471cd1SJavier Martin /* BCLK N divider */ 770b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_BCLKN, 77164aab899SAndrew F. Davis AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N); 7721d471cd1SJavier Martin 773bf31cbfbSAnnaliese McDermond return 0; 774bf31cbfbSAnnaliese McDermond } 775bf31cbfbSAnnaliese McDermond 776bf31cbfbSAnnaliese McDermond static int aic32x4_hw_params(struct snd_pcm_substream *substream, 777bf31cbfbSAnnaliese McDermond struct snd_pcm_hw_params *params, 778bf31cbfbSAnnaliese McDermond struct snd_soc_dai *dai) 779bf31cbfbSAnnaliese McDermond { 780bf31cbfbSAnnaliese McDermond struct snd_soc_component *component = dai->component; 781bf31cbfbSAnnaliese McDermond struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 782bf31cbfbSAnnaliese McDermond u8 iface1_reg = 0; 783bf31cbfbSAnnaliese McDermond u8 dacsetup_reg = 0; 784bf31cbfbSAnnaliese McDermond 785bf31cbfbSAnnaliese McDermond aic32x4_setup_clocks(component, params_rate(params), aic32x4->sysclk); 786bf31cbfbSAnnaliese McDermond 787bd8a5711SMark Brown switch (params_width(params)) { 788bd8a5711SMark Brown case 16: 78964aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 79077bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7911d471cd1SJavier Martin break; 792bd8a5711SMark Brown case 20: 79364aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 79477bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7951d471cd1SJavier Martin break; 796bd8a5711SMark Brown case 24: 79764aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 79877bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7991d471cd1SJavier Martin break; 800bd8a5711SMark Brown case 32: 80164aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 80277bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 8031d471cd1SJavier Martin break; 8041d471cd1SJavier Martin } 805b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 80664aab899SAndrew F. Davis AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 8071d471cd1SJavier Martin 808b44aa40fSMarkus Pargmann if (params_channels(params) == 1) { 80964aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 810b44aa40fSMarkus Pargmann } else { 811b44aa40fSMarkus Pargmann if (aic32x4->swapdacs) 81264aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 813b44aa40fSMarkus Pargmann else 81464aab899SAndrew F. Davis dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 815b44aa40fSMarkus Pargmann } 816b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 81764aab899SAndrew F. Davis AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 818b44aa40fSMarkus Pargmann 8191d471cd1SJavier Martin return 0; 8201d471cd1SJavier Martin } 8211d471cd1SJavier Martin 8221d471cd1SJavier Martin static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 8231d471cd1SJavier Martin { 824b154dc5dSKuninori Morimoto struct snd_soc_component *component = dai->component; 8251d471cd1SJavier Martin 826b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 827b7ddd9caSAndrew F. Davis AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 828b7ddd9caSAndrew F. Davis 8291d471cd1SJavier Martin return 0; 8301d471cd1SJavier Martin } 8311d471cd1SJavier Martin 832b154dc5dSKuninori Morimoto static int aic32x4_set_bias_level(struct snd_soc_component *component, 8331d471cd1SJavier Martin enum snd_soc_bias_level level) 8341d471cd1SJavier Martin { 835b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 83698b664e2SMarkus Pargmann int ret; 83798b664e2SMarkus Pargmann 8381d471cd1SJavier Martin switch (level) { 8391d471cd1SJavier Martin case SND_SOC_BIAS_ON: 84098b664e2SMarkus Pargmann /* Switch on master clock */ 84198b664e2SMarkus Pargmann ret = clk_prepare_enable(aic32x4->mclk); 84298b664e2SMarkus Pargmann if (ret) { 843b154dc5dSKuninori Morimoto dev_err(component->dev, "Failed to enable master clock\n"); 84498b664e2SMarkus Pargmann return ret; 84598b664e2SMarkus Pargmann } 84698b664e2SMarkus Pargmann 8471d471cd1SJavier Martin /* Switch on PLL */ 848b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_PLLPR, 849bc6ae96aSAxel Lin AIC32X4_PLLEN, AIC32X4_PLLEN); 8501d471cd1SJavier Martin 8511d471cd1SJavier Martin /* Switch on NDAC Divider */ 852b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_NDAC, 853bc6ae96aSAxel Lin AIC32X4_NDACEN, AIC32X4_NDACEN); 8541d471cd1SJavier Martin 8551d471cd1SJavier Martin /* Switch on MDAC Divider */ 856b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_MDAC, 857bc6ae96aSAxel Lin AIC32X4_MDACEN, AIC32X4_MDACEN); 8581d471cd1SJavier Martin 8591d471cd1SJavier Martin /* Switch on NADC Divider */ 860b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_NADC, 861bc6ae96aSAxel Lin AIC32X4_NADCEN, AIC32X4_NADCEN); 8621d471cd1SJavier Martin 8631d471cd1SJavier Martin /* Switch on MADC Divider */ 864b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_MADC, 865bc6ae96aSAxel Lin AIC32X4_MADCEN, AIC32X4_MADCEN); 8661d471cd1SJavier Martin 8671d471cd1SJavier Martin /* Switch on BCLK_N Divider */ 868b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_BCLKN, 869bc6ae96aSAxel Lin AIC32X4_BCLKEN, AIC32X4_BCLKEN); 8701d471cd1SJavier Martin break; 8711d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE: 8721d471cd1SJavier Martin break; 8731d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY: 874667e9334Sb-ak /* Initial cold start */ 875667e9334Sb-ak if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 876667e9334Sb-ak break; 877667e9334Sb-ak 8783154cc74SMarkus Pargmann /* Switch off BCLK_N Divider */ 879b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_BCLKN, 8803154cc74SMarkus Pargmann AIC32X4_BCLKEN, 0); 8811d471cd1SJavier Martin 8821d471cd1SJavier Martin /* Switch off MADC Divider */ 883b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_MADC, 884bc6ae96aSAxel Lin AIC32X4_MADCEN, 0); 8851d471cd1SJavier Martin 8863154cc74SMarkus Pargmann /* Switch off NADC Divider */ 887b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_NADC, 8883154cc74SMarkus Pargmann AIC32X4_NADCEN, 0); 8893154cc74SMarkus Pargmann 8903154cc74SMarkus Pargmann /* Switch off MDAC Divider */ 891b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_MDAC, 8923154cc74SMarkus Pargmann AIC32X4_MDACEN, 0); 8933154cc74SMarkus Pargmann 8943154cc74SMarkus Pargmann /* Switch off NDAC Divider */ 895b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_NDAC, 8963154cc74SMarkus Pargmann AIC32X4_NDACEN, 0); 8973154cc74SMarkus Pargmann 8983154cc74SMarkus Pargmann /* Switch off PLL */ 899b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_PLLPR, 9003154cc74SMarkus Pargmann AIC32X4_PLLEN, 0); 90198b664e2SMarkus Pargmann 90298b664e2SMarkus Pargmann /* Switch off master clock */ 90398b664e2SMarkus Pargmann clk_disable_unprepare(aic32x4->mclk); 9041d471cd1SJavier Martin break; 9051d471cd1SJavier Martin case SND_SOC_BIAS_OFF: 9061d471cd1SJavier Martin break; 9071d471cd1SJavier Martin } 9081d471cd1SJavier Martin return 0; 9091d471cd1SJavier Martin } 9101d471cd1SJavier Martin 911041f9d33SJeremy McDermond #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000 9121d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 9131d471cd1SJavier Martin | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 9141d471cd1SJavier Martin 91585e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = { 9161d471cd1SJavier Martin .hw_params = aic32x4_hw_params, 9171d471cd1SJavier Martin .digital_mute = aic32x4_mute, 9181d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt, 9191d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk, 9201d471cd1SJavier Martin }; 9211d471cd1SJavier Martin 9221d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = { 9231d471cd1SJavier Martin .name = "tlv320aic32x4-hifi", 9241d471cd1SJavier Martin .playback = { 9251d471cd1SJavier Martin .stream_name = "Playback", 9261d471cd1SJavier Martin .channels_min = 1, 9271d471cd1SJavier Martin .channels_max = 2, 9281d471cd1SJavier Martin .rates = AIC32X4_RATES, 9291d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 9301d471cd1SJavier Martin .capture = { 9311d471cd1SJavier Martin .stream_name = "Capture", 9321d471cd1SJavier Martin .channels_min = 1, 9331d471cd1SJavier Martin .channels_max = 2, 9341d471cd1SJavier Martin .rates = AIC32X4_RATES, 9351d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 9361d471cd1SJavier Martin .ops = &aic32x4_ops, 9371d471cd1SJavier Martin .symmetric_rates = 1, 9381d471cd1SJavier Martin }; 9391d471cd1SJavier Martin 940b154dc5dSKuninori Morimoto static void aic32x4_setup_gpios(struct snd_soc_component *component) 941b9045b9cSDan Murphy { 942b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 943b9045b9cSDan Murphy 944b9045b9cSDan Murphy /* setup GPIO functions */ 945b9045b9cSDan Murphy /* MFP1 */ 946b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 947b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DINCTL, 948b9045b9cSDan Murphy aic32x4->setup->gpio_func[0]); 949b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp1, 950b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp1)); 951b9045b9cSDan Murphy } 952b9045b9cSDan Murphy 953b9045b9cSDan Murphy /* MFP2 */ 954b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 955b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, 956b9045b9cSDan Murphy aic32x4->setup->gpio_func[1]); 957b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp2, 958b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp2)); 959b9045b9cSDan Murphy } 960b9045b9cSDan Murphy 961b9045b9cSDan Murphy /* MFP3 */ 962b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 963b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_SCLKCTL, 964b9045b9cSDan Murphy aic32x4->setup->gpio_func[2]); 965b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp3, 966b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp3)); 967b9045b9cSDan Murphy } 968b9045b9cSDan Murphy 969b9045b9cSDan Murphy /* MFP4 */ 970b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 971b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, 972b9045b9cSDan Murphy aic32x4->setup->gpio_func[3]); 973b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp4, 974b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp4)); 975b9045b9cSDan Murphy } 976b9045b9cSDan Murphy 977b9045b9cSDan Murphy /* MFP5 */ 978b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 979b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, 980b9045b9cSDan Murphy aic32x4->setup->gpio_func[4]); 981b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp5, 982b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp5)); 983b9045b9cSDan Murphy } 984b9045b9cSDan Murphy } 985b9045b9cSDan Murphy 986b154dc5dSKuninori Morimoto static int aic32x4_component_probe(struct snd_soc_component *component) 9871d471cd1SJavier Martin { 988b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 9891d471cd1SJavier Martin u32 tmp_reg; 9901d471cd1SJavier Martin 991a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 9921858fe97SJavier Martin ndelay(10); 9931858fe97SJavier Martin gpio_set_value(aic32x4->rstn_gpio, 1); 994674f9abdSPeter Seiderer mdelay(1); 9951858fe97SJavier Martin } 9961858fe97SJavier Martin 997b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RESET, 0x01); 9981d471cd1SJavier Martin 999b9045b9cSDan Murphy if (aic32x4->setup) 1000b154dc5dSKuninori Morimoto aic32x4_setup_gpios(component); 1001b9045b9cSDan Murphy 10021d471cd1SJavier Martin /* Power platform configuration */ 10031d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 1004*514b044cSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_MICBIAS, 1005*514b044cSAnnaliese McDermond AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 10061d471cd1SJavier Martin } 1007eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 1008b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 10090c93a167SWolfram Sang 10100c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 10110c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0; 1012b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 10130c93a167SWolfram Sang 1014b154dc5dSKuninori Morimoto tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 1015eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 10161d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36; 1017eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 10181d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP; 1019b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 10201d471cd1SJavier Martin 10211d471cd1SJavier Martin /* Mic PGA routing */ 1022609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 1023b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 102443bf38baSShahina Shaik AIC32X4_LMICPGANIN_IN2R_10K); 1025609e6025SMarkus Pargmann else 1026b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 102743bf38baSShahina Shaik AIC32X4_LMICPGANIN_CM1L_10K); 1028609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 1029b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 103043bf38baSShahina Shaik AIC32X4_RMICPGANIN_IN1L_10K); 1031609e6025SMarkus Pargmann else 1032b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 103343bf38baSShahina Shaik AIC32X4_RMICPGANIN_CM1R_10K); 10341d471cd1SJavier Martin 1035a405387cSJavier Martin /* 1036a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up 1037a405387cSJavier Martin * and down for the first capture to work properly. It seems related to 1038a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet. 1039a405387cSJavier Martin */ 1040b154dc5dSKuninori Morimoto tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 1041b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1042a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1043b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1044a405387cSJavier Martin 10451d471cd1SJavier Martin return 0; 10461d471cd1SJavier Martin } 10471d471cd1SJavier Martin 1048b154dc5dSKuninori Morimoto static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1049b154dc5dSKuninori Morimoto .probe = aic32x4_component_probe, 10501d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level, 1051aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls, 1052aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1053aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets, 1054aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1055aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes, 1056aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1057b154dc5dSKuninori Morimoto .suspend_bias_off = 1, 1058b154dc5dSKuninori Morimoto .idle_bias_on = 1, 1059b154dc5dSKuninori Morimoto .use_pmdown_time = 1, 1060b154dc5dSKuninori Morimoto .endianness = 1, 1061b154dc5dSKuninori Morimoto .non_legacy_dai_naming = 1, 10621d471cd1SJavier Martin }; 10631d471cd1SJavier Martin 10644d16700dSMarkus Pargmann static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 10654d16700dSMarkus Pargmann struct device_node *np) 10664d16700dSMarkus Pargmann { 1067b9045b9cSDan Murphy struct aic32x4_setup_data *aic32x4_setup; 1068*514b044cSAnnaliese McDermond int ret; 1069b9045b9cSDan Murphy 1070b9045b9cSDan Murphy aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1071b9045b9cSDan Murphy GFP_KERNEL); 1072b9045b9cSDan Murphy if (!aic32x4_setup) 1073b9045b9cSDan Murphy return -ENOMEM; 1074b9045b9cSDan Murphy 1075*514b044cSAnnaliese McDermond ret = of_property_match_string(np, "clock-names", "mclk"); 1076*514b044cSAnnaliese McDermond if (ret < 0) 1077*514b044cSAnnaliese McDermond return -EINVAL; 1078*514b044cSAnnaliese McDermond aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1079*514b044cSAnnaliese McDermond 10804d16700dSMarkus Pargmann aic32x4->swapdacs = false; 10814d16700dSMarkus Pargmann aic32x4->micpga_routing = 0; 10824d16700dSMarkus Pargmann aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 10834d16700dSMarkus Pargmann 1084b9045b9cSDan Murphy if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1085b9045b9cSDan Murphy aic32x4_setup->gpio_func, 5) >= 0) 1086b9045b9cSDan Murphy aic32x4->setup = aic32x4_setup; 10874d16700dSMarkus Pargmann return 0; 10884d16700dSMarkus Pargmann } 10894d16700dSMarkus Pargmann 1090239b669bSMarkus Pargmann static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1091239b669bSMarkus Pargmann { 1092239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1093239b669bSMarkus Pargmann 1094239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1095239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1096239b669bSMarkus Pargmann 1097239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1098239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1099239b669bSMarkus Pargmann 1100239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) 1101239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_av); 1102239b669bSMarkus Pargmann } 1103239b669bSMarkus Pargmann 1104239b669bSMarkus Pargmann static int aic32x4_setup_regulators(struct device *dev, 1105239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4) 1106239b669bSMarkus Pargmann { 1107239b669bSMarkus Pargmann int ret = 0; 1108239b669bSMarkus Pargmann 1109239b669bSMarkus Pargmann aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1110239b669bSMarkus Pargmann aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1111239b669bSMarkus Pargmann aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1112239b669bSMarkus Pargmann aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1113239b669bSMarkus Pargmann 1114239b669bSMarkus Pargmann /* Check if the regulator requirements are fulfilled */ 1115239b669bSMarkus Pargmann 1116239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_iov)) { 1117239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'iov'\n"); 1118239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_iov); 1119239b669bSMarkus Pargmann } 1120239b669bSMarkus Pargmann 1121239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_ldo)) { 1122239b669bSMarkus Pargmann if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1123239b669bSMarkus Pargmann return -EPROBE_DEFER; 1124239b669bSMarkus Pargmann 1125239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv)) { 1126239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1127239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_dv); 1128239b669bSMarkus Pargmann } 1129239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av)) { 1130239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1131239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_av); 1132239b669bSMarkus Pargmann } 1133239b669bSMarkus Pargmann } else { 1134239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv) && 1135239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1136239b669bSMarkus Pargmann return -EPROBE_DEFER; 1137239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av) && 1138239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1139239b669bSMarkus Pargmann return -EPROBE_DEFER; 1140239b669bSMarkus Pargmann } 1141239b669bSMarkus Pargmann 1142239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_iov); 1143239b669bSMarkus Pargmann if (ret) { 1144239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator iov\n"); 1145239b669bSMarkus Pargmann return ret; 1146239b669bSMarkus Pargmann } 1147239b669bSMarkus Pargmann 1148239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) { 1149239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_ldo); 1150239b669bSMarkus Pargmann if (ret) { 1151239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator ldo\n"); 1152239b669bSMarkus Pargmann goto error_ldo; 1153239b669bSMarkus Pargmann } 1154239b669bSMarkus Pargmann } 1155239b669bSMarkus Pargmann 1156239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) { 1157239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_dv); 1158239b669bSMarkus Pargmann if (ret) { 1159239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator dv\n"); 1160239b669bSMarkus Pargmann goto error_dv; 1161239b669bSMarkus Pargmann } 1162239b669bSMarkus Pargmann } 1163239b669bSMarkus Pargmann 1164239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) { 1165239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_av); 1166239b669bSMarkus Pargmann if (ret) { 1167239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator av\n"); 1168239b669bSMarkus Pargmann goto error_av; 1169239b669bSMarkus Pargmann } 1170239b669bSMarkus Pargmann } 1171239b669bSMarkus Pargmann 1172239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1173239b669bSMarkus Pargmann aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1174239b669bSMarkus Pargmann 1175239b669bSMarkus Pargmann return 0; 1176239b669bSMarkus Pargmann 1177239b669bSMarkus Pargmann error_av: 1178239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1179239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1180239b669bSMarkus Pargmann 1181239b669bSMarkus Pargmann error_dv: 1182239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1183239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1184239b669bSMarkus Pargmann 1185239b669bSMarkus Pargmann error_ldo: 1186239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1187239b669bSMarkus Pargmann return ret; 1188239b669bSMarkus Pargmann } 1189239b669bSMarkus Pargmann 11903bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap) 11911d471cd1SJavier Martin { 11921d471cd1SJavier Martin struct aic32x4_priv *aic32x4; 11933bcfd222SJeremy McDermond struct aic32x4_pdata *pdata = dev->platform_data; 11943bcfd222SJeremy McDermond struct device_node *np = dev->of_node; 11951d471cd1SJavier Martin int ret; 11961d471cd1SJavier Martin 11973bcfd222SJeremy McDermond if (IS_ERR(regmap)) 11983bcfd222SJeremy McDermond return PTR_ERR(regmap); 11993bcfd222SJeremy McDermond 12003bcfd222SJeremy McDermond aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1201658ecf77SAxel Lin GFP_KERNEL); 12021d471cd1SJavier Martin if (aic32x4 == NULL) 12031d471cd1SJavier Martin return -ENOMEM; 12041d471cd1SJavier Martin 1205b9045b9cSDan Murphy aic32x4->dev = dev; 12063bcfd222SJeremy McDermond dev_set_drvdata(dev, aic32x4); 12071d471cd1SJavier Martin 12081d471cd1SJavier Martin if (pdata) { 12091d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg; 12101d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs; 12111d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing; 12121858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio; 1213*514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 12144d16700dSMarkus Pargmann } else if (np) { 12154d16700dSMarkus Pargmann ret = aic32x4_parse_dt(aic32x4, np); 12164d16700dSMarkus Pargmann if (ret) { 12173bcfd222SJeremy McDermond dev_err(dev, "Failed to parse DT node\n"); 12184d16700dSMarkus Pargmann return ret; 12194d16700dSMarkus Pargmann } 12201d471cd1SJavier Martin } else { 12211d471cd1SJavier Martin aic32x4->power_cfg = 0; 12221d471cd1SJavier Martin aic32x4->swapdacs = false; 12231d471cd1SJavier Martin aic32x4->micpga_routing = 0; 12241858fe97SJavier Martin aic32x4->rstn_gpio = -1; 1225*514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 12261d471cd1SJavier Martin } 12271d471cd1SJavier Martin 12283bcfd222SJeremy McDermond aic32x4->mclk = devm_clk_get(dev, "mclk"); 122998b664e2SMarkus Pargmann if (IS_ERR(aic32x4->mclk)) { 12303bcfd222SJeremy McDermond dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n"); 123198b664e2SMarkus Pargmann return PTR_ERR(aic32x4->mclk); 123298b664e2SMarkus Pargmann } 123398b664e2SMarkus Pargmann 1234*514b044cSAnnaliese McDermond ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1235*514b044cSAnnaliese McDermond if (ret) 1236*514b044cSAnnaliese McDermond return ret; 1237*514b044cSAnnaliese McDermond 1238a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 12393bcfd222SJeremy McDermond ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1240752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1241752b7764SMark Brown if (ret != 0) 1242752b7764SMark Brown return ret; 1243752b7764SMark Brown } 1244752b7764SMark Brown 12453bcfd222SJeremy McDermond ret = aic32x4_setup_regulators(dev, aic32x4); 1246239b669bSMarkus Pargmann if (ret) { 12473bcfd222SJeremy McDermond dev_err(dev, "Failed to setup regulators\n"); 1248239b669bSMarkus Pargmann return ret; 1249239b669bSMarkus Pargmann } 1250239b669bSMarkus Pargmann 1251b154dc5dSKuninori Morimoto ret = devm_snd_soc_register_component(dev, 1252b154dc5dSKuninori Morimoto &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1253239b669bSMarkus Pargmann if (ret) { 1254b154dc5dSKuninori Morimoto dev_err(dev, "Failed to register component\n"); 1255239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 12561d471cd1SJavier Martin return ret; 12571d471cd1SJavier Martin } 12581d471cd1SJavier Martin 1259239b669bSMarkus Pargmann return 0; 1260239b669bSMarkus Pargmann } 12613bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_probe); 1262239b669bSMarkus Pargmann 12633bcfd222SJeremy McDermond int aic32x4_remove(struct device *dev) 12641d471cd1SJavier Martin { 12653bcfd222SJeremy McDermond struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1266239b669bSMarkus Pargmann 1267239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 1268239b669bSMarkus Pargmann 12691d471cd1SJavier Martin return 0; 12701d471cd1SJavier Martin } 12713bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_remove); 12721d471cd1SJavier Martin 12731d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 12741d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 12751d471cd1SJavier Martin MODULE_LICENSE("GPL"); 1276