116216333SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 21d471cd1SJavier Martin /* 31d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c 41d471cd1SJavier Martin * 51d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L. 61d471cd1SJavier Martin * 71d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com> 81d471cd1SJavier Martin * 91d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 101d471cd1SJavier Martin */ 111d471cd1SJavier Martin 121d471cd1SJavier Martin #include <linux/module.h> 131d471cd1SJavier Martin #include <linux/moduleparam.h> 141d471cd1SJavier Martin #include <linux/init.h> 151d471cd1SJavier Martin #include <linux/delay.h> 161d471cd1SJavier Martin #include <linux/pm.h> 171858fe97SJavier Martin #include <linux/gpio.h> 184d16700dSMarkus Pargmann #include <linux/of_gpio.h> 191d471cd1SJavier Martin #include <linux/cdev.h> 201d471cd1SJavier Martin #include <linux/slab.h> 2198b664e2SMarkus Pargmann #include <linux/clk.h> 22514b044cSAnnaliese McDermond #include <linux/of_clk.h> 23239b669bSMarkus Pargmann #include <linux/regulator/consumer.h> 241d471cd1SJavier Martin 251d471cd1SJavier Martin #include <sound/tlv320aic32x4.h> 261d471cd1SJavier Martin #include <sound/core.h> 271d471cd1SJavier Martin #include <sound/pcm.h> 281d471cd1SJavier Martin #include <sound/pcm_params.h> 291d471cd1SJavier Martin #include <sound/soc.h> 301d471cd1SJavier Martin #include <sound/soc-dapm.h> 311d471cd1SJavier Martin #include <sound/initval.h> 321d471cd1SJavier Martin #include <sound/tlv.h> 331d471cd1SJavier Martin 341d471cd1SJavier Martin #include "tlv320aic32x4.h" 351d471cd1SJavier Martin 361d471cd1SJavier Martin struct aic32x4_priv { 374d208ca4SMark Brown struct regmap *regmap; 381d471cd1SJavier Martin u32 power_cfg; 391d471cd1SJavier Martin u32 micpga_routing; 401d471cd1SJavier Martin bool swapdacs; 411858fe97SJavier Martin int rstn_gpio; 42514b044cSAnnaliese McDermond const char *mclk_name; 43239b669bSMarkus Pargmann 44239b669bSMarkus Pargmann struct regulator *supply_ldo; 45239b669bSMarkus Pargmann struct regulator *supply_iov; 46239b669bSMarkus Pargmann struct regulator *supply_dv; 47239b669bSMarkus Pargmann struct regulator *supply_av; 48b9045b9cSDan Murphy 49b9045b9cSDan Murphy struct aic32x4_setup_data *setup; 50b9045b9cSDan Murphy struct device *dev; 51b9045b9cSDan Murphy }; 52b9045b9cSDan Murphy 5304d979d7Sb-ak static int mic_bias_event(struct snd_soc_dapm_widget *w, 5404d979d7Sb-ak struct snd_kcontrol *kcontrol, int event) 5504d979d7Sb-ak { 5604d979d7Sb-ak struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 5704d979d7Sb-ak 5804d979d7Sb-ak switch (event) { 5904d979d7Sb-ak case SND_SOC_DAPM_POST_PMU: 6004d979d7Sb-ak /* Change Mic Bias Registor */ 6104d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 6204d979d7Sb-ak AIC32x4_MICBIAS_MASK, 6304d979d7Sb-ak AIC32X4_MICBIAS_LDOIN | 6404d979d7Sb-ak AIC32X4_MICBIAS_2075V); 6504d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 6604d979d7Sb-ak break; 6704d979d7Sb-ak case SND_SOC_DAPM_PRE_PMD: 6804d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 6904d979d7Sb-ak AIC32x4_MICBIAS_MASK, 0); 7004d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 7104d979d7Sb-ak __func__); 7204d979d7Sb-ak break; 7304d979d7Sb-ak } 7404d979d7Sb-ak 7504d979d7Sb-ak return 0; 7604d979d7Sb-ak } 7704d979d7Sb-ak 7804d979d7Sb-ak 79b9045b9cSDan Murphy static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 80b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 81b9045b9cSDan Murphy { 82b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 83b9045b9cSDan Murphy u8 val; 84b9045b9cSDan Murphy 85b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_DINCTL); 86b9045b9cSDan Murphy 87b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 88b9045b9cSDan Murphy 89b9045b9cSDan Murphy return 0; 90b9045b9cSDan Murphy }; 91b9045b9cSDan Murphy 92b9045b9cSDan Murphy static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 93b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 94b9045b9cSDan Murphy { 95b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 96b9045b9cSDan Murphy u8 val; 97b9045b9cSDan Murphy u8 gpio_check; 98b9045b9cSDan Murphy 99b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 100b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 101b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 102b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 103b9045b9cSDan Murphy __func__); 104b9045b9cSDan Murphy return -EINVAL; 105b9045b9cSDan Murphy } 106b9045b9cSDan Murphy 107b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 108b9045b9cSDan Murphy return 0; 109b9045b9cSDan Murphy 110b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 111b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 112b9045b9cSDan Murphy else 113b9045b9cSDan Murphy val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 114b9045b9cSDan Murphy 115b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 116b9045b9cSDan Murphy 117b9045b9cSDan Murphy return 0; 118b9045b9cSDan Murphy }; 119b9045b9cSDan Murphy 120b9045b9cSDan Murphy static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 121b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 122b9045b9cSDan Murphy { 123b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 124b9045b9cSDan Murphy u8 val; 125b9045b9cSDan Murphy 126b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 127b9045b9cSDan Murphy 128b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 129b9045b9cSDan Murphy 130b9045b9cSDan Murphy return 0; 131b9045b9cSDan Murphy }; 132b9045b9cSDan Murphy 133b9045b9cSDan Murphy static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 134b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 135b9045b9cSDan Murphy { 136b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 137b9045b9cSDan Murphy u8 val; 138b9045b9cSDan Murphy u8 gpio_check; 139b9045b9cSDan Murphy 140b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 141b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 142b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 143b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 144b9045b9cSDan Murphy __func__); 145b9045b9cSDan Murphy return -EINVAL; 146b9045b9cSDan Murphy } 147b9045b9cSDan Murphy 148b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 149b9045b9cSDan Murphy return 0; 150b9045b9cSDan Murphy 151b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 152b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 153b9045b9cSDan Murphy else 154b9045b9cSDan Murphy val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 155b9045b9cSDan Murphy 156b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, val); 157b9045b9cSDan Murphy 158b9045b9cSDan Murphy return 0; 159b9045b9cSDan Murphy }; 160b9045b9cSDan Murphy 161b9045b9cSDan Murphy static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 162b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 163b9045b9cSDan Murphy { 164b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 165b9045b9cSDan Murphy u8 val; 166b9045b9cSDan Murphy 167b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 168b9045b9cSDan Murphy ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 169b9045b9cSDan Murphy 170b9045b9cSDan Murphy return 0; 171b9045b9cSDan Murphy }; 172b9045b9cSDan Murphy 173b9045b9cSDan Murphy static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 174b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 175b9045b9cSDan Murphy { 176b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 177b9045b9cSDan Murphy u8 val; 178b9045b9cSDan Murphy u8 gpio_check; 179b9045b9cSDan Murphy 180b154dc5dSKuninori Morimoto val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 181b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 182b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 183b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 184b9045b9cSDan Murphy __func__); 185b9045b9cSDan Murphy return -EINVAL; 186b9045b9cSDan Murphy } 187b9045b9cSDan Murphy 188b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & 0x1)) 189b9045b9cSDan Murphy return 0; 190b9045b9cSDan Murphy 191b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 192b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 193b9045b9cSDan Murphy else 194b9045b9cSDan Murphy val &= 0xfe; 195b9045b9cSDan Murphy 196b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 197b9045b9cSDan Murphy 198b9045b9cSDan Murphy return 0; 199b9045b9cSDan Murphy }; 200b9045b9cSDan Murphy 201b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp1[] = { 202b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 203b9045b9cSDan Murphy }; 204b9045b9cSDan Murphy 205b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp2[] = { 206b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 207b9045b9cSDan Murphy }; 208b9045b9cSDan Murphy 209b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp3[] = { 210b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 211b9045b9cSDan Murphy }; 212b9045b9cSDan Murphy 213b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp4[] = { 214b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 215b9045b9cSDan Murphy }; 216b9045b9cSDan Murphy 217b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp5[] = { 218b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 219b9045b9cSDan Murphy aic32x4_set_mfp5_gpio), 2201d471cd1SJavier Martin }; 2211d471cd1SJavier Martin 2221d471cd1SJavier Martin /* 0dB min, 0.5dB steps */ 2231d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 224c671e79dSMarkus Pargmann /* -63.5dB min, 0.5dB steps */ 225c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 226c671e79dSMarkus Pargmann /* -6dB min, 1dB steps */ 227c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 228c671e79dSMarkus Pargmann /* -12dB min, 0.5dB steps */ 229c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 2301d471cd1SJavier Martin 23144ceee84SAnnaliese McDermond static const char * const lo_cm_text[] = { 23244ceee84SAnnaliese McDermond "Full Chip", "1.65V", 23344ceee84SAnnaliese McDermond }; 23444ceee84SAnnaliese McDermond 23544ceee84SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text); 23644ceee84SAnnaliese McDermond 237d3e6e374SAnnaliese McDermond static const char * const ptm_text[] = { 238d3e6e374SAnnaliese McDermond "P3", "P2", "P1", 239d3e6e374SAnnaliese McDermond }; 240d3e6e374SAnnaliese McDermond 241d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text); 242d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text); 243d3e6e374SAnnaliese McDermond 2441d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 245c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 246c671e79dSMarkus Pargmann AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 247d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum), 248d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum), 249c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 250c671e79dSMarkus Pargmann AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 251c671e79dSMarkus Pargmann tlv_driver_gain), 252c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 253c671e79dSMarkus Pargmann AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 254c671e79dSMarkus Pargmann tlv_driver_gain), 2551d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 2561d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1), 2571d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 2581d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1), 25944ceee84SAnnaliese McDermond SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum), 2601d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 2611d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1), 2621d471cd1SJavier Martin 2631d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 2641d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 2651d471cd1SJavier Martin 266c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 267c671e79dSMarkus Pargmann AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 2681d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 2691d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 2701d471cd1SJavier Martin 2711d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 2721d471cd1SJavier Martin 2731d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 2741d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 2751d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 2761d471cd1SJavier Martin 4, 0x07, 0), 2771d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 2781d471cd1SJavier Martin 0, 0x03, 0), 2791d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 2801d471cd1SJavier Martin 6, 0x03, 0), 2811d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 2821d471cd1SJavier Martin 1, 0x1F, 0), 2831d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 2841d471cd1SJavier Martin 0, 0x7F, 0), 2851d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 2861d471cd1SJavier Martin 3, 0x1F, 0), 2871d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 2881d471cd1SJavier Martin 3, 0x1F, 0), 2891d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 2901d471cd1SJavier Martin 0, 0x1F, 0), 2911d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 2921d471cd1SJavier Martin 0, 0x0F, 0), 2931d471cd1SJavier Martin }; 2941d471cd1SJavier Martin 2951d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 2961d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 2971d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 2981d471cd1SJavier Martin }; 2991d471cd1SJavier Martin 3001d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 3011d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 3021d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 3031d471cd1SJavier Martin }; 3041d471cd1SJavier Martin 3051d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 3061d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 3071d471cd1SJavier Martin }; 3081d471cd1SJavier Martin 3091d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 3101d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 3111d471cd1SJavier Martin }; 3121d471cd1SJavier Martin 31320d2cecbSJeremy McDermond static const char * const resistor_text[] = { 31420d2cecbSJeremy McDermond "Off", "10 kOhm", "20 kOhm", "40 kOhm", 3151d471cd1SJavier Martin }; 3161d471cd1SJavier Martin 3172213fc35SJeremy McDermond /* Left mixer pins */ 3182213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 3192213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 3202213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 3212213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 32220d2cecbSJeremy McDermond 3232213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 3242213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 3252213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 3262213fc35SJeremy McDermond 3272213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 3282213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 3292213fc35SJeremy McDermond }; 3302213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 3312213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 3322213fc35SJeremy McDermond }; 3332213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 3342213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 3352213fc35SJeremy McDermond }; 3362213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 3372213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 3382213fc35SJeremy McDermond }; 3392213fc35SJeremy McDermond static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 3402213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 3412213fc35SJeremy McDermond }; 3422213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 3432213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 3442213fc35SJeremy McDermond }; 3452213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 3462213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 34720d2cecbSJeremy McDermond }; 34820d2cecbSJeremy McDermond 3492213fc35SJeremy McDermond /* Right mixer pins */ 3502213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 3512213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 3522213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 3532213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 3542213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 3552213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 3562213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 35720d2cecbSJeremy McDermond 3582213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 3592213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 3602213fc35SJeremy McDermond }; 3612213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 3622213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 3632213fc35SJeremy McDermond }; 3642213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 3652213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 3662213fc35SJeremy McDermond }; 3672213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 3682213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 3692213fc35SJeremy McDermond }; 3702213fc35SJeremy McDermond static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 3712213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 3722213fc35SJeremy McDermond }; 3732213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 3742213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 3752213fc35SJeremy McDermond }; 3762213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 3772213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 3781d471cd1SJavier Martin }; 3791d471cd1SJavier Martin 3801d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 3811d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 3821d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 3831d471cd1SJavier Martin &hpl_output_mixer_controls[0], 3841d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)), 3851d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 3861d471cd1SJavier Martin 3871d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 3881d471cd1SJavier Martin &lol_output_mixer_controls[0], 3891d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)), 3901d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 3911d471cd1SJavier Martin 3921d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 3931d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 3941d471cd1SJavier Martin &hpr_output_mixer_controls[0], 3951d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)), 3961d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 3971d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 3981d471cd1SJavier Martin &lor_output_mixer_controls[0], 3991d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)), 4001d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 4012213fc35SJeremy McDermond 4021d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 4032213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4042213fc35SJeremy McDermond in1r_to_rmixer_controls), 4052213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4062213fc35SJeremy McDermond in2r_to_rmixer_controls), 4072213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4082213fc35SJeremy McDermond in3r_to_rmixer_controls), 4092213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4102213fc35SJeremy McDermond in2l_to_rmixer_controls), 4112213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4122213fc35SJeremy McDermond cmr_to_rmixer_controls), 4132213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4142213fc35SJeremy McDermond in1l_to_rmixer_controls), 4152213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4162213fc35SJeremy McDermond in3l_to_rmixer_controls), 4172213fc35SJeremy McDermond 4182213fc35SJeremy McDermond SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 4192213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4202213fc35SJeremy McDermond in1l_to_lmixer_controls), 4212213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4222213fc35SJeremy McDermond in2l_to_lmixer_controls), 4232213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4242213fc35SJeremy McDermond in3l_to_lmixer_controls), 4252213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4262213fc35SJeremy McDermond in1r_to_lmixer_controls), 4272213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4282213fc35SJeremy McDermond cml_to_lmixer_controls), 4292213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4302213fc35SJeremy McDermond in2r_to_lmixer_controls), 4312213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4322213fc35SJeremy McDermond in3r_to_lmixer_controls), 4332213fc35SJeremy McDermond 43404d979d7Sb-ak SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 43504d979d7Sb-ak SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 43604d979d7Sb-ak 4371d471cd1SJavier Martin 4381d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"), 4391d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"), 4401d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"), 4411d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"), 4421d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"), 4431d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"), 4441d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"), 4451d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"), 4461d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"), 4471d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"), 448c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_L"), 449c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_R"), 4501d471cd1SJavier Martin }; 4511d471cd1SJavier Martin 4521d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 4531d471cd1SJavier Martin /* Left Output */ 4541d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 4551d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 4561d471cd1SJavier Martin 4571d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"}, 4581d471cd1SJavier Martin {"HPL", NULL, "HPL Power"}, 4591d471cd1SJavier Martin 4601d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 4611d471cd1SJavier Martin 4621d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"}, 4631d471cd1SJavier Martin {"LOL", NULL, "LOL Power"}, 4641d471cd1SJavier Martin 4651d471cd1SJavier Martin /* Right Output */ 4661d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 4671d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 4681d471cd1SJavier Martin 4691d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"}, 4701d471cd1SJavier Martin {"HPR", NULL, "HPR Power"}, 4711d471cd1SJavier Martin 4721d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 4731d471cd1SJavier Martin 4741d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"}, 4751d471cd1SJavier Martin {"LOR", NULL, "LOR Power"}, 4761d471cd1SJavier Martin 4771d471cd1SJavier Martin /* Right Input */ 4782213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 4792213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 4802213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 4812213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 4821d471cd1SJavier Martin 4832213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 4842213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 4852213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 4862213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 4872213fc35SJeremy McDermond 4882213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 4892213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 4902213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 4912213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 4922213fc35SJeremy McDermond 4932213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 4942213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 4952213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 4962213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 4972213fc35SJeremy McDermond 4982213fc35SJeremy McDermond {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 4992213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 5002213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 5012213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 5022213fc35SJeremy McDermond 5032213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 5042213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 5052213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 5062213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 5072213fc35SJeremy McDermond 5082213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 5092213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 5102213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 5112213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 5122213fc35SJeremy McDermond 5132213fc35SJeremy McDermond /* Left Input */ 5142213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 5152213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 5162213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 5172213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 5182213fc35SJeremy McDermond 5192213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 5202213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5212213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5222213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5232213fc35SJeremy McDermond 5242213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 5252213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 5262213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 5272213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 5282213fc35SJeremy McDermond 5292213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 5302213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 5312213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 5322213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 5332213fc35SJeremy McDermond 5342213fc35SJeremy McDermond {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 5352213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 5362213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 5372213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 5382213fc35SJeremy McDermond 5392213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 5402213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 5412213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 5422213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 5432213fc35SJeremy McDermond 5442213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 5452213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 5462213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 5472213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 5481d471cd1SJavier Martin }; 5491d471cd1SJavier Martin 5504d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 5511d471cd1SJavier Martin { 5524d208ca4SMark Brown .selector_reg = 0, 5534d208ca4SMark Brown .selector_mask = 0xff, 5544d208ca4SMark Brown .window_start = 0, 5554d208ca4SMark Brown .window_len = 128, 556e8e08c52SMarkus Pargmann .range_min = 0, 5576d0d5103SMarkus Pargmann .range_max = AIC32X4_RMICPGAVOL, 5584d208ca4SMark Brown }, 5594d208ca4SMark Brown }; 5601d471cd1SJavier Martin 5613bcfd222SJeremy McDermond const struct regmap_config aic32x4_regmap_config = { 5624d208ca4SMark Brown .max_register = AIC32X4_RMICPGAVOL, 5634d208ca4SMark Brown .ranges = aic32x4_regmap_pages, 5644d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 5654d208ca4SMark Brown }; 5663bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_regmap_config); 5671d471cd1SJavier Martin 5681d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 5691d471cd1SJavier Martin int clk_id, unsigned int freq, int dir) 5701d471cd1SJavier Martin { 571b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 572aa6a60f7SAnnaliese McDermond struct clk *mclk; 573aa6a60f7SAnnaliese McDermond struct clk *pll; 5741d471cd1SJavier Martin 575aa6a60f7SAnnaliese McDermond pll = devm_clk_get(component->dev, "pll"); 5761092b097SChuhong Yuan if (IS_ERR(pll)) 5771092b097SChuhong Yuan return PTR_ERR(pll); 5781092b097SChuhong Yuan 579aa6a60f7SAnnaliese McDermond mclk = clk_get_parent(pll); 580aa6a60f7SAnnaliese McDermond 581aa6a60f7SAnnaliese McDermond return clk_set_rate(mclk, freq); 5821d471cd1SJavier Martin } 5831d471cd1SJavier Martin 5841d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 5851d471cd1SJavier Martin { 586b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 58760fb4be5SAndrew F. Davis u8 iface_reg_1 = 0; 58860fb4be5SAndrew F. Davis u8 iface_reg_2 = 0; 58960fb4be5SAndrew F. Davis u8 iface_reg_3 = 0; 5901d471cd1SJavier Martin 5911d471cd1SJavier Martin /* set master/slave audio interface */ 5921d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 5931d471cd1SJavier Martin case SND_SOC_DAIFMT_CBM_CFM: 5941d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 5951d471cd1SJavier Martin break; 5961d471cd1SJavier Martin case SND_SOC_DAIFMT_CBS_CFS: 5971d471cd1SJavier Martin break; 5981d471cd1SJavier Martin default: 5991d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 6001d471cd1SJavier Martin return -EINVAL; 6011d471cd1SJavier Martin } 6021d471cd1SJavier Martin 6031d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 6041d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S: 6051d471cd1SJavier Martin break; 6061d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A: 6074483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6084483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 60960fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6101d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */ 6111d471cd1SJavier Martin break; 6121d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B: 6134483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 6144483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 61560fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 6161d471cd1SJavier Martin break; 6171d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J: 6184483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 6194483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6201d471cd1SJavier Martin break; 6211d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J: 6224483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 6234483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6241d471cd1SJavier Martin break; 6251d471cd1SJavier Martin default: 6261d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 6271d471cd1SJavier Martin return -EINVAL; 6281d471cd1SJavier Martin } 6291d471cd1SJavier Martin 630b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 63160fb4be5SAndrew F. Davis AIC32X4_IFACE1_DATATYPE_MASK | 63260fb4be5SAndrew F. Davis AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 633b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE2, 63460fb4be5SAndrew F. Davis AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 635b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE3, 63660fb4be5SAndrew F. Davis AIC32X4_BCLKINV_MASK, iface_reg_3); 63760fb4be5SAndrew F. Davis 6381d471cd1SJavier Martin return 0; 6391d471cd1SJavier Martin } 6401d471cd1SJavier Martin 641fbafbf65SAnnaliese McDermond static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) 642fbafbf65SAnnaliese McDermond { 643fbafbf65SAnnaliese McDermond return snd_soc_component_write(component, AIC32X4_AOSR, aosr); 644fbafbf65SAnnaliese McDermond } 645fbafbf65SAnnaliese McDermond 646fbafbf65SAnnaliese McDermond static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) 647fbafbf65SAnnaliese McDermond { 648fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); 649fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRLSB, 650fbafbf65SAnnaliese McDermond (dosr & 0xff)); 651fbafbf65SAnnaliese McDermond 652fbafbf65SAnnaliese McDermond return 0; 653fbafbf65SAnnaliese McDermond } 654fbafbf65SAnnaliese McDermond 655c95e3a4bSAnnaliese McDermond static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 656c95e3a4bSAnnaliese McDermond u8 r_block, u8 p_block) 657c95e3a4bSAnnaliese McDermond { 658c95e3a4bSAnnaliese McDermond if (r_block > 18 || p_block > 25) 659c95e3a4bSAnnaliese McDermond return -EINVAL; 660c95e3a4bSAnnaliese McDermond 661c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 662c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 663c95e3a4bSAnnaliese McDermond 664c95e3a4bSAnnaliese McDermond return 0; 665c95e3a4bSAnnaliese McDermond } 666c95e3a4bSAnnaliese McDermond 667bf31cbfbSAnnaliese McDermond static int aic32x4_setup_clocks(struct snd_soc_component *component, 66896c3bb00SAnnaliese McDermond unsigned int sample_rate) 6691d471cd1SJavier Martin { 67096c3bb00SAnnaliese McDermond u8 aosr; 67196c3bb00SAnnaliese McDermond u16 dosr; 67296c3bb00SAnnaliese McDermond u8 adc_resource_class, dac_resource_class; 67396c3bb00SAnnaliese McDermond u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; 67496c3bb00SAnnaliese McDermond u8 dosr_increment; 67596c3bb00SAnnaliese McDermond u16 max_dosr, min_dosr; 67683b4f50cSYueHaibing unsigned long adc_clock_rate, dac_clock_rate; 677514b044cSAnnaliese McDermond int ret; 678514b044cSAnnaliese McDermond 679514b044cSAnnaliese McDermond struct clk_bulk_data clocks[] = { 680514b044cSAnnaliese McDermond { .id = "pll" }, 681a51b5006SAnnaliese McDermond { .id = "nadc" }, 682a51b5006SAnnaliese McDermond { .id = "madc" }, 683a51b5006SAnnaliese McDermond { .id = "ndac" }, 684a51b5006SAnnaliese McDermond { .id = "mdac" }, 6859b484124SAnnaliese McDermond { .id = "bdiv" }, 686514b044cSAnnaliese McDermond }; 687514b044cSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 688514b044cSAnnaliese McDermond if (ret) 689514b044cSAnnaliese McDermond return ret; 690514b044cSAnnaliese McDermond 69196c3bb00SAnnaliese McDermond if (sample_rate <= 48000) { 69296c3bb00SAnnaliese McDermond aosr = 128; 69396c3bb00SAnnaliese McDermond adc_resource_class = 6; 69496c3bb00SAnnaliese McDermond dac_resource_class = 8; 69596c3bb00SAnnaliese McDermond dosr_increment = 8; 69696c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 1); 69796c3bb00SAnnaliese McDermond } else if (sample_rate <= 96000) { 69896c3bb00SAnnaliese McDermond aosr = 64; 69996c3bb00SAnnaliese McDermond adc_resource_class = 6; 70096c3bb00SAnnaliese McDermond dac_resource_class = 8; 70196c3bb00SAnnaliese McDermond dosr_increment = 4; 70296c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 9); 70396c3bb00SAnnaliese McDermond } else if (sample_rate == 192000) { 70496c3bb00SAnnaliese McDermond aosr = 32; 70596c3bb00SAnnaliese McDermond adc_resource_class = 3; 70696c3bb00SAnnaliese McDermond dac_resource_class = 4; 70796c3bb00SAnnaliese McDermond dosr_increment = 2; 70896c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 13, 19); 70996c3bb00SAnnaliese McDermond } else { 71096c3bb00SAnnaliese McDermond dev_err(component->dev, "Sampling rate not supported\n"); 71196c3bb00SAnnaliese McDermond return -EINVAL; 71296c3bb00SAnnaliese McDermond } 713fbafbf65SAnnaliese McDermond 71496c3bb00SAnnaliese McDermond madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); 71596c3bb00SAnnaliese McDermond max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * 71696c3bb00SAnnaliese McDermond dosr_increment; 71796c3bb00SAnnaliese McDermond min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * 71896c3bb00SAnnaliese McDermond dosr_increment; 71996c3bb00SAnnaliese McDermond max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); 720c95e3a4bSAnnaliese McDermond 72196c3bb00SAnnaliese McDermond for (nadc = max_nadc; nadc > 0; --nadc) { 72296c3bb00SAnnaliese McDermond adc_clock_rate = nadc * madc * aosr * sample_rate; 72396c3bb00SAnnaliese McDermond for (dosr = max_dosr; dosr >= min_dosr; 72496c3bb00SAnnaliese McDermond dosr -= dosr_increment) { 72596c3bb00SAnnaliese McDermond min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); 72696c3bb00SAnnaliese McDermond max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / 72796c3bb00SAnnaliese McDermond (min_mdac * dosr * sample_rate); 72896c3bb00SAnnaliese McDermond for (mdac = min_mdac; mdac <= 128; ++mdac) { 72996c3bb00SAnnaliese McDermond for (ndac = max_ndac; ndac > 0; --ndac) { 73096c3bb00SAnnaliese McDermond dac_clock_rate = ndac * mdac * dosr * 73196c3bb00SAnnaliese McDermond sample_rate; 73296c3bb00SAnnaliese McDermond if (dac_clock_rate == adc_clock_rate) { 73396c3bb00SAnnaliese McDermond if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 73496c3bb00SAnnaliese McDermond continue; 73596c3bb00SAnnaliese McDermond 73696c3bb00SAnnaliese McDermond clk_set_rate(clocks[0].clk, 73796c3bb00SAnnaliese McDermond dac_clock_rate); 73896c3bb00SAnnaliese McDermond 73996c3bb00SAnnaliese McDermond clk_set_rate(clocks[1].clk, 74096c3bb00SAnnaliese McDermond sample_rate * aosr * 74196c3bb00SAnnaliese McDermond madc); 74296c3bb00SAnnaliese McDermond clk_set_rate(clocks[2].clk, 74396c3bb00SAnnaliese McDermond sample_rate * aosr); 74496c3bb00SAnnaliese McDermond aic32x4_set_aosr(component, 74596c3bb00SAnnaliese McDermond aosr); 74696c3bb00SAnnaliese McDermond 74796c3bb00SAnnaliese McDermond clk_set_rate(clocks[3].clk, 74896c3bb00SAnnaliese McDermond sample_rate * dosr * 74996c3bb00SAnnaliese McDermond mdac); 75096c3bb00SAnnaliese McDermond clk_set_rate(clocks[4].clk, 75196c3bb00SAnnaliese McDermond sample_rate * dosr); 75296c3bb00SAnnaliese McDermond aic32x4_set_dosr(component, 75396c3bb00SAnnaliese McDermond dosr); 75496c3bb00SAnnaliese McDermond 75596c3bb00SAnnaliese McDermond clk_set_rate(clocks[5].clk, 75696c3bb00SAnnaliese McDermond sample_rate * 32); 757bf31cbfbSAnnaliese McDermond return 0; 758bf31cbfbSAnnaliese McDermond } 75996c3bb00SAnnaliese McDermond } 76096c3bb00SAnnaliese McDermond } 76196c3bb00SAnnaliese McDermond } 76296c3bb00SAnnaliese McDermond } 76396c3bb00SAnnaliese McDermond 76496c3bb00SAnnaliese McDermond dev_err(component->dev, 76596c3bb00SAnnaliese McDermond "Could not set clocks to support sample rate.\n"); 76696c3bb00SAnnaliese McDermond return -EINVAL; 76796c3bb00SAnnaliese McDermond } 768bf31cbfbSAnnaliese McDermond 769bf31cbfbSAnnaliese McDermond static int aic32x4_hw_params(struct snd_pcm_substream *substream, 770bf31cbfbSAnnaliese McDermond struct snd_pcm_hw_params *params, 771bf31cbfbSAnnaliese McDermond struct snd_soc_dai *dai) 772bf31cbfbSAnnaliese McDermond { 773bf31cbfbSAnnaliese McDermond struct snd_soc_component *component = dai->component; 774bf31cbfbSAnnaliese McDermond struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 775bf31cbfbSAnnaliese McDermond u8 iface1_reg = 0; 776bf31cbfbSAnnaliese McDermond u8 dacsetup_reg = 0; 777bf31cbfbSAnnaliese McDermond 77896c3bb00SAnnaliese McDermond aic32x4_setup_clocks(component, params_rate(params)); 779bf31cbfbSAnnaliese McDermond 780bd8a5711SMark Brown switch (params_width(params)) { 781bd8a5711SMark Brown case 16: 78264aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 78377bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7841d471cd1SJavier Martin break; 785bd8a5711SMark Brown case 20: 78664aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 78777bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7881d471cd1SJavier Martin break; 789bd8a5711SMark Brown case 24: 79064aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 79177bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7921d471cd1SJavier Martin break; 793bd8a5711SMark Brown case 32: 79464aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 79577bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT); 7961d471cd1SJavier Martin break; 7971d471cd1SJavier Martin } 798b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1, 79964aab899SAndrew F. Davis AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 8001d471cd1SJavier Martin 801b44aa40fSMarkus Pargmann if (params_channels(params) == 1) { 80264aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 803b44aa40fSMarkus Pargmann } else { 804b44aa40fSMarkus Pargmann if (aic32x4->swapdacs) 80564aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 806b44aa40fSMarkus Pargmann else 80764aab899SAndrew F. Davis dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 808b44aa40fSMarkus Pargmann } 809b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 81064aab899SAndrew F. Davis AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 811b44aa40fSMarkus Pargmann 8121d471cd1SJavier Martin return 0; 8131d471cd1SJavier Martin } 8141d471cd1SJavier Martin 8151d471cd1SJavier Martin static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 8161d471cd1SJavier Martin { 817b154dc5dSKuninori Morimoto struct snd_soc_component *component = dai->component; 8181d471cd1SJavier Martin 819b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 820b7ddd9caSAndrew F. Davis AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 821b7ddd9caSAndrew F. Davis 8221d471cd1SJavier Martin return 0; 8231d471cd1SJavier Martin } 8241d471cd1SJavier Martin 825b154dc5dSKuninori Morimoto static int aic32x4_set_bias_level(struct snd_soc_component *component, 8261d471cd1SJavier Martin enum snd_soc_bias_level level) 8271d471cd1SJavier Martin { 82898b664e2SMarkus Pargmann int ret; 82998b664e2SMarkus Pargmann 830d25970b5SAnnaliese McDermond struct clk_bulk_data clocks[] = { 831d25970b5SAnnaliese McDermond { .id = "madc" }, 832d25970b5SAnnaliese McDermond { .id = "mdac" }, 833d25970b5SAnnaliese McDermond { .id = "bdiv" }, 834d25970b5SAnnaliese McDermond }; 835d25970b5SAnnaliese McDermond 836d25970b5SAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 837d25970b5SAnnaliese McDermond if (ret) 838d25970b5SAnnaliese McDermond return ret; 839d25970b5SAnnaliese McDermond 8401d471cd1SJavier Martin switch (level) { 8411d471cd1SJavier Martin case SND_SOC_BIAS_ON: 842d25970b5SAnnaliese McDermond ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); 84398b664e2SMarkus Pargmann if (ret) { 844d25970b5SAnnaliese McDermond dev_err(component->dev, "Failed to enable clocks\n"); 84598b664e2SMarkus Pargmann return ret; 84698b664e2SMarkus Pargmann } 8471d471cd1SJavier Martin break; 8481d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE: 8491d471cd1SJavier Martin break; 8501d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY: 851667e9334Sb-ak /* Initial cold start */ 852667e9334Sb-ak if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 853667e9334Sb-ak break; 854667e9334Sb-ak 855d25970b5SAnnaliese McDermond clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); 8561d471cd1SJavier Martin break; 8571d471cd1SJavier Martin case SND_SOC_BIAS_OFF: 8581d471cd1SJavier Martin break; 8591d471cd1SJavier Martin } 8601d471cd1SJavier Martin return 0; 8611d471cd1SJavier Martin } 8621d471cd1SJavier Martin 8636d56ee15SAnnaliese McDermond #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 8641d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 8651d471cd1SJavier Martin | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 8661d471cd1SJavier Martin 86785e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = { 8681d471cd1SJavier Martin .hw_params = aic32x4_hw_params, 8691d471cd1SJavier Martin .digital_mute = aic32x4_mute, 8701d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt, 8711d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk, 8721d471cd1SJavier Martin }; 8731d471cd1SJavier Martin 8741d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = { 8751d471cd1SJavier Martin .name = "tlv320aic32x4-hifi", 8761d471cd1SJavier Martin .playback = { 8771d471cd1SJavier Martin .stream_name = "Playback", 8781d471cd1SJavier Martin .channels_min = 1, 8791d471cd1SJavier Martin .channels_max = 2, 8801d471cd1SJavier Martin .rates = AIC32X4_RATES, 8811d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 8821d471cd1SJavier Martin .capture = { 8831d471cd1SJavier Martin .stream_name = "Capture", 8841d471cd1SJavier Martin .channels_min = 1, 8851d471cd1SJavier Martin .channels_max = 2, 8861d471cd1SJavier Martin .rates = AIC32X4_RATES, 8871d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 8881d471cd1SJavier Martin .ops = &aic32x4_ops, 8891d471cd1SJavier Martin .symmetric_rates = 1, 8901d471cd1SJavier Martin }; 8911d471cd1SJavier Martin 892b154dc5dSKuninori Morimoto static void aic32x4_setup_gpios(struct snd_soc_component *component) 893b9045b9cSDan Murphy { 894b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 895b9045b9cSDan Murphy 896b9045b9cSDan Murphy /* setup GPIO functions */ 897b9045b9cSDan Murphy /* MFP1 */ 898b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 899b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DINCTL, 900b9045b9cSDan Murphy aic32x4->setup->gpio_func[0]); 901b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp1, 902b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp1)); 903b9045b9cSDan Murphy } 904b9045b9cSDan Murphy 905b9045b9cSDan Murphy /* MFP2 */ 906b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 907b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, 908b9045b9cSDan Murphy aic32x4->setup->gpio_func[1]); 909b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp2, 910b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp2)); 911b9045b9cSDan Murphy } 912b9045b9cSDan Murphy 913b9045b9cSDan Murphy /* MFP3 */ 914b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 915b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_SCLKCTL, 916b9045b9cSDan Murphy aic32x4->setup->gpio_func[2]); 917b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp3, 918b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp3)); 919b9045b9cSDan Murphy } 920b9045b9cSDan Murphy 921b9045b9cSDan Murphy /* MFP4 */ 922b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 923b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, 924b9045b9cSDan Murphy aic32x4->setup->gpio_func[3]); 925b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp4, 926b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp4)); 927b9045b9cSDan Murphy } 928b9045b9cSDan Murphy 929b9045b9cSDan Murphy /* MFP5 */ 930b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 931b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, 932b9045b9cSDan Murphy aic32x4->setup->gpio_func[4]); 933b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp5, 934b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp5)); 935b9045b9cSDan Murphy } 936b9045b9cSDan Murphy } 937b9045b9cSDan Murphy 938b154dc5dSKuninori Morimoto static int aic32x4_component_probe(struct snd_soc_component *component) 9391d471cd1SJavier Martin { 940b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 9411d471cd1SJavier Martin u32 tmp_reg; 942fd2df3aeSAnnaliese McDermond int ret; 943fd2df3aeSAnnaliese McDermond 944fd2df3aeSAnnaliese McDermond struct clk_bulk_data clocks[] = { 945fd2df3aeSAnnaliese McDermond { .id = "codec_clkin" }, 946a51b5006SAnnaliese McDermond { .id = "pll" }, 9479b484124SAnnaliese McDermond { .id = "bdiv" }, 9489b484124SAnnaliese McDermond { .id = "mdac" }, 949fd2df3aeSAnnaliese McDermond }; 950fd2df3aeSAnnaliese McDermond 951fd2df3aeSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 952fd2df3aeSAnnaliese McDermond if (ret) 953fd2df3aeSAnnaliese McDermond return ret; 9541d471cd1SJavier Martin 955a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 9561858fe97SJavier Martin ndelay(10); 9571858fe97SJavier Martin gpio_set_value(aic32x4->rstn_gpio, 1); 958674f9abdSPeter Seiderer mdelay(1); 9591858fe97SJavier Martin } 9601858fe97SJavier Martin 961b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RESET, 0x01); 9621d471cd1SJavier Martin 963b9045b9cSDan Murphy if (aic32x4->setup) 964b154dc5dSKuninori Morimoto aic32x4_setup_gpios(component); 965b9045b9cSDan Murphy 966fd2df3aeSAnnaliese McDermond clk_set_parent(clocks[0].clk, clocks[1].clk); 9679b484124SAnnaliese McDermond clk_set_parent(clocks[2].clk, clocks[3].clk); 968fd2df3aeSAnnaliese McDermond 9691d471cd1SJavier Martin /* Power platform configuration */ 9701d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 971514b044cSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_MICBIAS, 972514b044cSAnnaliese McDermond AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 9731d471cd1SJavier Martin } 974eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 975b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 9760c93a167SWolfram Sang 9770c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 9780c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0; 979b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 9800c93a167SWolfram Sang 981b154dc5dSKuninori Morimoto tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 982eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 9831d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36; 984eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 9851d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP; 986b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 9871d471cd1SJavier Martin 9881d471cd1SJavier Martin /* Mic PGA routing */ 989609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 990b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 99143bf38baSShahina Shaik AIC32X4_LMICPGANIN_IN2R_10K); 992609e6025SMarkus Pargmann else 993b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN, 99443bf38baSShahina Shaik AIC32X4_LMICPGANIN_CM1L_10K); 995609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 996b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 99743bf38baSShahina Shaik AIC32X4_RMICPGANIN_IN1L_10K); 998609e6025SMarkus Pargmann else 999b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN, 100043bf38baSShahina Shaik AIC32X4_RMICPGANIN_CM1R_10K); 10011d471cd1SJavier Martin 1002a405387cSJavier Martin /* 1003a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up 1004a405387cSJavier Martin * and down for the first capture to work properly. It seems related to 1005a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet. 1006a405387cSJavier Martin */ 1007b154dc5dSKuninori Morimoto tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 1008b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1009a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1010b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1011a405387cSJavier Martin 10121d471cd1SJavier Martin return 0; 10131d471cd1SJavier Martin } 10141d471cd1SJavier Martin 1015b154dc5dSKuninori Morimoto static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1016b154dc5dSKuninori Morimoto .probe = aic32x4_component_probe, 10171d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level, 1018aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls, 1019aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1020aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets, 1021aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1022aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes, 1023aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1024b154dc5dSKuninori Morimoto .suspend_bias_off = 1, 1025b154dc5dSKuninori Morimoto .idle_bias_on = 1, 1026b154dc5dSKuninori Morimoto .use_pmdown_time = 1, 1027b154dc5dSKuninori Morimoto .endianness = 1, 1028b154dc5dSKuninori Morimoto .non_legacy_dai_naming = 1, 10291d471cd1SJavier Martin }; 10301d471cd1SJavier Martin 10314d16700dSMarkus Pargmann static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 10324d16700dSMarkus Pargmann struct device_node *np) 10334d16700dSMarkus Pargmann { 1034b9045b9cSDan Murphy struct aic32x4_setup_data *aic32x4_setup; 1035514b044cSAnnaliese McDermond int ret; 1036b9045b9cSDan Murphy 1037b9045b9cSDan Murphy aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1038b9045b9cSDan Murphy GFP_KERNEL); 1039b9045b9cSDan Murphy if (!aic32x4_setup) 1040b9045b9cSDan Murphy return -ENOMEM; 1041b9045b9cSDan Murphy 1042514b044cSAnnaliese McDermond ret = of_property_match_string(np, "clock-names", "mclk"); 1043514b044cSAnnaliese McDermond if (ret < 0) 1044514b044cSAnnaliese McDermond return -EINVAL; 1045514b044cSAnnaliese McDermond aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1046514b044cSAnnaliese McDermond 10474d16700dSMarkus Pargmann aic32x4->swapdacs = false; 10484d16700dSMarkus Pargmann aic32x4->micpga_routing = 0; 10494d16700dSMarkus Pargmann aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 10504d16700dSMarkus Pargmann 1051b9045b9cSDan Murphy if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1052b9045b9cSDan Murphy aic32x4_setup->gpio_func, 5) >= 0) 1053b9045b9cSDan Murphy aic32x4->setup = aic32x4_setup; 10544d16700dSMarkus Pargmann return 0; 10554d16700dSMarkus Pargmann } 10564d16700dSMarkus Pargmann 1057239b669bSMarkus Pargmann static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1058239b669bSMarkus Pargmann { 1059239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1060239b669bSMarkus Pargmann 1061239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1062239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1063239b669bSMarkus Pargmann 1064239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1065239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1066239b669bSMarkus Pargmann 1067239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) 1068239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_av); 1069239b669bSMarkus Pargmann } 1070239b669bSMarkus Pargmann 1071239b669bSMarkus Pargmann static int aic32x4_setup_regulators(struct device *dev, 1072239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4) 1073239b669bSMarkus Pargmann { 1074239b669bSMarkus Pargmann int ret = 0; 1075239b669bSMarkus Pargmann 1076239b669bSMarkus Pargmann aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1077239b669bSMarkus Pargmann aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1078239b669bSMarkus Pargmann aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1079239b669bSMarkus Pargmann aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1080239b669bSMarkus Pargmann 1081239b669bSMarkus Pargmann /* Check if the regulator requirements are fulfilled */ 1082239b669bSMarkus Pargmann 1083239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_iov)) { 1084239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'iov'\n"); 1085239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_iov); 1086239b669bSMarkus Pargmann } 1087239b669bSMarkus Pargmann 1088239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_ldo)) { 1089239b669bSMarkus Pargmann if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1090239b669bSMarkus Pargmann return -EPROBE_DEFER; 1091239b669bSMarkus Pargmann 1092239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv)) { 1093239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1094239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_dv); 1095239b669bSMarkus Pargmann } 1096239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av)) { 1097239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1098239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_av); 1099239b669bSMarkus Pargmann } 1100239b669bSMarkus Pargmann } else { 1101*45586c70SMasahiro Yamada if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1102239b669bSMarkus Pargmann return -EPROBE_DEFER; 1103*45586c70SMasahiro Yamada if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1104239b669bSMarkus Pargmann return -EPROBE_DEFER; 1105239b669bSMarkus Pargmann } 1106239b669bSMarkus Pargmann 1107239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_iov); 1108239b669bSMarkus Pargmann if (ret) { 1109239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator iov\n"); 1110239b669bSMarkus Pargmann return ret; 1111239b669bSMarkus Pargmann } 1112239b669bSMarkus Pargmann 1113239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) { 1114239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_ldo); 1115239b669bSMarkus Pargmann if (ret) { 1116239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator ldo\n"); 1117239b669bSMarkus Pargmann goto error_ldo; 1118239b669bSMarkus Pargmann } 1119239b669bSMarkus Pargmann } 1120239b669bSMarkus Pargmann 1121239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) { 1122239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_dv); 1123239b669bSMarkus Pargmann if (ret) { 1124239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator dv\n"); 1125239b669bSMarkus Pargmann goto error_dv; 1126239b669bSMarkus Pargmann } 1127239b669bSMarkus Pargmann } 1128239b669bSMarkus Pargmann 1129239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) { 1130239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_av); 1131239b669bSMarkus Pargmann if (ret) { 1132239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator av\n"); 1133239b669bSMarkus Pargmann goto error_av; 1134239b669bSMarkus Pargmann } 1135239b669bSMarkus Pargmann } 1136239b669bSMarkus Pargmann 1137239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1138239b669bSMarkus Pargmann aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1139239b669bSMarkus Pargmann 1140239b669bSMarkus Pargmann return 0; 1141239b669bSMarkus Pargmann 1142239b669bSMarkus Pargmann error_av: 1143239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1144239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1145239b669bSMarkus Pargmann 1146239b669bSMarkus Pargmann error_dv: 1147239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1148239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1149239b669bSMarkus Pargmann 1150239b669bSMarkus Pargmann error_ldo: 1151239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1152239b669bSMarkus Pargmann return ret; 1153239b669bSMarkus Pargmann } 1154239b669bSMarkus Pargmann 11553bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap) 11561d471cd1SJavier Martin { 11571d471cd1SJavier Martin struct aic32x4_priv *aic32x4; 11583bcfd222SJeremy McDermond struct aic32x4_pdata *pdata = dev->platform_data; 11593bcfd222SJeremy McDermond struct device_node *np = dev->of_node; 11601d471cd1SJavier Martin int ret; 11611d471cd1SJavier Martin 11623bcfd222SJeremy McDermond if (IS_ERR(regmap)) 11633bcfd222SJeremy McDermond return PTR_ERR(regmap); 11643bcfd222SJeremy McDermond 11653bcfd222SJeremy McDermond aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1166658ecf77SAxel Lin GFP_KERNEL); 11671d471cd1SJavier Martin if (aic32x4 == NULL) 11681d471cd1SJavier Martin return -ENOMEM; 11691d471cd1SJavier Martin 1170b9045b9cSDan Murphy aic32x4->dev = dev; 11713bcfd222SJeremy McDermond dev_set_drvdata(dev, aic32x4); 11721d471cd1SJavier Martin 11731d471cd1SJavier Martin if (pdata) { 11741d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg; 11751d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs; 11761d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing; 11771858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio; 1178514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 11794d16700dSMarkus Pargmann } else if (np) { 11804d16700dSMarkus Pargmann ret = aic32x4_parse_dt(aic32x4, np); 11814d16700dSMarkus Pargmann if (ret) { 11823bcfd222SJeremy McDermond dev_err(dev, "Failed to parse DT node\n"); 11834d16700dSMarkus Pargmann return ret; 11844d16700dSMarkus Pargmann } 11851d471cd1SJavier Martin } else { 11861d471cd1SJavier Martin aic32x4->power_cfg = 0; 11871d471cd1SJavier Martin aic32x4->swapdacs = false; 11881d471cd1SJavier Martin aic32x4->micpga_routing = 0; 11891858fe97SJavier Martin aic32x4->rstn_gpio = -1; 1190514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk"; 11911d471cd1SJavier Martin } 11921d471cd1SJavier Martin 1193514b044cSAnnaliese McDermond ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1194514b044cSAnnaliese McDermond if (ret) 1195514b044cSAnnaliese McDermond return ret; 1196514b044cSAnnaliese McDermond 1197a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 11983bcfd222SJeremy McDermond ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1199752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1200752b7764SMark Brown if (ret != 0) 1201752b7764SMark Brown return ret; 1202752b7764SMark Brown } 1203752b7764SMark Brown 12043bcfd222SJeremy McDermond ret = aic32x4_setup_regulators(dev, aic32x4); 1205239b669bSMarkus Pargmann if (ret) { 12063bcfd222SJeremy McDermond dev_err(dev, "Failed to setup regulators\n"); 1207239b669bSMarkus Pargmann return ret; 1208239b669bSMarkus Pargmann } 1209239b669bSMarkus Pargmann 1210b154dc5dSKuninori Morimoto ret = devm_snd_soc_register_component(dev, 1211b154dc5dSKuninori Morimoto &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1212239b669bSMarkus Pargmann if (ret) { 1213b154dc5dSKuninori Morimoto dev_err(dev, "Failed to register component\n"); 1214239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 12151d471cd1SJavier Martin return ret; 12161d471cd1SJavier Martin } 12171d471cd1SJavier Martin 1218239b669bSMarkus Pargmann return 0; 1219239b669bSMarkus Pargmann } 12203bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_probe); 1221239b669bSMarkus Pargmann 12223bcfd222SJeremy McDermond int aic32x4_remove(struct device *dev) 12231d471cd1SJavier Martin { 12243bcfd222SJeremy McDermond struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1225239b669bSMarkus Pargmann 1226239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 1227239b669bSMarkus Pargmann 12281d471cd1SJavier Martin return 0; 12291d471cd1SJavier Martin } 12303bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_remove); 12311d471cd1SJavier Martin 12321d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 12331d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 12341d471cd1SJavier Martin MODULE_LICENSE("GPL"); 1235