11d471cd1SJavier Martin /* 21d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c 31d471cd1SJavier Martin * 41d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L. 51d471cd1SJavier Martin * 61d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com> 71d471cd1SJavier Martin * 81d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 91d471cd1SJavier Martin * 101d471cd1SJavier Martin * This program is free software; you can redistribute it and/or modify 111d471cd1SJavier Martin * it under the terms of the GNU General Public License as published by 121d471cd1SJavier Martin * the Free Software Foundation; either version 2 of the License, or 131d471cd1SJavier Martin * (at your option) any later version. 141d471cd1SJavier Martin * 151d471cd1SJavier Martin * This program is distributed in the hope that it will be useful, 161d471cd1SJavier Martin * but WITHOUT ANY WARRANTY; without even the implied warranty of 171d471cd1SJavier Martin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 181d471cd1SJavier Martin * GNU General Public License for more details. 191d471cd1SJavier Martin * 201d471cd1SJavier Martin * You should have received a copy of the GNU General Public License 211d471cd1SJavier Martin * along with this program; if not, write to the Free Software 221d471cd1SJavier Martin * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 231d471cd1SJavier Martin * MA 02110-1301, USA. 241d471cd1SJavier Martin */ 251d471cd1SJavier Martin 261d471cd1SJavier Martin #include <linux/module.h> 271d471cd1SJavier Martin #include <linux/moduleparam.h> 281d471cd1SJavier Martin #include <linux/init.h> 291d471cd1SJavier Martin #include <linux/delay.h> 301d471cd1SJavier Martin #include <linux/pm.h> 311858fe97SJavier Martin #include <linux/gpio.h> 324d16700dSMarkus Pargmann #include <linux/of_gpio.h> 331d471cd1SJavier Martin #include <linux/cdev.h> 341d471cd1SJavier Martin #include <linux/slab.h> 3598b664e2SMarkus Pargmann #include <linux/clk.h> 36239b669bSMarkus Pargmann #include <linux/regulator/consumer.h> 371d471cd1SJavier Martin 381d471cd1SJavier Martin #include <sound/tlv320aic32x4.h> 391d471cd1SJavier Martin #include <sound/core.h> 401d471cd1SJavier Martin #include <sound/pcm.h> 411d471cd1SJavier Martin #include <sound/pcm_params.h> 421d471cd1SJavier Martin #include <sound/soc.h> 431d471cd1SJavier Martin #include <sound/soc-dapm.h> 441d471cd1SJavier Martin #include <sound/initval.h> 451d471cd1SJavier Martin #include <sound/tlv.h> 461d471cd1SJavier Martin 471d471cd1SJavier Martin #include "tlv320aic32x4.h" 481d471cd1SJavier Martin 491d471cd1SJavier Martin struct aic32x4_rate_divs { 501d471cd1SJavier Martin u32 mclk; 511d471cd1SJavier Martin u32 rate; 521d471cd1SJavier Martin u8 p_val; 531d471cd1SJavier Martin u8 pll_j; 541d471cd1SJavier Martin u16 pll_d; 551d471cd1SJavier Martin u16 dosr; 561d471cd1SJavier Martin u8 ndac; 571d471cd1SJavier Martin u8 mdac; 581d471cd1SJavier Martin u8 aosr; 591d471cd1SJavier Martin u8 nadc; 601d471cd1SJavier Martin u8 madc; 611d471cd1SJavier Martin u8 blck_N; 621d471cd1SJavier Martin }; 631d471cd1SJavier Martin 641d471cd1SJavier Martin struct aic32x4_priv { 654d208ca4SMark Brown struct regmap *regmap; 661d471cd1SJavier Martin u32 sysclk; 671d471cd1SJavier Martin u32 power_cfg; 681d471cd1SJavier Martin u32 micpga_routing; 691d471cd1SJavier Martin bool swapdacs; 701858fe97SJavier Martin int rstn_gpio; 7198b664e2SMarkus Pargmann struct clk *mclk; 72239b669bSMarkus Pargmann 73239b669bSMarkus Pargmann struct regulator *supply_ldo; 74239b669bSMarkus Pargmann struct regulator *supply_iov; 75239b669bSMarkus Pargmann struct regulator *supply_dv; 76239b669bSMarkus Pargmann struct regulator *supply_av; 77b9045b9cSDan Murphy 78b9045b9cSDan Murphy struct aic32x4_setup_data *setup; 79b9045b9cSDan Murphy struct device *dev; 80b9045b9cSDan Murphy }; 81b9045b9cSDan Murphy 82b9045b9cSDan Murphy static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 83b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 84b9045b9cSDan Murphy { 85b9045b9cSDan Murphy struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 86b9045b9cSDan Murphy u8 val; 87b9045b9cSDan Murphy 88b9045b9cSDan Murphy val = snd_soc_read(codec, AIC32X4_DINCTL); 89b9045b9cSDan Murphy 90b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 91b9045b9cSDan Murphy 92b9045b9cSDan Murphy return 0; 93b9045b9cSDan Murphy }; 94b9045b9cSDan Murphy 95b9045b9cSDan Murphy static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 96b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 97b9045b9cSDan Murphy { 98b9045b9cSDan Murphy struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 99b9045b9cSDan Murphy u8 val; 100b9045b9cSDan Murphy u8 gpio_check; 101b9045b9cSDan Murphy 102b9045b9cSDan Murphy val = snd_soc_read(codec, AIC32X4_DOUTCTL); 103b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 104b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 105b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 106b9045b9cSDan Murphy __func__); 107b9045b9cSDan Murphy return -EINVAL; 108b9045b9cSDan Murphy } 109b9045b9cSDan Murphy 110b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 111b9045b9cSDan Murphy return 0; 112b9045b9cSDan Murphy 113b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 114b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 115b9045b9cSDan Murphy else 116b9045b9cSDan Murphy val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 117b9045b9cSDan Murphy 118b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_DOUTCTL, val); 119b9045b9cSDan Murphy 120b9045b9cSDan Murphy return 0; 121b9045b9cSDan Murphy }; 122b9045b9cSDan Murphy 123b9045b9cSDan Murphy static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 124b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 125b9045b9cSDan Murphy { 126b9045b9cSDan Murphy struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 127b9045b9cSDan Murphy u8 val; 128b9045b9cSDan Murphy 129b9045b9cSDan Murphy val = snd_soc_read(codec, AIC32X4_SCLKCTL); 130b9045b9cSDan Murphy 131b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01); 132b9045b9cSDan Murphy 133b9045b9cSDan Murphy return 0; 134b9045b9cSDan Murphy }; 135b9045b9cSDan Murphy 136b9045b9cSDan Murphy static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 137b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 138b9045b9cSDan Murphy { 139b9045b9cSDan Murphy struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 140b9045b9cSDan Murphy u8 val; 141b9045b9cSDan Murphy u8 gpio_check; 142b9045b9cSDan Murphy 143b9045b9cSDan Murphy val = snd_soc_read(codec, AIC32X4_MISOCTL); 144b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 145b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 146b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 147b9045b9cSDan Murphy __func__); 148b9045b9cSDan Murphy return -EINVAL; 149b9045b9cSDan Murphy } 150b9045b9cSDan Murphy 151b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 152b9045b9cSDan Murphy return 0; 153b9045b9cSDan Murphy 154b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 155b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 156b9045b9cSDan Murphy else 157b9045b9cSDan Murphy val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 158b9045b9cSDan Murphy 159b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_MISOCTL, val); 160b9045b9cSDan Murphy 161b9045b9cSDan Murphy return 0; 162b9045b9cSDan Murphy }; 163b9045b9cSDan Murphy 164b9045b9cSDan Murphy static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 165b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 166b9045b9cSDan Murphy { 167b9045b9cSDan Murphy struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 168b9045b9cSDan Murphy u8 val; 169b9045b9cSDan Murphy 170b9045b9cSDan Murphy val = snd_soc_read(codec, AIC32X4_GPIOCTL); 171b9045b9cSDan Murphy ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 172b9045b9cSDan Murphy 173b9045b9cSDan Murphy return 0; 174b9045b9cSDan Murphy }; 175b9045b9cSDan Murphy 176b9045b9cSDan Murphy static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 177b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol) 178b9045b9cSDan Murphy { 179b9045b9cSDan Murphy struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 180b9045b9cSDan Murphy u8 val; 181b9045b9cSDan Murphy u8 gpio_check; 182b9045b9cSDan Murphy 183b9045b9cSDan Murphy val = snd_soc_read(codec, AIC32X4_GPIOCTL); 184b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 185b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 186b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 187b9045b9cSDan Murphy __func__); 188b9045b9cSDan Murphy return -EINVAL; 189b9045b9cSDan Murphy } 190b9045b9cSDan Murphy 191b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & 0x1)) 192b9045b9cSDan Murphy return 0; 193b9045b9cSDan Murphy 194b9045b9cSDan Murphy if (ucontrol->value.integer.value[0]) 195b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0]; 196b9045b9cSDan Murphy else 197b9045b9cSDan Murphy val &= 0xfe; 198b9045b9cSDan Murphy 199b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_GPIOCTL, val); 200b9045b9cSDan Murphy 201b9045b9cSDan Murphy return 0; 202b9045b9cSDan Murphy }; 203b9045b9cSDan Murphy 204b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp1[] = { 205b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 206b9045b9cSDan Murphy }; 207b9045b9cSDan Murphy 208b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp2[] = { 209b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 210b9045b9cSDan Murphy }; 211b9045b9cSDan Murphy 212b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp3[] = { 213b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 214b9045b9cSDan Murphy }; 215b9045b9cSDan Murphy 216b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp4[] = { 217b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 218b9045b9cSDan Murphy }; 219b9045b9cSDan Murphy 220b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp5[] = { 221b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 222b9045b9cSDan Murphy aic32x4_set_mfp5_gpio), 2231d471cd1SJavier Martin }; 2241d471cd1SJavier Martin 2251d471cd1SJavier Martin /* 0dB min, 0.5dB steps */ 2261d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 227c671e79dSMarkus Pargmann /* -63.5dB min, 0.5dB steps */ 228c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 229c671e79dSMarkus Pargmann /* -6dB min, 1dB steps */ 230c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 231c671e79dSMarkus Pargmann /* -12dB min, 0.5dB steps */ 232c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 2331d471cd1SJavier Martin 2341d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 235c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 236c671e79dSMarkus Pargmann AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 237c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 238c671e79dSMarkus Pargmann AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 239c671e79dSMarkus Pargmann tlv_driver_gain), 240c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 241c671e79dSMarkus Pargmann AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 242c671e79dSMarkus Pargmann tlv_driver_gain), 2431d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 2441d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1), 2451d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 2461d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1), 2471d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 2481d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1), 2491d471cd1SJavier Martin 2501d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 2511d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 2521d471cd1SJavier Martin 253c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 254c671e79dSMarkus Pargmann AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 2551d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 2561d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 2571d471cd1SJavier Martin 2581d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 2591d471cd1SJavier Martin 2601d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 2611d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 2621d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 2631d471cd1SJavier Martin 4, 0x07, 0), 2641d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 2651d471cd1SJavier Martin 0, 0x03, 0), 2661d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 2671d471cd1SJavier Martin 6, 0x03, 0), 2681d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 2691d471cd1SJavier Martin 1, 0x1F, 0), 2701d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 2711d471cd1SJavier Martin 0, 0x7F, 0), 2721d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 2731d471cd1SJavier Martin 3, 0x1F, 0), 2741d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 2751d471cd1SJavier Martin 3, 0x1F, 0), 2761d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 2771d471cd1SJavier Martin 0, 0x1F, 0), 2781d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 2791d471cd1SJavier Martin 0, 0x0F, 0), 2801d471cd1SJavier Martin }; 2811d471cd1SJavier Martin 2821d471cd1SJavier Martin static const struct aic32x4_rate_divs aic32x4_divs[] = { 2831d471cd1SJavier Martin /* 8k rate */ 2847e2a4dc5SAndrew F. Davis {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24}, 2857e2a4dc5SAndrew F. Davis {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24}, 2867e2a4dc5SAndrew F. Davis {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24}, 2871d471cd1SJavier Martin /* 11.025k rate */ 2887e2a4dc5SAndrew F. Davis {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16}, 2897e2a4dc5SAndrew F. Davis {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16}, 2901d471cd1SJavier Martin /* 16k rate */ 2917e2a4dc5SAndrew F. Davis {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12}, 2927e2a4dc5SAndrew F. Davis {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12}, 2937e2a4dc5SAndrew F. Davis {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12}, 2941d471cd1SJavier Martin /* 22.05k rate */ 2957e2a4dc5SAndrew F. Davis {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8}, 2967e2a4dc5SAndrew F. Davis {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8}, 2977e2a4dc5SAndrew F. Davis {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8}, 2981d471cd1SJavier Martin /* 32k rate */ 2997e2a4dc5SAndrew F. Davis {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6}, 3007e2a4dc5SAndrew F. Davis {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6}, 3011d471cd1SJavier Martin /* 44.1k rate */ 3027e2a4dc5SAndrew F. Davis {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4}, 3037e2a4dc5SAndrew F. Davis {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4}, 3047e2a4dc5SAndrew F. Davis {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4}, 3051d471cd1SJavier Martin /* 48k rate */ 3067e2a4dc5SAndrew F. Davis {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4}, 3077e2a4dc5SAndrew F. Davis {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4}, 3087e2a4dc5SAndrew F. Davis {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}, 309041f9d33SJeremy McDermond 310041f9d33SJeremy McDermond /* 96k rate */ 3117e2a4dc5SAndrew F. Davis {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1}, 3121d471cd1SJavier Martin }; 3131d471cd1SJavier Martin 3141d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 3151d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 3161d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 3171d471cd1SJavier Martin }; 3181d471cd1SJavier Martin 3191d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 3201d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 3211d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 3221d471cd1SJavier Martin }; 3231d471cd1SJavier Martin 3241d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 3251d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 3261d471cd1SJavier Martin }; 3271d471cd1SJavier Martin 3281d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 3291d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 3301d471cd1SJavier Martin }; 3311d471cd1SJavier Martin 33220d2cecbSJeremy McDermond static const char * const resistor_text[] = { 33320d2cecbSJeremy McDermond "Off", "10 kOhm", "20 kOhm", "40 kOhm", 3341d471cd1SJavier Martin }; 3351d471cd1SJavier Martin 3362213fc35SJeremy McDermond /* Left mixer pins */ 3372213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 3382213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 3392213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 3402213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 34120d2cecbSJeremy McDermond 3422213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 3432213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 3442213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 3452213fc35SJeremy McDermond 3462213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 3472213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 3482213fc35SJeremy McDermond }; 3492213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 3502213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 3512213fc35SJeremy McDermond }; 3522213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 3532213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 3542213fc35SJeremy McDermond }; 3552213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 3562213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 3572213fc35SJeremy McDermond }; 3582213fc35SJeremy McDermond static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 3592213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 3602213fc35SJeremy McDermond }; 3612213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 3622213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 3632213fc35SJeremy McDermond }; 3642213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 3652213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 36620d2cecbSJeremy McDermond }; 36720d2cecbSJeremy McDermond 3682213fc35SJeremy McDermond /* Right mixer pins */ 3692213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 3702213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 3712213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 3722213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 3732213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 3742213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 3752213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 37620d2cecbSJeremy McDermond 3772213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 3782213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 3792213fc35SJeremy McDermond }; 3802213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 3812213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 3822213fc35SJeremy McDermond }; 3832213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 3842213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 3852213fc35SJeremy McDermond }; 3862213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 3872213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 3882213fc35SJeremy McDermond }; 3892213fc35SJeremy McDermond static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 3902213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 3912213fc35SJeremy McDermond }; 3922213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 3932213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 3942213fc35SJeremy McDermond }; 3952213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 3962213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 3971d471cd1SJavier Martin }; 3981d471cd1SJavier Martin 3991d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 4001d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 4011d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 4021d471cd1SJavier Martin &hpl_output_mixer_controls[0], 4031d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)), 4041d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 4051d471cd1SJavier Martin 4061d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 4071d471cd1SJavier Martin &lol_output_mixer_controls[0], 4081d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)), 4091d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 4101d471cd1SJavier Martin 4111d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 4121d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 4131d471cd1SJavier Martin &hpr_output_mixer_controls[0], 4141d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)), 4151d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 4161d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 4171d471cd1SJavier Martin &lor_output_mixer_controls[0], 4181d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)), 4191d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 4202213fc35SJeremy McDermond 4211d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 4222213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4232213fc35SJeremy McDermond in1r_to_rmixer_controls), 4242213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4252213fc35SJeremy McDermond in2r_to_rmixer_controls), 4262213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4272213fc35SJeremy McDermond in3r_to_rmixer_controls), 4282213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4292213fc35SJeremy McDermond in2l_to_rmixer_controls), 4302213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4312213fc35SJeremy McDermond cmr_to_rmixer_controls), 4322213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4332213fc35SJeremy McDermond in1l_to_rmixer_controls), 4342213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4352213fc35SJeremy McDermond in3l_to_rmixer_controls), 4362213fc35SJeremy McDermond 4372213fc35SJeremy McDermond SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 4382213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4392213fc35SJeremy McDermond in1l_to_lmixer_controls), 4402213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4412213fc35SJeremy McDermond in2l_to_lmixer_controls), 4422213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4432213fc35SJeremy McDermond in3l_to_lmixer_controls), 4442213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 4452213fc35SJeremy McDermond in1r_to_lmixer_controls), 4462213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4472213fc35SJeremy McDermond cml_to_lmixer_controls), 4482213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4492213fc35SJeremy McDermond in2r_to_lmixer_controls), 4502213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 4512213fc35SJeremy McDermond in3r_to_lmixer_controls), 4522213fc35SJeremy McDermond 4531d471cd1SJavier Martin SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0), 4541d471cd1SJavier Martin 4551d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"), 4561d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"), 4571d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"), 4581d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"), 4591d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"), 4601d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"), 4611d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"), 4621d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"), 4631d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"), 4641d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"), 4651d471cd1SJavier Martin }; 4661d471cd1SJavier Martin 4671d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 4681d471cd1SJavier Martin /* Left Output */ 4691d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 4701d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 4711d471cd1SJavier Martin 4721d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"}, 4731d471cd1SJavier Martin {"HPL", NULL, "HPL Power"}, 4741d471cd1SJavier Martin 4751d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 4761d471cd1SJavier Martin 4771d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"}, 4781d471cd1SJavier Martin {"LOL", NULL, "LOL Power"}, 4791d471cd1SJavier Martin 4801d471cd1SJavier Martin /* Right Output */ 4811d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 4821d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 4831d471cd1SJavier Martin 4841d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"}, 4851d471cd1SJavier Martin {"HPR", NULL, "HPR Power"}, 4861d471cd1SJavier Martin 4871d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 4881d471cd1SJavier Martin 4891d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"}, 4901d471cd1SJavier Martin {"LOR", NULL, "LOR Power"}, 4911d471cd1SJavier Martin 4921d471cd1SJavier Martin /* Right Input */ 4932213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 4942213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 4952213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 4962213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 4971d471cd1SJavier Martin 4982213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 4992213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 5002213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 5012213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 5022213fc35SJeremy McDermond 5032213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 5042213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 5052213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 5062213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 5072213fc35SJeremy McDermond 5082213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 5092213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5102213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5112213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5122213fc35SJeremy McDermond 5132213fc35SJeremy McDermond {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 5142213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 5152213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 5162213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 5172213fc35SJeremy McDermond 5182213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 5192213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 5202213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 5212213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 5222213fc35SJeremy McDermond 5232213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 5242213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 5252213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 5262213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 5272213fc35SJeremy McDermond 5282213fc35SJeremy McDermond /* Left Input */ 5292213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 5302213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 5312213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 5322213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 5332213fc35SJeremy McDermond 5342213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 5352213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 5362213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 5372213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 5382213fc35SJeremy McDermond 5392213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 5402213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 5412213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 5422213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 5432213fc35SJeremy McDermond 5442213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 5452213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 5462213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 5472213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 5482213fc35SJeremy McDermond 5492213fc35SJeremy McDermond {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 5502213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 5512213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 5522213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 5532213fc35SJeremy McDermond 5542213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 5552213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 5562213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 5572213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 5582213fc35SJeremy McDermond 5592213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 5602213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 5612213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 5622213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 5631d471cd1SJavier Martin }; 5641d471cd1SJavier Martin 5654d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 5661d471cd1SJavier Martin { 5674d208ca4SMark Brown .selector_reg = 0, 5684d208ca4SMark Brown .selector_mask = 0xff, 5694d208ca4SMark Brown .window_start = 0, 5704d208ca4SMark Brown .window_len = 128, 571e8e08c52SMarkus Pargmann .range_min = 0, 5726d0d5103SMarkus Pargmann .range_max = AIC32X4_RMICPGAVOL, 5734d208ca4SMark Brown }, 5744d208ca4SMark Brown }; 5751d471cd1SJavier Martin 5763bcfd222SJeremy McDermond const struct regmap_config aic32x4_regmap_config = { 5774d208ca4SMark Brown .max_register = AIC32X4_RMICPGAVOL, 5784d208ca4SMark Brown .ranges = aic32x4_regmap_pages, 5794d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 5804d208ca4SMark Brown }; 5813bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_regmap_config); 5821d471cd1SJavier Martin 5831d471cd1SJavier Martin static inline int aic32x4_get_divs(int mclk, int rate) 5841d471cd1SJavier Martin { 5851d471cd1SJavier Martin int i; 5861d471cd1SJavier Martin 5871d471cd1SJavier Martin for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 5881d471cd1SJavier Martin if ((aic32x4_divs[i].rate == rate) 5891d471cd1SJavier Martin && (aic32x4_divs[i].mclk == mclk)) { 5901d471cd1SJavier Martin return i; 5911d471cd1SJavier Martin } 5921d471cd1SJavier Martin } 5931d471cd1SJavier Martin printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 5941d471cd1SJavier Martin return -EINVAL; 5951d471cd1SJavier Martin } 5961d471cd1SJavier Martin 5971d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 5981d471cd1SJavier Martin int clk_id, unsigned int freq, int dir) 5991d471cd1SJavier Martin { 6001d471cd1SJavier Martin struct snd_soc_codec *codec = codec_dai->codec; 6011d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 6021d471cd1SJavier Martin 6031d471cd1SJavier Martin switch (freq) { 6047e2a4dc5SAndrew F. Davis case 12000000: 6057e2a4dc5SAndrew F. Davis case 24000000: 6067e2a4dc5SAndrew F. Davis case 25000000: 6071d471cd1SJavier Martin aic32x4->sysclk = freq; 6081d471cd1SJavier Martin return 0; 6091d471cd1SJavier Martin } 6101d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 6111d471cd1SJavier Martin return -EINVAL; 6121d471cd1SJavier Martin } 6131d471cd1SJavier Martin 6141d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 6151d471cd1SJavier Martin { 6161d471cd1SJavier Martin struct snd_soc_codec *codec = codec_dai->codec; 6171d471cd1SJavier Martin u8 iface_reg_1; 6181d471cd1SJavier Martin u8 iface_reg_2; 6191d471cd1SJavier Martin u8 iface_reg_3; 6201d471cd1SJavier Martin 6211d471cd1SJavier Martin iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1); 6221d471cd1SJavier Martin iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2); 6231d471cd1SJavier Martin iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2); 6241d471cd1SJavier Martin iface_reg_2 = 0; 6251d471cd1SJavier Martin iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3); 6261d471cd1SJavier Martin iface_reg_3 = iface_reg_3 & ~(1 << 3); 6271d471cd1SJavier Martin 6281d471cd1SJavier Martin /* set master/slave audio interface */ 6291d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 6301d471cd1SJavier Martin case SND_SOC_DAIFMT_CBM_CFM: 6311d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 6321d471cd1SJavier Martin break; 6331d471cd1SJavier Martin case SND_SOC_DAIFMT_CBS_CFS: 6341d471cd1SJavier Martin break; 6351d471cd1SJavier Martin default: 6361d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 6371d471cd1SJavier Martin return -EINVAL; 6381d471cd1SJavier Martin } 6391d471cd1SJavier Martin 6401d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 6411d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S: 6421d471cd1SJavier Martin break; 6431d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A: 644*4483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 645*4483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6461d471cd1SJavier Martin iface_reg_3 |= (1 << 3); /* invert bit clock */ 6471d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */ 6481d471cd1SJavier Martin break; 6491d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B: 650*4483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE << 651*4483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6521d471cd1SJavier Martin iface_reg_3 |= (1 << 3); /* invert bit clock */ 6531d471cd1SJavier Martin break; 6541d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J: 655*4483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 656*4483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6571d471cd1SJavier Martin break; 6581d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J: 659*4483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 660*4483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT); 6611d471cd1SJavier Martin break; 6621d471cd1SJavier Martin default: 6631d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 6641d471cd1SJavier Martin return -EINVAL; 6651d471cd1SJavier Martin } 6661d471cd1SJavier Martin 6671d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1); 6681d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2); 6691d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3); 6701d471cd1SJavier Martin return 0; 6711d471cd1SJavier Martin } 6721d471cd1SJavier Martin 6731d471cd1SJavier Martin static int aic32x4_hw_params(struct snd_pcm_substream *substream, 6741d471cd1SJavier Martin struct snd_pcm_hw_params *params, 6751d471cd1SJavier Martin struct snd_soc_dai *dai) 6761d471cd1SJavier Martin { 6771d471cd1SJavier Martin struct snd_soc_codec *codec = dai->codec; 6781d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 6791d471cd1SJavier Martin u8 data; 6801d471cd1SJavier Martin int i; 6811d471cd1SJavier Martin 6821d471cd1SJavier Martin i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params)); 6831d471cd1SJavier Martin if (i < 0) { 6841d471cd1SJavier Martin printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 6851d471cd1SJavier Martin return i; 6861d471cd1SJavier Martin } 6871d471cd1SJavier Martin 6881d471cd1SJavier Martin /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */ 6891d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN); 6901d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK); 6911d471cd1SJavier Martin 6921d471cd1SJavier Martin /* We will fix R value to 1 and will make P & J=K.D as varialble */ 6931d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_PLLPR); 6941d471cd1SJavier Martin data &= ~(7 << 4); 6951d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLPR, 6961d471cd1SJavier Martin (data | (aic32x4_divs[i].p_val << 4) | 0x01)); 6971d471cd1SJavier Martin 6981d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j); 6991d471cd1SJavier Martin 7001d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8)); 7011d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PLLDLSB, 7021d471cd1SJavier Martin (aic32x4_divs[i].pll_d & 0xff)); 7031d471cd1SJavier Martin 7041d471cd1SJavier Martin /* NDAC divider value */ 7051d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_NDAC); 7061d471cd1SJavier Martin data &= ~(0x7f); 7071d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac); 7081d471cd1SJavier Martin 7091d471cd1SJavier Martin /* MDAC divider value */ 7101d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_MDAC); 7111d471cd1SJavier Martin data &= ~(0x7f); 7121d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac); 7131d471cd1SJavier Martin 7141d471cd1SJavier Martin /* DOSR MSB & LSB values */ 7151d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 7161d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DOSRLSB, 7171d471cd1SJavier Martin (aic32x4_divs[i].dosr & 0xff)); 7181d471cd1SJavier Martin 7191d471cd1SJavier Martin /* NADC divider value */ 7201d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_NADC); 7211d471cd1SJavier Martin data &= ~(0x7f); 7221d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc); 7231d471cd1SJavier Martin 7241d471cd1SJavier Martin /* MADC divider value */ 7251d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_MADC); 7261d471cd1SJavier Martin data &= ~(0x7f); 7271d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc); 7281d471cd1SJavier Martin 7291d471cd1SJavier Martin /* AOSR value */ 7301d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr); 7311d471cd1SJavier Martin 7321d471cd1SJavier Martin /* BCLK N divider */ 7331d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_BCLKN); 7341d471cd1SJavier Martin data &= ~(0x7f); 7351d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N); 7361d471cd1SJavier Martin 7371d471cd1SJavier Martin data = snd_soc_read(codec, AIC32X4_IFACE1); 7381d471cd1SJavier Martin data = data & ~(3 << 4); 739bd8a5711SMark Brown switch (params_width(params)) { 740bd8a5711SMark Brown case 16: 7411d471cd1SJavier Martin break; 742bd8a5711SMark Brown case 20: 7431d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT); 7441d471cd1SJavier Martin break; 745bd8a5711SMark Brown case 24: 7461d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT); 7471d471cd1SJavier Martin break; 748bd8a5711SMark Brown case 32: 7491d471cd1SJavier Martin data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT); 7501d471cd1SJavier Martin break; 7511d471cd1SJavier Martin } 7521d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_IFACE1, data); 7531d471cd1SJavier Martin 754b44aa40fSMarkus Pargmann if (params_channels(params) == 1) { 755b44aa40fSMarkus Pargmann data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 756b44aa40fSMarkus Pargmann } else { 757b44aa40fSMarkus Pargmann if (aic32x4->swapdacs) 758b44aa40fSMarkus Pargmann data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 759b44aa40fSMarkus Pargmann else 760b44aa40fSMarkus Pargmann data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 761b44aa40fSMarkus Pargmann } 762b44aa40fSMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK, 763b44aa40fSMarkus Pargmann data); 764b44aa40fSMarkus Pargmann 7651d471cd1SJavier Martin return 0; 7661d471cd1SJavier Martin } 7671d471cd1SJavier Martin 7681d471cd1SJavier Martin static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 7691d471cd1SJavier Martin { 7701d471cd1SJavier Martin struct snd_soc_codec *codec = dai->codec; 7711d471cd1SJavier Martin u8 dac_reg; 7721d471cd1SJavier Martin 7731d471cd1SJavier Martin dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON; 7741d471cd1SJavier Martin if (mute) 7751d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON); 7761d471cd1SJavier Martin else 7771d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg); 7781d471cd1SJavier Martin return 0; 7791d471cd1SJavier Martin } 7801d471cd1SJavier Martin 7811d471cd1SJavier Martin static int aic32x4_set_bias_level(struct snd_soc_codec *codec, 7821d471cd1SJavier Martin enum snd_soc_bias_level level) 7831d471cd1SJavier Martin { 78498b664e2SMarkus Pargmann struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 78598b664e2SMarkus Pargmann int ret; 78698b664e2SMarkus Pargmann 7871d471cd1SJavier Martin switch (level) { 7881d471cd1SJavier Martin case SND_SOC_BIAS_ON: 78998b664e2SMarkus Pargmann /* Switch on master clock */ 79098b664e2SMarkus Pargmann ret = clk_prepare_enable(aic32x4->mclk); 79198b664e2SMarkus Pargmann if (ret) { 79298b664e2SMarkus Pargmann dev_err(codec->dev, "Failed to enable master clock\n"); 79398b664e2SMarkus Pargmann return ret; 79498b664e2SMarkus Pargmann } 79598b664e2SMarkus Pargmann 7961d471cd1SJavier Martin /* Switch on PLL */ 797bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_PLLPR, 798bc6ae96aSAxel Lin AIC32X4_PLLEN, AIC32X4_PLLEN); 7991d471cd1SJavier Martin 8001d471cd1SJavier Martin /* Switch on NDAC Divider */ 801bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NDAC, 802bc6ae96aSAxel Lin AIC32X4_NDACEN, AIC32X4_NDACEN); 8031d471cd1SJavier Martin 8041d471cd1SJavier Martin /* Switch on MDAC Divider */ 805bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MDAC, 806bc6ae96aSAxel Lin AIC32X4_MDACEN, AIC32X4_MDACEN); 8071d471cd1SJavier Martin 8081d471cd1SJavier Martin /* Switch on NADC Divider */ 809bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_NADC, 810bc6ae96aSAxel Lin AIC32X4_NADCEN, AIC32X4_NADCEN); 8111d471cd1SJavier Martin 8121d471cd1SJavier Martin /* Switch on MADC Divider */ 813bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MADC, 814bc6ae96aSAxel Lin AIC32X4_MADCEN, AIC32X4_MADCEN); 8151d471cd1SJavier Martin 8161d471cd1SJavier Martin /* Switch on BCLK_N Divider */ 817bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_BCLKN, 818bc6ae96aSAxel Lin AIC32X4_BCLKEN, AIC32X4_BCLKEN); 8191d471cd1SJavier Martin break; 8201d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE: 8211d471cd1SJavier Martin break; 8221d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY: 8233154cc74SMarkus Pargmann /* Switch off BCLK_N Divider */ 8243154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_BCLKN, 8253154cc74SMarkus Pargmann AIC32X4_BCLKEN, 0); 8261d471cd1SJavier Martin 8271d471cd1SJavier Martin /* Switch off MADC Divider */ 828bc6ae96aSAxel Lin snd_soc_update_bits(codec, AIC32X4_MADC, 829bc6ae96aSAxel Lin AIC32X4_MADCEN, 0); 8301d471cd1SJavier Martin 8313154cc74SMarkus Pargmann /* Switch off NADC Divider */ 8323154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_NADC, 8333154cc74SMarkus Pargmann AIC32X4_NADCEN, 0); 8343154cc74SMarkus Pargmann 8353154cc74SMarkus Pargmann /* Switch off MDAC Divider */ 8363154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_MDAC, 8373154cc74SMarkus Pargmann AIC32X4_MDACEN, 0); 8383154cc74SMarkus Pargmann 8393154cc74SMarkus Pargmann /* Switch off NDAC Divider */ 8403154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_NDAC, 8413154cc74SMarkus Pargmann AIC32X4_NDACEN, 0); 8423154cc74SMarkus Pargmann 8433154cc74SMarkus Pargmann /* Switch off PLL */ 8443154cc74SMarkus Pargmann snd_soc_update_bits(codec, AIC32X4_PLLPR, 8453154cc74SMarkus Pargmann AIC32X4_PLLEN, 0); 84698b664e2SMarkus Pargmann 84798b664e2SMarkus Pargmann /* Switch off master clock */ 84898b664e2SMarkus Pargmann clk_disable_unprepare(aic32x4->mclk); 8491d471cd1SJavier Martin break; 8501d471cd1SJavier Martin case SND_SOC_BIAS_OFF: 8511d471cd1SJavier Martin break; 8521d471cd1SJavier Martin } 8531d471cd1SJavier Martin return 0; 8541d471cd1SJavier Martin } 8551d471cd1SJavier Martin 856041f9d33SJeremy McDermond #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000 8571d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 8581d471cd1SJavier Martin | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 8591d471cd1SJavier Martin 86085e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = { 8611d471cd1SJavier Martin .hw_params = aic32x4_hw_params, 8621d471cd1SJavier Martin .digital_mute = aic32x4_mute, 8631d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt, 8641d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk, 8651d471cd1SJavier Martin }; 8661d471cd1SJavier Martin 8671d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = { 8681d471cd1SJavier Martin .name = "tlv320aic32x4-hifi", 8691d471cd1SJavier Martin .playback = { 8701d471cd1SJavier Martin .stream_name = "Playback", 8711d471cd1SJavier Martin .channels_min = 1, 8721d471cd1SJavier Martin .channels_max = 2, 8731d471cd1SJavier Martin .rates = AIC32X4_RATES, 8741d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 8751d471cd1SJavier Martin .capture = { 8761d471cd1SJavier Martin .stream_name = "Capture", 8771d471cd1SJavier Martin .channels_min = 1, 8781d471cd1SJavier Martin .channels_max = 2, 8791d471cd1SJavier Martin .rates = AIC32X4_RATES, 8801d471cd1SJavier Martin .formats = AIC32X4_FORMATS,}, 8811d471cd1SJavier Martin .ops = &aic32x4_ops, 8821d471cd1SJavier Martin .symmetric_rates = 1, 8831d471cd1SJavier Martin }; 8841d471cd1SJavier Martin 885b9045b9cSDan Murphy static void aic32x4_setup_gpios(struct snd_soc_codec *codec) 886b9045b9cSDan Murphy { 887b9045b9cSDan Murphy struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 888b9045b9cSDan Murphy 889b9045b9cSDan Murphy /* setup GPIO functions */ 890b9045b9cSDan Murphy /* MFP1 */ 891b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 892b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_DINCTL, 893b9045b9cSDan Murphy aic32x4->setup->gpio_func[0]); 894b9045b9cSDan Murphy snd_soc_add_codec_controls(codec, aic32x4_mfp1, 895b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp1)); 896b9045b9cSDan Murphy } 897b9045b9cSDan Murphy 898b9045b9cSDan Murphy /* MFP2 */ 899b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 900b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_DOUTCTL, 901b9045b9cSDan Murphy aic32x4->setup->gpio_func[1]); 902b9045b9cSDan Murphy snd_soc_add_codec_controls(codec, aic32x4_mfp2, 903b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp2)); 904b9045b9cSDan Murphy } 905b9045b9cSDan Murphy 906b9045b9cSDan Murphy /* MFP3 */ 907b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 908b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_SCLKCTL, 909b9045b9cSDan Murphy aic32x4->setup->gpio_func[2]); 910b9045b9cSDan Murphy snd_soc_add_codec_controls(codec, aic32x4_mfp3, 911b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp3)); 912b9045b9cSDan Murphy } 913b9045b9cSDan Murphy 914b9045b9cSDan Murphy /* MFP4 */ 915b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 916b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_MISOCTL, 917b9045b9cSDan Murphy aic32x4->setup->gpio_func[3]); 918b9045b9cSDan Murphy snd_soc_add_codec_controls(codec, aic32x4_mfp4, 919b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp4)); 920b9045b9cSDan Murphy } 921b9045b9cSDan Murphy 922b9045b9cSDan Murphy /* MFP5 */ 923b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 924b9045b9cSDan Murphy snd_soc_write(codec, AIC32X4_GPIOCTL, 925b9045b9cSDan Murphy aic32x4->setup->gpio_func[4]); 926b9045b9cSDan Murphy snd_soc_add_codec_controls(codec, aic32x4_mfp5, 927b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp5)); 928b9045b9cSDan Murphy } 929b9045b9cSDan Murphy } 930b9045b9cSDan Murphy 931ec513886SJeremy McDermond static int aic32x4_codec_probe(struct snd_soc_codec *codec) 9321d471cd1SJavier Martin { 9331d471cd1SJavier Martin struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 9341d471cd1SJavier Martin u32 tmp_reg; 9351d471cd1SJavier Martin 936a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 9371858fe97SJavier Martin ndelay(10); 9381858fe97SJavier Martin gpio_set_value(aic32x4->rstn_gpio, 1); 9391858fe97SJavier Martin } 9401858fe97SJavier Martin 9411d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_RESET, 0x01); 9421d471cd1SJavier Martin 943b9045b9cSDan Murphy if (aic32x4->setup) 944b9045b9cSDan Murphy aic32x4_setup_gpios(codec); 945b9045b9cSDan Murphy 9461d471cd1SJavier Martin /* Power platform configuration */ 9471d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 9481d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN | 9491d471cd1SJavier Martin AIC32X4_MICBIAS_2075V); 9501d471cd1SJavier Martin } 951eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 9521d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 9530c93a167SWolfram Sang 9540c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 9550c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0; 9560c93a167SWolfram Sang snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg); 9570c93a167SWolfram Sang 9581d471cd1SJavier Martin tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE); 959eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 9601d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36; 961eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 9621d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP; 9631d471cd1SJavier Martin snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg); 9641d471cd1SJavier Martin 9651d471cd1SJavier Martin /* Mic PGA routing */ 966609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 96743bf38baSShahina Shaik snd_soc_write(codec, AIC32X4_LMICPGANIN, 96843bf38baSShahina Shaik AIC32X4_LMICPGANIN_IN2R_10K); 969609e6025SMarkus Pargmann else 97043bf38baSShahina Shaik snd_soc_write(codec, AIC32X4_LMICPGANIN, 97143bf38baSShahina Shaik AIC32X4_LMICPGANIN_CM1L_10K); 972609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 97343bf38baSShahina Shaik snd_soc_write(codec, AIC32X4_RMICPGANIN, 97443bf38baSShahina Shaik AIC32X4_RMICPGANIN_IN1L_10K); 975609e6025SMarkus Pargmann else 97643bf38baSShahina Shaik snd_soc_write(codec, AIC32X4_RMICPGANIN, 97743bf38baSShahina Shaik AIC32X4_RMICPGANIN_CM1R_10K); 9781d471cd1SJavier Martin 979a405387cSJavier Martin /* 980a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up 981a405387cSJavier Martin * and down for the first capture to work properly. It seems related to 982a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet. 983a405387cSJavier Martin */ 984a405387cSJavier Martin tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP); 985a405387cSJavier Martin snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg | 986a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN); 987a405387cSJavier Martin snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg); 988a405387cSJavier Martin 9891d471cd1SJavier Martin return 0; 9901d471cd1SJavier Martin } 9911d471cd1SJavier Martin 992a180ba45SBhumika Goyal static const struct snd_soc_codec_driver soc_codec_dev_aic32x4 = { 993ec513886SJeremy McDermond .probe = aic32x4_codec_probe, 9941d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level, 995f10c0a71SLars-Peter Clausen .suspend_bias_off = true, 996aac97b5fSLars-Peter Clausen 997a06809b8SKuninori Morimoto .component_driver = { 998aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls, 999aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1000aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets, 1001aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1002aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes, 1003aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1004a06809b8SKuninori Morimoto }, 10051d471cd1SJavier Martin }; 10061d471cd1SJavier Martin 10074d16700dSMarkus Pargmann static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 10084d16700dSMarkus Pargmann struct device_node *np) 10094d16700dSMarkus Pargmann { 1010b9045b9cSDan Murphy struct aic32x4_setup_data *aic32x4_setup; 1011b9045b9cSDan Murphy 1012b9045b9cSDan Murphy aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1013b9045b9cSDan Murphy GFP_KERNEL); 1014b9045b9cSDan Murphy if (!aic32x4_setup) 1015b9045b9cSDan Murphy return -ENOMEM; 1016b9045b9cSDan Murphy 10174d16700dSMarkus Pargmann aic32x4->swapdacs = false; 10184d16700dSMarkus Pargmann aic32x4->micpga_routing = 0; 10194d16700dSMarkus Pargmann aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 10204d16700dSMarkus Pargmann 1021b9045b9cSDan Murphy if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1022b9045b9cSDan Murphy aic32x4_setup->gpio_func, 5) >= 0) 1023b9045b9cSDan Murphy aic32x4->setup = aic32x4_setup; 10244d16700dSMarkus Pargmann return 0; 10254d16700dSMarkus Pargmann } 10264d16700dSMarkus Pargmann 1027239b669bSMarkus Pargmann static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1028239b669bSMarkus Pargmann { 1029239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1030239b669bSMarkus Pargmann 1031239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1032239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1033239b669bSMarkus Pargmann 1034239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1035239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1036239b669bSMarkus Pargmann 1037239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) 1038239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_av); 1039239b669bSMarkus Pargmann } 1040239b669bSMarkus Pargmann 1041239b669bSMarkus Pargmann static int aic32x4_setup_regulators(struct device *dev, 1042239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4) 1043239b669bSMarkus Pargmann { 1044239b669bSMarkus Pargmann int ret = 0; 1045239b669bSMarkus Pargmann 1046239b669bSMarkus Pargmann aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1047239b669bSMarkus Pargmann aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1048239b669bSMarkus Pargmann aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1049239b669bSMarkus Pargmann aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1050239b669bSMarkus Pargmann 1051239b669bSMarkus Pargmann /* Check if the regulator requirements are fulfilled */ 1052239b669bSMarkus Pargmann 1053239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_iov)) { 1054239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'iov'\n"); 1055239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_iov); 1056239b669bSMarkus Pargmann } 1057239b669bSMarkus Pargmann 1058239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_ldo)) { 1059239b669bSMarkus Pargmann if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1060239b669bSMarkus Pargmann return -EPROBE_DEFER; 1061239b669bSMarkus Pargmann 1062239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv)) { 1063239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1064239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_dv); 1065239b669bSMarkus Pargmann } 1066239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av)) { 1067239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1068239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_av); 1069239b669bSMarkus Pargmann } 1070239b669bSMarkus Pargmann } else { 1071239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv) && 1072239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1073239b669bSMarkus Pargmann return -EPROBE_DEFER; 1074239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av) && 1075239b669bSMarkus Pargmann PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1076239b669bSMarkus Pargmann return -EPROBE_DEFER; 1077239b669bSMarkus Pargmann } 1078239b669bSMarkus Pargmann 1079239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_iov); 1080239b669bSMarkus Pargmann if (ret) { 1081239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator iov\n"); 1082239b669bSMarkus Pargmann return ret; 1083239b669bSMarkus Pargmann } 1084239b669bSMarkus Pargmann 1085239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) { 1086239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_ldo); 1087239b669bSMarkus Pargmann if (ret) { 1088239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator ldo\n"); 1089239b669bSMarkus Pargmann goto error_ldo; 1090239b669bSMarkus Pargmann } 1091239b669bSMarkus Pargmann } 1092239b669bSMarkus Pargmann 1093239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) { 1094239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_dv); 1095239b669bSMarkus Pargmann if (ret) { 1096239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator dv\n"); 1097239b669bSMarkus Pargmann goto error_dv; 1098239b669bSMarkus Pargmann } 1099239b669bSMarkus Pargmann } 1100239b669bSMarkus Pargmann 1101239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) { 1102239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_av); 1103239b669bSMarkus Pargmann if (ret) { 1104239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator av\n"); 1105239b669bSMarkus Pargmann goto error_av; 1106239b669bSMarkus Pargmann } 1107239b669bSMarkus Pargmann } 1108239b669bSMarkus Pargmann 1109239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1110239b669bSMarkus Pargmann aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1111239b669bSMarkus Pargmann 1112239b669bSMarkus Pargmann return 0; 1113239b669bSMarkus Pargmann 1114239b669bSMarkus Pargmann error_av: 1115239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) 1116239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv); 1117239b669bSMarkus Pargmann 1118239b669bSMarkus Pargmann error_dv: 1119239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) 1120239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo); 1121239b669bSMarkus Pargmann 1122239b669bSMarkus Pargmann error_ldo: 1123239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov); 1124239b669bSMarkus Pargmann return ret; 1125239b669bSMarkus Pargmann } 1126239b669bSMarkus Pargmann 11273bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap) 11281d471cd1SJavier Martin { 11291d471cd1SJavier Martin struct aic32x4_priv *aic32x4; 11303bcfd222SJeremy McDermond struct aic32x4_pdata *pdata = dev->platform_data; 11313bcfd222SJeremy McDermond struct device_node *np = dev->of_node; 11321d471cd1SJavier Martin int ret; 11331d471cd1SJavier Martin 11343bcfd222SJeremy McDermond if (IS_ERR(regmap)) 11353bcfd222SJeremy McDermond return PTR_ERR(regmap); 11363bcfd222SJeremy McDermond 11373bcfd222SJeremy McDermond aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1138658ecf77SAxel Lin GFP_KERNEL); 11391d471cd1SJavier Martin if (aic32x4 == NULL) 11401d471cd1SJavier Martin return -ENOMEM; 11411d471cd1SJavier Martin 1142b9045b9cSDan Murphy aic32x4->dev = dev; 11433bcfd222SJeremy McDermond dev_set_drvdata(dev, aic32x4); 11441d471cd1SJavier Martin 11451d471cd1SJavier Martin if (pdata) { 11461d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg; 11471d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs; 11481d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing; 11491858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio; 11504d16700dSMarkus Pargmann } else if (np) { 11514d16700dSMarkus Pargmann ret = aic32x4_parse_dt(aic32x4, np); 11524d16700dSMarkus Pargmann if (ret) { 11533bcfd222SJeremy McDermond dev_err(dev, "Failed to parse DT node\n"); 11544d16700dSMarkus Pargmann return ret; 11554d16700dSMarkus Pargmann } 11561d471cd1SJavier Martin } else { 11571d471cd1SJavier Martin aic32x4->power_cfg = 0; 11581d471cd1SJavier Martin aic32x4->swapdacs = false; 11591d471cd1SJavier Martin aic32x4->micpga_routing = 0; 11601858fe97SJavier Martin aic32x4->rstn_gpio = -1; 11611d471cd1SJavier Martin } 11621d471cd1SJavier Martin 11633bcfd222SJeremy McDermond aic32x4->mclk = devm_clk_get(dev, "mclk"); 116498b664e2SMarkus Pargmann if (IS_ERR(aic32x4->mclk)) { 11653bcfd222SJeremy McDermond dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n"); 116698b664e2SMarkus Pargmann return PTR_ERR(aic32x4->mclk); 116798b664e2SMarkus Pargmann } 116898b664e2SMarkus Pargmann 1169a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) { 11703bcfd222SJeremy McDermond ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1171752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1172752b7764SMark Brown if (ret != 0) 1173752b7764SMark Brown return ret; 1174752b7764SMark Brown } 1175752b7764SMark Brown 11763bcfd222SJeremy McDermond ret = aic32x4_setup_regulators(dev, aic32x4); 1177239b669bSMarkus Pargmann if (ret) { 11783bcfd222SJeremy McDermond dev_err(dev, "Failed to setup regulators\n"); 1179239b669bSMarkus Pargmann return ret; 1180239b669bSMarkus Pargmann } 1181239b669bSMarkus Pargmann 11823bcfd222SJeremy McDermond ret = snd_soc_register_codec(dev, 11831d471cd1SJavier Martin &soc_codec_dev_aic32x4, &aic32x4_dai, 1); 1184239b669bSMarkus Pargmann if (ret) { 11853bcfd222SJeremy McDermond dev_err(dev, "Failed to register codec\n"); 1186239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 11871d471cd1SJavier Martin return ret; 11881d471cd1SJavier Martin } 11891d471cd1SJavier Martin 1190239b669bSMarkus Pargmann return 0; 1191239b669bSMarkus Pargmann } 11923bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_probe); 1193239b669bSMarkus Pargmann 11943bcfd222SJeremy McDermond int aic32x4_remove(struct device *dev) 11951d471cd1SJavier Martin { 11963bcfd222SJeremy McDermond struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1197239b669bSMarkus Pargmann 1198239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4); 1199239b669bSMarkus Pargmann 12003bcfd222SJeremy McDermond snd_soc_unregister_codec(dev); 12013bcfd222SJeremy McDermond 12021d471cd1SJavier Martin return 0; 12031d471cd1SJavier Martin } 12043bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_remove); 12051d471cd1SJavier Martin 12061d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 12071d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 12081d471cd1SJavier Martin MODULE_LICENSE("GPL"); 1209