116216333SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
21d471cd1SJavier Martin /*
31d471cd1SJavier Martin * linux/sound/soc/codecs/tlv320aic32x4.c
41d471cd1SJavier Martin *
51d471cd1SJavier Martin * Copyright 2011 Vista Silicon S.L.
61d471cd1SJavier Martin *
71d471cd1SJavier Martin * Author: Javier Martin <javier.martin@vista-silicon.com>
81d471cd1SJavier Martin *
91d471cd1SJavier Martin * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
101d471cd1SJavier Martin */
111d471cd1SJavier Martin
121d471cd1SJavier Martin #include <linux/module.h>
131d471cd1SJavier Martin #include <linux/moduleparam.h>
141d471cd1SJavier Martin #include <linux/init.h>
151d471cd1SJavier Martin #include <linux/delay.h>
161d471cd1SJavier Martin #include <linux/pm.h>
171858fe97SJavier Martin #include <linux/gpio.h>
184d16700dSMarkus Pargmann #include <linux/of_gpio.h>
191d471cd1SJavier Martin #include <linux/cdev.h>
201d471cd1SJavier Martin #include <linux/slab.h>
2198b664e2SMarkus Pargmann #include <linux/clk.h>
22514b044cSAnnaliese McDermond #include <linux/of_clk.h>
23239b669bSMarkus Pargmann #include <linux/regulator/consumer.h>
241d471cd1SJavier Martin
251d471cd1SJavier Martin #include <sound/tlv320aic32x4.h>
261d471cd1SJavier Martin #include <sound/core.h>
271d471cd1SJavier Martin #include <sound/pcm.h>
281d471cd1SJavier Martin #include <sound/pcm_params.h>
291d471cd1SJavier Martin #include <sound/soc.h>
301d471cd1SJavier Martin #include <sound/soc-dapm.h>
311d471cd1SJavier Martin #include <sound/initval.h>
321d471cd1SJavier Martin #include <sound/tlv.h>
331d471cd1SJavier Martin
341d471cd1SJavier Martin #include "tlv320aic32x4.h"
351d471cd1SJavier Martin
361d471cd1SJavier Martin struct aic32x4_priv {
374d208ca4SMark Brown struct regmap *regmap;
381d471cd1SJavier Martin u32 power_cfg;
391d471cd1SJavier Martin u32 micpga_routing;
401d471cd1SJavier Martin bool swapdacs;
411858fe97SJavier Martin int rstn_gpio;
42514b044cSAnnaliese McDermond const char *mclk_name;
43239b669bSMarkus Pargmann
44239b669bSMarkus Pargmann struct regulator *supply_ldo;
45239b669bSMarkus Pargmann struct regulator *supply_iov;
46239b669bSMarkus Pargmann struct regulator *supply_dv;
47239b669bSMarkus Pargmann struct regulator *supply_av;
48b9045b9cSDan Murphy
49b9045b9cSDan Murphy struct aic32x4_setup_data *setup;
50b9045b9cSDan Murphy struct device *dev;
51688d47cdSClaudius Heine enum aic32x4_type type;
52b4b5f29aSPhilipp Zabel
53b4b5f29aSPhilipp Zabel unsigned int fmt;
54b9045b9cSDan Murphy };
55b9045b9cSDan Murphy
aic32x4_reset_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)569d4befffSMichael Sit Wei Hong static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
579d4befffSMichael Sit Wei Hong struct snd_kcontrol *kcontrol, int event)
589d4befffSMichael Sit Wei Hong {
599d4befffSMichael Sit Wei Hong struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
609d4befffSMichael Sit Wei Hong u32 adc_reg;
619d4befffSMichael Sit Wei Hong
629d4befffSMichael Sit Wei Hong /*
639d4befffSMichael Sit Wei Hong * Workaround: the datasheet does not mention a required programming
649d4befffSMichael Sit Wei Hong * sequence but experiments show the ADC needs to be reset after each
659d4befffSMichael Sit Wei Hong * capture to avoid audible artifacts.
669d4befffSMichael Sit Wei Hong */
679d4befffSMichael Sit Wei Hong switch (event) {
689d4befffSMichael Sit Wei Hong case SND_SOC_DAPM_POST_PMD:
699d4befffSMichael Sit Wei Hong adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
709d4befffSMichael Sit Wei Hong snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
719d4befffSMichael Sit Wei Hong AIC32X4_LADC_EN | AIC32X4_RADC_EN);
729d4befffSMichael Sit Wei Hong snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
739d4befffSMichael Sit Wei Hong break;
749d4befffSMichael Sit Wei Hong }
759d4befffSMichael Sit Wei Hong return 0;
769d4befffSMichael Sit Wei Hong };
779d4befffSMichael Sit Wei Hong
mic_bias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)7804d979d7Sb-ak static int mic_bias_event(struct snd_soc_dapm_widget *w,
7904d979d7Sb-ak struct snd_kcontrol *kcontrol, int event)
8004d979d7Sb-ak {
8104d979d7Sb-ak struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
8204d979d7Sb-ak
8304d979d7Sb-ak switch (event) {
8404d979d7Sb-ak case SND_SOC_DAPM_POST_PMU:
8504d979d7Sb-ak /* Change Mic Bias Registor */
8604d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
8704d979d7Sb-ak AIC32x4_MICBIAS_MASK,
8804d979d7Sb-ak AIC32X4_MICBIAS_LDOIN |
8904d979d7Sb-ak AIC32X4_MICBIAS_2075V);
9004d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
9104d979d7Sb-ak break;
9204d979d7Sb-ak case SND_SOC_DAPM_PRE_PMD:
9304d979d7Sb-ak snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
9404d979d7Sb-ak AIC32x4_MICBIAS_MASK, 0);
9504d979d7Sb-ak printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
9604d979d7Sb-ak __func__);
9704d979d7Sb-ak break;
9804d979d7Sb-ak }
9904d979d7Sb-ak
10004d979d7Sb-ak return 0;
10104d979d7Sb-ak }
10204d979d7Sb-ak
10304d979d7Sb-ak
aic32x4_get_mfp1_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)104b9045b9cSDan Murphy static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
105b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol)
106b9045b9cSDan Murphy {
107b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
108b9045b9cSDan Murphy u8 val;
109b9045b9cSDan Murphy
110e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_DINCTL);
111b9045b9cSDan Murphy
112b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01);
113b9045b9cSDan Murphy
114b9045b9cSDan Murphy return 0;
115b9045b9cSDan Murphy };
116b9045b9cSDan Murphy
aic32x4_set_mfp2_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)117b9045b9cSDan Murphy static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
118b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol)
119b9045b9cSDan Murphy {
120b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
121b9045b9cSDan Murphy u8 val;
122b9045b9cSDan Murphy u8 gpio_check;
123b9045b9cSDan Murphy
124e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
125b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
126b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
127b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
128b9045b9cSDan Murphy __func__);
129b9045b9cSDan Murphy return -EINVAL;
130b9045b9cSDan Murphy }
131b9045b9cSDan Murphy
132b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
133b9045b9cSDan Murphy return 0;
134b9045b9cSDan Murphy
135b9045b9cSDan Murphy if (ucontrol->value.integer.value[0])
136b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0];
137b9045b9cSDan Murphy else
138b9045b9cSDan Murphy val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
139b9045b9cSDan Murphy
140b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
141b9045b9cSDan Murphy
142b9045b9cSDan Murphy return 0;
143b9045b9cSDan Murphy };
144b9045b9cSDan Murphy
aic32x4_get_mfp3_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)145b9045b9cSDan Murphy static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
146b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol)
147b9045b9cSDan Murphy {
148b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
149b9045b9cSDan Murphy u8 val;
150b9045b9cSDan Murphy
151e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
152b9045b9cSDan Murphy
153b9045b9cSDan Murphy ucontrol->value.integer.value[0] = (val & 0x01);
154b9045b9cSDan Murphy
155b9045b9cSDan Murphy return 0;
156b9045b9cSDan Murphy };
157b9045b9cSDan Murphy
aic32x4_set_mfp4_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)158b9045b9cSDan Murphy static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
159b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol)
160b9045b9cSDan Murphy {
161b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
162b9045b9cSDan Murphy u8 val;
163b9045b9cSDan Murphy u8 gpio_check;
164b9045b9cSDan Murphy
165e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_MISOCTL);
166b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
167b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
168b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
169b9045b9cSDan Murphy __func__);
170b9045b9cSDan Murphy return -EINVAL;
171b9045b9cSDan Murphy }
172b9045b9cSDan Murphy
173b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
174b9045b9cSDan Murphy return 0;
175b9045b9cSDan Murphy
176b9045b9cSDan Murphy if (ucontrol->value.integer.value[0])
177b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0];
178b9045b9cSDan Murphy else
179b9045b9cSDan Murphy val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
180b9045b9cSDan Murphy
181b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL, val);
182b9045b9cSDan Murphy
183b9045b9cSDan Murphy return 0;
184b9045b9cSDan Murphy };
185b9045b9cSDan Murphy
aic32x4_get_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)186b9045b9cSDan Murphy static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
187b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol)
188b9045b9cSDan Murphy {
189b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
190b9045b9cSDan Murphy u8 val;
191b9045b9cSDan Murphy
192e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
193b9045b9cSDan Murphy ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
194b9045b9cSDan Murphy
195b9045b9cSDan Murphy return 0;
196b9045b9cSDan Murphy };
197b9045b9cSDan Murphy
aic32x4_set_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)198b9045b9cSDan Murphy static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
199b9045b9cSDan Murphy struct snd_ctl_elem_value *ucontrol)
200b9045b9cSDan Murphy {
201b154dc5dSKuninori Morimoto struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
202b9045b9cSDan Murphy u8 val;
203b9045b9cSDan Murphy u8 gpio_check;
204b9045b9cSDan Murphy
205e348cf54SKuninori Morimoto val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
206b9045b9cSDan Murphy gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
207b9045b9cSDan Murphy if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
208b9045b9cSDan Murphy printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
209b9045b9cSDan Murphy __func__);
210b9045b9cSDan Murphy return -EINVAL;
211b9045b9cSDan Murphy }
212b9045b9cSDan Murphy
213b9045b9cSDan Murphy if (ucontrol->value.integer.value[0] == (val & 0x1))
214b9045b9cSDan Murphy return 0;
215b9045b9cSDan Murphy
216b9045b9cSDan Murphy if (ucontrol->value.integer.value[0])
217b9045b9cSDan Murphy val |= ucontrol->value.integer.value[0];
218b9045b9cSDan Murphy else
219b9045b9cSDan Murphy val &= 0xfe;
220b9045b9cSDan Murphy
221b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
222b9045b9cSDan Murphy
223b9045b9cSDan Murphy return 0;
224b9045b9cSDan Murphy };
225b9045b9cSDan Murphy
226b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp1[] = {
227b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
228b9045b9cSDan Murphy };
229b9045b9cSDan Murphy
230b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp2[] = {
231b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
232b9045b9cSDan Murphy };
233b9045b9cSDan Murphy
234b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp3[] = {
235b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
236b9045b9cSDan Murphy };
237b9045b9cSDan Murphy
238b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp4[] = {
239b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
240b9045b9cSDan Murphy };
241b9045b9cSDan Murphy
242b9045b9cSDan Murphy static const struct snd_kcontrol_new aic32x4_mfp5[] = {
243b9045b9cSDan Murphy SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
244b9045b9cSDan Murphy aic32x4_set_mfp5_gpio),
2451d471cd1SJavier Martin };
2461d471cd1SJavier Martin
2471d471cd1SJavier Martin /* 0dB min, 0.5dB steps */
2481d471cd1SJavier Martin static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
249c671e79dSMarkus Pargmann /* -63.5dB min, 0.5dB steps */
250c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
251c671e79dSMarkus Pargmann /* -6dB min, 1dB steps */
252c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
253c671e79dSMarkus Pargmann /* -12dB min, 0.5dB steps */
254c671e79dSMarkus Pargmann static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
2552169d6a0SMarek Vasut /* -6dB min, 1dB steps */
2562169d6a0SMarek Vasut static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
257b4525b61SClaudius Heine static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
258b4525b61SClaudius Heine
25944ceee84SAnnaliese McDermond static const char * const lo_cm_text[] = {
26044ceee84SAnnaliese McDermond "Full Chip", "1.65V",
26144ceee84SAnnaliese McDermond };
26244ceee84SAnnaliese McDermond
26344ceee84SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
26444ceee84SAnnaliese McDermond
265d3e6e374SAnnaliese McDermond static const char * const ptm_text[] = {
266d3e6e374SAnnaliese McDermond "P3", "P2", "P1",
267d3e6e374SAnnaliese McDermond };
268d3e6e374SAnnaliese McDermond
269d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
270d3e6e374SAnnaliese McDermond static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
271d3e6e374SAnnaliese McDermond
2721d471cd1SJavier Martin static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
273c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
274c671e79dSMarkus Pargmann AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
275d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
276d3e6e374SAnnaliese McDermond SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
277c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
278c671e79dSMarkus Pargmann AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
279c671e79dSMarkus Pargmann tlv_driver_gain),
280c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
281c671e79dSMarkus Pargmann AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
282c671e79dSMarkus Pargmann tlv_driver_gain),
2831d471cd1SJavier Martin SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
2841d471cd1SJavier Martin AIC32X4_HPRGAIN, 6, 0x01, 1),
2851d471cd1SJavier Martin SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
2861d471cd1SJavier Martin AIC32X4_LORGAIN, 6, 0x01, 1),
28744ceee84SAnnaliese McDermond SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
2881d471cd1SJavier Martin SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
2891d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 7, 0x01, 1),
2901d471cd1SJavier Martin
2911d471cd1SJavier Martin SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
2921d471cd1SJavier Martin SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
2931d471cd1SJavier Martin
294c671e79dSMarkus Pargmann SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
295c671e79dSMarkus Pargmann AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
2961d471cd1SJavier Martin SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
2971d471cd1SJavier Martin AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
2981d471cd1SJavier Martin
2991d471cd1SJavier Martin SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
3001d471cd1SJavier Martin
3011d471cd1SJavier Martin SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
3021d471cd1SJavier Martin SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
3031d471cd1SJavier Martin SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
3041d471cd1SJavier Martin 4, 0x07, 0),
3051d471cd1SJavier Martin SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
3061d471cd1SJavier Martin 0, 0x03, 0),
3071d471cd1SJavier Martin SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
3081d471cd1SJavier Martin 6, 0x03, 0),
3091d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
3101d471cd1SJavier Martin 1, 0x1F, 0),
3111d471cd1SJavier Martin SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
3121d471cd1SJavier Martin 0, 0x7F, 0),
3131d471cd1SJavier Martin SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
3141d471cd1SJavier Martin 3, 0x1F, 0),
3151d471cd1SJavier Martin SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
3161d471cd1SJavier Martin 3, 0x1F, 0),
3171d471cd1SJavier Martin SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
3181d471cd1SJavier Martin 0, 0x1F, 0),
3191d471cd1SJavier Martin SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
3201d471cd1SJavier Martin 0, 0x0F, 0),
3211d471cd1SJavier Martin };
3221d471cd1SJavier Martin
3231d471cd1SJavier Martin static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
3241d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
3251d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
3261d471cd1SJavier Martin };
3271d471cd1SJavier Martin
3281d471cd1SJavier Martin static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
3291d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
3301d471cd1SJavier Martin SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
3311d471cd1SJavier Martin };
3321d471cd1SJavier Martin
3331d471cd1SJavier Martin static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
3341d471cd1SJavier Martin SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
3351d471cd1SJavier Martin };
3361d471cd1SJavier Martin
3371d471cd1SJavier Martin static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
3381d471cd1SJavier Martin SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
3391d471cd1SJavier Martin };
3401d471cd1SJavier Martin
34120d2cecbSJeremy McDermond static const char * const resistor_text[] = {
34220d2cecbSJeremy McDermond "Off", "10 kOhm", "20 kOhm", "40 kOhm",
3431d471cd1SJavier Martin };
3441d471cd1SJavier Martin
3452213fc35SJeremy McDermond /* Left mixer pins */
3462213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
3472213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
3482213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
3492213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
35020d2cecbSJeremy McDermond
3512213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
3522213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
3532213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
3542213fc35SJeremy McDermond
3552213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
3562213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
3572213fc35SJeremy McDermond };
3582213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
3592213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
3602213fc35SJeremy McDermond };
3612213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
3622213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
3632213fc35SJeremy McDermond };
3642213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
3652213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
3662213fc35SJeremy McDermond };
3672213fc35SJeremy McDermond static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
3682213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
3692213fc35SJeremy McDermond };
3702213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
3712213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
3722213fc35SJeremy McDermond };
3732213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
3742213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
37520d2cecbSJeremy McDermond };
37620d2cecbSJeremy McDermond
3772213fc35SJeremy McDermond /* Right mixer pins */
3782213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
3792213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
3802213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
3812213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
3822213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
3832213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
3842213fc35SJeremy McDermond static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
38520d2cecbSJeremy McDermond
3862213fc35SJeremy McDermond static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
3872213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
3882213fc35SJeremy McDermond };
3892213fc35SJeremy McDermond static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
3902213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
3912213fc35SJeremy McDermond };
3922213fc35SJeremy McDermond static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
3932213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
3942213fc35SJeremy McDermond };
3952213fc35SJeremy McDermond static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
3962213fc35SJeremy McDermond SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
3972213fc35SJeremy McDermond };
3982213fc35SJeremy McDermond static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
3992213fc35SJeremy McDermond SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
4002213fc35SJeremy McDermond };
4012213fc35SJeremy McDermond static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
4022213fc35SJeremy McDermond SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
4032213fc35SJeremy McDermond };
4042213fc35SJeremy McDermond static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
4052213fc35SJeremy McDermond SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
4061d471cd1SJavier Martin };
4071d471cd1SJavier Martin
4081d471cd1SJavier Martin static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
4091d471cd1SJavier Martin SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
4101d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
4111d471cd1SJavier Martin &hpl_output_mixer_controls[0],
4121d471cd1SJavier Martin ARRAY_SIZE(hpl_output_mixer_controls)),
4131d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
4141d471cd1SJavier Martin
4151d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
4161d471cd1SJavier Martin &lol_output_mixer_controls[0],
4171d471cd1SJavier Martin ARRAY_SIZE(lol_output_mixer_controls)),
4181d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
4191d471cd1SJavier Martin
4201d471cd1SJavier Martin SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
4211d471cd1SJavier Martin SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
4221d471cd1SJavier Martin &hpr_output_mixer_controls[0],
4231d471cd1SJavier Martin ARRAY_SIZE(hpr_output_mixer_controls)),
4241d471cd1SJavier Martin SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
4251d471cd1SJavier Martin SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
4261d471cd1SJavier Martin &lor_output_mixer_controls[0],
4271d471cd1SJavier Martin ARRAY_SIZE(lor_output_mixer_controls)),
4281d471cd1SJavier Martin SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
4292213fc35SJeremy McDermond
4301d471cd1SJavier Martin SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
4312213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4322213fc35SJeremy McDermond in1r_to_rmixer_controls),
4332213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4342213fc35SJeremy McDermond in2r_to_rmixer_controls),
4352213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4362213fc35SJeremy McDermond in3r_to_rmixer_controls),
4372213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4382213fc35SJeremy McDermond in2l_to_rmixer_controls),
4392213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
4402213fc35SJeremy McDermond cmr_to_rmixer_controls),
4412213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
4422213fc35SJeremy McDermond in1l_to_rmixer_controls),
4432213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
4442213fc35SJeremy McDermond in3l_to_rmixer_controls),
4452213fc35SJeremy McDermond
4462213fc35SJeremy McDermond SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
4472213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4482213fc35SJeremy McDermond in1l_to_lmixer_controls),
4492213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4502213fc35SJeremy McDermond in2l_to_lmixer_controls),
4512213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4522213fc35SJeremy McDermond in3l_to_lmixer_controls),
4532213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
4542213fc35SJeremy McDermond in1r_to_lmixer_controls),
4552213fc35SJeremy McDermond SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
4562213fc35SJeremy McDermond cml_to_lmixer_controls),
4572213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
4582213fc35SJeremy McDermond in2r_to_lmixer_controls),
4592213fc35SJeremy McDermond SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
4602213fc35SJeremy McDermond in3r_to_lmixer_controls),
4612213fc35SJeremy McDermond
46204d979d7Sb-ak SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
46304d979d7Sb-ak SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
46404d979d7Sb-ak
4659d4befffSMichael Sit Wei Hong SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
4661d471cd1SJavier Martin
4671d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPL"),
4681d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("HPR"),
4691d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOL"),
4701d471cd1SJavier Martin SND_SOC_DAPM_OUTPUT("LOR"),
4711d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_L"),
4721d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN1_R"),
4731d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_L"),
4741d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN2_R"),
4751d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_L"),
4761d471cd1SJavier Martin SND_SOC_DAPM_INPUT("IN3_R"),
477c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_L"),
478c63adb28SAnnaliese McDermond SND_SOC_DAPM_INPUT("CM_R"),
4791d471cd1SJavier Martin };
4801d471cd1SJavier Martin
4811d471cd1SJavier Martin static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
4821d471cd1SJavier Martin /* Left Output */
4831d471cd1SJavier Martin {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
4841d471cd1SJavier Martin {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
4851d471cd1SJavier Martin
4861d471cd1SJavier Martin {"HPL Power", NULL, "HPL Output Mixer"},
4871d471cd1SJavier Martin {"HPL", NULL, "HPL Power"},
4881d471cd1SJavier Martin
4891d471cd1SJavier Martin {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
4901d471cd1SJavier Martin
4911d471cd1SJavier Martin {"LOL Power", NULL, "LOL Output Mixer"},
4921d471cd1SJavier Martin {"LOL", NULL, "LOL Power"},
4931d471cd1SJavier Martin
4941d471cd1SJavier Martin /* Right Output */
4951d471cd1SJavier Martin {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
4961d471cd1SJavier Martin {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
4971d471cd1SJavier Martin
4981d471cd1SJavier Martin {"HPR Power", NULL, "HPR Output Mixer"},
4991d471cd1SJavier Martin {"HPR", NULL, "HPR Power"},
5001d471cd1SJavier Martin
5011d471cd1SJavier Martin {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
5021d471cd1SJavier Martin
5031d471cd1SJavier Martin {"LOR Power", NULL, "LOR Output Mixer"},
5041d471cd1SJavier Martin {"LOR", NULL, "LOR Power"},
5051d471cd1SJavier Martin
5061d471cd1SJavier Martin /* Right Input */
5072213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
5082213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
5092213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
5102213fc35SJeremy McDermond {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
5111d471cd1SJavier Martin
5122213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
5132213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
5142213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
5152213fc35SJeremy McDermond {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
5162213fc35SJeremy McDermond
5172213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
5182213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
5192213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
5202213fc35SJeremy McDermond {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
5212213fc35SJeremy McDermond
5222213fc35SJeremy McDermond {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
5232213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
5242213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
5252213fc35SJeremy McDermond {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
5262213fc35SJeremy McDermond
5272213fc35SJeremy McDermond {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
5282213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
5292213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
5302213fc35SJeremy McDermond {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
5312213fc35SJeremy McDermond
5322213fc35SJeremy McDermond {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
5332213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
5342213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
5352213fc35SJeremy McDermond {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
5362213fc35SJeremy McDermond
5372213fc35SJeremy McDermond {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
5382213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
5392213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
5402213fc35SJeremy McDermond {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
5412213fc35SJeremy McDermond
5422213fc35SJeremy McDermond /* Left Input */
5432213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
5442213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
5452213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
5462213fc35SJeremy McDermond {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
5472213fc35SJeremy McDermond
5482213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
5492213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
5502213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
5512213fc35SJeremy McDermond {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
5522213fc35SJeremy McDermond
5532213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
5542213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
5552213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
5562213fc35SJeremy McDermond {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
5572213fc35SJeremy McDermond
5582213fc35SJeremy McDermond {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
5592213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
5602213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
5612213fc35SJeremy McDermond {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
5622213fc35SJeremy McDermond
5632213fc35SJeremy McDermond {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
5642213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
5652213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
5662213fc35SJeremy McDermond {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
5672213fc35SJeremy McDermond
5682213fc35SJeremy McDermond {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
5692213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
5702213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
5712213fc35SJeremy McDermond {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
5722213fc35SJeremy McDermond
5732213fc35SJeremy McDermond {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
5742213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
5752213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
5762213fc35SJeremy McDermond {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
5771d471cd1SJavier Martin };
5781d471cd1SJavier Martin
5794d208ca4SMark Brown static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
5801d471cd1SJavier Martin {
5814d208ca4SMark Brown .selector_reg = 0,
5824d208ca4SMark Brown .selector_mask = 0xff,
5834d208ca4SMark Brown .window_start = 0,
5844d208ca4SMark Brown .window_len = 128,
585e8e08c52SMarkus Pargmann .range_min = 0,
58629654ed8SAnnaliese McDermond .range_max = AIC32X4_REFPOWERUP,
5874d208ca4SMark Brown },
5884d208ca4SMark Brown };
5891d471cd1SJavier Martin
5903bcfd222SJeremy McDermond const struct regmap_config aic32x4_regmap_config = {
59129654ed8SAnnaliese McDermond .max_register = AIC32X4_REFPOWERUP,
5924d208ca4SMark Brown .ranges = aic32x4_regmap_pages,
5934d208ca4SMark Brown .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
5944d208ca4SMark Brown };
5953bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_regmap_config);
5961d471cd1SJavier Martin
aic32x4_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)5971d471cd1SJavier Martin static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
5981d471cd1SJavier Martin int clk_id, unsigned int freq, int dir)
5991d471cd1SJavier Martin {
600b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component;
601aa6a60f7SAnnaliese McDermond struct clk *mclk;
602aa6a60f7SAnnaliese McDermond struct clk *pll;
6031d471cd1SJavier Martin
604aa6a60f7SAnnaliese McDermond pll = devm_clk_get(component->dev, "pll");
6051092b097SChuhong Yuan if (IS_ERR(pll))
6061092b097SChuhong Yuan return PTR_ERR(pll);
6071092b097SChuhong Yuan
608aa6a60f7SAnnaliese McDermond mclk = clk_get_parent(pll);
609aa6a60f7SAnnaliese McDermond
610aa6a60f7SAnnaliese McDermond return clk_set_rate(mclk, freq);
6111d471cd1SJavier Martin }
6121d471cd1SJavier Martin
aic32x4_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)6131d471cd1SJavier Martin static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
6141d471cd1SJavier Martin {
615b154dc5dSKuninori Morimoto struct snd_soc_component *component = codec_dai->component;
616b4b5f29aSPhilipp Zabel struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
61760fb4be5SAndrew F. Davis u8 iface_reg_1 = 0;
61860fb4be5SAndrew F. Davis u8 iface_reg_2 = 0;
61960fb4be5SAndrew F. Davis u8 iface_reg_3 = 0;
6201d471cd1SJavier Martin
6210cc5a137SMark Brown switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
6220cc5a137SMark Brown case SND_SOC_DAIFMT_CBP_CFP:
6231d471cd1SJavier Martin iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
6241d471cd1SJavier Martin break;
6250cc5a137SMark Brown case SND_SOC_DAIFMT_CBC_CFC:
6261d471cd1SJavier Martin break;
6271d471cd1SJavier Martin default:
6280cc5a137SMark Brown printk(KERN_ERR "aic32x4: invalid clock provider\n");
6291d471cd1SJavier Martin return -EINVAL;
6301d471cd1SJavier Martin }
6311d471cd1SJavier Martin
6321d471cd1SJavier Martin switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
6331d471cd1SJavier Martin case SND_SOC_DAIFMT_I2S:
6341d471cd1SJavier Martin break;
6351d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_A:
6364483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE <<
6374483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT);
63860fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
6391d471cd1SJavier Martin iface_reg_2 = 0x01; /* add offset 1 */
6401d471cd1SJavier Martin break;
6411d471cd1SJavier Martin case SND_SOC_DAIFMT_DSP_B:
6424483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_DSP_MODE <<
6434483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT);
64460fb4be5SAndrew F. Davis iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
6451d471cd1SJavier Martin break;
6461d471cd1SJavier Martin case SND_SOC_DAIFMT_RIGHT_J:
6474483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
6484483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT);
6491d471cd1SJavier Martin break;
6501d471cd1SJavier Martin case SND_SOC_DAIFMT_LEFT_J:
6514483521dSAndrew F. Davis iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
6524483521dSAndrew F. Davis AIC32X4_IFACE1_DATATYPE_SHIFT);
6531d471cd1SJavier Martin break;
6541d471cd1SJavier Martin default:
6551d471cd1SJavier Martin printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
6561d471cd1SJavier Martin return -EINVAL;
6571d471cd1SJavier Martin }
6581d471cd1SJavier Martin
659b4b5f29aSPhilipp Zabel aic32x4->fmt = fmt;
660b4b5f29aSPhilipp Zabel
661b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1,
66260fb4be5SAndrew F. Davis AIC32X4_IFACE1_DATATYPE_MASK |
66360fb4be5SAndrew F. Davis AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
664b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE2,
66560fb4be5SAndrew F. Davis AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
666b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE3,
66760fb4be5SAndrew F. Davis AIC32X4_BCLKINV_MASK, iface_reg_3);
66860fb4be5SAndrew F. Davis
6691d471cd1SJavier Martin return 0;
6701d471cd1SJavier Martin }
6711d471cd1SJavier Martin
aic32x4_set_aosr(struct snd_soc_component * component,u8 aosr)672fbafbf65SAnnaliese McDermond static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
673fbafbf65SAnnaliese McDermond {
674fbafbf65SAnnaliese McDermond return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
675fbafbf65SAnnaliese McDermond }
676fbafbf65SAnnaliese McDermond
aic32x4_set_dosr(struct snd_soc_component * component,u16 dosr)677fbafbf65SAnnaliese McDermond static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
678fbafbf65SAnnaliese McDermond {
679fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
680fbafbf65SAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DOSRLSB,
681fbafbf65SAnnaliese McDermond (dosr & 0xff));
682fbafbf65SAnnaliese McDermond
683fbafbf65SAnnaliese McDermond return 0;
684fbafbf65SAnnaliese McDermond }
685fbafbf65SAnnaliese McDermond
aic32x4_set_processing_blocks(struct snd_soc_component * component,u8 r_block,u8 p_block)686c95e3a4bSAnnaliese McDermond static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
687c95e3a4bSAnnaliese McDermond u8 r_block, u8 p_block)
688c95e3a4bSAnnaliese McDermond {
689090c57daSMarek Vasut struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
690090c57daSMarek Vasut
691090c57daSMarek Vasut if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
692090c57daSMarek Vasut if (r_block || p_block > 3)
693090c57daSMarek Vasut return -EINVAL;
694090c57daSMarek Vasut
695090c57daSMarek Vasut snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
696090c57daSMarek Vasut } else { /* AIC32x4 */
697c95e3a4bSAnnaliese McDermond if (r_block > 18 || p_block > 25)
698c95e3a4bSAnnaliese McDermond return -EINVAL;
699c95e3a4bSAnnaliese McDermond
700c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
701c95e3a4bSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
702090c57daSMarek Vasut }
703c95e3a4bSAnnaliese McDermond
704c95e3a4bSAnnaliese McDermond return 0;
705c95e3a4bSAnnaliese McDermond }
706c95e3a4bSAnnaliese McDermond
aic32x4_setup_clocks(struct snd_soc_component * component,unsigned int sample_rate,unsigned int channels,unsigned int bit_depth)707bf31cbfbSAnnaliese McDermond static int aic32x4_setup_clocks(struct snd_soc_component *component,
70897ee967eSMark Brown unsigned int sample_rate, unsigned int channels,
709dcd79364SMichael Sit Wei Hong unsigned int bit_depth)
7101d471cd1SJavier Martin {
711090c57daSMarek Vasut struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
71296c3bb00SAnnaliese McDermond u8 aosr;
71396c3bb00SAnnaliese McDermond u16 dosr;
71496c3bb00SAnnaliese McDermond u8 adc_resource_class, dac_resource_class;
71596c3bb00SAnnaliese McDermond u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
71696c3bb00SAnnaliese McDermond u8 dosr_increment;
71796c3bb00SAnnaliese McDermond u16 max_dosr, min_dosr;
71883b4f50cSYueHaibing unsigned long adc_clock_rate, dac_clock_rate;
719514b044cSAnnaliese McDermond int ret;
720514b044cSAnnaliese McDermond
721ea9df984SColin Ian King static struct clk_bulk_data clocks[] = {
722514b044cSAnnaliese McDermond { .id = "pll" },
723a51b5006SAnnaliese McDermond { .id = "nadc" },
724a51b5006SAnnaliese McDermond { .id = "madc" },
725a51b5006SAnnaliese McDermond { .id = "ndac" },
726a51b5006SAnnaliese McDermond { .id = "mdac" },
7279b484124SAnnaliese McDermond { .id = "bdiv" },
728514b044cSAnnaliese McDermond };
729514b044cSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
730514b044cSAnnaliese McDermond if (ret)
731514b044cSAnnaliese McDermond return ret;
732514b044cSAnnaliese McDermond
73396c3bb00SAnnaliese McDermond if (sample_rate <= 48000) {
73496c3bb00SAnnaliese McDermond aosr = 128;
73596c3bb00SAnnaliese McDermond adc_resource_class = 6;
73696c3bb00SAnnaliese McDermond dac_resource_class = 8;
73796c3bb00SAnnaliese McDermond dosr_increment = 8;
738090c57daSMarek Vasut if (aic32x4->type == AIC32X4_TYPE_TAS2505)
739090c57daSMarek Vasut aic32x4_set_processing_blocks(component, 0, 1);
740090c57daSMarek Vasut else
74196c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 1);
74296c3bb00SAnnaliese McDermond } else if (sample_rate <= 96000) {
74396c3bb00SAnnaliese McDermond aosr = 64;
74496c3bb00SAnnaliese McDermond adc_resource_class = 6;
74596c3bb00SAnnaliese McDermond dac_resource_class = 8;
74696c3bb00SAnnaliese McDermond dosr_increment = 4;
747090c57daSMarek Vasut if (aic32x4->type == AIC32X4_TYPE_TAS2505)
748090c57daSMarek Vasut aic32x4_set_processing_blocks(component, 0, 1);
749090c57daSMarek Vasut else
75096c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 1, 9);
75196c3bb00SAnnaliese McDermond } else if (sample_rate == 192000) {
75296c3bb00SAnnaliese McDermond aosr = 32;
75396c3bb00SAnnaliese McDermond adc_resource_class = 3;
75496c3bb00SAnnaliese McDermond dac_resource_class = 4;
75596c3bb00SAnnaliese McDermond dosr_increment = 2;
756090c57daSMarek Vasut if (aic32x4->type == AIC32X4_TYPE_TAS2505)
757090c57daSMarek Vasut aic32x4_set_processing_blocks(component, 0, 1);
758090c57daSMarek Vasut else
75996c3bb00SAnnaliese McDermond aic32x4_set_processing_blocks(component, 13, 19);
76096c3bb00SAnnaliese McDermond } else {
76196c3bb00SAnnaliese McDermond dev_err(component->dev, "Sampling rate not supported\n");
76296c3bb00SAnnaliese McDermond return -EINVAL;
76396c3bb00SAnnaliese McDermond }
764fbafbf65SAnnaliese McDermond
765b4b5f29aSPhilipp Zabel /* PCM over I2S is always 2-channel */
766b4b5f29aSPhilipp Zabel if ((aic32x4->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
767b4b5f29aSPhilipp Zabel channels = 2;
768b4b5f29aSPhilipp Zabel
76996c3bb00SAnnaliese McDermond madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
77096c3bb00SAnnaliese McDermond max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
77196c3bb00SAnnaliese McDermond dosr_increment;
77296c3bb00SAnnaliese McDermond min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
77396c3bb00SAnnaliese McDermond dosr_increment;
77496c3bb00SAnnaliese McDermond max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
775c95e3a4bSAnnaliese McDermond
77696c3bb00SAnnaliese McDermond for (nadc = max_nadc; nadc > 0; --nadc) {
77796c3bb00SAnnaliese McDermond adc_clock_rate = nadc * madc * aosr * sample_rate;
77896c3bb00SAnnaliese McDermond for (dosr = max_dosr; dosr >= min_dosr;
77996c3bb00SAnnaliese McDermond dosr -= dosr_increment) {
78096c3bb00SAnnaliese McDermond min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
78196c3bb00SAnnaliese McDermond max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
78296c3bb00SAnnaliese McDermond (min_mdac * dosr * sample_rate);
78396c3bb00SAnnaliese McDermond for (mdac = min_mdac; mdac <= 128; ++mdac) {
78496c3bb00SAnnaliese McDermond for (ndac = max_ndac; ndac > 0; --ndac) {
78596c3bb00SAnnaliese McDermond dac_clock_rate = ndac * mdac * dosr *
78696c3bb00SAnnaliese McDermond sample_rate;
78796c3bb00SAnnaliese McDermond if (dac_clock_rate == adc_clock_rate) {
78896c3bb00SAnnaliese McDermond if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
78996c3bb00SAnnaliese McDermond continue;
79096c3bb00SAnnaliese McDermond
79196c3bb00SAnnaliese McDermond clk_set_rate(clocks[0].clk,
79296c3bb00SAnnaliese McDermond dac_clock_rate);
79396c3bb00SAnnaliese McDermond
79496c3bb00SAnnaliese McDermond clk_set_rate(clocks[1].clk,
79596c3bb00SAnnaliese McDermond sample_rate * aosr *
79696c3bb00SAnnaliese McDermond madc);
79796c3bb00SAnnaliese McDermond clk_set_rate(clocks[2].clk,
79896c3bb00SAnnaliese McDermond sample_rate * aosr);
79996c3bb00SAnnaliese McDermond aic32x4_set_aosr(component,
80096c3bb00SAnnaliese McDermond aosr);
80196c3bb00SAnnaliese McDermond
80296c3bb00SAnnaliese McDermond clk_set_rate(clocks[3].clk,
80396c3bb00SAnnaliese McDermond sample_rate * dosr *
80496c3bb00SAnnaliese McDermond mdac);
80596c3bb00SAnnaliese McDermond clk_set_rate(clocks[4].clk,
80696c3bb00SAnnaliese McDermond sample_rate * dosr);
80796c3bb00SAnnaliese McDermond aic32x4_set_dosr(component,
80896c3bb00SAnnaliese McDermond dosr);
80996c3bb00SAnnaliese McDermond
81096c3bb00SAnnaliese McDermond clk_set_rate(clocks[5].clk,
81197ee967eSMark Brown sample_rate * channels *
812dcd79364SMichael Sit Wei Hong bit_depth);
81340b37136SMiquel Raynal
814bf31cbfbSAnnaliese McDermond return 0;
815bf31cbfbSAnnaliese McDermond }
81696c3bb00SAnnaliese McDermond }
81796c3bb00SAnnaliese McDermond }
81896c3bb00SAnnaliese McDermond }
81996c3bb00SAnnaliese McDermond }
82096c3bb00SAnnaliese McDermond
82196c3bb00SAnnaliese McDermond dev_err(component->dev,
82296c3bb00SAnnaliese McDermond "Could not set clocks to support sample rate.\n");
82396c3bb00SAnnaliese McDermond return -EINVAL;
82496c3bb00SAnnaliese McDermond }
825bf31cbfbSAnnaliese McDermond
aic32x4_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)826bf31cbfbSAnnaliese McDermond static int aic32x4_hw_params(struct snd_pcm_substream *substream,
827bf31cbfbSAnnaliese McDermond struct snd_pcm_hw_params *params,
828bf31cbfbSAnnaliese McDermond struct snd_soc_dai *dai)
829bf31cbfbSAnnaliese McDermond {
830bf31cbfbSAnnaliese McDermond struct snd_soc_component *component = dai->component;
831bf31cbfbSAnnaliese McDermond struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
832bf31cbfbSAnnaliese McDermond u8 iface1_reg = 0;
833bf31cbfbSAnnaliese McDermond u8 dacsetup_reg = 0;
834bf31cbfbSAnnaliese McDermond
835dcd79364SMichael Sit Wei Hong aic32x4_setup_clocks(component, params_rate(params),
836dcd79364SMichael Sit Wei Hong params_channels(params),
837dcd79364SMichael Sit Wei Hong params_physical_width(params));
838bf31cbfbSAnnaliese McDermond
839dcd79364SMichael Sit Wei Hong switch (params_physical_width(params)) {
840bd8a5711SMark Brown case 16:
84164aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
84277bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT);
8431d471cd1SJavier Martin break;
844bd8a5711SMark Brown case 20:
84564aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
84677bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT);
8471d471cd1SJavier Martin break;
848bd8a5711SMark Brown case 24:
84964aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
85077bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT);
8511d471cd1SJavier Martin break;
852bd8a5711SMark Brown case 32:
85364aab899SAndrew F. Davis iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
85477bdb587SAndrew F. Davis AIC32X4_IFACE1_DATALEN_SHIFT);
8551d471cd1SJavier Martin break;
8561d471cd1SJavier Martin }
857b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_IFACE1,
85864aab899SAndrew F. Davis AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
8591d471cd1SJavier Martin
860b44aa40fSMarkus Pargmann if (params_channels(params) == 1) {
86164aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
862b44aa40fSMarkus Pargmann } else {
863b44aa40fSMarkus Pargmann if (aic32x4->swapdacs)
86464aab899SAndrew F. Davis dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
865b44aa40fSMarkus Pargmann else
86664aab899SAndrew F. Davis dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
867b44aa40fSMarkus Pargmann }
868b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
86964aab899SAndrew F. Davis AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
870b44aa40fSMarkus Pargmann
8711d471cd1SJavier Martin return 0;
8721d471cd1SJavier Martin }
8731d471cd1SJavier Martin
aic32x4_mute(struct snd_soc_dai * dai,int mute,int direction)874960af79dSKuninori Morimoto static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
8751d471cd1SJavier Martin {
876b154dc5dSKuninori Morimoto struct snd_soc_component *component = dai->component;
8771d471cd1SJavier Martin
878b154dc5dSKuninori Morimoto snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
879b7ddd9caSAndrew F. Davis AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
880b7ddd9caSAndrew F. Davis
8811d471cd1SJavier Martin return 0;
8821d471cd1SJavier Martin }
8831d471cd1SJavier Martin
aic32x4_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)884b154dc5dSKuninori Morimoto static int aic32x4_set_bias_level(struct snd_soc_component *component,
8851d471cd1SJavier Martin enum snd_soc_bias_level level)
8861d471cd1SJavier Martin {
88798b664e2SMarkus Pargmann int ret;
88898b664e2SMarkus Pargmann
889ea9df984SColin Ian King static struct clk_bulk_data clocks[] = {
890d25970b5SAnnaliese McDermond { .id = "madc" },
891d25970b5SAnnaliese McDermond { .id = "mdac" },
892d25970b5SAnnaliese McDermond { .id = "bdiv" },
893d25970b5SAnnaliese McDermond };
894d25970b5SAnnaliese McDermond
895d25970b5SAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
896d25970b5SAnnaliese McDermond if (ret)
897d25970b5SAnnaliese McDermond return ret;
898d25970b5SAnnaliese McDermond
8991d471cd1SJavier Martin switch (level) {
9001d471cd1SJavier Martin case SND_SOC_BIAS_ON:
901d25970b5SAnnaliese McDermond ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
90298b664e2SMarkus Pargmann if (ret) {
903d25970b5SAnnaliese McDermond dev_err(component->dev, "Failed to enable clocks\n");
90498b664e2SMarkus Pargmann return ret;
90598b664e2SMarkus Pargmann }
9061d471cd1SJavier Martin break;
9071d471cd1SJavier Martin case SND_SOC_BIAS_PREPARE:
9081d471cd1SJavier Martin break;
9091d471cd1SJavier Martin case SND_SOC_BIAS_STANDBY:
910667e9334Sb-ak /* Initial cold start */
911667e9334Sb-ak if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
912667e9334Sb-ak break;
913667e9334Sb-ak
914d25970b5SAnnaliese McDermond clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
9151d471cd1SJavier Martin break;
9161d471cd1SJavier Martin case SND_SOC_BIAS_OFF:
9171d471cd1SJavier Martin break;
9181d471cd1SJavier Martin }
9191d471cd1SJavier Martin return 0;
9201d471cd1SJavier Martin }
9211d471cd1SJavier Martin
9226d56ee15SAnnaliese McDermond #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
9231d471cd1SJavier Martin #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
924dcd79364SMichael Sit Wei Hong | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
925dcd79364SMichael Sit Wei Hong | SNDRV_PCM_FMTBIT_S32_LE)
9261d471cd1SJavier Martin
92785e7652dSLars-Peter Clausen static const struct snd_soc_dai_ops aic32x4_ops = {
9281d471cd1SJavier Martin .hw_params = aic32x4_hw_params,
929960af79dSKuninori Morimoto .mute_stream = aic32x4_mute,
9301d471cd1SJavier Martin .set_fmt = aic32x4_set_dai_fmt,
9311d471cd1SJavier Martin .set_sysclk = aic32x4_set_dai_sysclk,
932960af79dSKuninori Morimoto .no_capture_mute = 1,
9331d471cd1SJavier Martin };
9341d471cd1SJavier Martin
9351d471cd1SJavier Martin static struct snd_soc_dai_driver aic32x4_dai = {
9361d471cd1SJavier Martin .name = "tlv320aic32x4-hifi",
9371d471cd1SJavier Martin .playback = {
9381d471cd1SJavier Martin .stream_name = "Playback",
9391d471cd1SJavier Martin .channels_min = 1,
9401d471cd1SJavier Martin .channels_max = 2,
9411d471cd1SJavier Martin .rates = AIC32X4_RATES,
9421d471cd1SJavier Martin .formats = AIC32X4_FORMATS,},
9431d471cd1SJavier Martin .capture = {
9441d471cd1SJavier Martin .stream_name = "Capture",
9451d471cd1SJavier Martin .channels_min = 1,
946d1c859d3SMichael Sit Wei Hong .channels_max = 8,
9471d471cd1SJavier Martin .rates = AIC32X4_RATES,
9481d471cd1SJavier Martin .formats = AIC32X4_FORMATS,},
9491d471cd1SJavier Martin .ops = &aic32x4_ops,
950a9aef184SKuninori Morimoto .symmetric_rate = 1,
9511d471cd1SJavier Martin };
9521d471cd1SJavier Martin
aic32x4_setup_gpios(struct snd_soc_component * component)953b154dc5dSKuninori Morimoto static void aic32x4_setup_gpios(struct snd_soc_component *component)
954b9045b9cSDan Murphy {
955b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
956b9045b9cSDan Murphy
957b9045b9cSDan Murphy /* setup GPIO functions */
958b9045b9cSDan Murphy /* MFP1 */
959b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
960b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DINCTL,
961b9045b9cSDan Murphy aic32x4->setup->gpio_func[0]);
962b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp1,
963b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp1));
964b9045b9cSDan Murphy }
965b9045b9cSDan Murphy
966b9045b9cSDan Murphy /* MFP2 */
967b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
968b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_DOUTCTL,
969b9045b9cSDan Murphy aic32x4->setup->gpio_func[1]);
970b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp2,
971b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp2));
972b9045b9cSDan Murphy }
973b9045b9cSDan Murphy
974b9045b9cSDan Murphy /* MFP3 */
975b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
976b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_SCLKCTL,
977b9045b9cSDan Murphy aic32x4->setup->gpio_func[2]);
978b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp3,
979b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp3));
980b9045b9cSDan Murphy }
981b9045b9cSDan Murphy
982b9045b9cSDan Murphy /* MFP4 */
983b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
984b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_MISOCTL,
985b9045b9cSDan Murphy aic32x4->setup->gpio_func[3]);
986b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp4,
987b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp4));
988b9045b9cSDan Murphy }
989b9045b9cSDan Murphy
990b9045b9cSDan Murphy /* MFP5 */
991b9045b9cSDan Murphy if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
992b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_GPIOCTL,
993b9045b9cSDan Murphy aic32x4->setup->gpio_func[4]);
994b154dc5dSKuninori Morimoto snd_soc_add_component_controls(component, aic32x4_mfp5,
995b9045b9cSDan Murphy ARRAY_SIZE(aic32x4_mfp5));
996b9045b9cSDan Murphy }
997b9045b9cSDan Murphy }
998b9045b9cSDan Murphy
aic32x4_component_probe(struct snd_soc_component * component)999b154dc5dSKuninori Morimoto static int aic32x4_component_probe(struct snd_soc_component *component)
10001d471cd1SJavier Martin {
1001b154dc5dSKuninori Morimoto struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
10021d471cd1SJavier Martin u32 tmp_reg;
1003fd2df3aeSAnnaliese McDermond int ret;
1004fd2df3aeSAnnaliese McDermond
1005ea9df984SColin Ian King static struct clk_bulk_data clocks[] = {
1006fd2df3aeSAnnaliese McDermond { .id = "codec_clkin" },
1007a51b5006SAnnaliese McDermond { .id = "pll" },
10089b484124SAnnaliese McDermond { .id = "bdiv" },
10099b484124SAnnaliese McDermond { .id = "mdac" },
1010fd2df3aeSAnnaliese McDermond };
1011fd2df3aeSAnnaliese McDermond
1012fd2df3aeSAnnaliese McDermond ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1013fd2df3aeSAnnaliese McDermond if (ret)
1014fd2df3aeSAnnaliese McDermond return ret;
10151d471cd1SJavier Martin
1016b9045b9cSDan Murphy if (aic32x4->setup)
1017b154dc5dSKuninori Morimoto aic32x4_setup_gpios(component);
1018b9045b9cSDan Murphy
1019fd2df3aeSAnnaliese McDermond clk_set_parent(clocks[0].clk, clocks[1].clk);
10209b484124SAnnaliese McDermond clk_set_parent(clocks[2].clk, clocks[3].clk);
1021fd2df3aeSAnnaliese McDermond
10221d471cd1SJavier Martin /* Power platform configuration */
10231d471cd1SJavier Martin if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1024514b044cSAnnaliese McDermond snd_soc_component_write(component, AIC32X4_MICBIAS,
1025514b044cSAnnaliese McDermond AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
10261d471cd1SJavier Martin }
1027eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1028b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
10290c93a167SWolfram Sang
10300c93a167SWolfram Sang tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
10310c93a167SWolfram Sang AIC32X4_LDOCTLEN : 0;
1032b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
10330c93a167SWolfram Sang
1034e348cf54SKuninori Morimoto tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1035eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
10361d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN_18_36;
1037eb72cbdfSShahina Shaik if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
10381d471cd1SJavier Martin tmp_reg |= AIC32X4_LDOIN2HP;
1039b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
10401d471cd1SJavier Martin
10411d471cd1SJavier Martin /* Mic PGA routing */
1042609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1043b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN,
104443bf38baSShahina Shaik AIC32X4_LMICPGANIN_IN2R_10K);
1045609e6025SMarkus Pargmann else
1046b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_LMICPGANIN,
104743bf38baSShahina Shaik AIC32X4_LMICPGANIN_CM1L_10K);
1048609e6025SMarkus Pargmann if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1049b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN,
105043bf38baSShahina Shaik AIC32X4_RMICPGANIN_IN1L_10K);
1051609e6025SMarkus Pargmann else
1052b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_RMICPGANIN,
105343bf38baSShahina Shaik AIC32X4_RMICPGANIN_CM1R_10K);
10541d471cd1SJavier Martin
1055a405387cSJavier Martin /*
1056a405387cSJavier Martin * Workaround: for an unknown reason, the ADC needs to be powered up
1057a405387cSJavier Martin * and down for the first capture to work properly. It seems related to
1058a405387cSJavier Martin * a HW BUG or some kind of behavior not documented in the datasheet.
1059a405387cSJavier Martin */
1060e348cf54SKuninori Morimoto tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1061b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1062a405387cSJavier Martin AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1063b154dc5dSKuninori Morimoto snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1064a405387cSJavier Martin
1065ec96690dSMiquel Raynal /*
1066ec96690dSMiquel Raynal * Enable the fast charging feature and ensure the needed 40ms ellapsed
1067ec96690dSMiquel Raynal * before using the analog circuits.
1068ec96690dSMiquel Raynal */
1069ec96690dSMiquel Raynal snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1070ec96690dSMiquel Raynal AIC32X4_REFPOWERUP_40MS);
1071ec96690dSMiquel Raynal msleep(40);
1072ec96690dSMiquel Raynal
10731d471cd1SJavier Martin return 0;
10741d471cd1SJavier Martin }
10751d471cd1SJavier Martin
1076b154dc5dSKuninori Morimoto static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1077b154dc5dSKuninori Morimoto .probe = aic32x4_component_probe,
10781d471cd1SJavier Martin .set_bias_level = aic32x4_set_bias_level,
1079aac97b5fSLars-Peter Clausen .controls = aic32x4_snd_controls,
1080aac97b5fSLars-Peter Clausen .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1081aac97b5fSLars-Peter Clausen .dapm_widgets = aic32x4_dapm_widgets,
1082aac97b5fSLars-Peter Clausen .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1083aac97b5fSLars-Peter Clausen .dapm_routes = aic32x4_dapm_routes,
1084aac97b5fSLars-Peter Clausen .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1085b154dc5dSKuninori Morimoto .suspend_bias_off = 1,
1086b154dc5dSKuninori Morimoto .idle_bias_on = 1,
1087b154dc5dSKuninori Morimoto .use_pmdown_time = 1,
1088b154dc5dSKuninori Morimoto .endianness = 1,
10891d471cd1SJavier Martin };
10901d471cd1SJavier Martin
1091b4525b61SClaudius Heine static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
10922169d6a0SMarek Vasut SOC_SINGLE_S8_TLV("PCM Playback Volume",
10932169d6a0SMarek Vasut AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
1094b4525b61SClaudius Heine SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
10952169d6a0SMarek Vasut
10962169d6a0SMarek Vasut SOC_SINGLE_TLV("HP Driver Gain Volume",
10972169d6a0SMarek Vasut AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
10982169d6a0SMarek Vasut SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
10992169d6a0SMarek Vasut
11002169d6a0SMarek Vasut SOC_SINGLE_TLV("Speaker Driver Playback Volume",
11012169d6a0SMarek Vasut TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
11022169d6a0SMarek Vasut SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
11032169d6a0SMarek Vasut TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
1104b4525b61SClaudius Heine
1105b4525b61SClaudius Heine SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
1106b4525b61SClaudius Heine };
1107b4525b61SClaudius Heine
1108b4525b61SClaudius Heine static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
1109b4525b61SClaudius Heine SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
1110b4525b61SClaudius Heine };
1111b4525b61SClaudius Heine
1112b4525b61SClaudius Heine static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
1113b4525b61SClaudius Heine SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
1114b4525b61SClaudius Heine SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
1115b4525b61SClaudius Heine &hp_output_mixer_controls[0],
1116b4525b61SClaudius Heine ARRAY_SIZE(hp_output_mixer_controls)),
1117b4525b61SClaudius Heine SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
1118b4525b61SClaudius Heine
1119b4525b61SClaudius Heine SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
1120b4525b61SClaudius Heine
1121b4525b61SClaudius Heine SND_SOC_DAPM_OUTPUT("HP"),
1122b4525b61SClaudius Heine SND_SOC_DAPM_OUTPUT("Speaker"),
1123b4525b61SClaudius Heine };
1124b4525b61SClaudius Heine
1125b4525b61SClaudius Heine static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
1126b4525b61SClaudius Heine /* Left Output */
1127b4525b61SClaudius Heine {"HP Output Mixer", "DAC Switch", "DAC"},
1128b4525b61SClaudius Heine
1129b4525b61SClaudius Heine {"HP Power", NULL, "HP Output Mixer"},
1130b4525b61SClaudius Heine {"HP", NULL, "HP Power"},
1131b4525b61SClaudius Heine
1132b4525b61SClaudius Heine {"Speaker Driver", NULL, "DAC"},
1133b4525b61SClaudius Heine {"Speaker", NULL, "Speaker Driver"},
1134b4525b61SClaudius Heine };
1135b4525b61SClaudius Heine
1136b4525b61SClaudius Heine static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
1137b4525b61SClaudius Heine .name = "tas2505-hifi",
1138b4525b61SClaudius Heine .playback = {
1139b4525b61SClaudius Heine .stream_name = "Playback",
1140b4525b61SClaudius Heine .channels_min = 1,
11413694f996SMarek Vasut .channels_max = 2,
1142b4525b61SClaudius Heine .rates = SNDRV_PCM_RATE_8000_96000,
1143b4525b61SClaudius Heine .formats = AIC32X4_FORMATS,},
1144b4525b61SClaudius Heine .ops = &aic32x4_ops,
1145b4525b61SClaudius Heine .symmetric_rate = 1,
1146b4525b61SClaudius Heine };
1147b4525b61SClaudius Heine
aic32x4_tas2505_component_probe(struct snd_soc_component * component)1148b4525b61SClaudius Heine static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
1149b4525b61SClaudius Heine {
1150b4525b61SClaudius Heine struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1151b4525b61SClaudius Heine u32 tmp_reg;
1152b4525b61SClaudius Heine int ret;
1153b4525b61SClaudius Heine
1154ea9df984SColin Ian King static struct clk_bulk_data clocks[] = {
1155b4525b61SClaudius Heine { .id = "codec_clkin" },
1156b4525b61SClaudius Heine { .id = "pll" },
1157b4525b61SClaudius Heine { .id = "bdiv" },
1158b4525b61SClaudius Heine { .id = "mdac" },
1159b4525b61SClaudius Heine };
1160b4525b61SClaudius Heine
1161b4525b61SClaudius Heine ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1162b4525b61SClaudius Heine if (ret)
1163b4525b61SClaudius Heine return ret;
1164b4525b61SClaudius Heine
1165b4525b61SClaudius Heine if (aic32x4->setup)
1166b4525b61SClaudius Heine aic32x4_setup_gpios(component);
1167b4525b61SClaudius Heine
1168b4525b61SClaudius Heine clk_set_parent(clocks[0].clk, clocks[1].clk);
1169b4525b61SClaudius Heine clk_set_parent(clocks[2].clk, clocks[3].clk);
1170b4525b61SClaudius Heine
1171b4525b61SClaudius Heine /* Power platform configuration */
1172b4525b61SClaudius Heine if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1173b4525b61SClaudius Heine snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1174b4525b61SClaudius Heine
1175b4525b61SClaudius Heine tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1176b4525b61SClaudius Heine AIC32X4_LDOCTLEN : 0;
1177b4525b61SClaudius Heine snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1178b4525b61SClaudius Heine
1179b4525b61SClaudius Heine tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1180b4525b61SClaudius Heine if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1181b4525b61SClaudius Heine tmp_reg |= AIC32X4_LDOIN_18_36;
1182b4525b61SClaudius Heine if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1183b4525b61SClaudius Heine tmp_reg |= AIC32X4_LDOIN2HP;
1184b4525b61SClaudius Heine snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1185b4525b61SClaudius Heine
1186b4525b61SClaudius Heine /*
1187b4525b61SClaudius Heine * Enable the fast charging feature and ensure the needed 40ms ellapsed
1188b4525b61SClaudius Heine * before using the analog circuits.
1189b4525b61SClaudius Heine */
1190b4525b61SClaudius Heine snd_soc_component_write(component, TAS2505_REFPOWERUP,
1191b4525b61SClaudius Heine AIC32X4_REFPOWERUP_40MS);
1192b4525b61SClaudius Heine msleep(40);
1193b4525b61SClaudius Heine
1194b4525b61SClaudius Heine return 0;
1195b4525b61SClaudius Heine }
1196b4525b61SClaudius Heine
1197b4525b61SClaudius Heine static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
1198b4525b61SClaudius Heine .probe = aic32x4_tas2505_component_probe,
1199b4525b61SClaudius Heine .set_bias_level = aic32x4_set_bias_level,
1200b4525b61SClaudius Heine .controls = aic32x4_tas2505_snd_controls,
1201b4525b61SClaudius Heine .num_controls = ARRAY_SIZE(aic32x4_tas2505_snd_controls),
1202b4525b61SClaudius Heine .dapm_widgets = aic32x4_tas2505_dapm_widgets,
1203b4525b61SClaudius Heine .num_dapm_widgets = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
1204b4525b61SClaudius Heine .dapm_routes = aic32x4_tas2505_dapm_routes,
1205b4525b61SClaudius Heine .num_dapm_routes = ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
1206b4525b61SClaudius Heine .suspend_bias_off = 1,
1207b4525b61SClaudius Heine .idle_bias_on = 1,
1208b4525b61SClaudius Heine .use_pmdown_time = 1,
1209b4525b61SClaudius Heine .endianness = 1,
1210b4525b61SClaudius Heine };
1211b4525b61SClaudius Heine
aic32x4_parse_dt(struct aic32x4_priv * aic32x4,struct device_node * np)12124d16700dSMarkus Pargmann static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
12134d16700dSMarkus Pargmann struct device_node *np)
12144d16700dSMarkus Pargmann {
1215b9045b9cSDan Murphy struct aic32x4_setup_data *aic32x4_setup;
1216514b044cSAnnaliese McDermond int ret;
1217b9045b9cSDan Murphy
1218b9045b9cSDan Murphy aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1219b9045b9cSDan Murphy GFP_KERNEL);
1220b9045b9cSDan Murphy if (!aic32x4_setup)
1221b9045b9cSDan Murphy return -ENOMEM;
1222b9045b9cSDan Murphy
1223514b044cSAnnaliese McDermond ret = of_property_match_string(np, "clock-names", "mclk");
1224514b044cSAnnaliese McDermond if (ret < 0)
1225514b044cSAnnaliese McDermond return -EINVAL;
1226514b044cSAnnaliese McDermond aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1227514b044cSAnnaliese McDermond
12284d16700dSMarkus Pargmann aic32x4->swapdacs = false;
12294d16700dSMarkus Pargmann aic32x4->micpga_routing = 0;
12304d16700dSMarkus Pargmann aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
12314d16700dSMarkus Pargmann
1232b9045b9cSDan Murphy if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1233b9045b9cSDan Murphy aic32x4_setup->gpio_func, 5) >= 0)
1234b9045b9cSDan Murphy aic32x4->setup = aic32x4_setup;
12354d16700dSMarkus Pargmann return 0;
12364d16700dSMarkus Pargmann }
12374d16700dSMarkus Pargmann
aic32x4_disable_regulators(struct aic32x4_priv * aic32x4)1238239b669bSMarkus Pargmann static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1239239b669bSMarkus Pargmann {
1240239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov);
1241239b669bSMarkus Pargmann
1242239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo))
1243239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo);
1244239b669bSMarkus Pargmann
1245239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv))
1246239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv);
1247239b669bSMarkus Pargmann
1248239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av))
1249239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_av);
1250239b669bSMarkus Pargmann }
1251239b669bSMarkus Pargmann
aic32x4_setup_regulators(struct device * dev,struct aic32x4_priv * aic32x4)1252239b669bSMarkus Pargmann static int aic32x4_setup_regulators(struct device *dev,
1253239b669bSMarkus Pargmann struct aic32x4_priv *aic32x4)
1254239b669bSMarkus Pargmann {
1255239b669bSMarkus Pargmann int ret = 0;
1256239b669bSMarkus Pargmann
1257239b669bSMarkus Pargmann aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1258239b669bSMarkus Pargmann aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1259239b669bSMarkus Pargmann aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1260239b669bSMarkus Pargmann aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1261239b669bSMarkus Pargmann
1262239b669bSMarkus Pargmann /* Check if the regulator requirements are fulfilled */
1263239b669bSMarkus Pargmann
1264239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_iov)) {
1265239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'iov'\n");
1266239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_iov);
1267239b669bSMarkus Pargmann }
1268239b669bSMarkus Pargmann
1269239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_ldo)) {
1270239b669bSMarkus Pargmann if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1271239b669bSMarkus Pargmann return -EPROBE_DEFER;
1272239b669bSMarkus Pargmann
1273239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_dv)) {
1274239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1275239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_dv);
1276239b669bSMarkus Pargmann }
1277239b669bSMarkus Pargmann if (IS_ERR(aic32x4->supply_av)) {
1278239b669bSMarkus Pargmann dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1279239b669bSMarkus Pargmann return PTR_ERR(aic32x4->supply_av);
1280239b669bSMarkus Pargmann }
1281239b669bSMarkus Pargmann } else {
128245586c70SMasahiro Yamada if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1283239b669bSMarkus Pargmann return -EPROBE_DEFER;
128445586c70SMasahiro Yamada if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1285239b669bSMarkus Pargmann return -EPROBE_DEFER;
1286239b669bSMarkus Pargmann }
1287239b669bSMarkus Pargmann
1288239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_iov);
1289239b669bSMarkus Pargmann if (ret) {
1290239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator iov\n");
1291239b669bSMarkus Pargmann return ret;
1292239b669bSMarkus Pargmann }
1293239b669bSMarkus Pargmann
1294239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo)) {
1295239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_ldo);
1296239b669bSMarkus Pargmann if (ret) {
1297239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator ldo\n");
1298239b669bSMarkus Pargmann goto error_ldo;
1299239b669bSMarkus Pargmann }
1300239b669bSMarkus Pargmann }
1301239b669bSMarkus Pargmann
1302239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv)) {
1303239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_dv);
1304239b669bSMarkus Pargmann if (ret) {
1305239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator dv\n");
1306239b669bSMarkus Pargmann goto error_dv;
1307239b669bSMarkus Pargmann }
1308239b669bSMarkus Pargmann }
1309239b669bSMarkus Pargmann
1310239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_av)) {
1311239b669bSMarkus Pargmann ret = regulator_enable(aic32x4->supply_av);
1312239b669bSMarkus Pargmann if (ret) {
1313239b669bSMarkus Pargmann dev_err(dev, "Failed to enable regulator av\n");
1314239b669bSMarkus Pargmann goto error_av;
1315239b669bSMarkus Pargmann }
1316239b669bSMarkus Pargmann }
1317239b669bSMarkus Pargmann
1318239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1319239b669bSMarkus Pargmann aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1320239b669bSMarkus Pargmann
1321239b669bSMarkus Pargmann return 0;
1322239b669bSMarkus Pargmann
1323239b669bSMarkus Pargmann error_av:
1324239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_dv))
1325239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_dv);
1326239b669bSMarkus Pargmann
1327239b669bSMarkus Pargmann error_dv:
1328239b669bSMarkus Pargmann if (!IS_ERR(aic32x4->supply_ldo))
1329239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_ldo);
1330239b669bSMarkus Pargmann
1331239b669bSMarkus Pargmann error_ldo:
1332239b669bSMarkus Pargmann regulator_disable(aic32x4->supply_iov);
1333239b669bSMarkus Pargmann return ret;
1334239b669bSMarkus Pargmann }
1335239b669bSMarkus Pargmann
aic32x4_probe(struct device * dev,struct regmap * regmap,enum aic32x4_type type)1336*cac1636eSBiju Das int aic32x4_probe(struct device *dev, struct regmap *regmap,
1337*cac1636eSBiju Das enum aic32x4_type type)
13381d471cd1SJavier Martin {
13391d471cd1SJavier Martin struct aic32x4_priv *aic32x4;
13403bcfd222SJeremy McDermond struct aic32x4_pdata *pdata = dev->platform_data;
13413bcfd222SJeremy McDermond struct device_node *np = dev->of_node;
13421d471cd1SJavier Martin int ret;
13431d471cd1SJavier Martin
13443bcfd222SJeremy McDermond if (IS_ERR(regmap))
13453bcfd222SJeremy McDermond return PTR_ERR(regmap);
13463bcfd222SJeremy McDermond
13473bcfd222SJeremy McDermond aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1348658ecf77SAxel Lin GFP_KERNEL);
13491d471cd1SJavier Martin if (aic32x4 == NULL)
13501d471cd1SJavier Martin return -ENOMEM;
13511d471cd1SJavier Martin
1352b9045b9cSDan Murphy aic32x4->dev = dev;
1353*cac1636eSBiju Das aic32x4->type = type;
1354688d47cdSClaudius Heine
13553bcfd222SJeremy McDermond dev_set_drvdata(dev, aic32x4);
13561d471cd1SJavier Martin
13571d471cd1SJavier Martin if (pdata) {
13581d471cd1SJavier Martin aic32x4->power_cfg = pdata->power_cfg;
13591d471cd1SJavier Martin aic32x4->swapdacs = pdata->swapdacs;
13601d471cd1SJavier Martin aic32x4->micpga_routing = pdata->micpga_routing;
13611858fe97SJavier Martin aic32x4->rstn_gpio = pdata->rstn_gpio;
1362514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk";
13634d16700dSMarkus Pargmann } else if (np) {
13644d16700dSMarkus Pargmann ret = aic32x4_parse_dt(aic32x4, np);
13654d16700dSMarkus Pargmann if (ret) {
13663bcfd222SJeremy McDermond dev_err(dev, "Failed to parse DT node\n");
13674d16700dSMarkus Pargmann return ret;
13684d16700dSMarkus Pargmann }
13691d471cd1SJavier Martin } else {
13701d471cd1SJavier Martin aic32x4->power_cfg = 0;
13711d471cd1SJavier Martin aic32x4->swapdacs = false;
13721d471cd1SJavier Martin aic32x4->micpga_routing = 0;
13731858fe97SJavier Martin aic32x4->rstn_gpio = -1;
1374514b044cSAnnaliese McDermond aic32x4->mclk_name = "mclk";
13751d471cd1SJavier Martin }
13761d471cd1SJavier Martin
1377a74ab512SMarkus Pargmann if (gpio_is_valid(aic32x4->rstn_gpio)) {
13783bcfd222SJeremy McDermond ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1379752b7764SMark Brown GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1380752b7764SMark Brown if (ret != 0)
1381752b7764SMark Brown return ret;
1382752b7764SMark Brown }
1383752b7764SMark Brown
13843bcfd222SJeremy McDermond ret = aic32x4_setup_regulators(dev, aic32x4);
1385239b669bSMarkus Pargmann if (ret) {
13863bcfd222SJeremy McDermond dev_err(dev, "Failed to setup regulators\n");
1387239b669bSMarkus Pargmann return ret;
1388239b669bSMarkus Pargmann }
1389239b669bSMarkus Pargmann
1390df44bc16SMatthias Schiffer if (gpio_is_valid(aic32x4->rstn_gpio)) {
1391df44bc16SMatthias Schiffer ndelay(10);
1392df44bc16SMatthias Schiffer gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
1393df44bc16SMatthias Schiffer mdelay(1);
1394df44bc16SMatthias Schiffer }
1395df44bc16SMatthias Schiffer
1396df44bc16SMatthias Schiffer ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1397df44bc16SMatthias Schiffer if (ret)
1398df44bc16SMatthias Schiffer goto err_disable_regulators;
1399df44bc16SMatthias Schiffer
14001ca1156cSAnnaliese McDermond ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
14011ca1156cSAnnaliese McDermond if (ret)
14021ca1156cSAnnaliese McDermond goto err_disable_regulators;
14031ca1156cSAnnaliese McDermond
1404b4525b61SClaudius Heine switch (aic32x4->type) {
1405b4525b61SClaudius Heine case AIC32X4_TYPE_TAS2505:
1406b4525b61SClaudius Heine ret = devm_snd_soc_register_component(dev,
1407b4525b61SClaudius Heine &soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
1408b4525b61SClaudius Heine break;
1409b4525b61SClaudius Heine default:
1410b154dc5dSKuninori Morimoto ret = devm_snd_soc_register_component(dev,
1411b154dc5dSKuninori Morimoto &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1412b4525b61SClaudius Heine }
1413b4525b61SClaudius Heine
1414239b669bSMarkus Pargmann if (ret) {
1415b154dc5dSKuninori Morimoto dev_err(dev, "Failed to register component\n");
1416251e5c86SMatthias Schiffer goto err_disable_regulators;
14171d471cd1SJavier Martin }
14181d471cd1SJavier Martin
1419239b669bSMarkus Pargmann return 0;
1420251e5c86SMatthias Schiffer
1421251e5c86SMatthias Schiffer err_disable_regulators:
1422251e5c86SMatthias Schiffer aic32x4_disable_regulators(aic32x4);
1423251e5c86SMatthias Schiffer
1424251e5c86SMatthias Schiffer return ret;
1425239b669bSMarkus Pargmann }
14263bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_probe);
1427239b669bSMarkus Pargmann
aic32x4_remove(struct device * dev)14280f884099SUwe Kleine-König void aic32x4_remove(struct device *dev)
14291d471cd1SJavier Martin {
14303bcfd222SJeremy McDermond struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1431239b669bSMarkus Pargmann
1432239b669bSMarkus Pargmann aic32x4_disable_regulators(aic32x4);
14331d471cd1SJavier Martin }
14343bcfd222SJeremy McDermond EXPORT_SYMBOL(aic32x4_remove);
14351d471cd1SJavier Martin
14361d471cd1SJavier Martin MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
14371d471cd1SJavier Martin MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
14381d471cd1SJavier Martin MODULE_LICENSE("GPL");
1439