xref: /linux/sound/soc/codecs/tlv320aic31xx.h (revision db6d8d5fdf9537641c76ba7f32e02b4bcc600972)
1 /*
2  * ALSA SoC TLV320AIC31XX codec driver
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * This package is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13  *
14  */
15 #ifndef _TLV320AIC31XX_H
16 #define _TLV320AIC31XX_H
17 
18 #define AIC31XX_RATES	SNDRV_PCM_RATE_8000_192000
19 
20 #define AIC31XX_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
21 			 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
22 			 | SNDRV_PCM_FMTBIT_S32_LE)
23 
24 
25 #define AIC31XX_STEREO_CLASS_D_BIT	0x1
26 #define AIC31XX_MINIDSP_BIT		0x2
27 #define DAC31XX_BIT			0x4
28 
29 enum aic31xx_type {
30 	AIC3100	= 0,
31 	AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
32 	AIC3120 = AIC31XX_MINIDSP_BIT,
33 	AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT),
34 	DAC3100 = DAC31XX_BIT,
35 };
36 
37 struct aic31xx_pdata {
38 	enum aic31xx_type codec_type;
39 	unsigned int gpio_reset;
40 	int micbias_vg;
41 };
42 
43 #define AIC31XX_REG(page, reg)	((page * 128) + reg)
44 
45 /* Page Control Register */
46 #define AIC31XX_PAGECTL		AIC31XX_REG(0, 0)
47 
48 /* Page 0 Registers */
49 /* Software reset register */
50 #define AIC31XX_RESET		AIC31XX_REG(0, 1)
51 /* OT FLAG register */
52 #define AIC31XX_OT_FLAG		AIC31XX_REG(0, 3)
53 /* Clock clock Gen muxing, Multiplexers*/
54 #define AIC31XX_CLKMUX		AIC31XX_REG(0, 4)
55 /* PLL P and R-VAL register */
56 #define AIC31XX_PLLPR		AIC31XX_REG(0, 5)
57 /* PLL J-VAL register */
58 #define AIC31XX_PLLJ		AIC31XX_REG(0, 6)
59 /* PLL D-VAL MSB register */
60 #define AIC31XX_PLLDMSB		AIC31XX_REG(0, 7)
61 /* PLL D-VAL LSB register */
62 #define AIC31XX_PLLDLSB		AIC31XX_REG(0, 8)
63 /* DAC NDAC_VAL register*/
64 #define AIC31XX_NDAC		AIC31XX_REG(0, 11)
65 /* DAC MDAC_VAL register */
66 #define AIC31XX_MDAC		AIC31XX_REG(0, 12)
67 /* DAC OSR setting register 1, MSB value */
68 #define AIC31XX_DOSRMSB		AIC31XX_REG(0, 13)
69 /* DAC OSR setting register 2, LSB value */
70 #define AIC31XX_DOSRLSB		AIC31XX_REG(0, 14)
71 #define AIC31XX_MINI_DSP_INPOL	AIC31XX_REG(0, 16)
72 /* Clock setting register 8, PLL */
73 #define AIC31XX_NADC		AIC31XX_REG(0, 18)
74 /* Clock setting register 9, PLL */
75 #define AIC31XX_MADC		AIC31XX_REG(0, 19)
76 /* ADC Oversampling (AOSR) Register */
77 #define AIC31XX_AOSR		AIC31XX_REG(0, 20)
78 /* Clock setting register 9, Multiplexers */
79 #define AIC31XX_CLKOUTMUX	AIC31XX_REG(0, 25)
80 /* Clock setting register 10, CLOCKOUT M divider value */
81 #define AIC31XX_CLKOUTMVAL	AIC31XX_REG(0, 26)
82 /* Audio Interface Setting Register 1 */
83 #define AIC31XX_IFACE1		AIC31XX_REG(0, 27)
84 /* Audio Data Slot Offset Programming */
85 #define AIC31XX_DATA_OFFSET	AIC31XX_REG(0, 28)
86 /* Audio Interface Setting Register 2 */
87 #define AIC31XX_IFACE2		AIC31XX_REG(0, 29)
88 /* Clock setting register 11, BCLK N Divider */
89 #define AIC31XX_BCLKN		AIC31XX_REG(0, 30)
90 /* Audio Interface Setting Register 3, Secondary Audio Interface */
91 #define AIC31XX_IFACESEC1	AIC31XX_REG(0, 31)
92 /* Audio Interface Setting Register 4 */
93 #define AIC31XX_IFACESEC2	AIC31XX_REG(0, 32)
94 /* Audio Interface Setting Register 5 */
95 #define AIC31XX_IFACESEC3	AIC31XX_REG(0, 33)
96 /* I2C Bus Condition */
97 #define AIC31XX_I2C		AIC31XX_REG(0, 34)
98 /* ADC FLAG */
99 #define AIC31XX_ADCFLAG		AIC31XX_REG(0, 36)
100 /* DAC Flag Registers */
101 #define AIC31XX_DACFLAG1	AIC31XX_REG(0, 37)
102 #define AIC31XX_DACFLAG2	AIC31XX_REG(0, 38)
103 /* Sticky Interrupt flag (overflow) */
104 #define AIC31XX_OFFLAG		AIC31XX_REG(0, 39)
105 /* Sticy DAC Interrupt flags */
106 #define AIC31XX_INTRDACFLAG	AIC31XX_REG(0, 44)
107 /* Sticy ADC Interrupt flags */
108 #define AIC31XX_INTRADCFLAG	AIC31XX_REG(0, 45)
109 /* DAC Interrupt flags 2 */
110 #define AIC31XX_INTRDACFLAG2	AIC31XX_REG(0, 46)
111 /* ADC Interrupt flags 2 */
112 #define AIC31XX_INTRADCFLAG2	AIC31XX_REG(0, 47)
113 /* INT1 interrupt control */
114 #define AIC31XX_INT1CTRL	AIC31XX_REG(0, 48)
115 /* INT2 interrupt control */
116 #define AIC31XX_INT2CTRL	AIC31XX_REG(0, 49)
117 /* GPIO1 control */
118 #define AIC31XX_GPIO1		AIC31XX_REG(0, 50)
119 
120 #define AIC31XX_DACPRB		AIC31XX_REG(0, 60)
121 /* ADC Instruction Set Register */
122 #define AIC31XX_ADCPRB		AIC31XX_REG(0, 61)
123 /* DAC channel setup register */
124 #define AIC31XX_DACSETUP	AIC31XX_REG(0, 63)
125 /* DAC Mute and volume control register */
126 #define AIC31XX_DACMUTE		AIC31XX_REG(0, 64)
127 /* Left DAC channel digital volume control */
128 #define AIC31XX_LDACVOL		AIC31XX_REG(0, 65)
129 /* Right DAC channel digital volume control */
130 #define AIC31XX_RDACVOL		AIC31XX_REG(0, 66)
131 /* Headset detection */
132 #define AIC31XX_HSDETECT	AIC31XX_REG(0, 67)
133 /* ADC Digital Mic */
134 #define AIC31XX_ADCSETUP	AIC31XX_REG(0, 81)
135 /* ADC Digital Volume Control Fine Adjust */
136 #define AIC31XX_ADCFGA		AIC31XX_REG(0, 82)
137 /* ADC Digital Volume Control Coarse Adjust */
138 #define AIC31XX_ADCVOL		AIC31XX_REG(0, 83)
139 
140 
141 /* Page 1 Registers */
142 /* Headphone drivers */
143 #define AIC31XX_HPDRIVER	AIC31XX_REG(1, 31)
144 /* Class-D Speakear Amplifier */
145 #define AIC31XX_SPKAMP		AIC31XX_REG(1, 32)
146 /* HP Output Drivers POP Removal Settings */
147 #define AIC31XX_HPPOP		AIC31XX_REG(1, 33)
148 /* Output Driver PGA Ramp-Down Period Control */
149 #define AIC31XX_SPPGARAMP	AIC31XX_REG(1, 34)
150 /* DAC_L and DAC_R Output Mixer Routing */
151 #define AIC31XX_DACMIXERROUTE	AIC31XX_REG(1, 35)
152 /* Left Analog Vol to HPL */
153 #define AIC31XX_LANALOGHPL	AIC31XX_REG(1, 36)
154 /* Right Analog Vol to HPR */
155 #define AIC31XX_RANALOGHPR	AIC31XX_REG(1, 37)
156 /* Left Analog Vol to SPL */
157 #define AIC31XX_LANALOGSPL	AIC31XX_REG(1, 38)
158 /* Right Analog Vol to SPR */
159 #define AIC31XX_RANALOGSPR	AIC31XX_REG(1, 39)
160 /* HPL Driver */
161 #define AIC31XX_HPLGAIN		AIC31XX_REG(1, 40)
162 /* HPR Driver */
163 #define AIC31XX_HPRGAIN		AIC31XX_REG(1, 41)
164 /* SPL Driver */
165 #define AIC31XX_SPLGAIN		AIC31XX_REG(1, 42)
166 /* SPR Driver */
167 #define AIC31XX_SPRGAIN		AIC31XX_REG(1, 43)
168 /* HP Driver Control */
169 #define AIC31XX_HPCONTROL	AIC31XX_REG(1, 44)
170 /* MIC Bias Control */
171 #define AIC31XX_MICBIAS		AIC31XX_REG(1, 46)
172 /* MIC PGA*/
173 #define AIC31XX_MICPGA		AIC31XX_REG(1, 47)
174 /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */
175 #define AIC31XX_MICPGAPI	AIC31XX_REG(1, 48)
176 /* ADC Input Selection for M-Terminal */
177 #define AIC31XX_MICPGAMI	AIC31XX_REG(1, 49)
178 /* Input CM Settings */
179 #define AIC31XX_MICPGACM	AIC31XX_REG(1, 50)
180 
181 /* Bits, masks and shifts */
182 
183 /* AIC31XX_CLKMUX */
184 #define AIC31XX_PLL_CLKIN_MASK			0x0c
185 #define AIC31XX_PLL_CLKIN_SHIFT			2
186 #define AIC31XX_PLL_CLKIN_MCLK			0
187 #define AIC31XX_CODEC_CLKIN_MASK		0x03
188 #define AIC31XX_CODEC_CLKIN_SHIFT		0
189 #define AIC31XX_CODEC_CLKIN_PLL			3
190 #define AIC31XX_CODEC_CLKIN_BCLK		1
191 
192 /* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC,
193    AIC31XX_BCLKN */
194 #define AIC31XX_PLL_MASK		0x7f
195 #define AIC31XX_PM_MASK			0x80
196 
197 /* AIC31XX_IFACE1 */
198 #define AIC31XX_WORD_LEN_16BITS		0x00
199 #define AIC31XX_WORD_LEN_20BITS		0x01
200 #define AIC31XX_WORD_LEN_24BITS		0x02
201 #define AIC31XX_WORD_LEN_32BITS		0x03
202 #define AIC31XX_IFACE1_DATALEN_MASK	0x30
203 #define AIC31XX_IFACE1_DATALEN_SHIFT	(4)
204 #define AIC31XX_IFACE1_DATATYPE_MASK	0xC0
205 #define AIC31XX_IFACE1_DATATYPE_SHIFT	(6)
206 #define AIC31XX_I2S_MODE		0x00
207 #define AIC31XX_DSP_MODE		0x01
208 #define AIC31XX_RIGHT_JUSTIFIED_MODE	0x02
209 #define AIC31XX_LEFT_JUSTIFIED_MODE	0x03
210 #define AIC31XX_IFACE1_MASTER_MASK	0x0C
211 #define AIC31XX_BCLK_MASTER		0x08
212 #define AIC31XX_WCLK_MASTER		0x04
213 
214 /* AIC31XX_DATA_OFFSET */
215 #define AIC31XX_DATA_OFFSET_MASK	0xFF
216 
217 /* AIC31XX_IFACE2 */
218 #define AIC31XX_BCLKINV_MASK		0x08
219 #define AIC31XX_BDIVCLK_MASK		0x03
220 #define AIC31XX_DAC2BCLK		0x00
221 #define AIC31XX_DACMOD2BCLK		0x01
222 #define AIC31XX_ADC2BCLK		0x02
223 #define AIC31XX_ADCMOD2BCLK		0x03
224 
225 /* AIC31XX_ADCFLAG */
226 #define AIC31XX_ADCPWRSTATUS_MASK		0x40
227 
228 /* AIC31XX_DACFLAG1 */
229 #define AIC31XX_LDACPWRSTATUS_MASK		0x80
230 #define AIC31XX_RDACPWRSTATUS_MASK		0x08
231 #define AIC31XX_HPLDRVPWRSTATUS_MASK		0x20
232 #define AIC31XX_HPRDRVPWRSTATUS_MASK		0x02
233 #define AIC31XX_SPLDRVPWRSTATUS_MASK		0x10
234 #define AIC31XX_SPRDRVPWRSTATUS_MASK		0x01
235 
236 /* AIC31XX_INTRDACFLAG */
237 #define AIC31XX_HPSCDETECT_MASK			0x80
238 #define AIC31XX_BUTTONPRESS_MASK		0x20
239 #define AIC31XX_HSPLUG_MASK			0x10
240 #define AIC31XX_LDRCTHRES_MASK			0x08
241 #define AIC31XX_RDRCTHRES_MASK			0x04
242 #define AIC31XX_DACSINT_MASK			0x02
243 #define AIC31XX_DACAINT_MASK			0x01
244 
245 /* AIC31XX_INT1CTRL */
246 #define AIC31XX_HSPLUGDET_MASK			0x80
247 #define AIC31XX_BUTTONPRESSDET_MASK		0x40
248 #define AIC31XX_DRCTHRES_MASK			0x20
249 #define AIC31XX_AGCNOISE_MASK			0x10
250 #define AIC31XX_OC_MASK				0x08
251 #define AIC31XX_ENGINE_MASK			0x04
252 
253 /* AIC31XX_DACSETUP */
254 #define AIC31XX_SOFTSTEP_MASK			0x03
255 
256 /* AIC31XX_DACMUTE */
257 #define AIC31XX_DACMUTE_MASK			0x0C
258 
259 /* AIC31XX_MICBIAS */
260 #define AIC31XX_MICBIAS_MASK			0x03
261 #define AIC31XX_MICBIAS_SHIFT			0
262 
263 #endif	/* _TLV320AIC31XX_H */
264