1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC TLV320AIC31xx CODEC Driver 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ 6 * Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated 11 * high performance codecs which provides a stereo DAC, a mono ADC, 12 * and mono/stereo Class-D speaker driver. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/acpi.h> 24 #include <linux/of.h> 25 #include <linux/of_gpio.h> 26 #include <linux/slab.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <dt-bindings/sound/tlv320aic31xx-micbias.h> 34 35 #include "tlv320aic31xx.h" 36 37 static const struct reg_default aic31xx_reg_defaults[] = { 38 { AIC31XX_CLKMUX, 0x00 }, 39 { AIC31XX_PLLPR, 0x11 }, 40 { AIC31XX_PLLJ, 0x04 }, 41 { AIC31XX_PLLDMSB, 0x00 }, 42 { AIC31XX_PLLDLSB, 0x00 }, 43 { AIC31XX_NDAC, 0x01 }, 44 { AIC31XX_MDAC, 0x01 }, 45 { AIC31XX_DOSRMSB, 0x00 }, 46 { AIC31XX_DOSRLSB, 0x80 }, 47 { AIC31XX_NADC, 0x01 }, 48 { AIC31XX_MADC, 0x01 }, 49 { AIC31XX_AOSR, 0x80 }, 50 { AIC31XX_IFACE1, 0x00 }, 51 { AIC31XX_DATA_OFFSET, 0x00 }, 52 { AIC31XX_IFACE2, 0x00 }, 53 { AIC31XX_BCLKN, 0x01 }, 54 { AIC31XX_DACSETUP, 0x14 }, 55 { AIC31XX_DACMUTE, 0x0c }, 56 { AIC31XX_LDACVOL, 0x00 }, 57 { AIC31XX_RDACVOL, 0x00 }, 58 { AIC31XX_ADCSETUP, 0x00 }, 59 { AIC31XX_ADCFGA, 0x80 }, 60 { AIC31XX_ADCVOL, 0x00 }, 61 { AIC31XX_HPDRIVER, 0x04 }, 62 { AIC31XX_SPKAMP, 0x06 }, 63 { AIC31XX_DACMIXERROUTE, 0x00 }, 64 { AIC31XX_LANALOGHPL, 0x7f }, 65 { AIC31XX_RANALOGHPR, 0x7f }, 66 { AIC31XX_LANALOGSPL, 0x7f }, 67 { AIC31XX_RANALOGSPR, 0x7f }, 68 { AIC31XX_HPLGAIN, 0x02 }, 69 { AIC31XX_HPRGAIN, 0x02 }, 70 { AIC31XX_SPLGAIN, 0x00 }, 71 { AIC31XX_SPRGAIN, 0x00 }, 72 { AIC31XX_MICBIAS, 0x00 }, 73 { AIC31XX_MICPGA, 0x80 }, 74 { AIC31XX_MICPGAPI, 0x00 }, 75 { AIC31XX_MICPGAMI, 0x00 }, 76 }; 77 78 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 79 { 80 switch (reg) { 81 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 82 case AIC31XX_RESET: /* always clears after write */ 83 case AIC31XX_OT_FLAG: 84 case AIC31XX_ADCFLAG: 85 case AIC31XX_DACFLAG1: 86 case AIC31XX_DACFLAG2: 87 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 88 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 89 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 90 case AIC31XX_INTRDACFLAG2: 91 case AIC31XX_INTRADCFLAG2: 92 return true; 93 } 94 return false; 95 } 96 97 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 98 { 99 switch (reg) { 100 case AIC31XX_OT_FLAG: 101 case AIC31XX_ADCFLAG: 102 case AIC31XX_DACFLAG1: 103 case AIC31XX_DACFLAG2: 104 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 105 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 106 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 107 case AIC31XX_INTRDACFLAG2: 108 case AIC31XX_INTRADCFLAG2: 109 return false; 110 } 111 return true; 112 } 113 114 static const struct regmap_range_cfg aic31xx_ranges[] = { 115 { 116 .range_min = 0, 117 .range_max = 12 * 128, 118 .selector_reg = AIC31XX_PAGECTL, 119 .selector_mask = 0xff, 120 .selector_shift = 0, 121 .window_start = 0, 122 .window_len = 128, 123 }, 124 }; 125 126 static const struct regmap_config aic31xx_i2c_regmap = { 127 .reg_bits = 8, 128 .val_bits = 8, 129 .writeable_reg = aic31xx_writeable, 130 .volatile_reg = aic31xx_volatile, 131 .reg_defaults = aic31xx_reg_defaults, 132 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 133 .cache_type = REGCACHE_RBTREE, 134 .ranges = aic31xx_ranges, 135 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 136 .max_register = 12 * 128, 137 }; 138 139 static const char * const aic31xx_supply_names[] = { 140 "HPVDD", 141 "SPRVDD", 142 "SPLVDD", 143 "AVDD", 144 "IOVDD", 145 "DVDD", 146 }; 147 148 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names) 149 150 struct aic31xx_disable_nb { 151 struct notifier_block nb; 152 struct aic31xx_priv *aic31xx; 153 }; 154 155 struct aic31xx_priv { 156 struct snd_soc_component *component; 157 u8 i2c_regs_status; 158 struct device *dev; 159 struct regmap *regmap; 160 enum aic31xx_type codec_type; 161 struct gpio_desc *gpio_reset; 162 int micbias_vg; 163 struct aic31xx_pdata pdata; 164 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 165 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 166 unsigned int sysclk; 167 u8 p_div; 168 int rate_div_line; 169 bool master_dapm_route_applied; 170 int irq; 171 }; 172 173 struct aic31xx_rate_divs { 174 u32 mclk_p; 175 u32 rate; 176 u8 pll_j; 177 u16 pll_d; 178 u16 dosr; 179 u8 ndac; 180 u8 mdac; 181 u8 aosr; 182 u8 nadc; 183 u8 madc; 184 }; 185 186 /* ADC dividers can be disabled by configuring them to 0 */ 187 static const struct aic31xx_rate_divs aic31xx_divs[] = { 188 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */ 189 /* 8k rate */ 190 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2}, 191 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3}, 192 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2}, 193 /* 11.025k rate */ 194 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2}, 195 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3}, 196 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2}, 197 /* 16k rate */ 198 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2}, 199 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3}, 200 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2}, 201 /* 22.05k rate */ 202 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2}, 203 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3}, 204 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2}, 205 /* 32k rate */ 206 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2}, 207 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3}, 208 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2}, 209 /* 44.1k rate */ 210 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2}, 211 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3}, 212 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2}, 213 /* 48k rate */ 214 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2}, 215 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4}, 216 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2}, 217 /* 88.2k rate */ 218 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2}, 219 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3}, 220 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2}, 221 /* 96k rate */ 222 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2}, 223 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4}, 224 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2}, 225 /* 176.4k rate */ 226 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2}, 227 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3}, 228 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2}, 229 /* 192k rate */ 230 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2}, 231 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4}, 232 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2}, 233 }; 234 235 static const char * const ldac_in_text[] = { 236 "Off", "Left Data", "Right Data", "Mono" 237 }; 238 239 static const char * const rdac_in_text[] = { 240 "Off", "Right Data", "Left Data", "Mono" 241 }; 242 243 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 244 245 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 246 247 static const char * const mic_select_text[] = { 248 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 249 }; 250 251 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, 252 mic_select_text); 253 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, 254 mic_select_text); 255 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, 256 mic_select_text); 257 258 static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text); 259 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, 260 mic_select_text); 261 262 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 263 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 264 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 265 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 266 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 267 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 268 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 269 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 270 271 /* 272 * controls to be exported to the user space 273 */ 274 static const struct snd_kcontrol_new common31xx_snd_controls[] = { 275 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 276 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 277 278 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 279 AIC31XX_HPRGAIN, 2, 1, 0), 280 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 281 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 282 283 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 284 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 285 }; 286 287 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 288 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 289 adc_fgain_tlv), 290 291 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 292 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 293 0, -24, 40, 6, 0, adc_cgain_tlv), 294 295 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 296 119, 0, mic_pga_tlv), 297 }; 298 299 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 300 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 301 AIC31XX_SPRGAIN, 2, 1, 0), 302 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 303 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 304 305 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 306 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 307 }; 308 309 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 310 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 311 2, 1, 0), 312 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 313 3, 3, 0, class_D_drv_tlv), 314 315 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 316 0, 0x7F, 1, sp_vol_tlv), 317 }; 318 319 static const struct snd_kcontrol_new ldac_in_control = 320 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 321 322 static const struct snd_kcontrol_new rdac_in_control = 323 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 324 325 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 326 unsigned int mask, unsigned int wbits, int sleep, 327 int count) 328 { 329 unsigned int bits; 330 int counter = count; 331 int ret = regmap_read(aic31xx->regmap, reg, &bits); 332 333 while ((bits & mask) != wbits && counter && !ret) { 334 usleep_range(sleep, sleep * 2); 335 ret = regmap_read(aic31xx->regmap, reg, &bits); 336 counter--; 337 } 338 if ((bits & mask) != wbits) { 339 dev_err(aic31xx->dev, 340 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 341 __func__, reg, bits, wbits, ret, mask, 342 (count - counter) * sleep); 343 ret = -1; 344 } 345 return ret; 346 } 347 348 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 349 350 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 351 struct snd_kcontrol *kcontrol, int event) 352 { 353 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 354 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 355 unsigned int reg = AIC31XX_DACFLAG1; 356 unsigned int mask; 357 358 switch (WIDGET_BIT(w->reg, w->shift)) { 359 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 360 mask = AIC31XX_LDACPWRSTATUS_MASK; 361 break; 362 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 363 mask = AIC31XX_RDACPWRSTATUS_MASK; 364 break; 365 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 366 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 367 break; 368 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 369 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 370 break; 371 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 372 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 373 break; 374 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 375 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 376 break; 377 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 378 mask = AIC31XX_ADCPWRSTATUS_MASK; 379 reg = AIC31XX_ADCFLAG; 380 break; 381 default: 382 dev_err(component->dev, "Unknown widget '%s' calling %s\n", 383 w->name, __func__); 384 return -EINVAL; 385 } 386 387 switch (event) { 388 case SND_SOC_DAPM_POST_PMU: 389 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); 390 case SND_SOC_DAPM_POST_PMD: 391 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); 392 default: 393 dev_dbg(component->dev, 394 "Unhandled dapm widget event %d from %s\n", 395 event, w->name); 396 } 397 return 0; 398 } 399 400 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = { 401 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 402 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 403 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 404 }; 405 406 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = { 407 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 408 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 409 }; 410 411 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = { 412 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 413 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0), 414 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0), 415 }; 416 417 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = { 418 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 419 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0), 420 }; 421 422 static const struct snd_kcontrol_new p_term_mic1lp = 423 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 424 425 static const struct snd_kcontrol_new p_term_mic1rp = 426 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 427 428 static const struct snd_kcontrol_new p_term_mic1lm = 429 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 430 431 static const struct snd_kcontrol_new m_term_mic1lm = 432 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 433 434 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 435 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 436 437 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 438 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 439 440 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 441 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 442 443 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 444 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 445 446 static int mic_bias_event(struct snd_soc_dapm_widget *w, 447 struct snd_kcontrol *kcontrol, int event) 448 { 449 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 450 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 451 452 switch (event) { 453 case SND_SOC_DAPM_POST_PMU: 454 /* change mic bias voltage to user defined */ 455 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 456 AIC31XX_MICBIAS_MASK, 457 aic31xx->micbias_vg << 458 AIC31XX_MICBIAS_SHIFT); 459 dev_dbg(component->dev, "%s: turned on\n", __func__); 460 break; 461 case SND_SOC_DAPM_PRE_PMD: 462 /* turn mic bias off */ 463 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 464 AIC31XX_MICBIAS_MASK, 0); 465 dev_dbg(component->dev, "%s: turned off\n", __func__); 466 break; 467 } 468 return 0; 469 } 470 471 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = { 472 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 473 474 SND_SOC_DAPM_MUX("DAC Left Input", 475 SND_SOC_NOPM, 0, 0, &ldac_in_control), 476 SND_SOC_DAPM_MUX("DAC Right Input", 477 SND_SOC_NOPM, 0, 0, &rdac_in_control), 478 /* DACs */ 479 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 480 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 481 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 482 483 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 484 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 485 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 486 487 /* HP */ 488 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 489 &aic31xx_dapm_hpl_switch), 490 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 491 &aic31xx_dapm_hpr_switch), 492 493 /* Output drivers */ 494 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 495 NULL, 0, aic31xx_dapm_power_event, 496 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 497 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 498 NULL, 0, aic31xx_dapm_power_event, 499 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 500 501 /* Mic Bias */ 502 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 503 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 504 505 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */ 506 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0, 507 NULL, 0), 508 509 /* Outputs */ 510 SND_SOC_DAPM_OUTPUT("HPL"), 511 SND_SOC_DAPM_OUTPUT("HPR"), 512 }; 513 514 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = { 515 /* Inputs */ 516 SND_SOC_DAPM_INPUT("AIN1"), 517 SND_SOC_DAPM_INPUT("AIN2"), 518 519 /* Output Mixers */ 520 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 521 dac31xx_left_output_switches, 522 ARRAY_SIZE(dac31xx_left_output_switches)), 523 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 524 dac31xx_right_output_switches, 525 ARRAY_SIZE(dac31xx_right_output_switches)), 526 }; 527 528 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 529 /* Inputs */ 530 SND_SOC_DAPM_INPUT("MIC1LP"), 531 SND_SOC_DAPM_INPUT("MIC1RP"), 532 SND_SOC_DAPM_INPUT("MIC1LM"), 533 534 /* Input Selection to MIC_PGA */ 535 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 536 &p_term_mic1lp), 537 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 538 &p_term_mic1rp), 539 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 540 &p_term_mic1lm), 541 542 /* ADC */ 543 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 544 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 545 SND_SOC_DAPM_POST_PMD), 546 547 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 548 &m_term_mic1lm), 549 550 /* Enabling & Disabling MIC Gain Ctl */ 551 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 552 7, 1, NULL, 0), 553 554 /* Output Mixers */ 555 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 556 aic31xx_left_output_switches, 557 ARRAY_SIZE(aic31xx_left_output_switches)), 558 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 559 aic31xx_right_output_switches, 560 ARRAY_SIZE(aic31xx_right_output_switches)), 561 562 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 563 }; 564 565 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 566 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 567 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 568 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 569 SND_SOC_DAPM_POST_PMD), 570 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 571 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 572 SND_SOC_DAPM_POST_PMD), 573 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 574 &aic31xx_dapm_spl_switch), 575 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 576 &aic31xx_dapm_spr_switch), 577 SND_SOC_DAPM_OUTPUT("SPL"), 578 SND_SOC_DAPM_OUTPUT("SPR"), 579 }; 580 581 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 582 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 583 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 584 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 585 SND_SOC_DAPM_POST_PMD), 586 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 587 &aic31xx_dapm_spl_switch), 588 SND_SOC_DAPM_OUTPUT("SPK"), 589 }; 590 591 static const struct snd_soc_dapm_route 592 common31xx_audio_map[] = { 593 /* DAC Input Routing */ 594 {"DAC Left Input", "Left Data", "AIF IN"}, 595 {"DAC Left Input", "Right Data", "AIF IN"}, 596 {"DAC Left Input", "Mono", "AIF IN"}, 597 {"DAC Right Input", "Left Data", "AIF IN"}, 598 {"DAC Right Input", "Right Data", "AIF IN"}, 599 {"DAC Right Input", "Mono", "AIF IN"}, 600 {"DAC Left", NULL, "DAC Left Input"}, 601 {"DAC Right", NULL, "DAC Right Input"}, 602 603 /* HPL path */ 604 {"HP Left", "Switch", "Output Left"}, 605 {"HPL Driver", NULL, "HP Left"}, 606 {"HPL", NULL, "HPL Driver"}, 607 608 /* HPR path */ 609 {"HP Right", "Switch", "Output Right"}, 610 {"HPR Driver", NULL, "HP Right"}, 611 {"HPR", NULL, "HPR Driver"}, 612 }; 613 614 static const struct snd_soc_dapm_route 615 dac31xx_audio_map[] = { 616 /* Left Output */ 617 {"Output Left", "From Left DAC", "DAC Left"}, 618 {"Output Left", "From AIN1", "AIN1"}, 619 {"Output Left", "From AIN2", "AIN2"}, 620 621 /* Right Output */ 622 {"Output Right", "From Right DAC", "DAC Right"}, 623 {"Output Right", "From AIN2", "AIN2"}, 624 }; 625 626 static const struct snd_soc_dapm_route 627 aic31xx_audio_map[] = { 628 /* Mic input */ 629 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 630 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 631 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 632 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 633 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 634 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 635 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 636 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 637 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 638 639 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 640 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 641 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 642 643 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 644 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 645 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 646 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 647 648 {"ADC", NULL, "MIC_GAIN_CTL"}, 649 650 {"AIF OUT", NULL, "ADC"}, 651 652 /* Left Output */ 653 {"Output Left", "From Left DAC", "DAC Left"}, 654 {"Output Left", "From MIC1LP", "MIC1LP"}, 655 {"Output Left", "From MIC1RP", "MIC1RP"}, 656 657 /* Right Output */ 658 {"Output Right", "From Right DAC", "DAC Right"}, 659 {"Output Right", "From MIC1RP", "MIC1RP"}, 660 }; 661 662 static const struct snd_soc_dapm_route 663 aic311x_audio_map[] = { 664 /* SP L path */ 665 {"Speaker Left", "Switch", "Output Left"}, 666 {"SPL ClassD", NULL, "Speaker Left"}, 667 {"SPL", NULL, "SPL ClassD"}, 668 669 /* SP R path */ 670 {"Speaker Right", "Switch", "Output Right"}, 671 {"SPR ClassD", NULL, "Speaker Right"}, 672 {"SPR", NULL, "SPR ClassD"}, 673 }; 674 675 static const struct snd_soc_dapm_route 676 aic310x_audio_map[] = { 677 /* SP L path */ 678 {"Speaker", "Switch", "Output Left"}, 679 {"SPK ClassD", NULL, "Speaker"}, 680 {"SPK", NULL, "SPK ClassD"}, 681 }; 682 683 /* 684 * Always connected DAPM routes for codec clock master modes. 685 * If the codec is the master on the I2S bus, we need to power up components 686 * to have valid DAC_CLK. 687 * 688 * In order to have the I2S clocks on the bus either the DACs/ADC need to be 689 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set. 690 * 691 * Otherwise the codec will not generate clocks on the bus. 692 */ 693 static const struct snd_soc_dapm_route 694 common31xx_cm_audio_map[] = { 695 {"HPL", NULL, "AIF IN"}, 696 {"HPR", NULL, "AIF IN"}, 697 698 {"AIF IN", NULL, "Activate I2S clocks"}, 699 }; 700 701 static const struct snd_soc_dapm_route 702 aic31xx_cm_audio_map[] = { 703 {"AIF OUT", NULL, "MIC1LP"}, 704 {"AIF OUT", NULL, "MIC1RP"}, 705 {"AIF OUT", NULL, "MIC1LM"}, 706 707 {"AIF OUT", NULL, "Activate I2S clocks"}, 708 }; 709 710 static int aic31xx_add_controls(struct snd_soc_component *component) 711 { 712 int ret = 0; 713 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 714 715 if (!(aic31xx->codec_type & DAC31XX_BIT)) 716 ret = snd_soc_add_component_controls( 717 component, aic31xx_snd_controls, 718 ARRAY_SIZE(aic31xx_snd_controls)); 719 if (ret) 720 return ret; 721 722 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) 723 ret = snd_soc_add_component_controls( 724 component, aic311x_snd_controls, 725 ARRAY_SIZE(aic311x_snd_controls)); 726 else 727 ret = snd_soc_add_component_controls( 728 component, aic310x_snd_controls, 729 ARRAY_SIZE(aic310x_snd_controls)); 730 731 return ret; 732 } 733 734 static int aic31xx_add_widgets(struct snd_soc_component *component) 735 { 736 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 737 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 738 int ret = 0; 739 740 if (aic31xx->codec_type & DAC31XX_BIT) { 741 ret = snd_soc_dapm_new_controls( 742 dapm, dac31xx_dapm_widgets, 743 ARRAY_SIZE(dac31xx_dapm_widgets)); 744 if (ret) 745 return ret; 746 747 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map, 748 ARRAY_SIZE(dac31xx_audio_map)); 749 if (ret) 750 return ret; 751 } else { 752 ret = snd_soc_dapm_new_controls( 753 dapm, aic31xx_dapm_widgets, 754 ARRAY_SIZE(aic31xx_dapm_widgets)); 755 if (ret) 756 return ret; 757 758 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map, 759 ARRAY_SIZE(aic31xx_audio_map)); 760 if (ret) 761 return ret; 762 } 763 764 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 765 ret = snd_soc_dapm_new_controls( 766 dapm, aic311x_dapm_widgets, 767 ARRAY_SIZE(aic311x_dapm_widgets)); 768 if (ret) 769 return ret; 770 771 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 772 ARRAY_SIZE(aic311x_audio_map)); 773 if (ret) 774 return ret; 775 } else { 776 ret = snd_soc_dapm_new_controls( 777 dapm, aic310x_dapm_widgets, 778 ARRAY_SIZE(aic310x_dapm_widgets)); 779 if (ret) 780 return ret; 781 782 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 783 ARRAY_SIZE(aic310x_audio_map)); 784 if (ret) 785 return ret; 786 } 787 788 return 0; 789 } 790 791 static int aic31xx_setup_pll(struct snd_soc_component *component, 792 struct snd_pcm_hw_params *params) 793 { 794 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 795 int bclk_score = snd_soc_params_to_frame_size(params); 796 int mclk_p; 797 int bclk_n = 0; 798 int match = -1; 799 int i; 800 801 if (!aic31xx->sysclk || !aic31xx->p_div) { 802 dev_err(component->dev, "Master clock not supplied\n"); 803 return -EINVAL; 804 } 805 mclk_p = aic31xx->sysclk / aic31xx->p_div; 806 807 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 808 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, 809 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 810 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 811 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 812 813 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 814 if (aic31xx_divs[i].rate == params_rate(params) && 815 aic31xx_divs[i].mclk_p == mclk_p) { 816 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 817 snd_soc_params_to_frame_size(params); 818 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 819 snd_soc_params_to_frame_size(params); 820 if (s < bclk_score && bn > 0) { 821 match = i; 822 bclk_n = bn; 823 bclk_score = s; 824 } 825 } 826 } 827 828 if (match == -1) { 829 dev_err(component->dev, 830 "%s: Sample rate (%u) and format not supported\n", 831 __func__, params_rate(params)); 832 /* See bellow for details how fix this. */ 833 return -EINVAL; 834 } 835 if (bclk_score != 0) { 836 dev_warn(component->dev, "Can not produce exact bitclock"); 837 /* This is fine if using dsp format, but if using i2s 838 there may be trouble. To fix the issue edit the 839 aic31xx_divs table for your mclk and sample 840 rate. Details can be found from: 841 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf 842 Section: 5.6 CLOCK Generation and PLL 843 */ 844 } 845 i = match; 846 847 /* PLL configuration */ 848 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 849 (aic31xx->p_div << 4) | 0x01); 850 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 851 852 snd_soc_component_write(component, AIC31XX_PLLDMSB, 853 aic31xx_divs[i].pll_d >> 8); 854 snd_soc_component_write(component, AIC31XX_PLLDLSB, 855 aic31xx_divs[i].pll_d & 0xff); 856 857 /* DAC dividers configuration */ 858 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK, 859 aic31xx_divs[i].ndac); 860 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK, 861 aic31xx_divs[i].mdac); 862 863 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 864 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 865 866 /* ADC dividers configuration. Write reset value 1 if not used. */ 867 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK, 868 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 869 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK, 870 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 871 872 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr); 873 874 /* Bit clock divider configuration. */ 875 snd_soc_component_update_bits(component, AIC31XX_BCLKN, 876 AIC31XX_PLL_MASK, bclk_n); 877 878 aic31xx->rate_div_line = i; 879 880 dev_dbg(component->dev, 881 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 882 aic31xx_divs[i].pll_j, 883 aic31xx_divs[i].pll_d, 884 aic31xx->p_div, 885 aic31xx_divs[i].dosr, 886 aic31xx_divs[i].ndac, 887 aic31xx_divs[i].mdac, 888 aic31xx_divs[i].aosr, 889 aic31xx_divs[i].nadc, 890 aic31xx_divs[i].madc, 891 bclk_n 892 ); 893 894 return 0; 895 } 896 897 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 898 struct snd_pcm_hw_params *params, 899 struct snd_soc_dai *dai) 900 { 901 struct snd_soc_component *component = dai->component; 902 u8 data = 0; 903 904 dev_dbg(component->dev, "## %s: width %d rate %d\n", 905 __func__, params_width(params), 906 params_rate(params)); 907 908 switch (params_width(params)) { 909 case 16: 910 break; 911 case 20: 912 data = (AIC31XX_WORD_LEN_20BITS << 913 AIC31XX_IFACE1_DATALEN_SHIFT); 914 break; 915 case 24: 916 data = (AIC31XX_WORD_LEN_24BITS << 917 AIC31XX_IFACE1_DATALEN_SHIFT); 918 break; 919 case 32: 920 data = (AIC31XX_WORD_LEN_32BITS << 921 AIC31XX_IFACE1_DATALEN_SHIFT); 922 break; 923 default: 924 dev_err(component->dev, "%s: Unsupported width %d\n", 925 __func__, params_width(params)); 926 return -EINVAL; 927 } 928 929 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 930 AIC31XX_IFACE1_DATALEN_MASK, 931 data); 932 933 return aic31xx_setup_pll(component, params); 934 } 935 936 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute) 937 { 938 struct snd_soc_component *component = codec_dai->component; 939 940 if (mute) { 941 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 942 AIC31XX_DACMUTE_MASK, 943 AIC31XX_DACMUTE_MASK); 944 } else { 945 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 946 AIC31XX_DACMUTE_MASK, 0x0); 947 } 948 949 return 0; 950 } 951 952 static int aic31xx_clock_master_routes(struct snd_soc_component *component, 953 unsigned int fmt) 954 { 955 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 956 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 957 int ret; 958 959 fmt &= SND_SOC_DAIFMT_MASTER_MASK; 960 if (fmt == SND_SOC_DAIFMT_CBS_CFS && 961 aic31xx->master_dapm_route_applied) { 962 /* 963 * Remove the DAPM route(s) for codec clock master modes, 964 * if applied 965 */ 966 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map, 967 ARRAY_SIZE(common31xx_cm_audio_map)); 968 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 969 ret = snd_soc_dapm_del_routes(dapm, 970 aic31xx_cm_audio_map, 971 ARRAY_SIZE(aic31xx_cm_audio_map)); 972 973 if (ret) 974 return ret; 975 976 aic31xx->master_dapm_route_applied = false; 977 } else if (fmt != SND_SOC_DAIFMT_CBS_CFS && 978 !aic31xx->master_dapm_route_applied) { 979 /* 980 * Add the needed DAPM route(s) for codec clock master modes, 981 * if it is not done already 982 */ 983 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map, 984 ARRAY_SIZE(common31xx_cm_audio_map)); 985 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 986 ret = snd_soc_dapm_add_routes(dapm, 987 aic31xx_cm_audio_map, 988 ARRAY_SIZE(aic31xx_cm_audio_map)); 989 990 if (ret) 991 return ret; 992 993 aic31xx->master_dapm_route_applied = true; 994 } 995 996 return 0; 997 } 998 999 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1000 unsigned int fmt) 1001 { 1002 struct snd_soc_component *component = codec_dai->component; 1003 u8 iface_reg1 = 0; 1004 u8 iface_reg2 = 0; 1005 u8 dsp_a_val = 0; 1006 1007 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 1008 1009 /* set master/slave audio interface */ 1010 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1011 case SND_SOC_DAIFMT_CBM_CFM: 1012 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 1013 break; 1014 case SND_SOC_DAIFMT_CBS_CFM: 1015 iface_reg1 |= AIC31XX_WCLK_MASTER; 1016 break; 1017 case SND_SOC_DAIFMT_CBM_CFS: 1018 iface_reg1 |= AIC31XX_BCLK_MASTER; 1019 break; 1020 case SND_SOC_DAIFMT_CBS_CFS: 1021 break; 1022 default: 1023 dev_err(component->dev, "Invalid DAI master/slave interface\n"); 1024 return -EINVAL; 1025 } 1026 1027 /* signal polarity */ 1028 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1029 case SND_SOC_DAIFMT_NB_NF: 1030 break; 1031 case SND_SOC_DAIFMT_IB_NF: 1032 iface_reg2 |= AIC31XX_BCLKINV_MASK; 1033 break; 1034 default: 1035 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 1036 return -EINVAL; 1037 } 1038 1039 /* interface format */ 1040 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1041 case SND_SOC_DAIFMT_I2S: 1042 break; 1043 case SND_SOC_DAIFMT_DSP_A: 1044 dsp_a_val = 0x1; /* fall through */ 1045 case SND_SOC_DAIFMT_DSP_B: 1046 /* 1047 * NOTE: This CODEC samples on the falling edge of BCLK in 1048 * DSP mode, this is inverted compared to what most DAIs 1049 * expect, so we invert for this mode 1050 */ 1051 iface_reg2 ^= AIC31XX_BCLKINV_MASK; 1052 iface_reg1 |= (AIC31XX_DSP_MODE << 1053 AIC31XX_IFACE1_DATATYPE_SHIFT); 1054 break; 1055 case SND_SOC_DAIFMT_RIGHT_J: 1056 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 1057 AIC31XX_IFACE1_DATATYPE_SHIFT); 1058 break; 1059 case SND_SOC_DAIFMT_LEFT_J: 1060 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 1061 AIC31XX_IFACE1_DATATYPE_SHIFT); 1062 break; 1063 default: 1064 dev_err(component->dev, "Invalid DAI interface format\n"); 1065 return -EINVAL; 1066 } 1067 1068 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 1069 AIC31XX_IFACE1_DATATYPE_MASK | 1070 AIC31XX_IFACE1_MASTER_MASK, 1071 iface_reg1); 1072 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET, 1073 AIC31XX_DATA_OFFSET_MASK, 1074 dsp_a_val); 1075 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 1076 AIC31XX_BCLKINV_MASK, 1077 iface_reg2); 1078 1079 return aic31xx_clock_master_routes(component, fmt); 1080 } 1081 1082 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1083 int clk_id, unsigned int freq, int dir) 1084 { 1085 struct snd_soc_component *component = codec_dai->component; 1086 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1087 int i; 1088 1089 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 1090 __func__, clk_id, freq, dir); 1091 1092 for (i = 1; i < 8; i++) 1093 if (freq / i <= 20000000) 1094 break; 1095 if (freq/i > 20000000) { 1096 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", 1097 __func__, freq); 1098 return -EINVAL; 1099 } 1100 aic31xx->p_div = i; 1101 1102 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) 1103 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div) 1104 break; 1105 if (i == ARRAY_SIZE(aic31xx_divs)) { 1106 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 1107 __func__, freq); 1108 return -EINVAL; 1109 } 1110 1111 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 1112 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 1113 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 1114 1115 aic31xx->sysclk = freq; 1116 1117 return 0; 1118 } 1119 1120 static int aic31xx_regulator_event(struct notifier_block *nb, 1121 unsigned long event, void *data) 1122 { 1123 struct aic31xx_disable_nb *disable_nb = 1124 container_of(nb, struct aic31xx_disable_nb, nb); 1125 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 1126 1127 if (event & REGULATOR_EVENT_DISABLE) { 1128 /* 1129 * Put codec to reset and as at least one of the 1130 * supplies was disabled. 1131 */ 1132 if (aic31xx->gpio_reset) 1133 gpiod_set_value(aic31xx->gpio_reset, 1); 1134 1135 regcache_mark_dirty(aic31xx->regmap); 1136 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 1137 } 1138 1139 return 0; 1140 } 1141 1142 static int aic31xx_reset(struct aic31xx_priv *aic31xx) 1143 { 1144 int ret = 0; 1145 1146 if (aic31xx->gpio_reset) { 1147 gpiod_set_value(aic31xx->gpio_reset, 1); 1148 ndelay(10); /* At least 10ns */ 1149 gpiod_set_value(aic31xx->gpio_reset, 0); 1150 } else { 1151 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1); 1152 } 1153 mdelay(1); /* At least 1ms */ 1154 1155 return ret; 1156 } 1157 1158 static void aic31xx_clk_on(struct snd_soc_component *component) 1159 { 1160 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1161 u8 mask = AIC31XX_PM_MASK; 1162 u8 on = AIC31XX_PM_MASK; 1163 1164 dev_dbg(component->dev, "codec clock -> on (rate %d)\n", 1165 aic31xx_divs[aic31xx->rate_div_line].rate); 1166 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on); 1167 mdelay(10); 1168 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on); 1169 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on); 1170 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 1171 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on); 1172 if (aic31xx_divs[aic31xx->rate_div_line].madc) 1173 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on); 1174 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on); 1175 } 1176 1177 static void aic31xx_clk_off(struct snd_soc_component *component) 1178 { 1179 u8 mask = AIC31XX_PM_MASK; 1180 u8 off = 0; 1181 1182 dev_dbg(component->dev, "codec clock -> off\n"); 1183 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off); 1184 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off); 1185 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off); 1186 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off); 1187 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off); 1188 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off); 1189 } 1190 1191 static int aic31xx_power_on(struct snd_soc_component *component) 1192 { 1193 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1194 int ret; 1195 1196 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 1197 aic31xx->supplies); 1198 if (ret) 1199 return ret; 1200 1201 regcache_cache_only(aic31xx->regmap, false); 1202 1203 /* Reset device registers for a consistent power-on like state */ 1204 ret = aic31xx_reset(aic31xx); 1205 if (ret < 0) 1206 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret); 1207 1208 ret = regcache_sync(aic31xx->regmap); 1209 if (ret) { 1210 dev_err(component->dev, 1211 "Failed to restore cache: %d\n", ret); 1212 regcache_cache_only(aic31xx->regmap, true); 1213 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1214 aic31xx->supplies); 1215 return ret; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static void aic31xx_power_off(struct snd_soc_component *component) 1222 { 1223 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1224 1225 regcache_cache_only(aic31xx->regmap, true); 1226 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1227 aic31xx->supplies); 1228 } 1229 1230 static int aic31xx_set_bias_level(struct snd_soc_component *component, 1231 enum snd_soc_bias_level level) 1232 { 1233 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__, 1234 snd_soc_component_get_bias_level(component), level); 1235 1236 switch (level) { 1237 case SND_SOC_BIAS_ON: 1238 break; 1239 case SND_SOC_BIAS_PREPARE: 1240 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1241 aic31xx_clk_on(component); 1242 break; 1243 case SND_SOC_BIAS_STANDBY: 1244 switch (snd_soc_component_get_bias_level(component)) { 1245 case SND_SOC_BIAS_OFF: 1246 aic31xx_power_on(component); 1247 break; 1248 case SND_SOC_BIAS_PREPARE: 1249 aic31xx_clk_off(component); 1250 break; 1251 default: 1252 BUG(); 1253 } 1254 break; 1255 case SND_SOC_BIAS_OFF: 1256 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1257 aic31xx_power_off(component); 1258 break; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static int aic31xx_codec_probe(struct snd_soc_component *component) 1265 { 1266 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1267 int i, ret; 1268 1269 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1270 1271 aic31xx->component = component; 1272 1273 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1274 aic31xx->disable_nb[i].nb.notifier_call = 1275 aic31xx_regulator_event; 1276 aic31xx->disable_nb[i].aic31xx = aic31xx; 1277 ret = regulator_register_notifier(aic31xx->supplies[i].consumer, 1278 &aic31xx->disable_nb[i].nb); 1279 if (ret) { 1280 dev_err(component->dev, 1281 "Failed to request regulator notifier: %d\n", 1282 ret); 1283 return ret; 1284 } 1285 } 1286 1287 regcache_cache_only(aic31xx->regmap, true); 1288 regcache_mark_dirty(aic31xx->regmap); 1289 1290 ret = aic31xx_add_controls(component); 1291 if (ret) 1292 return ret; 1293 1294 ret = aic31xx_add_widgets(component); 1295 if (ret) 1296 return ret; 1297 1298 return 0; 1299 } 1300 1301 static void aic31xx_codec_remove(struct snd_soc_component *component) 1302 { 1303 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1304 int i; 1305 1306 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1307 regulator_unregister_notifier(aic31xx->supplies[i].consumer, 1308 &aic31xx->disable_nb[i].nb); 1309 } 1310 1311 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = { 1312 .probe = aic31xx_codec_probe, 1313 .remove = aic31xx_codec_remove, 1314 .set_bias_level = aic31xx_set_bias_level, 1315 .controls = common31xx_snd_controls, 1316 .num_controls = ARRAY_SIZE(common31xx_snd_controls), 1317 .dapm_widgets = common31xx_dapm_widgets, 1318 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets), 1319 .dapm_routes = common31xx_audio_map, 1320 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map), 1321 .suspend_bias_off = 1, 1322 .idle_bias_on = 1, 1323 .use_pmdown_time = 1, 1324 .endianness = 1, 1325 .non_legacy_dai_naming = 1, 1326 }; 1327 1328 static const struct snd_soc_dai_ops aic31xx_dai_ops = { 1329 .hw_params = aic31xx_hw_params, 1330 .set_sysclk = aic31xx_set_dai_sysclk, 1331 .set_fmt = aic31xx_set_dai_fmt, 1332 .digital_mute = aic31xx_dac_mute, 1333 }; 1334 1335 static struct snd_soc_dai_driver dac31xx_dai_driver[] = { 1336 { 1337 .name = "tlv320dac31xx-hifi", 1338 .playback = { 1339 .stream_name = "Playback", 1340 .channels_min = 2, 1341 .channels_max = 2, 1342 .rates = AIC31XX_RATES, 1343 .formats = AIC31XX_FORMATS, 1344 }, 1345 .ops = &aic31xx_dai_ops, 1346 .symmetric_rates = 1, 1347 } 1348 }; 1349 1350 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1351 { 1352 .name = "tlv320aic31xx-hifi", 1353 .playback = { 1354 .stream_name = "Playback", 1355 .channels_min = 2, 1356 .channels_max = 2, 1357 .rates = AIC31XX_RATES, 1358 .formats = AIC31XX_FORMATS, 1359 }, 1360 .capture = { 1361 .stream_name = "Capture", 1362 .channels_min = 2, 1363 .channels_max = 2, 1364 .rates = AIC31XX_RATES, 1365 .formats = AIC31XX_FORMATS, 1366 }, 1367 .ops = &aic31xx_dai_ops, 1368 .symmetric_rates = 1, 1369 } 1370 }; 1371 1372 #if defined(CONFIG_OF) 1373 static const struct of_device_id tlv320aic31xx_of_match[] = { 1374 { .compatible = "ti,tlv320aic310x" }, 1375 { .compatible = "ti,tlv320aic311x" }, 1376 { .compatible = "ti,tlv320aic3100" }, 1377 { .compatible = "ti,tlv320aic3110" }, 1378 { .compatible = "ti,tlv320aic3120" }, 1379 { .compatible = "ti,tlv320aic3111" }, 1380 { .compatible = "ti,tlv320dac3100" }, 1381 { .compatible = "ti,tlv320dac3101" }, 1382 {}, 1383 }; 1384 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1385 #endif /* CONFIG_OF */ 1386 1387 #ifdef CONFIG_ACPI 1388 static const struct acpi_device_id aic31xx_acpi_match[] = { 1389 { "10TI3100", 0 }, 1390 { } 1391 }; 1392 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match); 1393 #endif 1394 1395 static irqreturn_t aic31xx_irq(int irq, void *data) 1396 { 1397 struct aic31xx_priv *aic31xx = data; 1398 struct device *dev = aic31xx->dev; 1399 unsigned int value; 1400 bool handled = false; 1401 int ret; 1402 1403 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value); 1404 if (ret) { 1405 dev_err(dev, "Failed to read interrupt mask: %d\n", ret); 1406 goto exit; 1407 } 1408 1409 if (value) 1410 handled = true; 1411 else 1412 goto read_overflow; 1413 1414 if (value & AIC31XX_HPLSCDETECT) 1415 dev_err(dev, "Short circuit on Left output is detected\n"); 1416 if (value & AIC31XX_HPRSCDETECT) 1417 dev_err(dev, "Short circuit on Right output is detected\n"); 1418 if (value & ~(AIC31XX_HPLSCDETECT | 1419 AIC31XX_HPRSCDETECT)) 1420 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value); 1421 1422 read_overflow: 1423 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value); 1424 if (ret) { 1425 dev_err(dev, "Failed to read overflow flag: %d\n", ret); 1426 goto exit; 1427 } 1428 1429 if (value) 1430 handled = true; 1431 else 1432 goto exit; 1433 1434 if (value & AIC31XX_DAC_OF_LEFT) 1435 dev_warn(dev, "Left-channel DAC overflow has occurred\n"); 1436 if (value & AIC31XX_DAC_OF_RIGHT) 1437 dev_warn(dev, "Right-channel DAC overflow has occurred\n"); 1438 if (value & AIC31XX_DAC_OF_SHIFTER) 1439 dev_warn(dev, "DAC barrel shifter overflow has occurred\n"); 1440 if (value & AIC31XX_ADC_OF) 1441 dev_warn(dev, "ADC overflow has occurred\n"); 1442 if (value & AIC31XX_ADC_OF_SHIFTER) 1443 dev_warn(dev, "ADC barrel shifter overflow has occurred\n"); 1444 if (value & ~(AIC31XX_DAC_OF_LEFT | 1445 AIC31XX_DAC_OF_RIGHT | 1446 AIC31XX_DAC_OF_SHIFTER | 1447 AIC31XX_ADC_OF | 1448 AIC31XX_ADC_OF_SHIFTER)) 1449 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value); 1450 1451 exit: 1452 if (handled) 1453 return IRQ_HANDLED; 1454 else 1455 return IRQ_NONE; 1456 } 1457 1458 static int aic31xx_i2c_probe(struct i2c_client *i2c, 1459 const struct i2c_device_id *id) 1460 { 1461 struct aic31xx_priv *aic31xx; 1462 unsigned int micbias_value = MICBIAS_2_0V; 1463 int i, ret; 1464 1465 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1466 id->name, (int)id->driver_data); 1467 1468 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1469 if (!aic31xx) 1470 return -ENOMEM; 1471 1472 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap); 1473 if (IS_ERR(aic31xx->regmap)) { 1474 ret = PTR_ERR(aic31xx->regmap); 1475 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1476 ret); 1477 return ret; 1478 } 1479 aic31xx->dev = &i2c->dev; 1480 aic31xx->irq = i2c->irq; 1481 1482 aic31xx->codec_type = id->driver_data; 1483 1484 dev_set_drvdata(aic31xx->dev, aic31xx); 1485 1486 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg", 1487 &micbias_value); 1488 switch (micbias_value) { 1489 case MICBIAS_2_0V: 1490 case MICBIAS_2_5V: 1491 case MICBIAS_AVDDV: 1492 aic31xx->micbias_vg = micbias_value; 1493 break; 1494 default: 1495 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n", 1496 micbias_value); 1497 aic31xx->micbias_vg = MICBIAS_2_0V; 1498 } 1499 1500 if (dev_get_platdata(aic31xx->dev)) { 1501 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata)); 1502 aic31xx->codec_type = aic31xx->pdata.codec_type; 1503 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg; 1504 } 1505 1506 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset", 1507 GPIOD_OUT_LOW); 1508 if (IS_ERR(aic31xx->gpio_reset)) { 1509 dev_err(aic31xx->dev, "not able to acquire gpio\n"); 1510 return PTR_ERR(aic31xx->gpio_reset); 1511 } 1512 1513 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1514 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1515 1516 ret = devm_regulator_bulk_get(aic31xx->dev, 1517 ARRAY_SIZE(aic31xx->supplies), 1518 aic31xx->supplies); 1519 if (ret) { 1520 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret); 1521 return ret; 1522 } 1523 1524 if (aic31xx->irq > 0) { 1525 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1, 1526 AIC31XX_GPIO1_FUNC_MASK, 1527 AIC31XX_GPIO1_INT1 << 1528 AIC31XX_GPIO1_FUNC_SHIFT); 1529 1530 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL, 1531 AIC31XX_SC | 1532 AIC31XX_ENGINE); 1533 1534 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq, 1535 NULL, aic31xx_irq, 1536 IRQF_ONESHOT, "aic31xx-irq", 1537 aic31xx); 1538 if (ret) { 1539 dev_err(aic31xx->dev, "Unable to request IRQ\n"); 1540 return ret; 1541 } 1542 } 1543 1544 if (aic31xx->codec_type & DAC31XX_BIT) 1545 return devm_snd_soc_register_component(&i2c->dev, 1546 &soc_codec_driver_aic31xx, 1547 dac31xx_dai_driver, 1548 ARRAY_SIZE(dac31xx_dai_driver)); 1549 else 1550 return devm_snd_soc_register_component(&i2c->dev, 1551 &soc_codec_driver_aic31xx, 1552 aic31xx_dai_driver, 1553 ARRAY_SIZE(aic31xx_dai_driver)); 1554 } 1555 1556 static const struct i2c_device_id aic31xx_i2c_id[] = { 1557 { "tlv320aic310x", AIC3100 }, 1558 { "tlv320aic311x", AIC3110 }, 1559 { "tlv320aic3100", AIC3100 }, 1560 { "tlv320aic3110", AIC3110 }, 1561 { "tlv320aic3120", AIC3120 }, 1562 { "tlv320aic3111", AIC3111 }, 1563 { "tlv320dac3100", DAC3100 }, 1564 { "tlv320dac3101", DAC3101 }, 1565 { } 1566 }; 1567 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1568 1569 static struct i2c_driver aic31xx_i2c_driver = { 1570 .driver = { 1571 .name = "tlv320aic31xx-codec", 1572 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1573 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match), 1574 }, 1575 .probe = aic31xx_i2c_probe, 1576 .id_table = aic31xx_i2c_id, 1577 }; 1578 module_i2c_driver(aic31xx_i2c_driver); 1579 1580 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>"); 1581 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver"); 1582 MODULE_LICENSE("GPL v2"); 1583