xref: /linux/sound/soc/codecs/tlv320aic23.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2c1f27190SArun KS /*
3c1f27190SArun KS  * ALSA SoC TLV320AIC23 codec driver
4c1f27190SArun KS  *
5c1f27190SArun KS  * Author:      Arun KS, <arunks@mistralsolutions.com>
6c1f27190SArun KS  * Copyright:   (C) 2008 Mistral Solutions Pvt Ltd
7c1f27190SArun KS  */
8c1f27190SArun KS 
9c1f27190SArun KS #ifndef _TLV320AIC23_H
10c1f27190SArun KS #define _TLV320AIC23_H
11c1f27190SArun KS 
12b3fc5725SMax Filippov struct device;
13b3fc5725SMax Filippov struct regmap_config;
14b3fc5725SMax Filippov 
15b3fc5725SMax Filippov extern const struct regmap_config tlv320aic23_regmap;
16b3fc5725SMax Filippov int tlv320aic23_probe(struct device *dev, struct regmap *regmap);
17b3fc5725SMax Filippov 
18c1f27190SArun KS /* Codec TLV320AIC23 */
19c1f27190SArun KS #define TLV320AIC23_LINVOL		0x00
20c1f27190SArun KS #define TLV320AIC23_RINVOL		0x01
21c1f27190SArun KS #define TLV320AIC23_LCHNVOL		0x02
22c1f27190SArun KS #define TLV320AIC23_RCHNVOL		0x03
23c1f27190SArun KS #define TLV320AIC23_ANLG		0x04
24c1f27190SArun KS #define TLV320AIC23_DIGT		0x05
25c1f27190SArun KS #define TLV320AIC23_PWR			0x06
26c1f27190SArun KS #define TLV320AIC23_DIGT_FMT		0x07
27c1f27190SArun KS #define TLV320AIC23_SRATE		0x08
28c1f27190SArun KS #define TLV320AIC23_ACTIVE		0x09
29c1f27190SArun KS #define TLV320AIC23_RESET		0x0F
30c1f27190SArun KS 
31c1f27190SArun KS /* Left (right) line input volume control register */
32c1f27190SArun KS #define TLV320AIC23_LRS_ENABLED		0x0100
33c1f27190SArun KS #define TLV320AIC23_LIM_MUTED		0x0080
34c1f27190SArun KS #define TLV320AIC23_LIV_DEFAULT		0x0017
35c1f27190SArun KS #define TLV320AIC23_LIV_MAX		0x001f
36c1f27190SArun KS #define TLV320AIC23_LIV_MIN		0x0000
37c1f27190SArun KS 
38c1f27190SArun KS /* Left (right) channel headphone volume control register */
39c1f27190SArun KS #define TLV320AIC23_LZC_ON		0x0080
40c1f27190SArun KS #define TLV320AIC23_LHV_DEFAULT		0x0079
41c1f27190SArun KS #define TLV320AIC23_LHV_MAX		0x007f
42c1f27190SArun KS #define TLV320AIC23_LHV_MIN		0x0000
43c1f27190SArun KS 
44c1f27190SArun KS /* Analog audio path control register */
45c1f27190SArun KS #define TLV320AIC23_STA_REG(x)		((x)<<6)
46c1f27190SArun KS #define TLV320AIC23_STE_ENABLED		0x0020
47c1f27190SArun KS #define TLV320AIC23_DAC_SELECTED	0x0010
48c1f27190SArun KS #define TLV320AIC23_BYPASS_ON		0x0008
49c1f27190SArun KS #define TLV320AIC23_INSEL_MIC		0x0004
50c1f27190SArun KS #define TLV320AIC23_MICM_MUTED		0x0002
51c1f27190SArun KS #define TLV320AIC23_MICB_20DB		0x0001
52c1f27190SArun KS 
53c1f27190SArun KS /* Digital audio path control register */
54c1f27190SArun KS #define TLV320AIC23_DACM_MUTE		0x0008
55c1f27190SArun KS #define TLV320AIC23_DEEMP_32K		0x0002
56c1f27190SArun KS #define TLV320AIC23_DEEMP_44K		0x0004
57c1f27190SArun KS #define TLV320AIC23_DEEMP_48K		0x0006
58c1f27190SArun KS #define TLV320AIC23_ADCHP_ON		0x0001
59c1f27190SArun KS 
60c1f27190SArun KS /* Power control down register */
61c1f27190SArun KS #define TLV320AIC23_DEVICE_PWR_OFF  	0x0080
62c1f27190SArun KS #define TLV320AIC23_CLK_OFF		0x0040
63c1f27190SArun KS #define TLV320AIC23_OSC_OFF		0x0020
64c1f27190SArun KS #define TLV320AIC23_OUT_OFF		0x0010
65c1f27190SArun KS #define TLV320AIC23_DAC_OFF		0x0008
66c1f27190SArun KS #define TLV320AIC23_ADC_OFF		0x0004
67c1f27190SArun KS #define TLV320AIC23_MIC_OFF		0x0002
68c1f27190SArun KS #define TLV320AIC23_LINE_OFF		0x0001
69c1f27190SArun KS 
70c1f27190SArun KS /* Digital audio interface register */
71c1f27190SArun KS #define TLV320AIC23_MS_MASTER		0x0040
72c1f27190SArun KS #define TLV320AIC23_LRSWAP_ON		0x0020
73c1f27190SArun KS #define TLV320AIC23_LRP_ON		0x0010
74c1f27190SArun KS #define TLV320AIC23_IWL_16		0x0000
75c1f27190SArun KS #define TLV320AIC23_IWL_20		0x0004
76c1f27190SArun KS #define TLV320AIC23_IWL_24		0x0008
77c1f27190SArun KS #define TLV320AIC23_IWL_32		0x000C
78c1f27190SArun KS #define TLV320AIC23_FOR_I2S		0x0002
79c1f27190SArun KS #define TLV320AIC23_FOR_DSP		0x0003
80c1f27190SArun KS #define TLV320AIC23_FOR_LJUST		0x0001
81c1f27190SArun KS 
82c1f27190SArun KS /* Sample rate control register */
83c1f27190SArun KS #define TLV320AIC23_CLKOUT_HALF		0x0080
84c1f27190SArun KS #define TLV320AIC23_CLKIN_HALF		0x0040
85c1f27190SArun KS #define TLV320AIC23_BOSR_384fs		0x0002	/* BOSR_272fs in USB mode */
86c1f27190SArun KS #define TLV320AIC23_USB_CLK_ON		0x0001
87c1f27190SArun KS #define TLV320AIC23_SR_MASK             0xf
88c1f27190SArun KS #define TLV320AIC23_CLKOUT_SHIFT        7
89c1f27190SArun KS #define TLV320AIC23_CLKIN_SHIFT         6
90c1f27190SArun KS #define TLV320AIC23_SR_SHIFT            2
91c1f27190SArun KS #define TLV320AIC23_BOSR_SHIFT          1
92c1f27190SArun KS 
93c1f27190SArun KS /* Digital interface register */
94c1f27190SArun KS #define TLV320AIC23_ACT_ON		0x0001
95c1f27190SArun KS 
96c1f27190SArun KS /*
97c1f27190SArun KS  * AUDIO related MACROS
98c1f27190SArun KS  */
99c1f27190SArun KS 
100c1f27190SArun KS #define TLV320AIC23_DEFAULT_OUT_VOL	0x70
101c1f27190SArun KS #define TLV320AIC23_DEFAULT_IN_VOLUME	0x10
102c1f27190SArun KS 
103c1f27190SArun KS #define TLV320AIC23_OUT_VOL_MIN		TLV320AIC23_LHV_MIN
104c1f27190SArun KS #define TLV320AIC23_OUT_VOL_MAX		TLV320AIC23_LHV_MAX
105c1f27190SArun KS #define TLV320AIC23_OUT_VO_RANGE	(TLV320AIC23_OUT_VOL_MAX - \
106c1f27190SArun KS 					TLV320AIC23_OUT_VOL_MIN)
107c1f27190SArun KS #define TLV320AIC23_OUT_VOL_MASK	TLV320AIC23_OUT_VOL_MAX
108c1f27190SArun KS 
109c1f27190SArun KS #define TLV320AIC23_IN_VOL_MIN		TLV320AIC23_LIV_MIN
110c1f27190SArun KS #define TLV320AIC23_IN_VOL_MAX		TLV320AIC23_LIV_MAX
111c1f27190SArun KS #define TLV320AIC23_IN_VOL_RANGE	(TLV320AIC23_IN_VOL_MAX - \
112c1f27190SArun KS 					TLV320AIC23_IN_VOL_MIN)
113c1f27190SArun KS #define TLV320AIC23_IN_VOL_MASK		TLV320AIC23_IN_VOL_MAX
114c1f27190SArun KS 
115c1f27190SArun KS #define TLV320AIC23_SIDETONE_MASK	0x1c0
116c1f27190SArun KS #define TLV320AIC23_SIDETONE_0		0x100
117c1f27190SArun KS #define TLV320AIC23_SIDETONE_6		0x000
118c1f27190SArun KS #define TLV320AIC23_SIDETONE_9		0x040
119c1f27190SArun KS #define TLV320AIC23_SIDETONE_12		0x080
120c1f27190SArun KS #define TLV320AIC23_SIDETONE_18		0x0c0
121c1f27190SArun KS 
122c1f27190SArun KS #endif /* _TLV320AIC23_H */
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