xref: /linux/sound/soc/codecs/tas5720.h (revision c24a62be09d8a0c7ede1c209055a4ac6760a45ee)
11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2bd023adaSAndreas Dannenberg /*
3bd023adaSAndreas Dannenberg  * tas5720.h - ALSA SoC Texas Instruments TAS5720 Mono Audio Amplifier
4bd023adaSAndreas Dannenberg  *
55856d8bdSAlexander A. Klimov  * Copyright (C)2015-2016 Texas Instruments Incorporated -  https://www.ti.com
6bd023adaSAndreas Dannenberg  *
7bd023adaSAndreas Dannenberg  * Author: Andreas Dannenberg <dannenberg@ti.com>
8bd023adaSAndreas Dannenberg  */
9bd023adaSAndreas Dannenberg 
10bd023adaSAndreas Dannenberg #ifndef __TAS5720_H__
11bd023adaSAndreas Dannenberg #define __TAS5720_H__
12bd023adaSAndreas Dannenberg 
13*c24a62beSSteffen Aschbacher /* Register Address Map - first 3 regs are common for all variants */
14bd023adaSAndreas Dannenberg #define TAS5720_DEVICE_ID_REG		0x00
15bd023adaSAndreas Dannenberg #define TAS5720_POWER_CTRL_REG		0x01
16bd023adaSAndreas Dannenberg #define TAS5720_DIGITAL_CTRL1_REG	0x02
17bd023adaSAndreas Dannenberg #define TAS5720_DIGITAL_CTRL2_REG	0x03
18bd023adaSAndreas Dannenberg #define TAS5720_VOLUME_CTRL_REG		0x04
19bd023adaSAndreas Dannenberg #define TAS5720_ANALOG_CTRL_REG		0x06
20bd023adaSAndreas Dannenberg #define TAS5720_FAULT_REG		0x08
21bd023adaSAndreas Dannenberg #define TAS5720_DIGITAL_CLIP2_REG	0x10
22bd023adaSAndreas Dannenberg #define TAS5720_DIGITAL_CLIP1_REG	0x11
23bd023adaSAndreas Dannenberg #define TAS5720_MAX_REG			TAS5720_DIGITAL_CLIP1_REG
24bd023adaSAndreas Dannenberg 
25d5eb436aSAndreas Dannenberg /* Additional TAS5722-specific Registers */
26d5eb436aSAndreas Dannenberg #define TAS5722_DIGITAL_CTRL2_REG	0x13
27d5eb436aSAndreas Dannenberg #define TAS5722_ANALOG_CTRL2_REG	0x14
28d5eb436aSAndreas Dannenberg #define TAS5722_MAX_REG			TAS5722_ANALOG_CTRL2_REG
29d5eb436aSAndreas Dannenberg 
30*c24a62beSSteffen Aschbacher /* Register Address Map - volume controls for the TAS5720-Q1 variant */
31*c24a62beSSteffen Aschbacher #define TAS5720_Q1_VOLUME_CTRL_CFG_REG		0x03
32*c24a62beSSteffen Aschbacher #define TAS5720_Q1_VOLUME_CTRL_LEFT_REG		0x04
33*c24a62beSSteffen Aschbacher #define TAS5720_Q1_VOLUME_CTRL_RIGHT_REG	0x05
34*c24a62beSSteffen Aschbacher 
35bd023adaSAndreas Dannenberg /* TAS5720_DEVICE_ID_REG */
36*c24a62beSSteffen Aschbacher #define TAS5720A_Q1_DEVICE_ID		0x00
37bd023adaSAndreas Dannenberg #define TAS5720_DEVICE_ID		0x01
38872bcad2SAndreas Dannenberg #define TAS5722_DEVICE_ID		0x12
39bd023adaSAndreas Dannenberg 
40bd023adaSAndreas Dannenberg /* TAS5720_POWER_CTRL_REG */
41bd023adaSAndreas Dannenberg #define TAS5720_DIG_CLIP_MASK		GENMASK(7, 2)
42bd023adaSAndreas Dannenberg #define TAS5720_SLEEP			BIT(1)
43bd023adaSAndreas Dannenberg #define TAS5720_SDZ			BIT(0)
44bd023adaSAndreas Dannenberg 
45bd023adaSAndreas Dannenberg /* TAS5720_DIGITAL_CTRL1_REG */
46bd023adaSAndreas Dannenberg #define TAS5720_HPF_BYPASS		BIT(7)
47bd023adaSAndreas Dannenberg #define TAS5720_TDM_CFG_SRC		BIT(6)
48bd023adaSAndreas Dannenberg #define TAS5720_SSZ_DS			BIT(3)
49bd023adaSAndreas Dannenberg #define TAS5720_SAIF_RIGHTJ_24BIT	(0x0)
50bd023adaSAndreas Dannenberg #define TAS5720_SAIF_RIGHTJ_20BIT	(0x1)
51bd023adaSAndreas Dannenberg #define TAS5720_SAIF_RIGHTJ_18BIT	(0x2)
52bd023adaSAndreas Dannenberg #define TAS5720_SAIF_RIGHTJ_16BIT	(0x3)
53bd023adaSAndreas Dannenberg #define TAS5720_SAIF_I2S		(0x4)
54bd023adaSAndreas Dannenberg #define TAS5720_SAIF_LEFTJ		(0x5)
55bd023adaSAndreas Dannenberg #define TAS5720_SAIF_FORMAT_MASK	GENMASK(2, 0)
56bd023adaSAndreas Dannenberg 
57bd023adaSAndreas Dannenberg /* TAS5720_DIGITAL_CTRL2_REG */
58d5eb436aSAndreas Dannenberg #define TAS5722_VOL_RAMP_RATE		BIT(6)
59bd023adaSAndreas Dannenberg #define TAS5720_MUTE			BIT(4)
60bd023adaSAndreas Dannenberg #define TAS5720_TDM_SLOT_SEL_MASK	GENMASK(2, 0)
61bd023adaSAndreas Dannenberg 
62*c24a62beSSteffen Aschbacher /* TAS5720_Q1_VOLUME_CTRL_CFG_REG */
63*c24a62beSSteffen Aschbacher #define TAS5720_Q1_FADE			BIT(7)
64*c24a62beSSteffen Aschbacher #define TAS5720_Q1_MUTE			GENMASK(1, 0)
65*c24a62beSSteffen Aschbacher 
66bd023adaSAndreas Dannenberg /* TAS5720_ANALOG_CTRL_REG */
67bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_6_3_FSYNC	(0x0 << 4)
68bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_8_4_FSYNC	(0x1 << 4)
69bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_10_5_FSYNC	(0x2 << 4)
70bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_12_6_FSYNC	(0x3 << 4)
71bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_14_7_FSYNC	(0x4 << 4)
72bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_16_8_FSYNC	(0x5 << 4)
73bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_20_10_FSYNC	(0x6 << 4)
74bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_24_12_FSYNC	(0x7 << 4)
75bd023adaSAndreas Dannenberg #define TAS5720_PWM_RATE_MASK		GENMASK(6, 4)
76bd023adaSAndreas Dannenberg #define TAS5720_ANALOG_GAIN_19_2DBV	(0x0 << 2)
77bd023adaSAndreas Dannenberg #define TAS5720_ANALOG_GAIN_20_7DBV	(0x1 << 2)
78bd023adaSAndreas Dannenberg #define TAS5720_ANALOG_GAIN_23_5DBV	(0x2 << 2)
79bd023adaSAndreas Dannenberg #define TAS5720_ANALOG_GAIN_26_3DBV	(0x3 << 2)
80bd023adaSAndreas Dannenberg #define TAS5720_ANALOG_GAIN_MASK	GENMASK(3, 2)
81bd023adaSAndreas Dannenberg #define TAS5720_ANALOG_GAIN_SHIFT	(0x2)
82bd023adaSAndreas Dannenberg 
83*c24a62beSSteffen Aschbacher /* TAS5720_Q1_ANALOG_CTRL_REG */
84*c24a62beSSteffen Aschbacher #define TAS5720_Q1_CHAN_SEL		BIT(1)
85*c24a62beSSteffen Aschbacher 
86bd023adaSAndreas Dannenberg /* TAS5720_FAULT_REG */
87bd023adaSAndreas Dannenberg #define TAS5720_OC_THRESH_100PCT	(0x0 << 4)
88bd023adaSAndreas Dannenberg #define TAS5720_OC_THRESH_75PCT		(0x1 << 4)
89bd023adaSAndreas Dannenberg #define TAS5720_OC_THRESH_50PCT		(0x2 << 4)
90bd023adaSAndreas Dannenberg #define TAS5720_OC_THRESH_25PCT		(0x3 << 4)
91bd023adaSAndreas Dannenberg #define TAS5720_OC_THRESH_MASK		GENMASK(5, 4)
92bd023adaSAndreas Dannenberg #define TAS5720_CLKE			BIT(3)
93bd023adaSAndreas Dannenberg #define TAS5720_OCE			BIT(2)
94bd023adaSAndreas Dannenberg #define TAS5720_DCE			BIT(1)
95bd023adaSAndreas Dannenberg #define TAS5720_OTE			BIT(0)
96bd023adaSAndreas Dannenberg #define TAS5720_FAULT_MASK		GENMASK(3, 0)
97bd023adaSAndreas Dannenberg 
98bd023adaSAndreas Dannenberg /* TAS5720_DIGITAL_CLIP1_REG */
99bd023adaSAndreas Dannenberg #define TAS5720_CLIP1_MASK		GENMASK(7, 2)
100bd023adaSAndreas Dannenberg #define TAS5720_CLIP1_SHIFT		(0x2)
101bd023adaSAndreas Dannenberg 
102d5eb436aSAndreas Dannenberg /* TAS5722_DIGITAL_CTRL2_REG */
103d5eb436aSAndreas Dannenberg #define TAS5722_HPF_3_7HZ		(0x0 << 5)
104d5eb436aSAndreas Dannenberg #define TAS5722_HPF_7_4HZ		(0x1 << 5)
105d5eb436aSAndreas Dannenberg #define TAS5722_HPF_14_9HZ		(0x2 << 5)
106d5eb436aSAndreas Dannenberg #define TAS5722_HPF_29_7HZ		(0x3 << 5)
107d5eb436aSAndreas Dannenberg #define TAS5722_HPF_59_4HZ		(0x4 << 5)
108d5eb436aSAndreas Dannenberg #define TAS5722_HPF_118_4HZ		(0x5 << 5)
109d5eb436aSAndreas Dannenberg #define TAS5722_HPF_235_0HZ		(0x6 << 5)
110d5eb436aSAndreas Dannenberg #define TAS5722_HPF_463_2HZ		(0x7 << 5)
111d5eb436aSAndreas Dannenberg #define TAS5722_HPF_MASK		GENMASK(7, 5)
112d5eb436aSAndreas Dannenberg #define TAS5722_AUTO_SLEEP_OFF		(0x0 << 3)
113d5eb436aSAndreas Dannenberg #define TAS5722_AUTO_SLEEP_1024LR	(0x1 << 3)
114d5eb436aSAndreas Dannenberg #define TAS5722_AUTO_SLEEP_65536LR	(0x2 << 3)
115d5eb436aSAndreas Dannenberg #define TAS5722_AUTO_SLEEP_262144LR	(0x3 << 3)
116d5eb436aSAndreas Dannenberg #define TAS5722_AUTO_SLEEP_MASK		GENMASK(4, 3)
117d5eb436aSAndreas Dannenberg #define TAS5722_TDM_SLOT_16B		BIT(2)
118d5eb436aSAndreas Dannenberg #define TAS5722_MCLK_PIN_CFG		BIT(1)
119d5eb436aSAndreas Dannenberg #define TAS5722_VOL_CONTROL_LSB		BIT(0)
120d5eb436aSAndreas Dannenberg 
121d5eb436aSAndreas Dannenberg /* TAS5722_ANALOG_CTRL2_REG */
122d5eb436aSAndreas Dannenberg #define TAS5722_FAULTZ_PU		BIT(3)
123d5eb436aSAndreas Dannenberg #define TAS5722_VREG_LVL		BIT(2)
124d5eb436aSAndreas Dannenberg #define TAS5722_PWR_TUNE		BIT(0)
125d5eb436aSAndreas Dannenberg 
126bd023adaSAndreas Dannenberg #endif /* __TAS5720_H__ */
127