1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for the Texas Instruments TAS2764 CODEC 4 // Copyright (C) 2020 Texas Instruments Inc. 5 6 #include <linux/module.h> 7 #include <linux/moduleparam.h> 8 #include <linux/err.h> 9 #include <linux/init.h> 10 #include <linux/delay.h> 11 #include <linux/hwmon.h> 12 #include <linux/pm.h> 13 #include <linux/i2c.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/regmap.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/slab.h> 20 #include <sound/soc.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 26 #include "tas2764.h" 27 28 enum tas2764_devid { 29 DEVID_TAS2764 = 0, 30 DEVID_SN012776 = 1 31 }; 32 33 struct tas2764_priv { 34 struct snd_soc_component *component; 35 struct gpio_desc *reset_gpio; 36 struct gpio_desc *sdz_gpio; 37 struct regmap *regmap; 38 struct device *dev; 39 int irq; 40 enum tas2764_devid devid; 41 42 int v_sense_slot; 43 int i_sense_slot; 44 45 bool dac_powered; 46 bool unmuted; 47 48 struct { 49 int tx_mode; 50 unsigned int tx_mask; 51 } idle_slot_config; 52 }; 53 54 #include "tas2764-quirks.h" 55 56 static const char *tas2764_int_ltch0_msgs[8] = { 57 "fault: over temperature", /* INT_LTCH0 & BIT(0) */ 58 "fault: over current", 59 "fault: bad TDM clock", 60 "limiter active", 61 "fault: PVDD below limiter inflection point", 62 "fault: limiter max attenuation", 63 "fault: BOP infinite hold", 64 "fault: BOP mute", /* INT_LTCH0 & BIT(7) */ 65 }; 66 67 static const unsigned int tas2764_int_readout_regs[6] = { 68 TAS2764_INT_LTCH0, 69 TAS2764_INT_LTCH1, 70 TAS2764_INT_LTCH1_0, 71 TAS2764_INT_LTCH2, 72 TAS2764_INT_LTCH3, 73 TAS2764_INT_LTCH4, 74 }; 75 76 static irqreturn_t tas2764_irq(int irq, void *data) 77 { 78 struct tas2764_priv *tas2764 = data; 79 u8 latched[6] = {0, 0, 0, 0, 0, 0}; 80 int ret = IRQ_NONE; 81 int i; 82 83 for (i = 0; i < ARRAY_SIZE(latched); i++) 84 latched[i] = snd_soc_component_read(tas2764->component, 85 tas2764_int_readout_regs[i]); 86 87 for (i = 0; i < 8; i++) { 88 if (latched[0] & BIT(i)) { 89 dev_crit_ratelimited(tas2764->dev, "%s\n", 90 tas2764_int_ltch0_msgs[i]); 91 ret = IRQ_HANDLED; 92 } 93 } 94 95 if (latched[0]) { 96 dev_err_ratelimited(tas2764->dev, "other context to the fault: %02x,%02x,%02x,%02x,%02x", 97 latched[1], latched[2], latched[3], latched[4], latched[5]); 98 snd_soc_component_update_bits(tas2764->component, 99 TAS2764_INT_CLK_CFG, 100 TAS2764_INT_CLK_CFG_IRQZ_CLR, 101 TAS2764_INT_CLK_CFG_IRQZ_CLR); 102 } 103 104 return ret; 105 } 106 107 static void tas2764_reset(struct tas2764_priv *tas2764) 108 { 109 if (tas2764->reset_gpio) { 110 gpiod_set_value_cansleep(tas2764->reset_gpio, 0); 111 msleep(20); 112 gpiod_set_value_cansleep(tas2764->reset_gpio, 1); 113 usleep_range(1000, 2000); 114 } 115 116 snd_soc_component_write(tas2764->component, TAS2764_SW_RST, 117 TAS2764_RST); 118 usleep_range(1000, 2000); 119 } 120 121 static int tas2764_update_pwr_ctrl(struct tas2764_priv *tas2764) 122 { 123 struct snd_soc_component *component = tas2764->component; 124 unsigned int val; 125 int ret; 126 127 if (tas2764->dac_powered) 128 val = tas2764->unmuted ? 129 TAS2764_PWR_CTRL_ACTIVE : TAS2764_PWR_CTRL_MUTE; 130 else 131 val = TAS2764_PWR_CTRL_SHUTDOWN; 132 133 if (ENABLED_APPLE_QUIRKS & TAS2764_SHUTDOWN_DANCE) 134 return tas2764_do_quirky_pwr_ctrl_change(tas2764, val); 135 136 ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, 137 TAS2764_PWR_CTRL_MASK, val); 138 if (ret < 0) 139 return ret; 140 141 return 0; 142 } 143 144 #ifdef CONFIG_PM 145 static int tas2764_codec_suspend(struct snd_soc_component *component) 146 { 147 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); 148 int ret; 149 150 ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, 151 TAS2764_PWR_CTRL_MASK, 152 TAS2764_PWR_CTRL_SHUTDOWN); 153 154 if (ret < 0) 155 return ret; 156 157 if (tas2764->sdz_gpio) 158 gpiod_set_value_cansleep(tas2764->sdz_gpio, 0); 159 160 regcache_cache_only(tas2764->regmap, true); 161 regcache_mark_dirty(tas2764->regmap); 162 163 usleep_range(6000, 7000); 164 165 return 0; 166 } 167 168 static int tas2764_codec_resume(struct snd_soc_component *component) 169 { 170 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); 171 int ret; 172 173 if (tas2764->sdz_gpio) { 174 gpiod_set_value_cansleep(tas2764->sdz_gpio, 1); 175 usleep_range(1000, 2000); 176 } 177 178 ret = tas2764_update_pwr_ctrl(tas2764); 179 180 if (ret < 0) 181 return ret; 182 183 regcache_cache_only(tas2764->regmap, false); 184 185 return regcache_sync(tas2764->regmap); 186 } 187 #else 188 #define tas2764_codec_suspend NULL 189 #define tas2764_codec_resume NULL 190 #endif 191 192 static const char * const tas2764_ASI1_src[] = { 193 "I2C offset", "Left", "Right", "LeftRightDiv2", 194 }; 195 196 static SOC_ENUM_SINGLE_DECL( 197 tas2764_ASI1_src_enum, TAS2764_TDM_CFG2, TAS2764_TDM_CFG2_SCFG_SHIFT, 198 tas2764_ASI1_src); 199 200 static const struct snd_kcontrol_new tas2764_asi1_mux = 201 SOC_DAPM_ENUM("ASI1 Source", tas2764_ASI1_src_enum); 202 203 static const struct snd_kcontrol_new isense_switch = 204 SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN, 1, 1); 205 static const struct snd_kcontrol_new vsense_switch = 206 SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN, 1, 1); 207 208 static const struct snd_soc_dapm_widget tas2764_dapm_widgets[] = { 209 SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0), 210 SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2764_asi1_mux), 211 SND_SOC_DAPM_SWITCH("ISENSE", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN, 212 1, &isense_switch), 213 SND_SOC_DAPM_SWITCH("VSENSE", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN, 214 1, &vsense_switch), 215 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 216 SND_SOC_DAPM_OUTPUT("OUT"), 217 SND_SOC_DAPM_SIGGEN("VMON"), 218 SND_SOC_DAPM_SIGGEN("IMON") 219 }; 220 221 static const struct snd_soc_dapm_route tas2764_audio_map[] = { 222 {"ASI1 Sel", "I2C offset", "ASI1"}, 223 {"ASI1 Sel", "Left", "ASI1"}, 224 {"ASI1 Sel", "Right", "ASI1"}, 225 {"ASI1 Sel", "LeftRightDiv2", "ASI1"}, 226 {"DAC", NULL, "ASI1 Sel"}, 227 {"OUT", NULL, "DAC"}, 228 {"ISENSE", "Switch", "IMON"}, 229 {"VSENSE", "Switch", "VMON"}, 230 }; 231 232 static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction) 233 { 234 struct tas2764_priv *tas2764 = 235 snd_soc_component_get_drvdata(dai->component); 236 int ret; 237 238 if (!mute) { 239 tas2764->dac_powered = true; 240 ret = tas2764_update_pwr_ctrl(tas2764); 241 if (ret) 242 return ret; 243 } 244 245 tas2764->unmuted = !mute; 246 ret = tas2764_update_pwr_ctrl(tas2764); 247 if (ret) 248 return ret; 249 250 if (mute) { 251 /* Wait for ramp-down */ 252 usleep_range(6000, 7000); 253 254 tas2764->dac_powered = false; 255 ret = tas2764_update_pwr_ctrl(tas2764); 256 if (ret) 257 return ret; 258 259 /* Wait a bit after shutdown */ 260 usleep_range(2000, 3000); 261 } 262 263 return 0; 264 } 265 266 static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth) 267 { 268 struct snd_soc_component *component = tas2764->component; 269 int sense_en; 270 int val; 271 int ret; 272 273 switch (bitwidth) { 274 case SNDRV_PCM_FORMAT_S16_LE: 275 ret = snd_soc_component_update_bits(component, 276 TAS2764_TDM_CFG2, 277 TAS2764_TDM_CFG2_RXW_MASK, 278 TAS2764_TDM_CFG2_RXW_16BITS); 279 break; 280 case SNDRV_PCM_FORMAT_S24_LE: 281 ret = snd_soc_component_update_bits(component, 282 TAS2764_TDM_CFG2, 283 TAS2764_TDM_CFG2_RXW_MASK, 284 TAS2764_TDM_CFG2_RXW_24BITS); 285 break; 286 case SNDRV_PCM_FORMAT_S32_LE: 287 ret = snd_soc_component_update_bits(component, 288 TAS2764_TDM_CFG2, 289 TAS2764_TDM_CFG2_RXW_MASK, 290 TAS2764_TDM_CFG2_RXW_32BITS); 291 break; 292 293 default: 294 return -EINVAL; 295 } 296 297 if (ret < 0) 298 return ret; 299 300 val = snd_soc_component_read(tas2764->component, TAS2764_PWR_CTRL); 301 if (val < 0) 302 return val; 303 304 if (val & (1 << TAS2764_VSENSE_POWER_EN)) 305 sense_en = 0; 306 else 307 sense_en = TAS2764_TDM_CFG5_VSNS_ENABLE; 308 309 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5, 310 TAS2764_TDM_CFG5_VSNS_ENABLE, 311 sense_en); 312 if (ret < 0) 313 return ret; 314 315 if (val & (1 << TAS2764_ISENSE_POWER_EN)) 316 sense_en = 0; 317 else 318 sense_en = TAS2764_TDM_CFG6_ISNS_ENABLE; 319 320 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6, 321 TAS2764_TDM_CFG6_ISNS_ENABLE, 322 sense_en); 323 if (ret < 0) 324 return ret; 325 326 return 0; 327 } 328 329 static int tas2764_set_samplerate(struct tas2764_priv *tas2764, int samplerate) 330 { 331 struct snd_soc_component *component = tas2764->component; 332 int ramp_rate_val; 333 int ret; 334 335 switch (samplerate) { 336 case 48000: 337 ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ | 338 TAS2764_TDM_CFG0_44_1_48KHZ; 339 break; 340 case 44100: 341 ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ | 342 TAS2764_TDM_CFG0_44_1_48KHZ; 343 break; 344 case 96000: 345 ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ | 346 TAS2764_TDM_CFG0_88_2_96KHZ; 347 break; 348 case 88200: 349 ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ | 350 TAS2764_TDM_CFG0_88_2_96KHZ; 351 break; 352 default: 353 return -EINVAL; 354 } 355 356 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG0, 357 TAS2764_TDM_CFG0_SMP_MASK | 358 TAS2764_TDM_CFG0_MASK, 359 ramp_rate_val); 360 if (ret < 0) 361 return ret; 362 363 return 0; 364 } 365 366 static int tas2764_hw_params(struct snd_pcm_substream *substream, 367 struct snd_pcm_hw_params *params, 368 struct snd_soc_dai *dai) 369 { 370 struct snd_soc_component *component = dai->component; 371 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); 372 int ret; 373 374 ret = tas2764_set_bitwidth(tas2764, params_format(params)); 375 if (ret < 0) 376 return ret; 377 378 return tas2764_set_samplerate(tas2764, params_rate(params)); 379 } 380 381 static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 382 { 383 struct snd_soc_component *component = dai->component; 384 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); 385 u8 tdm_rx_start_slot = 0, asi_cfg_0 = 0, asi_cfg_1 = 0, asi_cfg_4 = 0; 386 int ret; 387 388 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 389 case SND_SOC_DAIFMT_NB_IF: 390 asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START; 391 fallthrough; 392 case SND_SOC_DAIFMT_NB_NF: 393 asi_cfg_1 = TAS2764_TDM_CFG1_RX_RISING; 394 asi_cfg_4 = TAS2764_TDM_CFG4_TX_FALLING; 395 break; 396 case SND_SOC_DAIFMT_IB_IF: 397 asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START; 398 fallthrough; 399 case SND_SOC_DAIFMT_IB_NF: 400 asi_cfg_1 = TAS2764_TDM_CFG1_RX_FALLING; 401 asi_cfg_4 = TAS2764_TDM_CFG4_TX_RISING; 402 break; 403 } 404 405 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1, 406 TAS2764_TDM_CFG1_RX_MASK, 407 asi_cfg_1); 408 if (ret < 0) 409 return ret; 410 411 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG4, 412 TAS2764_TDM_CFG4_TX_MASK, 413 asi_cfg_4); 414 if (ret < 0) 415 return ret; 416 417 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 418 case SND_SOC_DAIFMT_I2S: 419 asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START; 420 fallthrough; 421 case SND_SOC_DAIFMT_DSP_A: 422 tdm_rx_start_slot = 1; 423 break; 424 case SND_SOC_DAIFMT_DSP_B: 425 case SND_SOC_DAIFMT_LEFT_J: 426 tdm_rx_start_slot = 0; 427 break; 428 default: 429 dev_err(tas2764->dev, 430 "DAI Format is not found, fmt=0x%x\n", fmt); 431 return -EINVAL; 432 } 433 434 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG0, 435 TAS2764_TDM_CFG0_FRAME_START, 436 asi_cfg_0); 437 if (ret < 0) 438 return ret; 439 440 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1, 441 TAS2764_TDM_CFG1_MASK, 442 (tdm_rx_start_slot << TAS2764_TDM_CFG1_51_SHIFT)); 443 if (ret < 0) 444 return ret; 445 446 return 0; 447 } 448 449 static int tas2764_set_dai_tdm_slot(struct snd_soc_dai *dai, 450 unsigned int tx_mask, 451 unsigned int rx_mask, 452 int slots, int slot_width) 453 { 454 struct snd_soc_component *component = dai->component; 455 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); 456 int left_slot, right_slot; 457 int slots_cfg; 458 int slot_size; 459 int ret; 460 461 if (tx_mask == 0 || rx_mask != 0) 462 return -EINVAL; 463 464 left_slot = __ffs(tx_mask); 465 tx_mask &= ~(1 << left_slot); 466 if (tx_mask == 0) { 467 right_slot = left_slot; 468 } else { 469 right_slot = __ffs(tx_mask); 470 tx_mask &= ~(1 << right_slot); 471 } 472 473 if (tx_mask != 0 || left_slot >= slots || right_slot >= slots) 474 return -EINVAL; 475 476 slots_cfg = (right_slot << TAS2764_TDM_CFG3_RXS_SHIFT) | left_slot; 477 478 ret = snd_soc_component_write(component, TAS2764_TDM_CFG3, slots_cfg); 479 if (ret) 480 return ret; 481 482 switch (slot_width) { 483 case 16: 484 slot_size = TAS2764_TDM_CFG2_RXS_16BITS; 485 break; 486 case 24: 487 slot_size = TAS2764_TDM_CFG2_RXS_24BITS; 488 break; 489 case 32: 490 slot_size = TAS2764_TDM_CFG2_RXS_32BITS; 491 break; 492 default: 493 return -EINVAL; 494 } 495 496 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG2, 497 TAS2764_TDM_CFG2_RXS_MASK, 498 slot_size); 499 if (ret < 0) 500 return ret; 501 502 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG5, 503 TAS2764_TDM_CFG5_50_MASK, 504 tas2764->v_sense_slot); 505 if (ret < 0) 506 return ret; 507 508 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG6, 509 TAS2764_TDM_CFG6_50_MASK, 510 tas2764->i_sense_slot); 511 if (ret < 0) 512 return ret; 513 514 return 0; 515 } 516 517 static int tas2764_write_sdout_idle_mask(struct tas2764_priv *tas2764, u32 mask) 518 { 519 struct snd_soc_component *component = tas2764->component; 520 int i, ret; 521 522 /* Hardware supports up to 64 slots, but we don't */ 523 for (i = 0; i < 4; i++) { 524 ret = snd_soc_component_write(component, 525 TAS2764_SDOUT_HIZ_1 + i, 526 (mask >> (i * 8)) & 0xff); 527 if (ret < 0) 528 return ret; 529 } 530 531 return 0; 532 } 533 534 static int tas2764_set_dai_tdm_idle(struct snd_soc_dai *dai, 535 unsigned int tx_mask, unsigned int rx_mask, 536 int tx_mode, int rx_mode) 537 { 538 struct snd_soc_component *component = dai->component; 539 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); 540 int ret; 541 542 /* We don't support setting anything on SDIN */ 543 if (rx_mode) 544 return -EOPNOTSUPP; 545 546 if (tas2764->idle_slot_config.tx_mask == tx_mask && 547 tas2764->idle_slot_config.tx_mode == tx_mode) 548 return 0; 549 550 switch (tx_mode) { 551 case SND_SOC_DAI_TDM_IDLE_ZERO: 552 if (!tx_mask) 553 return -EINVAL; 554 555 ret = tas2764_write_sdout_idle_mask(tas2764, tx_mask); 556 if (ret < 0) 557 return ret; 558 559 ret = snd_soc_component_update_bits(component, 560 TAS2764_SDOUT_HIZ_9, 561 TAS2764_SDOUT_HIZ_9_FORCE_0_EN, 562 TAS2764_SDOUT_HIZ_9_FORCE_0_EN); 563 if (ret < 0) 564 return ret; 565 566 tas2764->idle_slot_config.tx_mask = tx_mask; 567 tas2764->idle_slot_config.tx_mode = tx_mode; 568 break; 569 case SND_SOC_DAI_TDM_IDLE_HIZ: 570 case SND_SOC_DAI_TDM_IDLE_OFF: 571 /* HiZ mode does not support a slot mask */ 572 ret = tas2764_write_sdout_idle_mask(tas2764, 0); 573 if (ret < 0) 574 return ret; 575 576 ret = snd_soc_component_update_bits(component, 577 TAS2764_SDOUT_HIZ_9, 578 TAS2764_SDOUT_HIZ_9_FORCE_0_EN, 0); 579 if (ret < 0) 580 return ret; 581 582 tas2764->idle_slot_config.tx_mask = 0; 583 tas2764->idle_slot_config.tx_mode = tx_mode; 584 break; 585 default: 586 return -EOPNOTSUPP; 587 } 588 589 return 0; 590 } 591 592 /* The SDOUT idle slot mask must be cropped based on the BCLK ratio */ 593 static int tas2764_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 594 { 595 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(dai->component); 596 597 if (!tas2764->idle_slot_config.tx_mask) 598 return 0; 599 600 tas2764->idle_slot_config.tx_mask &= GENMASK((ratio / 8) - 1, 0); 601 602 return tas2764_write_sdout_idle_mask(tas2764, tas2764->idle_slot_config.tx_mask); 603 } 604 605 static const struct snd_soc_dai_ops tas2764_dai_ops = { 606 .mute_stream = tas2764_mute, 607 .hw_params = tas2764_hw_params, 608 .set_fmt = tas2764_set_fmt, 609 .set_bclk_ratio = tas2764_set_bclk_ratio, 610 .set_tdm_slot = tas2764_set_dai_tdm_slot, 611 .set_tdm_idle = tas2764_set_dai_tdm_idle, 612 .no_capture_mute = 1, 613 }; 614 615 #define TAS2764_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 616 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 617 618 #define TAS2764_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 619 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_88200) 620 621 static struct snd_soc_dai_driver tas2764_dai_driver[] = { 622 { 623 .name = "tas2764 ASI1", 624 .id = 0, 625 .playback = { 626 .stream_name = "ASI1 Playback", 627 .channels_min = 1, 628 .channels_max = 2, 629 .rates = TAS2764_RATES, 630 .formats = TAS2764_FORMATS, 631 }, 632 .capture = { 633 .stream_name = "ASI1 Capture", 634 .channels_min = 0, 635 .channels_max = 2, 636 .rates = TAS2764_RATES, 637 .formats = TAS2764_FORMATS, 638 }, 639 .ops = &tas2764_dai_ops, 640 .symmetric_rate = 1, 641 }, 642 }; 643 644 static uint8_t sn012776_bop_presets[] = { 645 0x01, 0x32, 0x02, 0x22, 0x83, 0x2d, 0x80, 0x02, 0x06, 646 0x32, 0x46, 0x30, 0x02, 0x06, 0x38, 0x40, 0x30, 0x02, 647 0x06, 0x3e, 0x37, 0x30, 0xff, 0xe6 648 }; 649 650 static const struct regmap_config tas2764_i2c_regmap; 651 652 static int tas2764_apply_init_quirks(struct tas2764_priv *tas2764) 653 { 654 int ret, i; 655 656 for (i = 0; i < ARRAY_SIZE(tas2764_quirk_init_sequences); i++) { 657 const struct tas2764_quirk_init_sequence *init_seq = 658 &tas2764_quirk_init_sequences[i]; 659 660 if (!init_seq->seq) 661 continue; 662 663 if (!(BIT(i) & ENABLED_APPLE_QUIRKS)) 664 continue; 665 666 ret = regmap_multi_reg_write(tas2764->regmap, init_seq->seq, 667 init_seq->len); 668 669 if (ret < 0) 670 return ret; 671 } 672 673 return 0; 674 } 675 676 static int tas2764_read_die_temp(struct tas2764_priv *tas2764, long *result) 677 { 678 int ret, reg; 679 680 ret = regmap_read(tas2764->regmap, TAS2764_TEMP, ®); 681 if (ret) 682 return ret; 683 /* 684 * As per datasheet, subtract 93 from raw value to get degrees 685 * Celsius. hwmon wants millidegrees. 686 * 687 * NOTE: The TAS2764 datasheet mentions initialising TAS2764_TEMP 688 * such that the temperature is 2.6 *C, however the register 689 * is actually initialised to 0. The ADC is also powered down during 690 * software shutdown. The last sampled temperature will persist 691 * in the register while the amp is in this power state. 692 */ 693 if (reg == 0) 694 return -ENODATA; 695 696 *result = (reg - 93) * 1000; 697 return 0; 698 } 699 700 static int tas2764_hwmon_is_fault(struct tas2764_priv *tas2764, long *result) 701 { 702 int ret; 703 long temp; 704 705 ret = tas2764_read_die_temp(tas2764, &temp); 706 if (ret == -ENODATA) { 707 *result = true; 708 return 0; 709 } 710 711 return ret; 712 } 713 714 static umode_t tas2764_hwmon_is_visible(const void *data, 715 enum hwmon_sensor_types type, u32 attr, 716 int channel) 717 { 718 if (type != hwmon_temp) 719 return 0; 720 721 switch (attr) { 722 case hwmon_temp_input: 723 case hwmon_temp_fault: 724 return 0444; 725 default: 726 break; 727 } 728 729 return 0; 730 } 731 732 static int tas2764_hwmon_read(struct device *dev, 733 enum hwmon_sensor_types type, 734 u32 attr, int channel, long *val) 735 { 736 struct tas2764_priv *tas2764 = dev_get_drvdata(dev); 737 int ret; 738 739 switch (attr) { 740 case hwmon_temp_input: 741 ret = tas2764_read_die_temp(tas2764, val); 742 break; 743 case hwmon_temp_fault: 744 ret = tas2764_hwmon_is_fault(tas2764, val); 745 break; 746 default: 747 ret = -EOPNOTSUPP; 748 break; 749 } 750 751 return ret; 752 } 753 754 static const struct hwmon_channel_info *const tas2764_hwmon_info[] = { 755 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_FAULT), 756 NULL 757 }; 758 759 static const struct hwmon_ops tas2764_hwmon_ops = { 760 .is_visible = tas2764_hwmon_is_visible, 761 .read = tas2764_hwmon_read, 762 }; 763 764 static const struct hwmon_chip_info tas2764_hwmon_chip_info = { 765 .ops = &tas2764_hwmon_ops, 766 .info = tas2764_hwmon_info, 767 }; 768 769 static int tas2764_codec_probe(struct snd_soc_component *component) 770 { 771 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component); 772 int ret, i; 773 774 tas2764->component = component; 775 776 if (tas2764->sdz_gpio) { 777 gpiod_set_value_cansleep(tas2764->sdz_gpio, 1); 778 usleep_range(1000, 2000); 779 } 780 781 tas2764_reset(tas2764); 782 regmap_reinit_cache(tas2764->regmap, &tas2764_i2c_regmap); 783 784 if (tas2764->irq) { 785 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK0, 0x00); 786 if (ret < 0) 787 return ret; 788 789 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK1, 0xff); 790 if (ret < 0) 791 return ret; 792 793 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK2, 0xff); 794 if (ret < 0) 795 return ret; 796 797 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK3, 0xff); 798 if (ret < 0) 799 return ret; 800 801 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK4, 0xff); 802 if (ret < 0) 803 return ret; 804 805 ret = devm_request_threaded_irq(tas2764->dev, tas2764->irq, NULL, tas2764_irq, 806 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 807 "tas2764", tas2764); 808 if (ret) 809 dev_warn(tas2764->dev, "failed to request IRQ: %d\n", ret); 810 } 811 812 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5, 813 TAS2764_TDM_CFG5_VSNS_ENABLE, 0); 814 if (ret < 0) 815 return ret; 816 817 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6, 818 TAS2764_TDM_CFG6_ISNS_ENABLE, 0); 819 if (ret < 0) 820 return ret; 821 822 switch (tas2764->devid) { 823 case DEVID_SN012776: 824 ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL, 825 TAS2764_PWR_CTRL_BOP_SRC, 826 TAS2764_PWR_CTRL_BOP_SRC); 827 if (ret < 0) 828 return ret; 829 830 for (i = 0; i < ARRAY_SIZE(sn012776_bop_presets); i++) { 831 ret = snd_soc_component_write(component, 832 TAS2764_BOP_CFG0 + i, 833 sn012776_bop_presets[i]); 834 835 if (ret < 0) 836 return ret; 837 } 838 839 /* Apply all enabled Apple quirks */ 840 ret = tas2764_apply_init_quirks(tas2764); 841 842 if (ret < 0) 843 return ret; 844 845 break; 846 default: 847 break; 848 } 849 850 return 0; 851 } 852 853 static DECLARE_TLV_DB_SCALE(tas2764_digital_tlv, 1100, 50, 0); 854 static DECLARE_TLV_DB_SCALE(tas2764_playback_volume, -10050, 50, 1); 855 856 static const char * const tas2764_hpf_texts[] = { 857 "Disabled", "2 Hz", "50 Hz", "100 Hz", "200 Hz", 858 "400 Hz", "800 Hz" 859 }; 860 861 static SOC_ENUM_SINGLE_DECL( 862 tas2764_hpf_enum, TAS2764_DC_BLK0, 863 TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT, tas2764_hpf_texts); 864 865 static const char * const tas2764_oce_texts[] = { 866 "Disable", "Retry", 867 }; 868 869 static SOC_ENUM_SINGLE_DECL( 870 tas2764_oce_enum, TAS2764_MISC_CFG1, 871 TAS2764_MISC_CFG1_OCE_RETRY_SHIFT, tas2764_oce_texts); 872 873 static const struct snd_kcontrol_new tas2764_snd_controls[] = { 874 SOC_SINGLE_TLV("Speaker Volume", TAS2764_DVC, 0, 875 TAS2764_DVC_MAX, 1, tas2764_playback_volume), 876 SOC_SINGLE_TLV("Amp Gain Volume", TAS2764_CHNL_0, 1, 0x14, 0, 877 tas2764_digital_tlv), 878 SOC_ENUM("HPF Corner Frequency", tas2764_hpf_enum), 879 SOC_ENUM("OCE Handling", tas2764_oce_enum), 880 }; 881 882 static const struct snd_soc_component_driver soc_component_driver_tas2764 = { 883 .probe = tas2764_codec_probe, 884 .suspend = tas2764_codec_suspend, 885 .resume = tas2764_codec_resume, 886 .controls = tas2764_snd_controls, 887 .num_controls = ARRAY_SIZE(tas2764_snd_controls), 888 .dapm_widgets = tas2764_dapm_widgets, 889 .num_dapm_widgets = ARRAY_SIZE(tas2764_dapm_widgets), 890 .dapm_routes = tas2764_audio_map, 891 .num_dapm_routes = ARRAY_SIZE(tas2764_audio_map), 892 .idle_bias_on = 1, 893 .endianness = 1, 894 }; 895 896 static const struct reg_default tas2764_reg_defaults[] = { 897 { TAS2764_PAGE, 0x00 }, 898 { TAS2764_SW_RST, 0x00 }, 899 { TAS2764_PWR_CTRL, 0x1a }, 900 { TAS2764_DVC, 0x00 }, 901 { TAS2764_CHNL_0, 0x28 }, 902 { TAS2764_TDM_CFG0, 0x09 }, 903 { TAS2764_TDM_CFG1, 0x02 }, 904 { TAS2764_TDM_CFG2, 0x0a }, 905 { TAS2764_TDM_CFG3, 0x10 }, 906 { TAS2764_TDM_CFG5, 0x42 }, 907 { TAS2764_INT_CLK_CFG, 0x19 }, 908 }; 909 910 static const struct regmap_range_cfg tas2764_regmap_ranges[] = { 911 { 912 .range_min = 0, 913 .range_max = 0xffff, 914 .selector_reg = TAS2764_PAGE, 915 .selector_mask = 0xff, 916 .selector_shift = 0, 917 .window_start = 0, 918 .window_len = 128, 919 }, 920 }; 921 922 static bool tas2764_volatile_register(struct device *dev, unsigned int reg) 923 { 924 switch (reg) { 925 case TAS2764_SW_RST: 926 case TAS2764_TEMP: 927 case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4: 928 case TAS2764_INT_CLK_CFG: 929 return true; 930 case TAS2764_REG(0xf0, 0x0) ... TAS2764_REG(0xff, 0x0): 931 /* TI's undocumented registers for the application of quirks */ 932 return true; 933 default: 934 return false; 935 } 936 } 937 938 static const struct regmap_config tas2764_i2c_regmap = { 939 .reg_bits = 8, 940 .val_bits = 8, 941 .volatile_reg = tas2764_volatile_register, 942 .reg_defaults = tas2764_reg_defaults, 943 .num_reg_defaults = ARRAY_SIZE(tas2764_reg_defaults), 944 .cache_type = REGCACHE_RBTREE, 945 .ranges = tas2764_regmap_ranges, 946 .num_ranges = ARRAY_SIZE(tas2764_regmap_ranges), 947 .max_register = 0xffff, 948 }; 949 950 static int tas2764_parse_dt(struct device *dev, struct tas2764_priv *tas2764) 951 { 952 int ret = 0; 953 954 tas2764->reset_gpio = devm_gpiod_get_optional(tas2764->dev, "reset", 955 GPIOD_OUT_HIGH); 956 if (IS_ERR(tas2764->reset_gpio)) { 957 if (PTR_ERR(tas2764->reset_gpio) == -EPROBE_DEFER) { 958 tas2764->reset_gpio = NULL; 959 return -EPROBE_DEFER; 960 } 961 } 962 963 tas2764->sdz_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 964 if (IS_ERR(tas2764->sdz_gpio)) { 965 if (PTR_ERR(tas2764->sdz_gpio) == -EPROBE_DEFER) 966 return -EPROBE_DEFER; 967 968 tas2764->sdz_gpio = NULL; 969 } 970 971 ret = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no", 972 &tas2764->i_sense_slot); 973 if (ret) 974 tas2764->i_sense_slot = 0; 975 976 ret = fwnode_property_read_u32(dev->fwnode, "ti,vmon-slot-no", 977 &tas2764->v_sense_slot); 978 if (ret) 979 tas2764->v_sense_slot = 2; 980 981 return 0; 982 } 983 984 static int tas2764_i2c_probe(struct i2c_client *client) 985 { 986 struct tas2764_priv *tas2764; 987 int result; 988 989 tas2764 = devm_kzalloc(&client->dev, sizeof(struct tas2764_priv), 990 GFP_KERNEL); 991 if (!tas2764) 992 return -ENOMEM; 993 994 tas2764->devid = (kernel_ulong_t)of_device_get_match_data(&client->dev); 995 996 tas2764->dev = &client->dev; 997 tas2764->irq = client->irq; 998 i2c_set_clientdata(client, tas2764); 999 dev_set_drvdata(&client->dev, tas2764); 1000 1001 tas2764->regmap = devm_regmap_init_i2c(client, &tas2764_i2c_regmap); 1002 if (IS_ERR(tas2764->regmap)) { 1003 result = PTR_ERR(tas2764->regmap); 1004 dev_err(&client->dev, "Failed to allocate register map: %d\n", 1005 result); 1006 return result; 1007 } 1008 1009 if (client->dev.of_node) { 1010 result = tas2764_parse_dt(&client->dev, tas2764); 1011 if (result) { 1012 dev_err(tas2764->dev, "%s: Failed to parse devicetree\n", 1013 __func__); 1014 return result; 1015 } 1016 } 1017 1018 if (IS_REACHABLE(CONFIG_HWMON)) { 1019 struct device *hwmon; 1020 1021 hwmon = devm_hwmon_device_register_with_info(&client->dev, "tas2764", 1022 tas2764, 1023 &tas2764_hwmon_chip_info, 1024 NULL); 1025 if (IS_ERR(hwmon)) { 1026 return dev_err_probe(&client->dev, PTR_ERR(hwmon), 1027 "Failed to register temp sensor\n"); 1028 } 1029 } 1030 1031 1032 return devm_snd_soc_register_component(tas2764->dev, 1033 &soc_component_driver_tas2764, 1034 tas2764_dai_driver, 1035 ARRAY_SIZE(tas2764_dai_driver)); 1036 } 1037 1038 static const struct i2c_device_id tas2764_i2c_id[] = { 1039 { "tas2764"}, 1040 { } 1041 }; 1042 MODULE_DEVICE_TABLE(i2c, tas2764_i2c_id); 1043 1044 #if defined(CONFIG_OF) 1045 static const struct of_device_id tas2764_of_match[] = { 1046 { .compatible = "ti,tas2764", .data = (void *)DEVID_TAS2764 }, 1047 { .compatible = "ti,sn012776", .data = (void *)DEVID_SN012776 }, 1048 {}, 1049 }; 1050 MODULE_DEVICE_TABLE(of, tas2764_of_match); 1051 #endif 1052 1053 static struct i2c_driver tas2764_i2c_driver = { 1054 .driver = { 1055 .name = "tas2764", 1056 .of_match_table = of_match_ptr(tas2764_of_match), 1057 }, 1058 .probe = tas2764_i2c_probe, 1059 .id_table = tas2764_i2c_id, 1060 }; 1061 module_i2c_driver(tas2764_i2c_driver); 1062 1063 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 1064 MODULE_DESCRIPTION("TAS2764 I2C Smart Amplifier driver"); 1065 MODULE_LICENSE("GPL v2"); 1066