xref: /linux/sound/soc/codecs/tas2552.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
25df7f71dSDan Murphy /*
35df7f71dSDan Murphy  * tas2552.h - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier
45df7f71dSDan Murphy  *
5*5856d8bdSAlexander A. Klimov  * Copyright (C) 2014 Texas Instruments Incorporated -  https://www.ti.com
65df7f71dSDan Murphy  *
75df7f71dSDan Murphy  * Author: Dan Murphy <dmurphy@ti.com>
85df7f71dSDan Murphy  */
95df7f71dSDan Murphy 
105df7f71dSDan Murphy #ifndef __TAS2552_H__
115df7f71dSDan Murphy #define __TAS2552_H__
125df7f71dSDan Murphy 
135df7f71dSDan Murphy /* Register Address Map */
145df7f71dSDan Murphy #define TAS2552_DEVICE_STATUS		0x00
155df7f71dSDan Murphy #define TAS2552_CFG_1			0x01
165df7f71dSDan Murphy #define TAS2552_CFG_2			0x02
175df7f71dSDan Murphy #define TAS2552_CFG_3			0x03
185df7f71dSDan Murphy #define TAS2552_DOUT			0x04
195df7f71dSDan Murphy #define TAS2552_SER_CTRL_1		0x05
205df7f71dSDan Murphy #define TAS2552_SER_CTRL_2		0x06
215df7f71dSDan Murphy #define TAS2552_OUTPUT_DATA		0x07
225df7f71dSDan Murphy #define TAS2552_PLL_CTRL_1		0x08
235df7f71dSDan Murphy #define TAS2552_PLL_CTRL_2		0x09
245df7f71dSDan Murphy #define TAS2552_PLL_CTRL_3		0x0a
255df7f71dSDan Murphy #define TAS2552_BTIP			0x0b
265df7f71dSDan Murphy #define TAS2552_BTS_CTRL		0x0c
275df7f71dSDan Murphy #define TAS2552_RESERVED_0D		0x0d
285df7f71dSDan Murphy #define TAS2552_LIMIT_RATE_HYS		0x0e
295df7f71dSDan Murphy #define TAS2552_LIMIT_RELEASE		0x0f
305df7f71dSDan Murphy #define TAS2552_LIMIT_INT_COUNT		0x10
315df7f71dSDan Murphy #define TAS2552_PDM_CFG			0x11
325df7f71dSDan Murphy #define TAS2552_PGA_GAIN		0x12
335df7f71dSDan Murphy #define TAS2552_EDGE_RATE_CTRL		0x13
342a9dd1dbSPeter Ujfalusi #define TAS2552_BOOST_APT_CTRL		0x14
355df7f71dSDan Murphy #define TAS2552_VER_NUM			0x16
365df7f71dSDan Murphy #define TAS2552_VBAT_DATA		0x19
3795f1044fSAxel Lin #define TAS2552_MAX_REG			TAS2552_VBAT_DATA
385df7f71dSDan Murphy 
395df7f71dSDan Murphy /* CFG1 Register Masks */
407de544fdSPeter Ujfalusi #define TAS2552_DEV_RESET		(1 << 0)
417de544fdSPeter Ujfalusi #define TAS2552_SWS			(1 << 1)
427de544fdSPeter Ujfalusi #define TAS2552_MUTE			(1 << 2)
437de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_MCLK		(0x0 << 4)
447de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_BCLK		(0x1 << 4)
457de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_IVCLKIN		(0x2 << 4)
467de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_1_8_FIXED 	(0x3 << 4)
477de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_MASK	 	TAS2552_PLL_SRC_1_8_FIXED
485df7f71dSDan Murphy 
495df7f71dSDan Murphy /* CFG2 Register Masks */
505df7f71dSDan Murphy #define TAS2552_CLASSD_EN		(1 << 7)
515df7f71dSDan Murphy #define TAS2552_BOOST_EN		(1 << 6)
525df7f71dSDan Murphy #define TAS2552_APT_EN			(1 << 5)
535df7f71dSDan Murphy #define TAS2552_PLL_ENABLE		(1 << 3)
545df7f71dSDan Murphy #define TAS2552_LIM_EN			(1 << 2)
555df7f71dSDan Murphy #define TAS2552_IVSENSE_EN		(1 << 1)
565df7f71dSDan Murphy 
57a571cb17SPeter Ujfalusi /* CFG3 Register Masks */
58a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_8KHZ		(0x0 << 0)
59a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_11_12KHZ	(0x1 << 0)
60a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_16KHZ		(0x2 << 0)
61a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_22_24KHZ	(0x3 << 0)
62a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_32KHZ		(0x4 << 0)
63a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_44_48KHZ	(0x5 << 0)
64a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_88_96KHZ	(0x6 << 0)
65a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_176_192KHZ	(0x7 << 0)
66a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_MASK		TAS2552_WCLK_FREQ_176_192KHZ
67a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_MUTED	(0x0 << 3)
68a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_LEFT	(0x1 << 3)
69a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_RIGHT	(0x2 << 3)
70a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_AVG_L_R	(0x3 << 3)
71a571cb17SPeter Ujfalusi #define TAS2552_PDM_IN_SEL		(1 << 5)
72a571cb17SPeter Ujfalusi #define TAS2552_I2S_OUT_SEL		(1 << 6)
73a571cb17SPeter Ujfalusi #define TAS2552_ANALOG_IN_SEL		(1 << 7)
74a571cb17SPeter Ujfalusi 
753f747a81SPeter Ujfalusi /* DOUT Register Masks */
763f747a81SPeter Ujfalusi #define TAS2552_SDOUT_TRISTATE		(1 << 2)
773f747a81SPeter Ujfalusi 
781b68c7dcSPeter Ujfalusi /* Serial Interface Control Register Masks */
79d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_16BIT	(0x0 << 0)
80d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_20BIT	(0x1 << 0)
81d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_24BIT	(0x2 << 0)
82d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_32BIT	(0x3 << 0)
83d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_MASK		TAS2552_WORDLENGTH_32BIT
841b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_I2S		(0x0 << 2)
851b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_DSP		(0x1 << 2)
861b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_RIGHT_J	(0x2 << 2)
871b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_LEFT_J	(0x3 << 2)
881b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_MASK		TAS2552_DATAFORMAT_LEFT_J
89d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_32		(0x0 << 4)
90d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_64		(0x1 << 4)
91d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_128	(0x2 << 4)
92d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_256	(0x3 << 4)
93d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_MASK	TAS2552_CLKSPERFRAME_256
941b68c7dcSPeter Ujfalusi #define TAS2552_BCLKDIR			(1 << 6)
951b68c7dcSPeter Ujfalusi #define TAS2552_WCLKDIR			(1 << 7)
965df7f71dSDan Murphy 
975df7f71dSDan Murphy /* OUTPUT_DATA register */
98b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_I_DATA		(0x0)
99b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_V_DATA		(0x1)
100b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_VBAT_DATA	(0x2)
101b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_VBOOST_DATA	(0x3)
102b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_PGA_GAIN	(0x4)
103b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_IV_DATA	(0x5)
104b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_VBAT_VBOOST_GAIN	(0x6)
105b2822f19SPeter Ujfalusi #define TAS2552_DATA_OUT_DISABLED	(0x7)
106b2822f19SPeter Ujfalusi #define TAS2552_L_DATA_OUT(x)		((x) << 0)
107b2822f19SPeter Ujfalusi #define TAS2552_R_DATA_OUT(x)		((x) << 3)
108b2822f19SPeter Ujfalusi #define TAS2552_PDM_DATA_SEL_I		(0x0 << 6)
109b2822f19SPeter Ujfalusi #define TAS2552_PDM_DATA_SEL_V		(0x1 << 6)
110b2822f19SPeter Ujfalusi #define TAS2552_PDM_DATA_SEL_I_V	(0x2 << 6)
111b2822f19SPeter Ujfalusi #define TAS2552_PDM_DATA_SEL_V_I	(0x3 << 6)
112b2822f19SPeter Ujfalusi #define TAS2552_PDM_DATA_SEL_MASK	TAS2552_PDM_DATA_SEL_V_I
1135df7f71dSDan Murphy 
1145df7f71dSDan Murphy /* PDM CFG Register */
11589683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_PLL		(0x0 << 0)
11689683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_IVCLKIN	(0x1 << 0)
11789683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_BCLK	(0x2 << 0)
11889683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_MCLK	(0x3 << 0)
11989683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_MASK	TAS2552_PDM_CLK_SEL_MCLK
12089683fdeSPeter Ujfalusi #define TAS2552_PDM_DATA_ES	 	(1 << 2)
1215df7f71dSDan Murphy 
1222a9dd1dbSPeter Ujfalusi /* Boost Auto-pass through register */
1232a9dd1dbSPeter Ujfalusi #define TAS2552_APT_DELAY_50		(0x0 << 0)
1242a9dd1dbSPeter Ujfalusi #define TAS2552_APT_DELAY_75		(0x1 << 0)
1252a9dd1dbSPeter Ujfalusi #define TAS2552_APT_DELAY_125		(0x2 << 0)
1262a9dd1dbSPeter Ujfalusi #define TAS2552_APT_DELAY_200		(0x3 << 0)
1272a9dd1dbSPeter Ujfalusi #define TAS2552_APT_THRESH_05_02	(0x0 << 2)
1282a9dd1dbSPeter Ujfalusi #define TAS2552_APT_THRESH_10_07	(0x1 << 2)
1292a9dd1dbSPeter Ujfalusi #define TAS2552_APT_THRESH_14_11	(0x2 << 2)
1302a9dd1dbSPeter Ujfalusi #define TAS2552_APT_THRESH_20_17	(0x3 << 2)
1315df7f71dSDan Murphy 
1325df7f71dSDan Murphy /* PLL Control Register */
1335df7f71dSDan Murphy #define TAS2552_PLL_J_MASK		0x7f
1341014f7efSPeter Ujfalusi #define TAS2552_PLL_D_UPPER(x)		(((x) >> 8) & 0x3f)
1351014f7efSPeter Ujfalusi #define TAS2552_PLL_D_LOWER(x)		((x) & 0xff)
1361014f7efSPeter Ujfalusi #define TAS2552_PLL_BYPASS		(1 << 7)
1375df7f71dSDan Murphy 
1385df7f71dSDan Murphy #endif
139