xref: /linux/sound/soc/codecs/tas2552.h (revision 1014f7eff9a1d4f3f796c83e933adf2462c79005)
15df7f71dSDan Murphy /*
25df7f71dSDan Murphy  * tas2552.h - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier
35df7f71dSDan Murphy  *
45df7f71dSDan Murphy  * Copyright (C) 2014 Texas Instruments Incorporated -  http://www.ti.com
55df7f71dSDan Murphy  *
65df7f71dSDan Murphy  * Author: Dan Murphy <dmurphy@ti.com>
75df7f71dSDan Murphy  *
85df7f71dSDan Murphy  * This program is free software; you can redistribute it and/or
95df7f71dSDan Murphy  * modify it under the terms of the GNU General Public License
105df7f71dSDan Murphy  * version 2 as published by the Free Software Foundation.
115df7f71dSDan Murphy  *
125df7f71dSDan Murphy  * This program is distributed in the hope that it will be useful, but
135df7f71dSDan Murphy  * WITHOUT ANY WARRANTY; without even the implied warranty of
145df7f71dSDan Murphy  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
155df7f71dSDan Murphy  * General Public License for more details.
165df7f71dSDan Murphy  */
175df7f71dSDan Murphy 
185df7f71dSDan Murphy #ifndef __TAS2552_H__
195df7f71dSDan Murphy #define __TAS2552_H__
205df7f71dSDan Murphy 
215df7f71dSDan Murphy /* Register Address Map */
225df7f71dSDan Murphy #define TAS2552_DEVICE_STATUS	0x00
235df7f71dSDan Murphy #define TAS2552_CFG_1			0x01
245df7f71dSDan Murphy #define TAS2552_CFG_2			0x02
255df7f71dSDan Murphy #define TAS2552_CFG_3			0x03
265df7f71dSDan Murphy #define TAS2552_DOUT			0x04
275df7f71dSDan Murphy #define TAS2552_SER_CTRL_1		0x05
285df7f71dSDan Murphy #define TAS2552_SER_CTRL_2		0x06
295df7f71dSDan Murphy #define TAS2552_OUTPUT_DATA		0x07
305df7f71dSDan Murphy #define TAS2552_PLL_CTRL_1		0x08
315df7f71dSDan Murphy #define TAS2552_PLL_CTRL_2		0x09
325df7f71dSDan Murphy #define TAS2552_PLL_CTRL_3		0x0a
335df7f71dSDan Murphy #define TAS2552_BTIP			0x0b
345df7f71dSDan Murphy #define TAS2552_BTS_CTRL		0x0c
355df7f71dSDan Murphy #define TAS2552_RESERVED_0D		0x0d
365df7f71dSDan Murphy #define TAS2552_LIMIT_RATE_HYS	0x0e
375df7f71dSDan Murphy #define TAS2552_LIMIT_RELEASE	0x0f
385df7f71dSDan Murphy #define TAS2552_LIMIT_INT_COUNT	0x10
395df7f71dSDan Murphy #define TAS2552_PDM_CFG			0x11
405df7f71dSDan Murphy #define TAS2552_PGA_GAIN		0x12
415df7f71dSDan Murphy #define TAS2552_EDGE_RATE_CTRL	0x13
425df7f71dSDan Murphy #define TAS2552_BOOST_PT_CTRL	0x14
435df7f71dSDan Murphy #define TAS2552_VER_NUM			0x16
445df7f71dSDan Murphy #define TAS2552_VBAT_DATA		0x19
455df7f71dSDan Murphy #define TAS2552_MAX_REG			0x20
465df7f71dSDan Murphy 
475df7f71dSDan Murphy /* CFG1 Register Masks */
487de544fdSPeter Ujfalusi #define TAS2552_DEV_RESET		(1 << 0)
497de544fdSPeter Ujfalusi #define TAS2552_SWS			(1 << 1)
507de544fdSPeter Ujfalusi #define TAS2552_MUTE			(1 << 2)
517de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_MCLK		(0x0 << 4)
527de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_BCLK		(0x1 << 4)
537de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_IVCLKIN		(0x2 << 4)
547de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_1_8_FIXED 	(0x3 << 4)
557de544fdSPeter Ujfalusi #define TAS2552_PLL_SRC_MASK	 	TAS2552_PLL_SRC_1_8_FIXED
565df7f71dSDan Murphy 
575df7f71dSDan Murphy /* CFG2 Register Masks */
585df7f71dSDan Murphy #define TAS2552_CLASSD_EN		(1 << 7)
595df7f71dSDan Murphy #define TAS2552_BOOST_EN		(1 << 6)
605df7f71dSDan Murphy #define TAS2552_APT_EN			(1 << 5)
615df7f71dSDan Murphy #define TAS2552_PLL_ENABLE		(1 << 3)
625df7f71dSDan Murphy #define TAS2552_LIM_EN			(1 << 2)
635df7f71dSDan Murphy #define TAS2552_IVSENSE_EN		(1 << 1)
645df7f71dSDan Murphy 
65a571cb17SPeter Ujfalusi /* CFG3 Register Masks */
66a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_8KHZ		(0x0 << 0)
67a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_11_12KHZ	(0x1 << 0)
68a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_16KHZ		(0x2 << 0)
69a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_22_24KHZ	(0x3 << 0)
70a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_32KHZ		(0x4 << 0)
71a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_44_48KHZ	(0x5 << 0)
72a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_88_96KHZ	(0x6 << 0)
73a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_176_192KHZ	(0x7 << 0)
74a571cb17SPeter Ujfalusi #define TAS2552_WCLK_FREQ_MASK		TAS2552_WCLK_FREQ_176_192KHZ
75a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_MUTED	(0x0 << 3)
76a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_LEFT	(0x1 << 3)
77a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_RIGHT	(0x2 << 3)
78a571cb17SPeter Ujfalusi #define TAS2552_DIN_SRC_SEL_AVG_L_R	(0x3 << 3)
79a571cb17SPeter Ujfalusi #define TAS2552_PDM_IN_SEL		(1 << 5)
80a571cb17SPeter Ujfalusi #define TAS2552_I2S_OUT_SEL		(1 << 6)
81a571cb17SPeter Ujfalusi #define TAS2552_ANALOG_IN_SEL		(1 << 7)
82a571cb17SPeter Ujfalusi 
833f747a81SPeter Ujfalusi /* DOUT Register Masks */
843f747a81SPeter Ujfalusi #define TAS2552_SDOUT_TRISTATE		(1 << 2)
853f747a81SPeter Ujfalusi 
861b68c7dcSPeter Ujfalusi /* Serial Interface Control Register Masks */
87d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_16BIT	(0x0 << 0)
88d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_20BIT	(0x1 << 0)
89d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_24BIT	(0x2 << 0)
90d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_32BIT	(0x3 << 0)
91d20b098dSPeter Ujfalusi #define TAS2552_WORDLENGTH_MASK		TAS2552_WORDLENGTH_32BIT
921b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_I2S		(0x0 << 2)
931b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_DSP		(0x1 << 2)
941b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_RIGHT_J	(0x2 << 2)
951b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_LEFT_J	(0x3 << 2)
961b68c7dcSPeter Ujfalusi #define TAS2552_DATAFORMAT_MASK		TAS2552_DATAFORMAT_LEFT_J
97d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_32		(0x0 << 4)
98d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_64		(0x1 << 4)
99d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_128	(0x2 << 4)
100d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_256	(0x3 << 4)
101d20b098dSPeter Ujfalusi #define TAS2552_CLKSPERFRAME_MASK	TAS2552_CLKSPERFRAME_256
1021b68c7dcSPeter Ujfalusi #define TAS2552_BCLKDIR			(1 << 6)
1031b68c7dcSPeter Ujfalusi #define TAS2552_WCLKDIR			(1 << 7)
1045df7f71dSDan Murphy 
1055df7f71dSDan Murphy /* OUTPUT_DATA register */
1065df7f71dSDan Murphy #define TAS2552_PDM_DATA_I		0x00
1075df7f71dSDan Murphy #define TAS2552_PDM_DATA_V		(1 << 6)
1085df7f71dSDan Murphy #define TAS2552_PDM_DATA_I_V	(1 << 7)
1095df7f71dSDan Murphy #define TAS2552_PDM_DATA_V_I	(0x11 << 6)
1105df7f71dSDan Murphy 
1115df7f71dSDan Murphy /* PDM CFG Register */
11289683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_PLL		(0x0 << 0)
11389683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_IVCLKIN	(0x1 << 0)
11489683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_BCLK	(0x2 << 0)
11589683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_MCLK	(0x3 << 0)
11689683fdeSPeter Ujfalusi #define TAS2552_PDM_CLK_SEL_MASK	TAS2552_PDM_CLK_SEL_MCLK
11789683fdeSPeter Ujfalusi #define TAS2552_PDM_DATA_ES	 	(1 << 2)
1185df7f71dSDan Murphy 
1195df7f71dSDan Murphy /* Boost pass-through register */
1205df7f71dSDan Murphy #define TAS2552_APT_DELAY_50	0x00
1215df7f71dSDan Murphy #define TAS2552_APT_DELAY_75	(1 << 1)
1225df7f71dSDan Murphy #define TAS2552_APT_DELAY_125	(1 << 2)
1235df7f71dSDan Murphy #define TAS2552_APT_DELAY_200	(1 << 3)
1245df7f71dSDan Murphy 
1255df7f71dSDan Murphy #define TAS2552_APT_THRESH_2_5		0x00
1265df7f71dSDan Murphy #define TAS2552_APT_THRESH_1_7		(1 << 3)
1275df7f71dSDan Murphy #define TAS2552_APT_THRESH_1_4_1_1	(1 << 4)
1285df7f71dSDan Murphy #define TAS2552_APT_THRESH_2_1_7	(0x11 << 2)
1295df7f71dSDan Murphy 
1305df7f71dSDan Murphy /* PLL Control Register */
1315df7f71dSDan Murphy #define TAS2552_PLL_J_MASK		0x7f
132*1014f7efSPeter Ujfalusi #define TAS2552_PLL_D_UPPER(x)		(((x) >> 8) & 0x3f)
133*1014f7efSPeter Ujfalusi #define TAS2552_PLL_D_LOWER(x)		((x) & 0xff)
134*1014f7efSPeter Ujfalusi #define TAS2552_PLL_BYPASS		(1 << 7)
1355df7f71dSDan Murphy 
1365df7f71dSDan Murphy #endif
137