1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system 4 * 5 * Copyright: 2011 Raumfeld GmbH 6 * Author: Johannes Stezenbach <js@sig21.net> 7 * 8 * based on code from: 9 * Wolfson Microelectronics PLC. 10 * Mark Brown <broonie@opensource.wolfsonmicro.com> 11 * Freescale Semiconductor, Inc. 12 * Timur Tabi <timur@freescale.com> 13 */ 14 15 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__ 16 17 #include <linux/module.h> 18 #include <linux/moduleparam.h> 19 #include <linux/init.h> 20 #include <linux/cleanup.h> 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/pm.h> 24 #include <linux/i2c.h> 25 #include <linux/of.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/gpio/consumer.h> 29 #include <linux/slab.h> 30 #include <linux/workqueue.h> 31 #include <sound/core.h> 32 #include <sound/pcm.h> 33 #include <sound/pcm_params.h> 34 #include <sound/soc.h> 35 #include <sound/soc-dapm.h> 36 #include <sound/initval.h> 37 #include <sound/tlv.h> 38 39 #include <sound/sta32x.h> 40 #include "sta32x.h" 41 42 #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \ 43 SNDRV_PCM_RATE_44100 | \ 44 SNDRV_PCM_RATE_48000 | \ 45 SNDRV_PCM_RATE_88200 | \ 46 SNDRV_PCM_RATE_96000 | \ 47 SNDRV_PCM_RATE_176400 | \ 48 SNDRV_PCM_RATE_192000) 49 50 #define STA32X_FORMATS \ 51 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \ 52 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \ 53 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 54 55 /* Power-up register defaults */ 56 static const struct reg_default sta32x_regs[] = { 57 { 0x0, 0x63 }, 58 { 0x1, 0x80 }, 59 { 0x2, 0xc2 }, 60 { 0x3, 0x40 }, 61 { 0x4, 0xc2 }, 62 { 0x5, 0x5c }, 63 { 0x6, 0x10 }, 64 { 0x7, 0xff }, 65 { 0x8, 0x60 }, 66 { 0x9, 0x60 }, 67 { 0xa, 0x60 }, 68 { 0xb, 0x80 }, 69 { 0xc, 0x00 }, 70 { 0xd, 0x00 }, 71 { 0xe, 0x00 }, 72 { 0xf, 0x40 }, 73 { 0x10, 0x80 }, 74 { 0x11, 0x77 }, 75 { 0x12, 0x6a }, 76 { 0x13, 0x69 }, 77 { 0x14, 0x6a }, 78 { 0x15, 0x69 }, 79 { 0x16, 0x00 }, 80 { 0x17, 0x00 }, 81 { 0x18, 0x00 }, 82 { 0x19, 0x00 }, 83 { 0x1a, 0x00 }, 84 { 0x1b, 0x00 }, 85 { 0x1c, 0x00 }, 86 { 0x1d, 0x00 }, 87 { 0x1e, 0x00 }, 88 { 0x1f, 0x00 }, 89 { 0x20, 0x00 }, 90 { 0x21, 0x00 }, 91 { 0x22, 0x00 }, 92 { 0x23, 0x00 }, 93 { 0x24, 0x00 }, 94 { 0x25, 0x00 }, 95 { 0x26, 0x00 }, 96 { 0x27, 0x2d }, 97 { 0x28, 0xc0 }, 98 { 0x2b, 0x00 }, 99 { 0x2c, 0x0c }, 100 }; 101 102 static const struct regmap_range sta32x_write_regs_range[] = { 103 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2), 104 }; 105 106 static const struct regmap_range sta32x_read_regs_range[] = { 107 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2), 108 }; 109 110 static const struct regmap_range sta32x_volatile_regs_range[] = { 111 regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD), 112 }; 113 114 static const struct regmap_access_table sta32x_write_regs = { 115 .yes_ranges = sta32x_write_regs_range, 116 .n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range), 117 }; 118 119 static const struct regmap_access_table sta32x_read_regs = { 120 .yes_ranges = sta32x_read_regs_range, 121 .n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range), 122 }; 123 124 static const struct regmap_access_table sta32x_volatile_regs = { 125 .yes_ranges = sta32x_volatile_regs_range, 126 .n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range), 127 }; 128 129 /* regulator power supply names */ 130 static const char *sta32x_supply_names[] = { 131 "Vdda", /* analog supply, 3.3VV */ 132 "Vdd3", /* digital supply, 3.3V */ 133 "Vcc" /* power amp spply, 10V - 36V */ 134 }; 135 136 /* codec private data */ 137 struct sta32x_priv { 138 struct regmap *regmap; 139 struct clk *xti_clk; 140 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)]; 141 struct snd_soc_component *component; 142 struct sta32x_platform_data *pdata; 143 144 unsigned int mclk; 145 unsigned int format; 146 147 u32 coef_shadow[STA32X_COEF_COUNT]; 148 struct delayed_work watchdog_work; 149 int shutdown; 150 struct gpio_desc *gpiod_nreset; 151 struct mutex coeff_lock; 152 }; 153 154 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1); 155 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1); 156 static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0); 157 158 static const char *sta32x_drc_ac[] = { 159 "Anti-Clipping", "Dynamic Range Compression" }; 160 static const char *sta32x_auto_eq_mode[] = { 161 "User", "Preset", "Loudness" }; 162 static const char *sta32x_auto_gc_mode[] = { 163 "User", "AC no clipping", "AC limited clipping (10%)", 164 "DRC nighttime listening mode" }; 165 static const char *sta32x_auto_xo_mode[] = { 166 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz", 167 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" }; 168 static const char *sta32x_preset_eq_mode[] = { 169 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft", 170 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1", 171 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2", 172 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7", 173 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12", 174 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" }; 175 static const char *sta32x_limiter_select[] = { 176 "Limiter Disabled", "Limiter #1", "Limiter #2" }; 177 static const char *sta32x_limiter_attack_rate[] = { 178 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024", 179 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752", 180 "0.0645", "0.0564", "0.0501", "0.0451" }; 181 static const char *sta32x_limiter_release_rate[] = { 182 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", 183 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", 184 "0.0134", "0.0117", "0.0110", "0.0104" }; 185 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv, 186 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), 187 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), 188 ); 189 190 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv, 191 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), 192 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), 193 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), 194 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), 195 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), 196 ); 197 198 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv, 199 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), 200 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), 201 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), 202 ); 203 204 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv, 205 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), 206 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), 207 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), 208 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), 209 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), 210 ); 211 212 static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum, 213 STA32X_CONFD, STA32X_CONFD_DRC_SHIFT, 214 sta32x_drc_ac); 215 static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum, 216 STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT, 217 sta32x_auto_eq_mode); 218 static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum, 219 STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT, 220 sta32x_auto_gc_mode); 221 static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum, 222 STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT, 223 sta32x_auto_xo_mode); 224 static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum, 225 STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT, 226 sta32x_preset_eq_mode); 227 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum, 228 STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT, 229 sta32x_limiter_select); 230 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum, 231 STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT, 232 sta32x_limiter_select); 233 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum, 234 STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT, 235 sta32x_limiter_select); 236 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum, 237 STA32X_L1AR, STA32X_LxA_SHIFT, 238 sta32x_limiter_attack_rate); 239 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum, 240 STA32X_L2AR, STA32X_LxA_SHIFT, 241 sta32x_limiter_attack_rate); 242 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum, 243 STA32X_L1AR, STA32X_LxR_SHIFT, 244 sta32x_limiter_release_rate); 245 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum, 246 STA32X_L2AR, STA32X_LxR_SHIFT, 247 sta32x_limiter_release_rate); 248 249 /* byte array controls for setting biquad, mixer, scaling coefficients; 250 * for biquads all five coefficients need to be set in one go, 251 * mixer and pre/postscale coefs can be set individually; 252 * each coef is 24bit, the bytes are ordered in the same way 253 * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0) 254 */ 255 256 static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol, 257 struct snd_ctl_elem_info *uinfo) 258 { 259 int numcoef = kcontrol->private_value >> 16; 260 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 261 uinfo->count = 3 * numcoef; 262 return 0; 263 } 264 265 static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol, 266 struct snd_ctl_elem_value *ucontrol) 267 { 268 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 269 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 270 int numcoef = kcontrol->private_value >> 16; 271 int index = kcontrol->private_value & 0xffff; 272 unsigned int cfud, val; 273 int i; 274 275 guard(mutex)(&sta32x->coeff_lock); 276 277 /* preserve reserved bits in STA32X_CFUD */ 278 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); 279 cfud &= 0xf0; 280 /* 281 * chip documentation does not say if the bits are self clearing, 282 * so do it explicitly 283 */ 284 regmap_write(sta32x->regmap, STA32X_CFUD, cfud); 285 286 regmap_write(sta32x->regmap, STA32X_CFADDR2, index); 287 if (numcoef == 1) 288 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04); 289 else if (numcoef == 5) 290 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08); 291 else 292 return -EINVAL; 293 294 295 for (i = 0; i < 3 * numcoef; i++) { 296 regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val); 297 ucontrol->value.bytes.data[i] = val; 298 } 299 300 return 0; 301 } 302 303 static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, 304 struct snd_ctl_elem_value *ucontrol) 305 { 306 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 307 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 308 int numcoef = kcontrol->private_value >> 16; 309 int index = kcontrol->private_value & 0xffff; 310 unsigned int cfud; 311 int i; 312 313 /* preserve reserved bits in STA32X_CFUD */ 314 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); 315 cfud &= 0xf0; 316 /* 317 * chip documentation does not say if the bits are self clearing, 318 * so do it explicitly 319 */ 320 regmap_write(sta32x->regmap, STA32X_CFUD, cfud); 321 322 regmap_write(sta32x->regmap, STA32X_CFADDR2, index); 323 for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++) 324 sta32x->coef_shadow[index + i] = 325 (ucontrol->value.bytes.data[3 * i] << 16) 326 | (ucontrol->value.bytes.data[3 * i + 1] << 8) 327 | (ucontrol->value.bytes.data[3 * i + 2]); 328 for (i = 0; i < 3 * numcoef; i++) 329 regmap_write(sta32x->regmap, STA32X_B1CF1 + i, 330 ucontrol->value.bytes.data[i]); 331 if (numcoef == 1) 332 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01); 333 else if (numcoef == 5) 334 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02); 335 else 336 return -EINVAL; 337 338 return 0; 339 } 340 341 static int sta32x_sync_coef_shadow(struct snd_soc_component *component) 342 { 343 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 344 unsigned int cfud; 345 int i; 346 347 /* preserve reserved bits in STA32X_CFUD */ 348 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); 349 cfud &= 0xf0; 350 351 for (i = 0; i < STA32X_COEF_COUNT; i++) { 352 regmap_write(sta32x->regmap, STA32X_CFADDR2, i); 353 regmap_write(sta32x->regmap, STA32X_B1CF1, 354 (sta32x->coef_shadow[i] >> 16) & 0xff); 355 regmap_write(sta32x->regmap, STA32X_B1CF2, 356 (sta32x->coef_shadow[i] >> 8) & 0xff); 357 regmap_write(sta32x->regmap, STA32X_B1CF3, 358 (sta32x->coef_shadow[i]) & 0xff); 359 /* 360 * chip documentation does not say if the bits are 361 * self-clearing, so do it explicitly 362 */ 363 regmap_write(sta32x->regmap, STA32X_CFUD, cfud); 364 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01); 365 } 366 return 0; 367 } 368 369 static int sta32x_cache_sync(struct snd_soc_component *component) 370 { 371 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 372 unsigned int mute; 373 int rc; 374 375 /* mute during register sync */ 376 regmap_read(sta32x->regmap, STA32X_MMUTE, &mute); 377 regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE); 378 sta32x_sync_coef_shadow(component); 379 rc = regcache_sync(sta32x->regmap); 380 regmap_write(sta32x->regmap, STA32X_MMUTE, mute); 381 return rc; 382 } 383 384 /* work around ESD issue where sta32x resets and loses all configuration */ 385 static void sta32x_watchdog(struct work_struct *work) 386 { 387 struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv, 388 watchdog_work.work); 389 struct snd_soc_component *component = sta32x->component; 390 unsigned int confa, confa_cached; 391 392 /* check if sta32x has reset itself */ 393 confa_cached = snd_soc_component_read(component, STA32X_CONFA); 394 regcache_cache_bypass(sta32x->regmap, true); 395 confa = snd_soc_component_read(component, STA32X_CONFA); 396 regcache_cache_bypass(sta32x->regmap, false); 397 if (confa != confa_cached) { 398 regcache_mark_dirty(sta32x->regmap); 399 sta32x_cache_sync(component); 400 } 401 402 if (!sta32x->shutdown) 403 queue_delayed_work(system_power_efficient_wq, 404 &sta32x->watchdog_work, 405 round_jiffies_relative(HZ)); 406 } 407 408 static void sta32x_watchdog_start(struct sta32x_priv *sta32x) 409 { 410 if (sta32x->pdata->needs_esd_watchdog) { 411 sta32x->shutdown = 0; 412 queue_delayed_work(system_power_efficient_wq, 413 &sta32x->watchdog_work, 414 round_jiffies_relative(HZ)); 415 } 416 } 417 418 static void sta32x_watchdog_stop(struct sta32x_priv *sta32x) 419 { 420 if (sta32x->pdata->needs_esd_watchdog) { 421 sta32x->shutdown = 1; 422 cancel_delayed_work_sync(&sta32x->watchdog_work); 423 } 424 } 425 426 #define SINGLE_COEF(xname, index) \ 427 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 428 .info = sta32x_coefficient_info, \ 429 .get = sta32x_coefficient_get,\ 430 .put = sta32x_coefficient_put, \ 431 .private_value = index | (1 << 16) } 432 433 #define BIQUAD_COEFS(xname, index) \ 434 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 435 .info = sta32x_coefficient_info, \ 436 .get = sta32x_coefficient_get,\ 437 .put = sta32x_coefficient_put, \ 438 .private_value = index | (5 << 16) } 439 440 static const struct snd_kcontrol_new sta32x_snd_controls[] = { 441 SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv), 442 SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1), 443 SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1), 444 SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1), 445 SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1), 446 SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv), 447 SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv), 448 SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv), 449 SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0), 450 SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum), 451 SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0), 452 SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0), 453 SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0), 454 SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0), 455 SOC_ENUM("Automode EQ", sta32x_auto_eq_enum), 456 SOC_ENUM("Automode GC", sta32x_auto_gc_enum), 457 SOC_ENUM("Automode XO", sta32x_auto_xo_enum), 458 SOC_ENUM("Preset EQ", sta32x_preset_eq_enum), 459 SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), 460 SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), 461 SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), 462 SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), 463 SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), 464 SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), 465 SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), 466 SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum), 467 SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum), 468 SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum), 469 SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv), 470 SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv), 471 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum), 472 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum), 473 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum), 474 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum), 475 476 /* depending on mode, the attack/release thresholds have 477 * two different enum definitions; provide both 478 */ 479 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, 480 16, 0, sta32x_limiter_ac_attack_tlv), 481 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, 482 16, 0, sta32x_limiter_ac_attack_tlv), 483 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, 484 16, 0, sta32x_limiter_ac_release_tlv), 485 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, 486 16, 0, sta32x_limiter_ac_release_tlv), 487 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, 488 16, 0, sta32x_limiter_drc_attack_tlv), 489 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, 490 16, 0, sta32x_limiter_drc_attack_tlv), 491 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, 492 16, 0, sta32x_limiter_drc_release_tlv), 493 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, 494 16, 0, sta32x_limiter_drc_release_tlv), 495 496 BIQUAD_COEFS("Ch1 - Biquad 1", 0), 497 BIQUAD_COEFS("Ch1 - Biquad 2", 5), 498 BIQUAD_COEFS("Ch1 - Biquad 3", 10), 499 BIQUAD_COEFS("Ch1 - Biquad 4", 15), 500 BIQUAD_COEFS("Ch2 - Biquad 1", 20), 501 BIQUAD_COEFS("Ch2 - Biquad 2", 25), 502 BIQUAD_COEFS("Ch2 - Biquad 3", 30), 503 BIQUAD_COEFS("Ch2 - Biquad 4", 35), 504 BIQUAD_COEFS("High-pass", 40), 505 BIQUAD_COEFS("Low-pass", 45), 506 SINGLE_COEF("Ch1 - Prescale", 50), 507 SINGLE_COEF("Ch2 - Prescale", 51), 508 SINGLE_COEF("Ch1 - Postscale", 52), 509 SINGLE_COEF("Ch2 - Postscale", 53), 510 SINGLE_COEF("Ch3 - Postscale", 54), 511 SINGLE_COEF("Thermal warning - Postscale", 55), 512 SINGLE_COEF("Ch1 - Mix 1", 56), 513 SINGLE_COEF("Ch1 - Mix 2", 57), 514 SINGLE_COEF("Ch2 - Mix 1", 58), 515 SINGLE_COEF("Ch2 - Mix 2", 59), 516 SINGLE_COEF("Ch3 - Mix 1", 60), 517 SINGLE_COEF("Ch3 - Mix 2", 61), 518 }; 519 520 static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = { 521 SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0), 522 SND_SOC_DAPM_OUTPUT("LEFT"), 523 SND_SOC_DAPM_OUTPUT("RIGHT"), 524 SND_SOC_DAPM_OUTPUT("SUB"), 525 }; 526 527 static const struct snd_soc_dapm_route sta32x_dapm_routes[] = { 528 { "LEFT", NULL, "DAC" }, 529 { "RIGHT", NULL, "DAC" }, 530 { "SUB", NULL, "DAC" }, 531 }; 532 533 /* MCLK interpolation ratio per fs */ 534 static struct { 535 int fs; 536 int ir; 537 } interpolation_ratios[] = { 538 { 32000, 0 }, 539 { 44100, 0 }, 540 { 48000, 0 }, 541 { 88200, 1 }, 542 { 96000, 1 }, 543 { 176400, 2 }, 544 { 192000, 2 }, 545 }; 546 547 /* MCLK to fs clock ratios */ 548 static int mcs_ratio_table[3][7] = { 549 { 768, 512, 384, 256, 128, 576, 0 }, 550 { 384, 256, 192, 128, 64, 0 }, 551 { 384, 256, 192, 128, 64, 0 }, 552 }; 553 554 /** 555 * sta32x_set_dai_sysclk - configure MCLK 556 * @codec_dai: the codec DAI 557 * @clk_id: the clock ID (ignored) 558 * @freq: the MCLK input frequency 559 * @dir: the clock direction (ignored) 560 * 561 * The value of MCLK is used to determine which sample rates are supported 562 * by the STA32X, based on the mclk_ratios table. 563 * 564 * This function must be called by the machine driver's 'startup' function, 565 * otherwise the list of supported sample rates will not be available in 566 * time for ALSA. 567 * 568 * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause 569 * theoretically possible sample rates to be enabled. Call it again with a 570 * proper value set one the external clock is set (most probably you would do 571 * that from a machine's driver 'hw_param' hook. 572 */ 573 static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 574 int clk_id, unsigned int freq, int dir) 575 { 576 struct snd_soc_component *component = codec_dai->component; 577 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 578 579 dev_dbg(component->dev, "mclk=%u\n", freq); 580 sta32x->mclk = freq; 581 582 return 0; 583 } 584 585 /** 586 * sta32x_set_dai_fmt - configure the codec for the selected audio format 587 * @codec_dai: the codec DAI 588 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format 589 * 590 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the 591 * codec accordingly. 592 */ 593 static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai, 594 unsigned int fmt) 595 { 596 struct snd_soc_component *component = codec_dai->component; 597 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 598 u8 confb = 0; 599 600 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 601 case SND_SOC_DAIFMT_CBC_CFC: 602 break; 603 default: 604 return -EINVAL; 605 } 606 607 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 608 case SND_SOC_DAIFMT_I2S: 609 case SND_SOC_DAIFMT_RIGHT_J: 610 case SND_SOC_DAIFMT_LEFT_J: 611 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 612 break; 613 default: 614 return -EINVAL; 615 } 616 617 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 618 case SND_SOC_DAIFMT_NB_NF: 619 confb |= STA32X_CONFB_C2IM; 620 break; 621 case SND_SOC_DAIFMT_NB_IF: 622 confb |= STA32X_CONFB_C1IM; 623 break; 624 default: 625 return -EINVAL; 626 } 627 628 return regmap_update_bits(sta32x->regmap, STA32X_CONFB, 629 STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb); 630 } 631 632 /** 633 * sta32x_hw_params - program the STA32X with the given hardware parameters. 634 * @substream: the audio stream 635 * @params: the hardware parameters to set 636 * @dai: the SOC DAI (ignored) 637 * 638 * This function programs the hardware with the values provided. 639 * Specifically, the sample rate and the data format. 640 */ 641 static int sta32x_hw_params(struct snd_pcm_substream *substream, 642 struct snd_pcm_hw_params *params, 643 struct snd_soc_dai *dai) 644 { 645 struct snd_soc_component *component = dai->component; 646 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 647 int i, mcs = -EINVAL, ir = -EINVAL; 648 unsigned int confa, confb; 649 unsigned int rate, ratio; 650 int ret; 651 652 if (!sta32x->mclk) { 653 dev_err(component->dev, 654 "sta32x->mclk is unset. Unable to determine ratio\n"); 655 return -EIO; 656 } 657 658 rate = params_rate(params); 659 ratio = sta32x->mclk / rate; 660 dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio); 661 662 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { 663 if (interpolation_ratios[i].fs == rate) { 664 ir = interpolation_ratios[i].ir; 665 break; 666 } 667 } 668 669 if (ir < 0) { 670 dev_err(component->dev, "Unsupported samplerate: %u\n", rate); 671 return -EINVAL; 672 } 673 674 for (i = 0; i < 6; i++) { 675 if (mcs_ratio_table[ir][i] == ratio) { 676 mcs = i; 677 break; 678 } 679 } 680 681 if (mcs < 0) { 682 dev_err(component->dev, "Unresolvable ratio: %u\n", ratio); 683 return -EINVAL; 684 } 685 686 confa = (ir << STA32X_CONFA_IR_SHIFT) | 687 (mcs << STA32X_CONFA_MCS_SHIFT); 688 confb = 0; 689 690 switch (params_width(params)) { 691 case 24: 692 dev_dbg(component->dev, "24bit\n"); 693 fallthrough; 694 case 32: 695 dev_dbg(component->dev, "24bit or 32bit\n"); 696 switch (sta32x->format) { 697 case SND_SOC_DAIFMT_I2S: 698 confb |= 0x0; 699 break; 700 case SND_SOC_DAIFMT_LEFT_J: 701 confb |= 0x1; 702 break; 703 case SND_SOC_DAIFMT_RIGHT_J: 704 confb |= 0x2; 705 break; 706 } 707 708 break; 709 case 20: 710 dev_dbg(component->dev, "20bit\n"); 711 switch (sta32x->format) { 712 case SND_SOC_DAIFMT_I2S: 713 confb |= 0x4; 714 break; 715 case SND_SOC_DAIFMT_LEFT_J: 716 confb |= 0x5; 717 break; 718 case SND_SOC_DAIFMT_RIGHT_J: 719 confb |= 0x6; 720 break; 721 } 722 723 break; 724 case 18: 725 dev_dbg(component->dev, "18bit\n"); 726 switch (sta32x->format) { 727 case SND_SOC_DAIFMT_I2S: 728 confb |= 0x8; 729 break; 730 case SND_SOC_DAIFMT_LEFT_J: 731 confb |= 0x9; 732 break; 733 case SND_SOC_DAIFMT_RIGHT_J: 734 confb |= 0xa; 735 break; 736 } 737 738 break; 739 case 16: 740 dev_dbg(component->dev, "16bit\n"); 741 switch (sta32x->format) { 742 case SND_SOC_DAIFMT_I2S: 743 confb |= 0x0; 744 break; 745 case SND_SOC_DAIFMT_LEFT_J: 746 confb |= 0xd; 747 break; 748 case SND_SOC_DAIFMT_RIGHT_J: 749 confb |= 0xe; 750 break; 751 } 752 753 break; 754 default: 755 return -EINVAL; 756 } 757 758 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA, 759 STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK, 760 confa); 761 if (ret < 0) 762 return ret; 763 764 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB, 765 STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB, 766 confb); 767 if (ret < 0) 768 return ret; 769 770 return 0; 771 } 772 773 static int sta32x_startup_sequence(struct sta32x_priv *sta32x) 774 { 775 if (sta32x->gpiod_nreset) { 776 gpiod_set_value(sta32x->gpiod_nreset, 0); 777 mdelay(1); 778 gpiod_set_value(sta32x->gpiod_nreset, 1); 779 mdelay(1); 780 } 781 782 return 0; 783 } 784 785 /** 786 * sta32x_set_bias_level - DAPM callback 787 * @component: the component device 788 * @level: DAPM power level 789 * 790 * This is called by ALSA to put the component into low power mode 791 * or to wake it up. If the component is powered off completely 792 * all registers must be restored after power on. 793 */ 794 static int sta32x_set_bias_level(struct snd_soc_component *component, 795 enum snd_soc_bias_level level) 796 { 797 int ret; 798 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 799 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 800 801 dev_dbg(component->dev, "level = %d\n", level); 802 switch (level) { 803 case SND_SOC_BIAS_ON: 804 break; 805 806 case SND_SOC_BIAS_PREPARE: 807 /* Full power on */ 808 regmap_update_bits(sta32x->regmap, STA32X_CONFF, 809 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 810 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); 811 break; 812 813 case SND_SOC_BIAS_STANDBY: 814 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 815 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), 816 sta32x->supplies); 817 if (ret != 0) { 818 dev_err(component->dev, 819 "Failed to enable supplies: %d\n", ret); 820 return ret; 821 } 822 823 sta32x_startup_sequence(sta32x); 824 sta32x_cache_sync(component); 825 sta32x_watchdog_start(sta32x); 826 } 827 828 /* Power down */ 829 regmap_update_bits(sta32x->regmap, STA32X_CONFF, 830 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 831 0); 832 833 break; 834 835 case SND_SOC_BIAS_OFF: 836 /* The chip runs through the power down sequence for us. */ 837 regmap_update_bits(sta32x->regmap, STA32X_CONFF, 838 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0); 839 msleep(300); 840 sta32x_watchdog_stop(sta32x); 841 842 gpiod_set_value(sta32x->gpiod_nreset, 0); 843 844 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), 845 sta32x->supplies); 846 break; 847 } 848 return 0; 849 } 850 851 static const struct snd_soc_dai_ops sta32x_dai_ops = { 852 .hw_params = sta32x_hw_params, 853 .set_sysclk = sta32x_set_dai_sysclk, 854 .set_fmt = sta32x_set_dai_fmt, 855 }; 856 857 static struct snd_soc_dai_driver sta32x_dai = { 858 .name = "sta32x-hifi", 859 .playback = { 860 .stream_name = "Playback", 861 .channels_min = 2, 862 .channels_max = 2, 863 .rates = STA32X_RATES, 864 .formats = STA32X_FORMATS, 865 }, 866 .ops = &sta32x_dai_ops, 867 }; 868 869 static int sta32x_probe(struct snd_soc_component *component) 870 { 871 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 872 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 873 struct sta32x_platform_data *pdata = sta32x->pdata; 874 int i, ret = 0, thermal = 0; 875 876 sta32x->component = component; 877 878 if (sta32x->xti_clk) { 879 ret = clk_prepare_enable(sta32x->xti_clk); 880 if (ret != 0) { 881 dev_err(component->dev, 882 "Failed to enable clock: %d\n", ret); 883 return ret; 884 } 885 } 886 887 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), 888 sta32x->supplies); 889 if (ret != 0) { 890 dev_err(component->dev, "Failed to enable supplies: %d\n", ret); 891 goto err_clk_disable_unprepare; 892 } 893 894 ret = sta32x_startup_sequence(sta32x); 895 if (ret < 0) { 896 dev_err(component->dev, "Failed to startup device\n"); 897 goto err_regulator_bulk_disable; 898 } 899 900 /* CONFA */ 901 if (!pdata->thermal_warning_recovery) 902 thermal |= STA32X_CONFA_TWAB; 903 if (!pdata->thermal_warning_adjustment) 904 thermal |= STA32X_CONFA_TWRB; 905 if (!pdata->fault_detect_recovery) 906 thermal |= STA32X_CONFA_FDRB; 907 regmap_update_bits(sta32x->regmap, STA32X_CONFA, 908 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB | 909 STA32X_CONFA_FDRB, 910 thermal); 911 912 /* CONFC */ 913 regmap_update_bits(sta32x->regmap, STA32X_CONFC, 914 STA32X_CONFC_CSZ_MASK, 915 pdata->drop_compensation_ns 916 << STA32X_CONFC_CSZ_SHIFT); 917 918 /* CONFE */ 919 regmap_update_bits(sta32x->regmap, STA32X_CONFE, 920 STA32X_CONFE_MPCV, 921 pdata->max_power_use_mpcc ? 922 STA32X_CONFE_MPCV : 0); 923 regmap_update_bits(sta32x->regmap, STA32X_CONFE, 924 STA32X_CONFE_MPC, 925 pdata->max_power_correction ? 926 STA32X_CONFE_MPC : 0); 927 regmap_update_bits(sta32x->regmap, STA32X_CONFE, 928 STA32X_CONFE_AME, 929 pdata->am_reduction_mode ? 930 STA32X_CONFE_AME : 0); 931 regmap_update_bits(sta32x->regmap, STA32X_CONFE, 932 STA32X_CONFE_PWMS, 933 pdata->odd_pwm_speed_mode ? 934 STA32X_CONFE_PWMS : 0); 935 936 /* CONFF */ 937 regmap_update_bits(sta32x->regmap, STA32X_CONFF, 938 STA32X_CONFF_IDE, 939 pdata->invalid_input_detect_mute ? 940 STA32X_CONFF_IDE : 0); 941 942 /* select output configuration */ 943 regmap_update_bits(sta32x->regmap, STA32X_CONFF, 944 STA32X_CONFF_OCFG_MASK, 945 pdata->output_conf 946 << STA32X_CONFF_OCFG_SHIFT); 947 948 /* channel to output mapping */ 949 regmap_update_bits(sta32x->regmap, STA32X_C1CFG, 950 STA32X_CxCFG_OM_MASK, 951 pdata->ch1_output_mapping 952 << STA32X_CxCFG_OM_SHIFT); 953 regmap_update_bits(sta32x->regmap, STA32X_C2CFG, 954 STA32X_CxCFG_OM_MASK, 955 pdata->ch2_output_mapping 956 << STA32X_CxCFG_OM_SHIFT); 957 regmap_update_bits(sta32x->regmap, STA32X_C3CFG, 958 STA32X_CxCFG_OM_MASK, 959 pdata->ch3_output_mapping 960 << STA32X_CxCFG_OM_SHIFT); 961 962 /* initialize coefficient shadow RAM with reset values */ 963 for (i = 4; i <= 49; i += 5) 964 sta32x->coef_shadow[i] = 0x400000; 965 for (i = 50; i <= 54; i++) 966 sta32x->coef_shadow[i] = 0x7fffff; 967 sta32x->coef_shadow[55] = 0x5a9df7; 968 sta32x->coef_shadow[56] = 0x7fffff; 969 sta32x->coef_shadow[59] = 0x7fffff; 970 sta32x->coef_shadow[60] = 0x400000; 971 sta32x->coef_shadow[61] = 0x400000; 972 973 if (sta32x->pdata->needs_esd_watchdog) 974 INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog); 975 976 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_STANDBY); 977 /* Bias level configuration will have done an extra enable */ 978 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); 979 980 return 0; 981 982 err_regulator_bulk_disable: 983 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); 984 err_clk_disable_unprepare: 985 clk_disable_unprepare(sta32x->xti_clk); 986 return ret; 987 } 988 989 static void sta32x_remove(struct snd_soc_component *component) 990 { 991 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component); 992 993 sta32x_watchdog_stop(sta32x); 994 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); 995 996 clk_disable_unprepare(sta32x->xti_clk); 997 } 998 999 static const struct snd_soc_component_driver sta32x_component = { 1000 .probe = sta32x_probe, 1001 .remove = sta32x_remove, 1002 .set_bias_level = sta32x_set_bias_level, 1003 .controls = sta32x_snd_controls, 1004 .num_controls = ARRAY_SIZE(sta32x_snd_controls), 1005 .dapm_widgets = sta32x_dapm_widgets, 1006 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets), 1007 .dapm_routes = sta32x_dapm_routes, 1008 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes), 1009 .suspend_bias_off = 1, 1010 .idle_bias_on = 1, 1011 .use_pmdown_time = 1, 1012 .endianness = 1, 1013 }; 1014 1015 static const struct regmap_config sta32x_regmap = { 1016 .reg_bits = 8, 1017 .val_bits = 8, 1018 .max_register = STA32X_FDRC2, 1019 .reg_defaults = sta32x_regs, 1020 .num_reg_defaults = ARRAY_SIZE(sta32x_regs), 1021 .cache_type = REGCACHE_MAPLE, 1022 .wr_table = &sta32x_write_regs, 1023 .rd_table = &sta32x_read_regs, 1024 .volatile_table = &sta32x_volatile_regs, 1025 }; 1026 1027 #ifdef CONFIG_OF 1028 static const struct of_device_id st32x_dt_ids[] = { 1029 { .compatible = "st,sta32x", }, 1030 { } 1031 }; 1032 MODULE_DEVICE_TABLE(of, st32x_dt_ids); 1033 1034 static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x) 1035 { 1036 struct device_node *np = dev->of_node; 1037 struct sta32x_platform_data *pdata; 1038 u16 tmp; 1039 1040 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1041 if (!pdata) 1042 return -ENOMEM; 1043 1044 of_property_read_u8(np, "st,output-conf", 1045 &pdata->output_conf); 1046 of_property_read_u8(np, "st,ch1-output-mapping", 1047 &pdata->ch1_output_mapping); 1048 of_property_read_u8(np, "st,ch2-output-mapping", 1049 &pdata->ch2_output_mapping); 1050 of_property_read_u8(np, "st,ch3-output-mapping", 1051 &pdata->ch3_output_mapping); 1052 1053 pdata->fault_detect_recovery = 1054 of_property_read_bool(np, "st,fault-detect-recovery"); 1055 pdata->thermal_warning_recovery = 1056 of_property_read_bool(np, "st,thermal-warning-recovery"); 1057 pdata->thermal_warning_adjustment = 1058 of_property_read_bool(np, "st,thermal-warning-adjustment"); 1059 pdata->needs_esd_watchdog = 1060 of_property_read_bool(np, "st,needs_esd_watchdog"); 1061 1062 tmp = 140; 1063 of_property_read_u16(np, "st,drop-compensation-ns", &tmp); 1064 pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20; 1065 1066 /* CONFE */ 1067 pdata->max_power_use_mpcc = 1068 of_property_read_bool(np, "st,max-power-use-mpcc"); 1069 pdata->max_power_correction = 1070 of_property_read_bool(np, "st,max-power-correction"); 1071 pdata->am_reduction_mode = 1072 of_property_read_bool(np, "st,am-reduction-mode"); 1073 pdata->odd_pwm_speed_mode = 1074 of_property_read_bool(np, "st,odd-pwm-speed-mode"); 1075 1076 /* CONFF */ 1077 pdata->invalid_input_detect_mute = 1078 of_property_read_bool(np, "st,invalid-input-detect-mute"); 1079 1080 sta32x->pdata = pdata; 1081 1082 return 0; 1083 } 1084 #endif 1085 1086 static int sta32x_i2c_probe(struct i2c_client *i2c) 1087 { 1088 struct device *dev = &i2c->dev; 1089 struct sta32x_priv *sta32x; 1090 int ret, i; 1091 1092 sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv), 1093 GFP_KERNEL); 1094 if (!sta32x) 1095 return -ENOMEM; 1096 1097 mutex_init(&sta32x->coeff_lock); 1098 sta32x->pdata = dev_get_platdata(dev); 1099 1100 #ifdef CONFIG_OF 1101 if (dev->of_node) { 1102 ret = sta32x_probe_dt(dev, sta32x); 1103 if (ret < 0) 1104 return ret; 1105 } 1106 #endif 1107 1108 /* Clock */ 1109 sta32x->xti_clk = devm_clk_get(dev, "xti"); 1110 if (IS_ERR(sta32x->xti_clk)) { 1111 ret = PTR_ERR(sta32x->xti_clk); 1112 1113 if (ret == -EPROBE_DEFER) 1114 return ret; 1115 1116 sta32x->xti_clk = NULL; 1117 } 1118 1119 /* GPIOs */ 1120 sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset", 1121 GPIOD_OUT_LOW); 1122 if (IS_ERR(sta32x->gpiod_nreset)) 1123 return PTR_ERR(sta32x->gpiod_nreset); 1124 1125 /* regulators */ 1126 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++) 1127 sta32x->supplies[i].supply = sta32x_supply_names[i]; 1128 1129 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies), 1130 sta32x->supplies); 1131 if (ret != 0) { 1132 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 1133 return ret; 1134 } 1135 1136 sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap); 1137 if (IS_ERR(sta32x->regmap)) { 1138 ret = PTR_ERR(sta32x->regmap); 1139 dev_err(dev, "Failed to init regmap: %d\n", ret); 1140 return ret; 1141 } 1142 1143 i2c_set_clientdata(i2c, sta32x); 1144 1145 ret = devm_snd_soc_register_component(dev, &sta32x_component, 1146 &sta32x_dai, 1); 1147 if (ret < 0) 1148 dev_err(dev, "Failed to register component (%d)\n", ret); 1149 1150 return ret; 1151 } 1152 1153 static const struct i2c_device_id sta32x_i2c_id[] = { 1154 { .name = "sta326" }, 1155 { .name = "sta328" }, 1156 { .name = "sta329" }, 1157 { } 1158 }; 1159 MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id); 1160 1161 static struct i2c_driver sta32x_i2c_driver = { 1162 .driver = { 1163 .name = "sta32x", 1164 .of_match_table = of_match_ptr(st32x_dt_ids), 1165 }, 1166 .probe = sta32x_i2c_probe, 1167 .id_table = sta32x_i2c_id, 1168 }; 1169 1170 module_i2c_driver(sta32x_i2c_driver); 1171 1172 MODULE_DESCRIPTION("ASoC STA32X driver"); 1173 MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>"); 1174 MODULE_LICENSE("GPL"); 1175