1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // sma1307.c -- sma1307 ALSA SoC Audio driver 3 // 4 // Copyright 2024 Iron Device Corporation 5 // 6 // Auther: Gyuhwa Park <gyuwha.park@irondevice.com> 7 // Auther: Kiseok Jo <kiseok.jo@irondevice.com> 8 9 #include <linux/firmware.h> 10 #include <linux/i2c.h> 11 #include <linux/of_gpio.h> 12 #include <linux/regmap.h> 13 #include <sound/pcm_params.h> 14 #include <sound/tlv.h> 15 #include "sma1307.h" 16 17 #define CHECK_PERIOD_TIME 1 /* sec per HZ */ 18 #define PLL_MATCH(_input_clk_name, _output_clk_name, _input_clk,\ 19 _post_n, _n, _vco, _p_cp)\ 20 {\ 21 .input_clk_name = _input_clk_name,\ 22 .output_clk_name = _output_clk_name,\ 23 .input_clk = _input_clk,\ 24 .post_n = _post_n,\ 25 .n = _n,\ 26 .vco = _vco,\ 27 .p_cp = _p_cp,\ 28 } 29 30 static const char *setting_file = "sma1307_setting.bin"; 31 #define SMA1307_SETTING_CHECKSUM 0x100000 32 33 /* PLL clock setting Table */ 34 struct sma1307_pll_match { 35 char *input_clk_name; 36 char *output_clk_name; 37 unsigned int input_clk; 38 unsigned int post_n; 39 unsigned int n; 40 unsigned int vco; 41 unsigned int p_cp; 42 }; 43 44 struct sma1307_data { 45 char *name; 46 void (*init)(struct regmap *regmap); 47 }; 48 49 struct sma1307_priv { 50 bool check_fault_status; 51 bool force_mute_status; 52 bool sw_ot1_prot; 53 char *name; 54 enum sma1307_mode amp_mode; 55 int binary_mode; 56 int dapm_aif_in; 57 int dapm_aif_out0; 58 int dapm_aif_out1; 59 int dapm_sdo_en; 60 int dapm_sdo_setting; 61 int num_of_pll_matches; 62 int check_fault_period; 63 struct delayed_work check_fault_work; 64 struct device *dev; 65 struct kobject *kobj; 66 struct mutex default_lock; 67 struct regmap *regmap; 68 struct sma1307_setting_file set; 69 const struct sma1307_pll_match *pll_matches; 70 const struct sma1307_data *data; 71 unsigned int cur_vol; 72 unsigned int format; 73 unsigned int frame_size; 74 unsigned int init_vol; 75 unsigned int last_bclk; 76 unsigned int otp_trm2; 77 unsigned int otp_trm3; 78 unsigned int rev_num; 79 unsigned int sys_clk_id; 80 unsigned int tdm_slot0_rx; 81 unsigned int tdm_slot1_rx; 82 unsigned int tdm_slot0_tx; 83 unsigned int tdm_slot1_tx; 84 unsigned int tsdw_cnt; 85 }; 86 87 static const struct sma1307_pll_match sma1307_pll_matches[] = { 88 /* in_clk_name, out_clk_name, input_clk post_n, n, vco, p_cp */ 89 PLL_MATCH("1.411MHz", "24.554MHz", 90 1411200, 0x06, 0xD1, 0x88, 0x00), 91 PLL_MATCH("1.536MHz", "24.576MHz", 92 1536000, 0x06, 0xC0, 0x88, 0x00), 93 PLL_MATCH("2.822MHz", "24.554MHz", 94 2822400, 0x06, 0xD1, 0x88, 0x04), 95 PLL_MATCH("3.072MHz", "24.576MHz", 96 3072000, 0x06, 0x60, 0x88, 0x00), 97 PLL_MATCH("6.144MHz", "24.576MHz", 98 6144000, 0x06, 0x60, 0x88, 0x04), 99 PLL_MATCH("12.288MHz", "24.576MHz", 100 12288000, 0x06, 0x60, 0x88, 0x08), 101 PLL_MATCH("19.2MHz", "24.48MHz", 102 19200000, 0x06, 0x7B, 0x88, 0x0C), 103 PLL_MATCH("24.576MHz", "24.576MHz", 104 24576000, 0x06, 0x60, 0x88, 0x0C), 105 }; 106 107 static struct snd_soc_component *sma1307_amp_component; 108 109 static void sma1307_startup(struct snd_soc_component *); 110 static void sma1307_shutdown(struct snd_soc_component *); 111 static void sma1307_reset(struct snd_soc_component *); 112 static void sma1307_set_binary(struct snd_soc_component *); 113 static void sma1307_set_default(struct snd_soc_component *); 114 115 /* Initial register value - 6.0W SPK (8ohm load) */ 116 static const struct reg_default sma1307_reg_def[] = { 117 { 0x00, 0x80 }, 118 { 0x01, 0x00 }, 119 { 0x02, 0x52 }, 120 { 0x03, 0x4C }, 121 { 0x04, 0x47 }, 122 { 0x05, 0x42 }, 123 { 0x06, 0x40 }, 124 { 0x07, 0x40 }, 125 { 0x08, 0x3C }, 126 { 0x09, 0x2F }, 127 { 0x0A, 0x32 }, 128 { 0x0B, 0x50 }, 129 { 0x0C, 0x8C }, 130 { 0x0D, 0x00 }, 131 { 0x0E, 0x3F }, 132 { 0x0F, 0x00 }, 133 { 0x10, 0x00 }, 134 { 0x11, 0x00 }, 135 { 0x12, 0x00 }, 136 { 0x13, 0x09 }, 137 { 0x14, 0x12 }, 138 { 0x1C, 0x00 }, 139 { 0x1D, 0x85 }, 140 { 0x1E, 0xA1 }, 141 { 0x1F, 0x67 }, 142 { 0x22, 0x00 }, 143 { 0x23, 0x1F }, 144 { 0x24, 0x7A }, 145 { 0x25, 0x00 }, 146 { 0x26, 0xFF }, 147 { 0x27, 0x39 }, 148 { 0x28, 0x54 }, 149 { 0x29, 0x92 }, 150 { 0x2A, 0xB0 }, 151 { 0x2B, 0xED }, 152 { 0x2C, 0xED }, 153 { 0x2D, 0xFF }, 154 { 0x2E, 0xFF }, 155 { 0x2F, 0xFF }, 156 { 0x30, 0xFF }, 157 { 0x31, 0xFF }, 158 { 0x32, 0xFF }, 159 { 0x34, 0x01 }, 160 { 0x35, 0x17 }, 161 { 0x36, 0x92 }, 162 { 0x37, 0x00 }, 163 { 0x38, 0x01 }, 164 { 0x39, 0x10 }, 165 { 0x3E, 0x01 }, 166 { 0x3F, 0x08 }, 167 { 0x8B, 0x05 }, 168 { 0x8C, 0x50 }, 169 { 0x8D, 0x80 }, 170 { 0x8E, 0x10 }, 171 { 0x8F, 0x02 }, 172 { 0x90, 0x02 }, 173 { 0x91, 0x83 }, 174 { 0x92, 0xC0 }, 175 { 0x93, 0x00 }, 176 { 0x94, 0xA4 }, 177 { 0x95, 0x74 }, 178 { 0x96, 0x57 }, 179 { 0xA2, 0xCC }, 180 { 0xA3, 0x28 }, 181 { 0xA4, 0x40 }, 182 { 0xA5, 0x01 }, 183 { 0xA6, 0x41 }, 184 { 0xA7, 0x08 }, 185 { 0xA8, 0x04 }, 186 { 0xA9, 0x27 }, 187 { 0xAA, 0x10 }, 188 { 0xAB, 0x10 }, 189 { 0xAC, 0x10 }, 190 { 0xAD, 0x0F }, 191 { 0xAE, 0xCD }, 192 { 0xAF, 0x70 }, 193 { 0xB0, 0x03 }, 194 { 0xB1, 0xEF }, 195 { 0xB2, 0x03 }, 196 { 0xB3, 0xEF }, 197 { 0xB4, 0xF3 }, 198 { 0xB5, 0x3D }, 199 }; 200 201 static bool sma1307_readable_register(struct device *dev, unsigned int reg) 202 { 203 if (reg > SMA1307_FF_DEVICE_INDEX) 204 return false; 205 206 switch (reg) { 207 case SMA1307_00_SYSTEM_CTRL ... SMA1307_1F_TONE_FINE_VOLUME: 208 case SMA1307_22_COMP_HYS_SEL ... SMA1307_32_BROWN_OUT_PROT19: 209 case SMA1307_34_OCP_SPK ... SMA1307_39_PMT_NZ_VAL: 210 case SMA1307_3B_TEST1 ... SMA1307_3F_ATEST2: 211 case SMA1307_8B_PLL_POST_N ... SMA1307_9A_OTP_TRM3: 212 case SMA1307_A0_PAD_CTRL0 ... SMA1307_BE_MCBS_CTRL2: 213 case SMA1307_F5_READY_FOR_V_SAR: 214 case SMA1307_F7_READY_FOR_T_SAR ... SMA1307_FF_DEVICE_INDEX: 215 break; 216 default: 217 return false; 218 } 219 return true; 220 } 221 222 static bool sma1307_writeable_register(struct device *dev, unsigned int reg) 223 { 224 if (reg > SMA1307_FF_DEVICE_INDEX) 225 return false; 226 227 switch (reg) { 228 case SMA1307_00_SYSTEM_CTRL ... SMA1307_1F_TONE_FINE_VOLUME: 229 case SMA1307_22_COMP_HYS_SEL ... SMA1307_32_BROWN_OUT_PROT19: 230 case SMA1307_34_OCP_SPK ... SMA1307_39_PMT_NZ_VAL: 231 case SMA1307_3B_TEST1 ... SMA1307_3F_ATEST2: 232 case SMA1307_8B_PLL_POST_N ... SMA1307_9A_OTP_TRM3: 233 case SMA1307_A0_PAD_CTRL0 ... SMA1307_BE_MCBS_CTRL2: 234 break; 235 default: 236 return false; 237 } 238 return true; 239 } 240 241 static bool sma1307_volatile_register(struct device *dev, unsigned int reg) 242 { 243 if (reg > SMA1307_FF_DEVICE_INDEX) 244 return false; 245 246 switch (reg) { 247 case SMA1307_F8_STATUS_T1 ... SMA1307_FF_DEVICE_INDEX: 248 break; 249 default: 250 return false; 251 } 252 return true; 253 } 254 255 /* DB scale conversion of speaker volume */ 256 static const DECLARE_TLV_DB_SCALE(sma1307_spk_tlv, -6000, 50, 0); 257 258 static const char *const sma1307_aif_in_source_text[] = { 259 "Mono", "Left", "Right" 260 }; 261 262 static const char *const sma1307_sdo_setting_text[] = { 263 "Data_One_48k", "Data_Two_48k", "Data_Two_24k", 264 "Clk_PLL", "Clk_OSC" 265 }; 266 267 static const char *const sma1307_aif_out_source_text[] = { 268 "Disable", "After_FmtC", "After_Mixer", "After_DSP", 269 "Vrms2_Avg", "Battery", "Temperature", "After_Delay" 270 }; 271 272 static const char *const sma1307_tdm_slot_text[] = { 273 "Slot0", "Slot1", "Slot2", "Slot3", 274 "Slot4", "Slot5", "Slot6", "Slot7" 275 }; 276 277 static const char *const sma1307_binary_mode_text[] = { 278 "Mode0", "Mode1", "Mode2", "Mode3", "Mode4" 279 }; 280 281 static const char *const sma1307_reset_text[] = { 282 "Reset" 283 }; 284 285 static const struct soc_enum sma1307_aif_in_source_enum = 286 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_aif_in_source_text), 287 sma1307_aif_in_source_text); 288 static const struct soc_enum sma1307_sdo_setting_enum = 289 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_sdo_setting_text), 290 sma1307_sdo_setting_text); 291 static const struct soc_enum sma1307_aif_out_source_enum = 292 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_aif_out_source_text), 293 sma1307_aif_out_source_text); 294 static const struct soc_enum sma1307_tdm_slot_enum = 295 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_tdm_slot_text), 296 sma1307_tdm_slot_text); 297 static const struct soc_enum sma1307_binary_mode_enum = 298 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_binary_mode_text), 299 sma1307_binary_mode_text); 300 static const struct soc_enum sma1307_reset_enum = 301 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1307_reset_text), 302 sma1307_reset_text); 303 304 static int sma1307_force_mute_get(struct snd_kcontrol *kcontrol, 305 struct snd_ctl_elem_value *ucontrol) 306 { 307 struct snd_soc_component *component = 308 snd_soc_kcontrol_component(kcontrol); 309 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 310 311 ucontrol->value.integer.value[0] = (int)sma1307->force_mute_status; 312 313 return 0; 314 } 315 316 static int sma1307_force_mute_put(struct snd_kcontrol *kcontrol, 317 struct snd_ctl_elem_value *ucontrol) 318 { 319 struct snd_soc_component *component = 320 snd_soc_kcontrol_component(kcontrol); 321 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 322 bool change = false, val = (bool)ucontrol->value.integer.value[0]; 323 324 if (sma1307->force_mute_status == val) { 325 change = false; 326 } else { 327 change = true; 328 sma1307->force_mute_status = val; 329 } 330 331 return change; 332 } 333 334 static int sma1307_tdm_slot_get(struct snd_kcontrol *kcontrol, 335 struct snd_ctl_elem_value *ucontrol) 336 { 337 struct snd_soc_component *component = 338 snd_soc_kcontrol_component(kcontrol); 339 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 340 int val1, val2; 341 342 regmap_read(sma1307->regmap, SMA1307_A5_TDM1, &val1); 343 regmap_read(sma1307->regmap, SMA1307_A6_TDM2, &val2); 344 345 if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX0_POS_NAME)) { 346 ucontrol->value.integer.value[0] 347 = (val1 & SMA1307_TDM_SLOT0_RX_POS_MASK) >> 3; 348 sma1307->tdm_slot0_rx = ucontrol->value.integer.value[0]; 349 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX1_POS_NAME)) { 350 ucontrol->value.integer.value[0] 351 = val1 & SMA1307_TDM_SLOT1_RX_POS_MASK; 352 sma1307->tdm_slot1_rx = ucontrol->value.integer.value[0]; 353 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX0_POS_NAME)) { 354 ucontrol->value.integer.value[0] 355 = (val2 & SMA1307_TDM_SLOT0_TX_POS_MASK) >> 3; 356 sma1307->tdm_slot0_tx = ucontrol->value.integer.value[0]; 357 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX1_POS_NAME)) { 358 ucontrol->value.integer.value[0] 359 = val2 & SMA1307_TDM_SLOT1_TX_POS_MASK; 360 sma1307->tdm_slot1_tx = ucontrol->value.integer.value[0]; 361 } else { 362 return -EINVAL; 363 } 364 365 return 0; 366 } 367 368 static int sma1307_tdm_slot_put(struct snd_kcontrol *kcontrol, 369 struct snd_ctl_elem_value *ucontrol) 370 { 371 struct snd_soc_component *component = 372 snd_soc_kcontrol_component(kcontrol); 373 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 374 int val = (int)ucontrol->value.integer.value[0]; 375 bool change; 376 377 if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX0_POS_NAME)) { 378 if (sma1307->tdm_slot0_rx == val) 379 change = false; 380 else { 381 change = true; 382 sma1307->tdm_slot0_rx = val; 383 regmap_update_bits(sma1307->regmap, SMA1307_A5_TDM1, 384 SMA1307_TDM_SLOT0_RX_POS_MASK, val << 3); 385 } 386 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_RX1_POS_NAME)) { 387 if (sma1307->tdm_slot1_rx == val) 388 change = false; 389 else { 390 change = true; 391 sma1307->tdm_slot1_rx = val; 392 regmap_update_bits(sma1307->regmap, SMA1307_A5_TDM1, 393 SMA1307_TDM_SLOT1_RX_POS_MASK, val); 394 } 395 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX0_POS_NAME)) { 396 if (sma1307->tdm_slot0_tx == val) 397 change = false; 398 else { 399 change = true; 400 sma1307->tdm_slot0_tx = val; 401 regmap_update_bits(sma1307->regmap, SMA1307_A6_TDM2, 402 SMA1307_TDM_SLOT0_TX_POS_MASK, val << 3); 403 } 404 } else if (!strcmp(kcontrol->id.name, SMA1307_TDM_TX1_POS_NAME)) { 405 if (sma1307->tdm_slot1_tx == val) 406 change = false; 407 else { 408 change = true; 409 sma1307->tdm_slot1_tx = val; 410 regmap_update_bits(sma1307->regmap, SMA1307_A6_TDM2, 411 SMA1307_TDM_SLOT1_TX_POS_MASK, val); 412 } 413 } else { 414 dev_err(sma1307->dev, "%s: Invalid Control ID - %s\n", 415 __func__, kcontrol->id.name); 416 return -EINVAL; 417 } 418 419 return change; 420 } 421 422 static int sma1307_sw_ot1_prot_get(struct snd_kcontrol *kcontrol, 423 struct snd_ctl_elem_value *ucontrol) 424 { 425 struct snd_soc_component *component = 426 snd_soc_kcontrol_component(kcontrol); 427 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 428 429 ucontrol->value.integer.value[0] = (int)sma1307->sw_ot1_prot; 430 431 return 0; 432 } 433 434 static int sma1307_sw_ot1_prot_put(struct snd_kcontrol *kcontrol, 435 struct snd_ctl_elem_value *ucontrol) 436 { 437 struct snd_soc_component *component = 438 snd_soc_kcontrol_component(kcontrol); 439 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 440 bool change = false, val = (bool)ucontrol->value.integer.value[0]; 441 442 if (sma1307->sw_ot1_prot == val) 443 change = false; 444 else { 445 change = true; 446 sma1307->sw_ot1_prot = val; 447 } 448 449 return change; 450 } 451 452 static int sma1307_check_fault_status_get(struct snd_kcontrol *kcontrol, 453 struct snd_ctl_elem_value *ucontrol) 454 { 455 struct snd_soc_component *component = 456 snd_soc_kcontrol_component(kcontrol); 457 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 458 459 ucontrol->value.integer.value[0] = (int)sma1307->check_fault_status; 460 461 return 0; 462 } 463 464 static int sma1307_check_fault_status_put(struct snd_kcontrol *kcontrol, 465 struct snd_ctl_elem_value *ucontrol) 466 { 467 struct snd_soc_component *component = 468 snd_soc_kcontrol_component(kcontrol); 469 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 470 bool change = false, val = (bool)ucontrol->value.integer.value[0]; 471 472 if (sma1307->check_fault_status == val) { 473 change = false; 474 } else { 475 change = true; 476 sma1307->check_fault_status = val; 477 } 478 479 return change; 480 } 481 482 static int sma1307_check_fault_period_get(struct snd_kcontrol *kcontrol, 483 struct snd_ctl_elem_value *ucontrol) 484 { 485 struct snd_soc_component *component = 486 snd_soc_kcontrol_component(kcontrol); 487 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 488 489 ucontrol->value.integer.value[0] = sma1307->check_fault_period; 490 491 return 0; 492 } 493 494 static int sma1307_check_fault_period_put(struct snd_kcontrol *kcontrol, 495 struct snd_ctl_elem_value *ucontrol) 496 { 497 struct snd_soc_component *component = 498 snd_soc_kcontrol_component(kcontrol); 499 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 500 struct soc_mixer_control *mc = 501 (struct soc_mixer_control *)kcontrol->private_value; 502 bool change = false; 503 int val = ucontrol->value.integer.value[0]; 504 505 if (val < mc->min || val > mc->max) 506 return -EINVAL; 507 if (sma1307->check_fault_period == val) { 508 change = false; 509 } else { 510 change = true; 511 sma1307->check_fault_period = val; 512 } 513 514 return change; 515 } 516 517 static int sma1307_reset_put(struct snd_kcontrol *kcontrol, 518 struct snd_ctl_elem_value *ucontrol) 519 { 520 struct snd_soc_component *component = 521 snd_soc_kcontrol_component(kcontrol); 522 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 523 524 regmap_update_bits(sma1307->regmap, SMA1307_00_SYSTEM_CTRL, 525 SMA1307_RESET_MASK, SMA1307_RESET_ON); 526 sma1307_reset(component); 527 528 snd_ctl_notify(component->card->snd_card, SNDRV_CTL_EVENT_MASK_VALUE, 529 &kcontrol->id); 530 531 return true; 532 } 533 534 static int sma1307_binary_mode_put(struct snd_kcontrol *kcontrol, 535 struct snd_ctl_elem_value *ucontrol) 536 { 537 struct snd_soc_component *component = 538 snd_soc_kcontrol_component(kcontrol); 539 struct sma1307_priv *sma1307 = snd_kcontrol_chip(kcontrol); 540 541 sma1307->binary_mode = (int)ucontrol->value.enumerated.item[0]; 542 if (sma1307->set.status) 543 sma1307_set_binary(component); 544 545 return snd_soc_put_enum_double(kcontrol, ucontrol); 546 } 547 548 static void sma1307_startup(struct snd_soc_component *component) 549 { 550 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 551 552 regmap_update_bits(sma1307->regmap, SMA1307_A2_TOP_MAN1, 553 SMA1307_PLL_MASK, SMA1307_PLL_ON); 554 regmap_update_bits(sma1307->regmap, SMA1307_00_SYSTEM_CTRL, 555 SMA1307_POWER_MASK, SMA1307_POWER_ON); 556 557 if (sma1307->amp_mode == SMA1307_MONO_MODE) { 558 regmap_update_bits(sma1307->regmap, 559 SMA1307_10_SYSTEM_CTRL1, 560 SMA1307_SPK_MODE_MASK, 561 SMA1307_SPK_MONO); 562 } else { 563 regmap_update_bits(sma1307->regmap, 564 SMA1307_10_SYSTEM_CTRL1, 565 SMA1307_SPK_MODE_MASK, 566 SMA1307_SPK_STEREO); 567 } 568 569 if (sma1307->check_fault_status) { 570 if (sma1307->check_fault_period > 0) 571 queue_delayed_work(system_freezable_wq, 572 &sma1307->check_fault_work, 573 sma1307->check_fault_period * HZ); 574 else 575 queue_delayed_work(system_freezable_wq, 576 &sma1307->check_fault_work, 577 CHECK_PERIOD_TIME * HZ); 578 } 579 } 580 581 static void sma1307_shutdown(struct snd_soc_component *component) 582 { 583 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 584 585 /* for SMA1307A */ 586 cancel_delayed_work_sync(&sma1307->check_fault_work); 587 588 regmap_update_bits(sma1307->regmap, SMA1307_0E_MUTE_VOL_CTRL, 589 SMA1307_SPK_MUTE_MASK, SMA1307_SPK_MUTE); 590 /* Need to wait time for mute slope */ 591 msleep(55); 592 593 regmap_update_bits(sma1307->regmap, SMA1307_10_SYSTEM_CTRL1, 594 SMA1307_SPK_MODE_MASK, SMA1307_SPK_OFF); 595 regmap_update_bits(sma1307->regmap, SMA1307_A2_TOP_MAN1, 596 SMA1307_PLL_MASK, SMA1307_PLL_OFF); 597 regmap_update_bits(sma1307->regmap, SMA1307_00_SYSTEM_CTRL, 598 SMA1307_POWER_MASK, SMA1307_POWER_OFF); 599 } 600 601 static int sma1307_aif_in_event(struct snd_soc_dapm_widget *w, 602 struct snd_kcontrol *kcontrol, int event) 603 { 604 struct snd_soc_component *component = 605 snd_soc_dapm_to_component(w->dapm); 606 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 607 unsigned int mux = sma1307->dapm_aif_in; 608 609 switch (event) { 610 case SND_SOC_DAPM_PRE_PMU: 611 switch (mux) { 612 case SMA1307_MONO_MODE: 613 regmap_update_bits(sma1307->regmap, 614 SMA1307_11_SYSTEM_CTRL2, 615 SMA1307_MONOMIX_MASK, 616 SMA1307_MONOMIX_ON); 617 break; 618 case SMA1307_LEFT_MODE: 619 regmap_update_bits(sma1307->regmap, 620 SMA1307_11_SYSTEM_CTRL2, 621 SMA1307_MONOMIX_MASK, 622 SMA1307_MONOMIX_OFF); 623 regmap_update_bits(sma1307->regmap, 624 SMA1307_11_SYSTEM_CTRL2, 625 SMA1307_LR_DATA_SW_MASK, 626 SMA1307_LR_DATA_SW_NORMAL); 627 break; 628 case SMA1307_RIGHT_MODE: 629 regmap_update_bits(sma1307->regmap, 630 SMA1307_11_SYSTEM_CTRL2, 631 SMA1307_MONOMIX_MASK, 632 SMA1307_MONOMIX_OFF); 633 regmap_update_bits(sma1307->regmap, 634 SMA1307_11_SYSTEM_CTRL2, 635 SMA1307_LR_DATA_SW_MASK, 636 SMA1307_LR_DATA_SW_SWAP); 637 break; 638 default: 639 640 dev_err(sma1307->dev, "%s: Invalid value (%d)\n", 641 __func__, mux); 642 return -EINVAL; 643 } 644 sma1307->amp_mode = mux; 645 break; 646 } 647 return 0; 648 } 649 650 static int sma1307_sdo_setting_event(struct snd_soc_dapm_widget *w, 651 struct snd_kcontrol *kcontrol, int event) 652 { 653 struct snd_soc_component *component = 654 snd_soc_dapm_to_component(w->dapm); 655 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 656 unsigned int mux = sma1307->dapm_sdo_setting; 657 658 switch (event) { 659 case SND_SOC_DAPM_PRE_PMU: 660 switch (mux) { 661 case SMA1307_OUT_DATA_ONE_48K: 662 regmap_update_bits(sma1307->regmap, 663 SMA1307_A2_TOP_MAN1, 664 SMA1307_SDO_OUTPUT2_MASK, 665 SMA1307_ONE_SDO_PER_CH); 666 regmap_update_bits(sma1307->regmap, 667 SMA1307_A3_TOP_MAN2, 668 SMA1307_SDO_OUTPUT3_MASK 669 | 670 SMA1307_DATA_CLK_SEL_MASK, 671 SMA1307_SDO_OUTPUT3_DIS 672 | SMA1307_SDO_DATA); 673 break; 674 case SMA1307_OUT_DATA_TWO_48K: 675 regmap_update_bits(sma1307->regmap, 676 SMA1307_A2_TOP_MAN1, 677 SMA1307_SDO_OUTPUT2_MASK, 678 SMA1307_TWO_SDO_PER_CH); 679 regmap_update_bits(sma1307->regmap, 680 SMA1307_A3_TOP_MAN2, 681 SMA1307_SDO_OUTPUT3_MASK 682 | 683 SMA1307_DATA_CLK_SEL_MASK, 684 SMA1307_SDO_OUTPUT3_DIS 685 | SMA1307_SDO_DATA); 686 break; 687 case SMA1307_OUT_DATA_TWO_24K: 688 regmap_update_bits(sma1307->regmap, 689 SMA1307_A2_TOP_MAN1, 690 SMA1307_SDO_OUTPUT2_MASK, 691 SMA1307_TWO_SDO_PER_CH); 692 regmap_update_bits(sma1307->regmap, 693 SMA1307_A3_TOP_MAN2, 694 SMA1307_SDO_OUTPUT3_MASK 695 | 696 SMA1307_DATA_CLK_SEL_MASK, 697 SMA1307_TWO_SDO_PER_CH_24K 698 | SMA1307_SDO_DATA); 699 break; 700 case SMA1307_OUT_CLK_PLL: 701 regmap_update_bits(sma1307->regmap, 702 SMA1307_A3_TOP_MAN2, 703 SMA1307_DATA_CLK_SEL_MASK, 704 SMA1307_SDO_CLK_PLL); 705 706 break; 707 case SMA1307_OUT_CLK_OSC: 708 regmap_update_bits(sma1307->regmap, 709 SMA1307_A3_TOP_MAN2, 710 SMA1307_DATA_CLK_SEL_MASK, 711 SMA1307_SDO_CLK_OSC); 712 713 break; 714 default: 715 dev_err(sma1307->dev, "%s: Invalid value (%d)\n", 716 __func__, mux); 717 return -EINVAL; 718 } 719 break; 720 } 721 return 0; 722 } 723 724 static int sma1307_aif_out_event(struct snd_soc_dapm_widget *w, 725 struct snd_kcontrol *kcontrol, int event) 726 { 727 struct snd_soc_component *component = 728 snd_soc_dapm_to_component(w->dapm); 729 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 730 unsigned int mux = 0, val = 0, mask = 0; 731 732 if (!strcmp(w->name, SMA1307_AIF_OUT0_NAME)) { 733 mux = sma1307->dapm_aif_out0; 734 val = mux; 735 mask = SMA1307_SDO_OUT0_SEL_MASK; 736 } else if (!strcmp(w->name, SMA1307_AIF_OUT1_NAME)) { 737 mux = sma1307->dapm_aif_out1; 738 val = mux << 3; 739 mask = SMA1307_SDO_OUT1_SEL_MASK; 740 } else { 741 dev_err(sma1307->dev, "%s: Invalid widget - %s\n", 742 __func__, w->name); 743 return -EINVAL; 744 } 745 switch (event) { 746 case SND_SOC_DAPM_PRE_PMU: 747 regmap_update_bits(sma1307->regmap, SMA1307_09_OUTPUT_CTRL, 748 mask, val); 749 break; 750 } 751 return 0; 752 } 753 754 static int sma1307_sdo_event(struct snd_soc_dapm_widget *w, 755 struct snd_kcontrol *kcontrol, int event) 756 { 757 struct snd_soc_component *component = 758 snd_soc_dapm_to_component(w->dapm); 759 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 760 761 switch (event) { 762 case SND_SOC_DAPM_PRE_PMU: 763 regmap_update_bits(sma1307->regmap, 764 SMA1307_09_OUTPUT_CTRL, 765 SMA1307_PORT_CONFIG_MASK, 766 SMA1307_OUTPUT_PORT_ENABLE); 767 regmap_update_bits(sma1307->regmap, 768 SMA1307_A3_TOP_MAN2, 769 SMA1307_SDO_OUTPUT_MASK, 770 SMA1307_LOGIC_OUTPUT); 771 break; 772 case SND_SOC_DAPM_POST_PMD: 773 regmap_update_bits(sma1307->regmap, 774 SMA1307_09_OUTPUT_CTRL, 775 SMA1307_PORT_CONFIG_MASK, 776 SMA1307_INPUT_PORT_ONLY); 777 regmap_update_bits(sma1307->regmap, 778 SMA1307_A3_TOP_MAN2, 779 SMA1307_SDO_OUTPUT_MASK, 780 SMA1307_HIGH_Z_OUTPUT); 781 break; 782 } 783 return 0; 784 } 785 786 static int sma1307_power_event(struct snd_soc_dapm_widget *w, 787 struct snd_kcontrol *kcontrol, int event) 788 { 789 struct snd_soc_component *component = 790 snd_soc_dapm_to_component(w->dapm); 791 792 switch (event) { 793 case SND_SOC_DAPM_POST_PMU: 794 sma1307_startup(component); 795 break; 796 case SND_SOC_DAPM_PRE_PMD: 797 sma1307_shutdown(component); 798 break; 799 } 800 return 0; 801 } 802 803 static int sma1307_dapm_aif_in_get(struct snd_kcontrol *kcontrol, 804 struct snd_ctl_elem_value *ucontrol) 805 { 806 struct snd_soc_dapm_context *dapm = 807 snd_soc_dapm_kcontrol_dapm(kcontrol); 808 struct sma1307_priv *sma1307 = 809 snd_soc_component_get_drvdata(dapm->component); 810 811 ucontrol->value.enumerated.item[0] = (unsigned int)sma1307->dapm_aif_in; 812 snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 813 814 return 0; 815 } 816 817 static int sma1307_dapm_aif_in_put(struct snd_kcontrol *kcontrol, 818 struct snd_ctl_elem_value *ucontrol) 819 { 820 struct snd_soc_dapm_context *dapm = 821 snd_soc_dapm_kcontrol_dapm(kcontrol); 822 struct sma1307_priv *sma1307 = 823 snd_soc_component_get_drvdata(dapm->component); 824 int val = (int)ucontrol->value.enumerated.item[0]; 825 bool change; 826 827 if ((val < 0) || (val >= ARRAY_SIZE(sma1307_aif_in_source_text))) { 828 dev_err(sma1307->dev, "%s: Out of range\n", __func__); 829 return -EINVAL; 830 } 831 832 if (sma1307->dapm_aif_in != val) { 833 change = true; 834 sma1307->dapm_aif_in = val; 835 } else 836 change = false; 837 838 snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 839 840 return change; 841 } 842 843 static int sma1307_dapm_sdo_setting_get(struct snd_kcontrol *kcontrol, 844 struct snd_ctl_elem_value *ucontrol) 845 { 846 struct snd_soc_dapm_context *dapm = 847 snd_soc_dapm_kcontrol_dapm(kcontrol); 848 struct sma1307_priv *sma1307 = 849 snd_soc_component_get_drvdata(dapm->component); 850 851 ucontrol->value.enumerated.item[0] = 852 (unsigned int)sma1307->dapm_sdo_setting; 853 snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 854 855 return 0; 856 } 857 858 static int sma1307_dapm_sdo_setting_put(struct snd_kcontrol *kcontrol, 859 struct snd_ctl_elem_value *ucontrol) 860 { 861 struct snd_soc_dapm_context *dapm = 862 snd_soc_dapm_kcontrol_dapm(kcontrol); 863 struct sma1307_priv *sma1307 = 864 snd_soc_component_get_drvdata(dapm->component); 865 int val = (int)ucontrol->value.enumerated.item[0]; 866 bool change; 867 868 if ((val < 0) || (val >= ARRAY_SIZE(sma1307_sdo_setting_text))) { 869 dev_err(sma1307->dev, "%s: Out of range\n", __func__); 870 return -EINVAL; 871 } 872 873 if (sma1307->dapm_sdo_setting != val) { 874 change = true; 875 sma1307->dapm_sdo_setting = val; 876 } else 877 change = false; 878 879 snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 880 881 return change; 882 } 883 884 static int sma1307_dapm_aif_out_get(struct snd_kcontrol *kcontrol, 885 struct snd_ctl_elem_value *ucontrol) 886 { 887 struct snd_soc_dapm_context *dapm = 888 snd_soc_dapm_kcontrol_dapm(kcontrol); 889 struct sma1307_priv *sma1307 = 890 snd_soc_component_get_drvdata(dapm->component); 891 unsigned int val = 0; 892 893 if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT0_NAME)) { 894 val = (unsigned int)sma1307->dapm_aif_out0; 895 } else if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT1_NAME)) { 896 val = (unsigned int)sma1307->dapm_aif_out1; 897 } else { 898 dev_err(sma1307->dev, "%s: Invalid Control ID - %s\n", 899 __func__, kcontrol->id.name); 900 return -EINVAL; 901 } 902 ucontrol->value.enumerated.item[0] = val; 903 snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 904 905 return 0; 906 } 907 908 static int sma1307_dapm_aif_out_put(struct snd_kcontrol *kcontrol, 909 struct snd_ctl_elem_value *ucontrol) 910 { 911 struct snd_soc_dapm_context *dapm = 912 snd_soc_dapm_kcontrol_dapm(kcontrol); 913 struct sma1307_priv *sma1307 = 914 snd_soc_component_get_drvdata(dapm->component); 915 int val = (int)ucontrol->value.enumerated.item[0]; 916 bool change; 917 918 if ((val < 0) || (val >= ARRAY_SIZE(sma1307_aif_out_source_text))) { 919 dev_err(sma1307->dev, "%s: Out of range\n", __func__); 920 return -EINVAL; 921 } 922 923 if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT0_NAME)) { 924 if (sma1307->dapm_aif_out0 != val) { 925 change = true; 926 sma1307->dapm_aif_out0 = val; 927 } else 928 change = false; 929 } else if (!strcmp(kcontrol->id.name, SMA1307_AIF_OUT1_NAME)) { 930 if (sma1307->dapm_aif_out1 != val) { 931 change = true; 932 sma1307->dapm_aif_out1 = val; 933 } else 934 change = false; 935 } else { 936 dev_err(sma1307->dev, "%s: Invalid Control ID - %s\n", 937 __func__, kcontrol->id.name); 938 return -EINVAL; 939 } 940 941 snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 942 943 return change; 944 } 945 946 static int sma1307_dapm_sdo_enable_get(struct snd_kcontrol *kcontrol, 947 struct snd_ctl_elem_value *ucontrol) 948 { 949 struct snd_soc_dapm_context *dapm = 950 snd_soc_dapm_kcontrol_dapm(kcontrol); 951 struct sma1307_priv *sma1307 = 952 snd_soc_component_get_drvdata(dapm->component); 953 954 ucontrol->value.integer.value[0] = (long)sma1307->dapm_sdo_en; 955 snd_soc_dapm_put_volsw(kcontrol, ucontrol); 956 957 return 0; 958 } 959 960 static int sma1307_dapm_sdo_enable_put(struct snd_kcontrol *kcontrol, 961 struct snd_ctl_elem_value *ucontrol) 962 { 963 struct snd_soc_dapm_context *dapm = 964 snd_soc_dapm_kcontrol_dapm(kcontrol); 965 struct sma1307_priv *sma1307 = 966 snd_soc_component_get_drvdata(dapm->component); 967 int val = (int)ucontrol->value.integer.value[0]; 968 bool change; 969 970 if ((val < 0) || (val > 1)) { 971 dev_err(sma1307->dev, "%s: Out of range\n", __func__); 972 return -EINVAL; 973 } 974 975 if (sma1307->dapm_sdo_en != val) { 976 change = true; 977 sma1307->dapm_sdo_en = val; 978 } else 979 change = false; 980 981 snd_soc_dapm_put_volsw(kcontrol, ucontrol); 982 983 return change; 984 } 985 986 static const struct snd_kcontrol_new sma1307_aif_in_source_control = { 987 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 988 .name = SMA1307_AIF_IN_NAME, 989 .info = snd_soc_info_enum_double, 990 .get = sma1307_dapm_aif_in_get, 991 .put = sma1307_dapm_aif_in_put, 992 .private_value = (unsigned long)&sma1307_aif_in_source_enum 993 }; 994 995 static const struct snd_kcontrol_new sma1307_sdo_setting_control = { 996 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 997 .name = "SDO Setting", 998 .info = snd_soc_info_enum_double, 999 .get = sma1307_dapm_sdo_setting_get, 1000 .put = sma1307_dapm_sdo_setting_put, 1001 .private_value = (unsigned long)&sma1307_sdo_setting_enum 1002 }; 1003 1004 static const struct snd_kcontrol_new sma1307_aif_out0_source_control = { 1005 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1006 .name = SMA1307_AIF_OUT0_NAME, 1007 .info = snd_soc_info_enum_double, 1008 .get = sma1307_dapm_aif_out_get, 1009 .put = sma1307_dapm_aif_out_put, 1010 .private_value = (unsigned long)&sma1307_aif_out_source_enum 1011 }; 1012 1013 static const struct snd_kcontrol_new sma1307_aif_out1_source_control = { 1014 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1015 .name = SMA1307_AIF_OUT1_NAME, 1016 .info = snd_soc_info_enum_double, 1017 .get = sma1307_dapm_aif_out_get, 1018 .put = sma1307_dapm_aif_out_put, 1019 .private_value = (unsigned long)&sma1307_aif_out_source_enum 1020 }; 1021 1022 static const struct snd_kcontrol_new sma1307_sdo_control = 1023 SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, 0, 1, 0, 1024 sma1307_dapm_sdo_enable_get, sma1307_dapm_sdo_enable_put); 1025 1026 static const struct snd_kcontrol_new sma1307_enable_control = 1027 SOC_DAPM_SINGLE("Switch", SMA1307_00_SYSTEM_CTRL, 0, 1, 0); 1028 1029 static const struct snd_kcontrol_new sma1307_binary_mode_control[] = { 1030 SOC_ENUM_EXT("Binary Mode", sma1307_binary_mode_enum, 1031 snd_soc_get_enum_double, sma1307_binary_mode_put), 1032 }; 1033 1034 static const struct snd_kcontrol_new sma1307_snd_controls[] = { 1035 SOC_SINGLE_TLV(SMA1307_VOL_CTRL_NAME, SMA1307_0A_SPK_VOL, 1036 0, 167, 1, sma1307_spk_tlv), 1037 SOC_ENUM_EXT(SMA1307_TDM_RX0_POS_NAME, sma1307_tdm_slot_enum, 1038 sma1307_tdm_slot_get, sma1307_tdm_slot_put), 1039 SOC_ENUM_EXT(SMA1307_TDM_RX1_POS_NAME, sma1307_tdm_slot_enum, 1040 sma1307_tdm_slot_get, sma1307_tdm_slot_put), 1041 SOC_ENUM_EXT(SMA1307_TDM_TX0_POS_NAME, sma1307_tdm_slot_enum, 1042 sma1307_tdm_slot_get, sma1307_tdm_slot_put), 1043 SOC_ENUM_EXT(SMA1307_TDM_TX1_POS_NAME, sma1307_tdm_slot_enum, 1044 sma1307_tdm_slot_get, sma1307_tdm_slot_put), 1045 SOC_ENUM_EXT(SMA1307_RESET_CTRL_NAME, sma1307_reset_enum, 1046 snd_soc_get_enum_double, sma1307_reset_put), 1047 SOC_SINGLE_BOOL_EXT(SMA1307_FORCE_MUTE_CTRL_NAME, 0, 1048 sma1307_force_mute_get, sma1307_force_mute_put), 1049 SOC_SINGLE_BOOL_EXT(SMA1307_OT1_SW_PROT_CTRL_NAME, 0, 1050 sma1307_sw_ot1_prot_get, sma1307_sw_ot1_prot_put), 1051 SOC_SINGLE_BOOL_EXT(SMA1307_CHECK_FAULT_STATUS_NAME, 0, 1052 sma1307_check_fault_status_get, 1053 sma1307_check_fault_status_put), 1054 SOC_SINGLE_EXT(SMA1307_CHECK_FAULT_PERIOD_NAME, SND_SOC_NOPM, 0, 600, 0, 1055 sma1307_check_fault_period_get, 1056 sma1307_check_fault_period_put), 1057 }; 1058 1059 static const struct snd_soc_dapm_widget sma1307_dapm_widgets[] = { 1060 /* platform domain */ 1061 SND_SOC_DAPM_OUTPUT("SPK"), 1062 SND_SOC_DAPM_INPUT("SDO"), 1063 1064 /* path domain */ 1065 SND_SOC_DAPM_MUX_E(SMA1307_AIF_IN_NAME, SND_SOC_NOPM, 0, 0, 1066 &sma1307_aif_in_source_control, 1067 sma1307_aif_in_event, 1068 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1069 SND_SOC_DAPM_MUX_E("SDO Setting", SND_SOC_NOPM, 0, 0, 1070 &sma1307_sdo_setting_control, 1071 sma1307_sdo_setting_event, 1072 SND_SOC_DAPM_PRE_PMU), 1073 SND_SOC_DAPM_MUX_E(SMA1307_AIF_OUT0_NAME, SND_SOC_NOPM, 0, 0, 1074 &sma1307_aif_out0_source_control, 1075 sma1307_aif_out_event, 1076 SND_SOC_DAPM_PRE_PMU), 1077 SND_SOC_DAPM_MUX_E(SMA1307_AIF_OUT1_NAME, SND_SOC_NOPM, 0, 0, 1078 &sma1307_aif_out1_source_control, 1079 sma1307_aif_out_event, 1080 SND_SOC_DAPM_PRE_PMU), 1081 SND_SOC_DAPM_SWITCH_E("SDO Enable", SND_SOC_NOPM, 0, 0, 1082 &sma1307_sdo_control, 1083 sma1307_sdo_event, 1084 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1085 SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0), 1086 SND_SOC_DAPM_OUT_DRV_E("AMP Power", SND_SOC_NOPM, 0, 0, NULL, 0, 1087 sma1307_power_event, 1088 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD | 1089 SND_SOC_DAPM_POST_PMU), 1090 SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 0, 1091 &sma1307_enable_control), 1092 1093 /* stream domain */ 1094 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 1095 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 1096 }; 1097 1098 static const struct snd_soc_dapm_route sma1307_audio_map[] = { 1099 /* Playback */ 1100 { "AIF IN Source", "Mono", "AIF IN" }, 1101 { "AIF IN Source", "Left", "AIF IN" }, 1102 { "AIF IN Source", "Right", "AIF IN" }, 1103 1104 { "SDO Enable", "Switch", "AIF IN" }, 1105 1106 { "SDO Setting", "Data_One_48k", "SDO Enable" }, 1107 { "SDO Setting", "Data_Two_48k", "SDO Enable" }, 1108 { "SDO Setting", "Data_Two_24k", "SDO Enable" }, 1109 { "SDO Setting", "Clk_PLL", "SDO Enable" }, 1110 { "SDO Setting", "Clk_OSC", "SDO Enable" }, 1111 1112 { "AIF OUT0 Source", "Disable", "SDO Setting" }, 1113 { "AIF OUT0 Source", "After_FmtC", "SDO Setting" }, 1114 { "AIF OUT0 Source", "After_Mixer", "SDO Setting" }, 1115 { "AIF OUT0 Source", "After_DSP", "SDO Setting" }, 1116 { "AIF OUT0 Source", "Vrms2_Avg", "SDO Setting" }, 1117 { "AIF OUT0 Source", "Battery", "SDO Setting" }, 1118 { "AIF OUT0 Source", "Temperature", "SDO Setting" }, 1119 { "AIF OUT0 Source", "After_Delay", "SDO Setting" }, 1120 1121 { "AIF OUT1 Source", "Disable", "SDO Setting" }, 1122 { "AIF OUT1 Source", "After_FmtC", "SDO Setting" }, 1123 { "AIF OUT1 Source", "After_Mixer", "SDO Setting" }, 1124 { "AIF OUT1 Source", "After_DSP", "SDO Setting" }, 1125 { "AIF OUT1 Source", "Vrms2_Avg", "SDO Setting" }, 1126 { "AIF OUT1 Source", "Battery", "SDO Setting" }, 1127 { "AIF OUT1 Source", "Temperature", "SDO Setting" }, 1128 { "AIF OUT1 Source", "After_Delay", "SDO Setting" }, 1129 1130 { "Entry", NULL, "AIF OUT0 Source" }, 1131 { "Entry", NULL, "AIF OUT1 Source" }, 1132 { "Entry", NULL, "AIF IN Source" }, 1133 1134 { "AMP Power", NULL, "Entry" }, 1135 1136 { "AMP Enable", "Switch", "AMP Power" }, 1137 { "SPK", NULL, "AMP Enable" }, 1138 1139 /* Capture */ 1140 { "AIF OUT", NULL, "AMP Enable" }, 1141 }; 1142 1143 static void sma1307_setup_pll(struct snd_soc_component *component, 1144 unsigned int bclk) 1145 { 1146 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1147 1148 int i = 0; 1149 1150 dev_dbg(component->dev, "%s: BCLK = %dHz\n", __func__, bclk); 1151 1152 if (sma1307->sys_clk_id == SMA1307_PLL_CLKIN_MCLK) { 1153 dev_warn(component->dev, "%s: MCLK is not supported\n", 1154 __func__); 1155 } else if (sma1307->sys_clk_id == SMA1307_PLL_CLKIN_BCLK) { 1156 for (i = 0; i < sma1307->num_of_pll_matches; i++) { 1157 if (sma1307->pll_matches[i].input_clk == bclk) 1158 break; 1159 } 1160 if (i == sma1307->num_of_pll_matches) { 1161 dev_warn(component->dev, 1162 "%s: No matching value between pll table and SCK\n", 1163 __func__); 1164 return; 1165 } 1166 1167 regmap_update_bits(sma1307->regmap, 1168 SMA1307_A2_TOP_MAN1, 1169 SMA1307_PLL_MASK, SMA1307_PLL_ON); 1170 } 1171 1172 regmap_write(sma1307->regmap, SMA1307_8B_PLL_POST_N, 1173 sma1307->pll_matches[i].post_n); 1174 regmap_write(sma1307->regmap, SMA1307_8C_PLL_N, 1175 sma1307->pll_matches[i].n); 1176 regmap_write(sma1307->regmap, SMA1307_8D_PLL_A_SETTING, 1177 sma1307->pll_matches[i].vco); 1178 regmap_write(sma1307->regmap, SMA1307_8E_PLL_P_CP, 1179 sma1307->pll_matches[i].p_cp); 1180 } 1181 1182 static int sma1307_dai_hw_params_amp(struct snd_pcm_substream *substream, 1183 struct snd_pcm_hw_params *params, 1184 struct snd_soc_dai *dai) 1185 { 1186 struct snd_soc_component *component = dai->component; 1187 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1188 unsigned int bclk = 0; 1189 1190 if (sma1307->format == SND_SOC_DAIFMT_DSP_A) 1191 bclk = params_rate(params) * sma1307->frame_size; 1192 else 1193 bclk = params_rate(params) * params_physical_width(params) 1194 * params_channels(params); 1195 1196 dev_dbg(component->dev, 1197 "%s: rate = %d : bit size = %d : channel = %d\n", 1198 __func__, params_rate(params), params_width(params), 1199 params_channels(params)); 1200 1201 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1202 if (sma1307->sys_clk_id == SMA1307_PLL_CLKIN_BCLK) { 1203 if (sma1307->last_bclk != bclk) { 1204 sma1307_setup_pll(component, bclk); 1205 sma1307->last_bclk = bclk; 1206 } 1207 } 1208 1209 switch (params_rate(params)) { 1210 case 8000: 1211 case 12000: 1212 case 16000: 1213 case 24000: 1214 case 32000: 1215 case 44100: 1216 case 48000: 1217 break; 1218 1219 case 96000: 1220 dev_warn(component->dev, 1221 "%s: %d rate not support SDO\n", __func__, 1222 params_rate(params)); 1223 break; 1224 1225 default: 1226 dev_err(component->dev, "%s: not support rate : %d\n", 1227 __func__, params_rate(params)); 1228 1229 return -EINVAL; 1230 } 1231 1232 /* substream->stream is SNDRV_PCM_STREAM_CAPTURE */ 1233 } else { 1234 1235 switch (params_format(params)) { 1236 case SNDRV_PCM_FORMAT_S16_LE: 1237 regmap_update_bits(sma1307->regmap, 1238 SMA1307_A4_TOP_MAN3, 1239 SMA1307_SCK_RATE_MASK 1240 | 1241 SMA1307_DATA_WIDTH_MASK, 1242 SMA1307_SCK_32FS | 1243 SMA1307_DATA_16BIT); 1244 break; 1245 1246 case SNDRV_PCM_FORMAT_S24_LE: 1247 regmap_update_bits(sma1307->regmap, 1248 SMA1307_A4_TOP_MAN3, 1249 SMA1307_SCK_RATE_MASK 1250 | 1251 SMA1307_DATA_WIDTH_MASK, 1252 SMA1307_SCK_64FS | 1253 SMA1307_DATA_24BIT); 1254 break; 1255 1256 case SNDRV_PCM_FORMAT_S32_LE: 1257 regmap_update_bits(sma1307->regmap, 1258 SMA1307_A4_TOP_MAN3, 1259 SMA1307_SCK_RATE_MASK 1260 | 1261 SMA1307_DATA_WIDTH_MASK, 1262 SMA1307_SCK_64FS | 1263 SMA1307_DATA_24BIT); 1264 break; 1265 default: 1266 dev_err(component->dev, 1267 "%s: not support data bit : %d\n", __func__, 1268 params_format(params)); 1269 return -EINVAL; 1270 } 1271 } 1272 1273 switch (sma1307->format) { 1274 case SND_SOC_DAIFMT_I2S: 1275 regmap_update_bits(sma1307->regmap, 1276 SMA1307_01_INPUT_CTRL1, 1277 SMA1307_I2S_MODE_MASK, 1278 SMA1307_STANDARD_I2S); 1279 regmap_update_bits(sma1307->regmap, 1280 SMA1307_A4_TOP_MAN3, 1281 SMA1307_INTERFACE_MASK, 1282 SMA1307_I2S_FORMAT); 1283 break; 1284 case SND_SOC_DAIFMT_LEFT_J: 1285 regmap_update_bits(sma1307->regmap, 1286 SMA1307_01_INPUT_CTRL1, 1287 SMA1307_I2S_MODE_MASK, SMA1307_LJ); 1288 regmap_update_bits(sma1307->regmap, 1289 SMA1307_A4_TOP_MAN3, 1290 SMA1307_INTERFACE_MASK, 1291 SMA1307_LJ_FORMAT); 1292 break; 1293 case SND_SOC_DAIFMT_RIGHT_J: 1294 switch (params_width(params)) { 1295 case 16: 1296 regmap_update_bits(sma1307->regmap, 1297 SMA1307_01_INPUT_CTRL1, 1298 SMA1307_I2S_MODE_MASK, 1299 SMA1307_RJ_16BIT); 1300 break; 1301 case 24: 1302 case 32: 1303 regmap_update_bits(sma1307->regmap, 1304 SMA1307_01_INPUT_CTRL1, 1305 SMA1307_I2S_MODE_MASK, 1306 SMA1307_RJ_24BIT); 1307 break; 1308 } 1309 break; 1310 case SND_SOC_DAIFMT_DSP_A: 1311 regmap_update_bits(sma1307->regmap, 1312 SMA1307_01_INPUT_CTRL1, 1313 SMA1307_I2S_MODE_MASK, 1314 SMA1307_STANDARD_I2S); 1315 regmap_update_bits(sma1307->regmap, 1316 SMA1307_A4_TOP_MAN3, 1317 SMA1307_INTERFACE_MASK, 1318 SMA1307_TDM_FORMAT); 1319 break; 1320 } 1321 1322 switch (params_width(params)) { 1323 case 16: 1324 case 24: 1325 case 32: 1326 break; 1327 default: 1328 dev_err(component->dev, 1329 "%s: not support data bit : %d\n", __func__, 1330 params_format(params)); 1331 return -EINVAL; 1332 } 1333 1334 return 0; 1335 } 1336 1337 static int sma1307_dai_set_sysclk_amp(struct snd_soc_dai *dai, 1338 int clk_id, unsigned int freq, int dir) 1339 { 1340 struct snd_soc_component *component = dai->component; 1341 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1342 1343 switch (clk_id) { 1344 case SMA1307_EXTERNAL_CLOCK_19_2: 1345 case SMA1307_EXTERNAL_CLOCK_24_576: 1346 case SMA1307_PLL_CLKIN_MCLK: 1347 case SMA1307_PLL_CLKIN_BCLK: 1348 break; 1349 default: 1350 dev_err(component->dev, "%s: Invalid clk id: %d\n", 1351 __func__, clk_id); 1352 return -EINVAL; 1353 } 1354 sma1307->sys_clk_id = clk_id; 1355 1356 return 0; 1357 } 1358 1359 static int sma1307_dai_set_fmt_amp(struct snd_soc_dai *dai, unsigned int fmt) 1360 { 1361 struct snd_soc_component *component = dai->component; 1362 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1363 1364 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1365 1366 case SND_SOC_DAIFMT_CBC_CFC: 1367 dev_dbg(component->dev, 1368 "%s: %s\n", __func__, "I2S/TDM Device mode"); 1369 regmap_update_bits(sma1307->regmap, 1370 SMA1307_01_INPUT_CTRL1, 1371 SMA1307_CONTROLLER_DEVICE_MASK, 1372 SMA1307_DEVICE_MODE); 1373 break; 1374 1375 case SND_SOC_DAIFMT_CBP_CFP: 1376 dev_dbg(component->dev, 1377 "%s: %s\n", __func__, "I2S/TDM Controller mode"); 1378 regmap_update_bits(sma1307->regmap, 1379 SMA1307_01_INPUT_CTRL1, 1380 SMA1307_CONTROLLER_DEVICE_MASK, 1381 SMA1307_CONTROLLER_MODE); 1382 break; 1383 1384 default: 1385 dev_err(component->dev, 1386 "%s: Unsupported Controller/Device : 0x%x\n", 1387 __func__, fmt); 1388 return -EINVAL; 1389 } 1390 1391 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1392 case SND_SOC_DAIFMT_I2S: 1393 case SND_SOC_DAIFMT_RIGHT_J: 1394 case SND_SOC_DAIFMT_LEFT_J: 1395 case SND_SOC_DAIFMT_DSP_A: 1396 case SND_SOC_DAIFMT_DSP_B: 1397 sma1307->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1398 break; 1399 default: 1400 dev_err(component->dev, 1401 "%s: Unsupported Audio Interface Format : 0x%x\n", 1402 __func__, fmt); 1403 return -EINVAL; 1404 } 1405 1406 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1407 1408 case SND_SOC_DAIFMT_IB_NF: 1409 dev_dbg(component->dev, "%s: %s\n", 1410 __func__, "Invert BCLK + Normal Frame"); 1411 regmap_update_bits(sma1307->regmap, 1412 SMA1307_01_INPUT_CTRL1, 1413 SMA1307_SCK_RISING_MASK, 1414 SMA1307_SCK_RISING_EDGE); 1415 break; 1416 case SND_SOC_DAIFMT_IB_IF: 1417 dev_dbg(component->dev, "%s: %s\n", 1418 __func__, "Invert BCLK + Invert Frame"); 1419 regmap_update_bits(sma1307->regmap, 1420 SMA1307_01_INPUT_CTRL1, 1421 SMA1307_LEFTPOL_MASK 1422 | SMA1307_SCK_RISING_MASK, 1423 SMA1307_HIGH_FIRST_CH 1424 | SMA1307_SCK_RISING_EDGE); 1425 break; 1426 case SND_SOC_DAIFMT_NB_IF: 1427 dev_dbg(component->dev, "%s: %s\n", 1428 __func__, "Normal BCLK + Invert Frame"); 1429 regmap_update_bits(sma1307->regmap, 1430 SMA1307_01_INPUT_CTRL1, 1431 SMA1307_LEFTPOL_MASK, 1432 SMA1307_HIGH_FIRST_CH); 1433 break; 1434 case SND_SOC_DAIFMT_NB_NF: 1435 dev_dbg(component->dev, "%s: %s\n", 1436 __func__, "Normal BCLK + Normal Frame"); 1437 break; 1438 default: 1439 dev_err(component->dev, 1440 "%s: Unsupported Bit & Frameclock : 0x%x\n", 1441 __func__, fmt); 1442 return -EINVAL; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int sma1307_dai_set_tdm_slot(struct snd_soc_dai *dai, 1449 unsigned int tx_mask, unsigned int rx_mask, 1450 int slots, int slot_width) 1451 { 1452 struct snd_soc_component *component = dai->component; 1453 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1454 1455 dev_dbg(component->dev, "%s: slots = %d, slot_width - %d\n", 1456 __func__, slots, slot_width); 1457 1458 sma1307->frame_size = slot_width * slots; 1459 1460 regmap_update_bits(sma1307->regmap, 1461 SMA1307_A4_TOP_MAN3, 1462 SMA1307_INTERFACE_MASK, SMA1307_TDM_FORMAT); 1463 1464 regmap_update_bits(sma1307->regmap, 1465 SMA1307_A5_TDM1, 1466 SMA1307_TDM_TX_MODE_MASK, 1467 SMA1307_TDM_TX_MONO); 1468 1469 switch (slot_width) { 1470 case 16: 1471 regmap_update_bits(sma1307->regmap, 1472 SMA1307_A6_TDM2, 1473 SMA1307_TDM_DL_MASK, 1474 SMA1307_TDM_DL_16); 1475 break; 1476 case 32: 1477 regmap_update_bits(sma1307->regmap, 1478 SMA1307_A6_TDM2, 1479 SMA1307_TDM_DL_MASK, 1480 SMA1307_TDM_DL_32); 1481 break; 1482 default: 1483 dev_err(component->dev, "%s: not support TDM %d slot_width\n", 1484 __func__, slot_width); 1485 return -EINVAL; 1486 } 1487 1488 switch (slots) { 1489 case 4: 1490 regmap_update_bits(sma1307->regmap, 1491 SMA1307_A6_TDM2, 1492 SMA1307_TDM_N_SLOT_MASK, 1493 SMA1307_TDM_N_SLOT_4); 1494 break; 1495 case 8: 1496 regmap_update_bits(sma1307->regmap, 1497 SMA1307_A6_TDM2, 1498 SMA1307_TDM_N_SLOT_MASK, 1499 SMA1307_TDM_N_SLOT_8); 1500 break; 1501 default: 1502 dev_err(component->dev, "%s: not support TDM %d slots\n", 1503 __func__, slots); 1504 return -EINVAL; 1505 } 1506 1507 if (sma1307->tdm_slot0_rx < slots) 1508 regmap_update_bits(sma1307->regmap, 1509 SMA1307_A5_TDM1, 1510 SMA1307_TDM_SLOT0_RX_POS_MASK, 1511 sma1307->tdm_slot0_rx << 3); 1512 else 1513 dev_err(component->dev, "%s: Incorrect tdm-slot0-rx %d set\n", 1514 __func__, sma1307->tdm_slot0_rx); 1515 1516 if (sma1307->tdm_slot1_rx < slots) 1517 regmap_update_bits(sma1307->regmap, 1518 SMA1307_A5_TDM1, 1519 SMA1307_TDM_SLOT1_RX_POS_MASK, 1520 sma1307->tdm_slot1_rx); 1521 else 1522 dev_err(component->dev, "%s: Incorrect tdm-slot1-rx %d set\n", 1523 __func__, sma1307->tdm_slot1_rx); 1524 1525 if (sma1307->tdm_slot0_tx < slots) 1526 regmap_update_bits(sma1307->regmap, 1527 SMA1307_A6_TDM2, 1528 SMA1307_TDM_SLOT0_TX_POS_MASK, 1529 sma1307->tdm_slot0_tx << 3); 1530 else 1531 dev_err(component->dev, "%s: Incorrect tdm-slot0-tx %d set\n", 1532 __func__, sma1307->tdm_slot0_tx); 1533 1534 if (sma1307->tdm_slot1_tx < slots) 1535 regmap_update_bits(sma1307->regmap, 1536 SMA1307_A6_TDM2, 1537 SMA1307_TDM_SLOT1_TX_POS_MASK, 1538 sma1307->tdm_slot1_tx); 1539 else 1540 dev_err(component->dev, "%s: Incorrect tdm-slot1-tx %d set\n", 1541 __func__, sma1307->tdm_slot1_tx); 1542 1543 return 0; 1544 } 1545 1546 static int sma1307_dai_mute_stream(struct snd_soc_dai *dai, int mute, 1547 int stream) 1548 { 1549 struct snd_soc_component *component = dai->component; 1550 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1551 1552 if (stream == SNDRV_PCM_STREAM_CAPTURE) 1553 return 0; 1554 if (mute) { 1555 dev_dbg(component->dev, "%s: %s\n", __func__, "MUTE"); 1556 regmap_update_bits(sma1307->regmap, 1557 SMA1307_0E_MUTE_VOL_CTRL, 1558 SMA1307_SPK_MUTE_MASK, 1559 SMA1307_SPK_MUTE); 1560 } else { 1561 if (!sma1307->force_mute_status) { 1562 dev_dbg(component->dev, "%s: %s\n", __func__, 1563 "UNMUTE"); 1564 regmap_update_bits(sma1307->regmap, 1565 SMA1307_0E_MUTE_VOL_CTRL, 1566 SMA1307_SPK_MUTE_MASK, 1567 SMA1307_SPK_UNMUTE); 1568 } else { 1569 dev_dbg(sma1307->dev, "%s: FORCE MUTE!!!\n", __func__); 1570 } 1571 } 1572 1573 return 0; 1574 } 1575 1576 static const struct snd_soc_dai_ops sma1307_dai_ops_amp = { 1577 .hw_params = sma1307_dai_hw_params_amp, 1578 .set_fmt = sma1307_dai_set_fmt_amp, 1579 .set_sysclk = sma1307_dai_set_sysclk_amp, 1580 .set_tdm_slot = sma1307_dai_set_tdm_slot, 1581 .mute_stream = sma1307_dai_mute_stream, 1582 }; 1583 1584 #define SMA1307_RATES_PLAYBACK SNDRV_PCM_RATE_8000_96000 1585 #define SMA1307_RATES_CAPTURE SNDRV_PCM_RATE_8000_48000 1586 #define SMA1307_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1587 SNDRV_PCM_FMTBIT_S32_LE) 1588 1589 static struct snd_soc_dai_driver sma1307_dai[] = { 1590 { 1591 .name = "sma1307-amplifier", 1592 .id = 0, 1593 .playback = { 1594 .stream_name = "Playback", 1595 .channels_min = 1, 1596 .channels_max = 2, 1597 .rates = SMA1307_RATES_PLAYBACK, 1598 .formats = SMA1307_FORMATS, 1599 }, 1600 .capture = { 1601 .stream_name = "Capture", 1602 .channels_min = 1, 1603 .channels_max = 2, 1604 .rates = SMA1307_RATES_CAPTURE, 1605 .formats = SMA1307_FORMATS, 1606 }, 1607 .ops = &sma1307_dai_ops_amp, 1608 }, 1609 }; 1610 1611 static void sma1307_check_fault_worker(struct work_struct *work) 1612 { 1613 struct sma1307_priv *sma1307 = 1614 container_of(work, struct sma1307_priv, check_fault_work.work); 1615 unsigned int status1_val, status2_val; 1616 char *envp[3] = { NULL, NULL, NULL }; 1617 1618 if (sma1307->tsdw_cnt) 1619 regmap_read(sma1307->regmap, 1620 SMA1307_0A_SPK_VOL, &sma1307->cur_vol); 1621 else 1622 regmap_read(sma1307->regmap, 1623 SMA1307_0A_SPK_VOL, &sma1307->init_vol); 1624 1625 regmap_read(sma1307->regmap, SMA1307_FA_STATUS1, &status1_val); 1626 regmap_read(sma1307->regmap, SMA1307_FB_STATUS2, &status2_val); 1627 1628 if (~status1_val & SMA1307_OT1_OK_STATUS) { 1629 dev_crit(sma1307->dev, 1630 "%s: OT1(Over Temperature Level 1)\n", __func__); 1631 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OT1"); 1632 if (sma1307->sw_ot1_prot) { 1633 /* Volume control (Current Volume -3dB) */ 1634 if ((sma1307->cur_vol + 6) <= 0xFA) { 1635 sma1307->cur_vol += 6; 1636 regmap_write(sma1307->regmap, 1637 SMA1307_0A_SPK_VOL, 1638 sma1307->cur_vol); 1639 envp[1] = kasprintf(GFP_KERNEL, 1640 "VOLUME=0x%02X", sma1307->cur_vol); 1641 } 1642 } 1643 sma1307->tsdw_cnt++; 1644 } else if (sma1307->tsdw_cnt) { 1645 regmap_write(sma1307->regmap, 1646 SMA1307_0A_SPK_VOL, sma1307->init_vol); 1647 sma1307->tsdw_cnt = 0; 1648 sma1307->cur_vol = sma1307->init_vol; 1649 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OT1_CLEAR"); 1650 envp[1] = kasprintf(GFP_KERNEL, 1651 "VOLUME=0x%02X", sma1307->cur_vol); 1652 } 1653 1654 if (~status1_val & SMA1307_OT2_OK_STATUS) { 1655 dev_crit(sma1307->dev, 1656 "%s: OT2(Over Temperature Level 2)\n", __func__); 1657 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OT2"); 1658 } 1659 if (status1_val & SMA1307_UVLO_STATUS) { 1660 dev_crit(sma1307->dev, 1661 "%s: UVLO(Under Voltage Lock Out)\n", __func__); 1662 envp[0] = kasprintf(GFP_KERNEL, "STATUS=UVLO"); 1663 } 1664 if (status1_val & SMA1307_OVP_BST_STATUS) { 1665 dev_crit(sma1307->dev, 1666 "%s: OVP_BST(Over Voltage Protection)\n", __func__); 1667 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OVP_BST"); 1668 } 1669 if (status2_val & SMA1307_OCP_SPK_STATUS) { 1670 dev_crit(sma1307->dev, 1671 "%s: OCP_SPK(Over Current Protect SPK)\n", __func__); 1672 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OCP_SPK"); 1673 } 1674 if (status2_val & SMA1307_OCP_BST_STATUS) { 1675 dev_crit(sma1307->dev, 1676 "%s: OCP_BST(Over Current Protect Boost)\n", __func__); 1677 envp[0] = kasprintf(GFP_KERNEL, "STATUS=OCP_BST"); 1678 } 1679 if (status2_val & SMA1307_CLK_MON_STATUS) { 1680 dev_crit(sma1307->dev, 1681 "%s: CLK_FAULT(No clock input)\n", __func__); 1682 envp[0] = kasprintf(GFP_KERNEL, "STATUS=CLK_FAULT"); 1683 } 1684 1685 if (envp[0] != NULL) { 1686 if (kobject_uevent_env(sma1307->kobj, KOBJ_CHANGE, envp)) 1687 dev_err(sma1307->dev, 1688 "%s: Error sending uevent\n", __func__); 1689 kfree(envp[0]); 1690 kfree(envp[1]); 1691 } 1692 1693 if (sma1307->check_fault_status) { 1694 if (sma1307->check_fault_period > 0) 1695 queue_delayed_work(system_freezable_wq, 1696 &sma1307->check_fault_work, 1697 sma1307->check_fault_period * HZ); 1698 else 1699 queue_delayed_work(system_freezable_wq, 1700 &sma1307->check_fault_work, 1701 CHECK_PERIOD_TIME * HZ); 1702 } 1703 } 1704 1705 static void sma1307_setting_loaded(struct sma1307_priv *sma1307, const char *file) 1706 { 1707 const struct firmware *fw; 1708 int size, offset, num_mode; 1709 int ret; 1710 1711 ret = request_firmware(&fw, file, sma1307->dev); 1712 1713 if (ret) { 1714 dev_err(sma1307->dev, "%s: failed to read \"%s\": %pe\n", 1715 __func__, setting_file, ERR_PTR(ret)); 1716 sma1307->set.status = false; 1717 return; 1718 } else if ((fw->size) < SMA1307_SETTING_HEADER_SIZE) { 1719 dev_err(sma1307->dev, "%s: Invalid file\n", __func__); 1720 release_firmware(fw); 1721 sma1307->set.status = false; 1722 return; 1723 } 1724 1725 int *data __free(kfree) = kzalloc(fw->size, GFP_KERNEL); 1726 if (!data) { 1727 release_firmware(fw); 1728 sma1307->set.status = false; 1729 return; 1730 } 1731 size = fw->size >> 2; 1732 memcpy(data, fw->data, fw->size); 1733 1734 release_firmware(fw); 1735 1736 /* HEADER */ 1737 sma1307->set.header_size = SMA1307_SETTING_HEADER_SIZE; 1738 sma1307->set.checksum = data[sma1307->set.header_size - 2]; 1739 sma1307->set.num_mode = data[sma1307->set.header_size - 1]; 1740 num_mode = sma1307->set.num_mode; 1741 sma1307->set.header = devm_kzalloc(sma1307->dev, 1742 sma1307->set.header_size, 1743 GFP_KERNEL); 1744 if (!sma1307->set.header) { 1745 sma1307->set.status = false; 1746 return; 1747 } 1748 1749 memcpy(sma1307->set.header, data, 1750 sma1307->set.header_size * sizeof(int)); 1751 1752 if ((sma1307->set.checksum >> 8) != SMA1307_SETTING_CHECKSUM) { 1753 dev_err(sma1307->dev, "%s: failed by dismatch \"%s\"\n", 1754 __func__, setting_file); 1755 sma1307->set.status = false; 1756 return; 1757 } 1758 1759 /* DEFAULT */ 1760 sma1307->set.def_size = SMA1307_SETTING_DEFAULT_SIZE; 1761 sma1307->set.def 1762 = devm_kzalloc(sma1307->dev, 1763 sma1307->set.def_size * sizeof(int), GFP_KERNEL); 1764 if (!sma1307->set.def) { 1765 sma1307->set.status = false; 1766 return; 1767 } 1768 1769 memcpy(sma1307->set.def, 1770 &data[sma1307->set.header_size], 1771 sma1307->set.def_size * sizeof(int)); 1772 1773 /* MODE */ 1774 offset = sma1307->set.header_size + sma1307->set.def_size; 1775 sma1307->set.mode_size = DIV_ROUND_CLOSEST(size - offset, num_mode + 1); 1776 for (int i = 0; i < num_mode; i++) { 1777 sma1307->set.mode_set[i] 1778 = devm_kzalloc(sma1307->dev, 1779 sma1307->set.mode_size * 2 * sizeof(int), 1780 GFP_KERNEL); 1781 if (!sma1307->set.mode_set[i]) { 1782 for (int j = 0; j < i; j++) 1783 kfree(sma1307->set.mode_set[j]); 1784 sma1307->set.status = false; 1785 return; 1786 } 1787 1788 for (int j = 0; j < sma1307->set.mode_size; j++) { 1789 sma1307->set.mode_set[i][2 * j] 1790 = data[offset + ((num_mode + 1) * j)]; 1791 sma1307->set.mode_set[i][2 * j + 1] 1792 = data[offset + ((num_mode + 1) * j + i + 1)]; 1793 } 1794 } 1795 1796 sma1307->set.status = true; 1797 1798 } 1799 1800 static void sma1307_reset(struct snd_soc_component *component) 1801 { 1802 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1803 unsigned int status = 0; 1804 1805 regmap_read(sma1307->regmap, SMA1307_FF_DEVICE_INDEX, &status); 1806 1807 sma1307->rev_num = status & SMA1307_REV_NUM_STATUS; 1808 dev_dbg(component->dev, "%s: SMA1307 Revision %d\n", 1809 __func__, sma1307->rev_num); 1810 regmap_read(sma1307->regmap, SMA1307_99_OTP_TRM2, &sma1307->otp_trm2); 1811 regmap_read(sma1307->regmap, SMA1307_9A_OTP_TRM3, &sma1307->otp_trm3); 1812 1813 if ((sma1307->otp_trm2 & SMA1307_OTP_STAT_MASK) != SMA1307_OTP_STAT_1) 1814 dev_warn(component->dev, "%s: SMA1307 OTP Status Fail\n", 1815 __func__); 1816 1817 /* Register Initial Value Setting */ 1818 sma1307_setting_loaded(sma1307, setting_file); 1819 if (sma1307->set.status) 1820 sma1307_set_binary(component); 1821 else 1822 sma1307_set_default(component); 1823 1824 regmap_update_bits(sma1307->regmap, 1825 SMA1307_93_INT_CTRL, 1826 SMA1307_DIS_INT_MASK, SMA1307_HIGH_Z_INT); 1827 regmap_write(sma1307->regmap, SMA1307_0A_SPK_VOL, sma1307->init_vol); 1828 } 1829 1830 static void sma1307_set_binary(struct snd_soc_component *component) 1831 { 1832 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1833 int i = 0, mode = 0; 1834 1835 for (i = 0; i < (sma1307->set.def_size); i++) { 1836 if (sma1307_writeable_register(sma1307->dev, i) 1837 && ((i < SMA1307_97_OTP_TRM0) 1838 || (i > SMA1307_9A_OTP_TRM3))) { 1839 regmap_write(sma1307->regmap, i, sma1307->set.def[i]); 1840 1841 } 1842 } 1843 for (i = 0; i < (sma1307->set.mode_size); i++) { 1844 if (sma1307_writeable_register(sma1307->dev, i) 1845 && ((i < SMA1307_97_OTP_TRM0) 1846 || (i > SMA1307_9A_OTP_TRM3))) { 1847 mode = sma1307->binary_mode; 1848 regmap_write(sma1307->regmap, 1849 sma1307->set.mode_set[mode][2 * i], 1850 sma1307->set.mode_set[mode][2 * i + 1851 1]); 1852 } 1853 } 1854 } 1855 1856 static void sma1307_set_default(struct snd_soc_component *component) 1857 { 1858 struct sma1307_priv *sma1307 = snd_soc_component_get_drvdata(component); 1859 int i = 0; 1860 1861 for (i = 0; i < (unsigned int)ARRAY_SIZE(sma1307_reg_def); i++) 1862 regmap_write(sma1307->regmap, 1863 sma1307_reg_def[i].reg, 1864 sma1307_reg_def[i].def); 1865 1866 if (!strcmp(sma1307->name, DEVICE_NAME_SMA1307AQ)) 1867 sma1307->data->init(sma1307->regmap); 1868 } 1869 1870 static int sma1307_probe(struct snd_soc_component *component) 1871 { 1872 struct snd_soc_dapm_context *dapm = 1873 snd_soc_component_get_dapm(component); 1874 1875 snd_soc_dapm_sync(dapm); 1876 1877 sma1307_amp_component = component; 1878 1879 snd_soc_add_component_controls(component, sma1307_binary_mode_control, 1880 ARRAY_SIZE(sma1307_binary_mode_control)); 1881 sma1307_reset(component); 1882 1883 return 0; 1884 } 1885 1886 static const struct snd_soc_component_driver sma1307_component = { 1887 .probe = sma1307_probe, 1888 .controls = sma1307_snd_controls, 1889 .num_controls = ARRAY_SIZE(sma1307_snd_controls), 1890 .dapm_widgets = sma1307_dapm_widgets, 1891 .num_dapm_widgets = ARRAY_SIZE(sma1307_dapm_widgets), 1892 .dapm_routes = sma1307_audio_map, 1893 .num_dapm_routes = ARRAY_SIZE(sma1307_audio_map), 1894 }; 1895 1896 static const struct regmap_config sma_i2c_regmap = { 1897 .reg_bits = 8, 1898 .val_bits = 8, 1899 1900 .max_register = SMA1307_FF_DEVICE_INDEX, 1901 .readable_reg = sma1307_readable_register, 1902 .writeable_reg = sma1307_writeable_register, 1903 .volatile_reg = sma1307_volatile_register, 1904 1905 .reg_defaults = sma1307_reg_def, 1906 .num_reg_defaults = ARRAY_SIZE(sma1307_reg_def), 1907 }; 1908 1909 static void sma1307aq_init(struct regmap *regmap) 1910 { 1911 /* Guidelines for driving 4ohm load */ 1912 /* Brown Out Protection */ 1913 regmap_write(regmap, SMA1307_02_BROWN_OUT_PROT1, 0x62); 1914 regmap_write(regmap, SMA1307_03_BROWN_OUT_PROT2, 0x5D); 1915 regmap_write(regmap, SMA1307_04_BROWN_OUT_PROT3, 0x57); 1916 regmap_write(regmap, SMA1307_05_BROWN_OUT_PROT8, 0x54); 1917 regmap_write(regmap, SMA1307_06_BROWN_OUT_PROT9, 0x51); 1918 regmap_write(regmap, 1919 SMA1307_07_BROWN_OUT_PROT10, 0x4D); 1920 regmap_write(regmap, 1921 SMA1307_08_BROWN_OUT_PROT11, 0x4B); 1922 regmap_write(regmap, SMA1307_27_BROWN_OUT_PROT4, 0x3C); 1923 regmap_write(regmap, SMA1307_28_BROWN_OUT_PROT5, 0x5B); 1924 regmap_write(regmap, 1925 SMA1307_29_BROWN_OUT_PROT12, 0x78); 1926 regmap_write(regmap, 1927 SMA1307_2A_BROWN_OUT_PROT13, 0x96); 1928 regmap_write(regmap, 1929 SMA1307_2B_BROWN_OUT_PROT14, 0xB4); 1930 regmap_write(regmap, 1931 SMA1307_2C_BROWN_OUT_PROT15, 0xD3); 1932 /* FDPEC Gain */ 1933 regmap_write(regmap, SMA1307_35_FDPEC_CTRL0, 0x16); 1934 /* FLT Vdd */ 1935 regmap_write(regmap, SMA1307_92_FDPEC_CTRL1, 0xA0); 1936 /* Boost Max */ 1937 regmap_write(regmap, SMA1307_AB_BOOST_CTRL4, 0x0F); 1938 } 1939 1940 static const struct sma1307_data sma1307aq_data = { 1941 .name = DEVICE_NAME_SMA1307AQ, 1942 .init = sma1307aq_init, 1943 }; 1944 1945 static int sma1307_i2c_probe(struct i2c_client *client) 1946 { 1947 struct sma1307_priv *sma1307; 1948 const struct sma1307_data *data; 1949 int ret = 0; 1950 unsigned int device_info; 1951 1952 sma1307 = devm_kzalloc(&client->dev, 1953 sizeof(*sma1307), GFP_KERNEL); 1954 if (!sma1307) 1955 return -ENOMEM; 1956 1957 sma1307->regmap = devm_regmap_init_i2c(client, &sma_i2c_regmap); 1958 if (IS_ERR(sma1307->regmap)) { 1959 return dev_err_probe(&client->dev, PTR_ERR(sma1307->regmap), 1960 "%s: failed to allocate register map\n", __func__); 1961 } 1962 1963 data = device_get_match_data(&client->dev); 1964 if (!data) 1965 return -ENODEV; 1966 1967 sma1307->data = data; 1968 1969 /* set initial value as normal AMP IC status */ 1970 sma1307->name = client->name; 1971 sma1307->format = SND_SOC_DAIFMT_I2S; 1972 sma1307->sys_clk_id = SMA1307_PLL_CLKIN_BCLK; 1973 sma1307->num_of_pll_matches = ARRAY_SIZE(sma1307_pll_matches); 1974 1975 sma1307->check_fault_period = CHECK_PERIOD_TIME; 1976 sma1307->check_fault_status = true; 1977 sma1307->init_vol = 0x32; 1978 sma1307->cur_vol = sma1307->init_vol; 1979 sma1307->sw_ot1_prot = true; 1980 1981 mutex_init(&sma1307->default_lock); 1982 1983 INIT_DELAYED_WORK(&sma1307->check_fault_work, 1984 sma1307_check_fault_worker); 1985 1986 sma1307->dev = &client->dev; 1987 sma1307->kobj = &client->dev.kobj; 1988 1989 i2c_set_clientdata(client, sma1307); 1990 1991 sma1307->pll_matches = sma1307_pll_matches; 1992 1993 regmap_read(sma1307->regmap, 1994 SMA1307_FF_DEVICE_INDEX, &device_info); 1995 1996 if ((device_info & 0xF8) != SMA1307_DEVICE_ID) { 1997 dev_err(&client->dev, 1998 "%s: device initialization error (0x%02X)", 1999 __func__, device_info); 2000 return -ENODEV; 2001 } 2002 dev_dbg(&client->dev, "%s: chip version 0x%02X\n", 2003 __func__, device_info); 2004 2005 i2c_set_clientdata(client, sma1307); 2006 2007 ret = devm_snd_soc_register_component(&client->dev, 2008 &sma1307_component, sma1307_dai, 2009 1); 2010 2011 if (ret) { 2012 dev_err(&client->dev, "%s: failed to register component\n", 2013 __func__); 2014 2015 return ret; 2016 } 2017 2018 return ret; 2019 } 2020 2021 static void sma1307_i2c_remove(struct i2c_client *client) 2022 { 2023 struct sma1307_priv *sma1307 = 2024 (struct sma1307_priv *)i2c_get_clientdata(client); 2025 2026 cancel_delayed_work_sync(&sma1307->check_fault_work); 2027 } 2028 2029 static const struct i2c_device_id sma1307_i2c_id[] = { 2030 { "sma1307a" }, 2031 { "sma1307aq" }, 2032 { } 2033 }; 2034 2035 MODULE_DEVICE_TABLE(i2c, sma1307_i2c_id); 2036 2037 static const struct of_device_id sma1307_of_match[] = { 2038 { 2039 .compatible = "irondevice,sma1307a", 2040 }, 2041 { 2042 .compatible = "irondevice,sma1307aq", 2043 .data = &sma1307aq_data //AEC-Q100 Qualificated 2044 }, 2045 { } 2046 }; 2047 2048 MODULE_DEVICE_TABLE(of, sma1307_of_match); 2049 2050 static struct i2c_driver sma1307_i2c_driver = { 2051 .driver = { 2052 .name = "sma1307", 2053 .of_match_table = sma1307_of_match, 2054 }, 2055 .probe = sma1307_i2c_probe, 2056 .remove = sma1307_i2c_remove, 2057 .id_table = sma1307_i2c_id, 2058 }; 2059 2060 module_i2c_driver(sma1307_i2c_driver); 2061 2062 MODULE_DESCRIPTION("ALSA SoC SMA1307 driver"); 2063 MODULE_AUTHOR("Gyuhwa Park, <gyuhwa.park@irondevice.com>"); 2064 MODULE_AUTHOR("KS Jo, <kiseok.jo@irondevice.com>"); 2065 MODULE_LICENSE("GPL"); 2066