1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // 3 // sma1303.c -- sma1303 ALSA SoC Audio driver 4 // 5 // Copyright 2023 Iron Device Corporation 6 // 7 // Auther: Gyuhwa Park <gyuhwa.park@irondevice.com> 8 // Kiseok Jo <kiseok.jo@irondevice.com> 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/regmap.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <linux/of_device.h> 25 #include <linux/slab.h> 26 #include <asm/div64.h> 27 28 #include "sma1303.h" 29 30 #define CHECK_PERIOD_TIME 1 /* sec per HZ */ 31 #define MAX_CONTROL_NAME 48 32 33 #define PLL_MATCH(_input_clk_name, _output_clk_name, _input_clk,\ 34 _post_n, _n, _vco, _p_cp)\ 35 {\ 36 .input_clk_name = _input_clk_name,\ 37 .output_clk_name = _output_clk_name,\ 38 .input_clk = _input_clk,\ 39 .post_n = _post_n,\ 40 .n = _n,\ 41 .vco = _vco,\ 42 .p_cp = _p_cp,\ 43 } 44 45 enum sma1303_type { 46 SMA1303, 47 }; 48 49 struct sma1303_pll_match { 50 char *input_clk_name; 51 char *output_clk_name; 52 unsigned int input_clk; 53 unsigned int post_n; 54 unsigned int n; 55 unsigned int vco; 56 unsigned int p_cp; 57 }; 58 59 struct sma1303_priv { 60 enum sma1303_type devtype; 61 struct attribute_group *attr_grp; 62 struct delayed_work check_fault_work; 63 struct device *dev; 64 struct kobject *kobj; 65 struct regmap *regmap; 66 struct sma1303_pll_match *pll_matches; 67 bool amp_power_status; 68 bool force_mute_status; 69 int num_of_pll_matches; 70 int retry_cnt; 71 unsigned int amp_mode; 72 unsigned int cur_vol; 73 unsigned int format; 74 unsigned int frame_size; 75 unsigned int init_vol; 76 unsigned int last_bclk; 77 unsigned int last_ocp_val; 78 unsigned int last_over_temp; 79 unsigned int rev_num; 80 unsigned int sys_clk_id; 81 unsigned int tdm_slot_rx; 82 unsigned int tdm_slot_tx; 83 unsigned int tsdw_cnt; 84 long check_fault_period; 85 long check_fault_status; 86 }; 87 88 static struct sma1303_pll_match sma1303_pll_matches[] = { 89 PLL_MATCH("1.411MHz", "24.595MHz", 1411200, 0x07, 0xF4, 0x8B, 0x03), 90 PLL_MATCH("1.536MHz", "24.576MHz", 1536000, 0x07, 0xE0, 0x8B, 0x03), 91 PLL_MATCH("3.072MHz", "24.576MHz", 3072000, 0x07, 0x70, 0x8B, 0x03), 92 PLL_MATCH("6.144MHz", "24.576MHz", 6144000, 0x07, 0x70, 0x8B, 0x07), 93 PLL_MATCH("12.288MHz", "24.576MHz", 12288000, 0x07, 0x70, 0x8B, 0x0B), 94 PLL_MATCH("19.2MHz", "24.343MHz", 19200000, 0x07, 0x47, 0x8B, 0x0A), 95 PLL_MATCH("24.576MHz", "24.576MHz", 24576000, 0x07, 0x70, 0x8B, 0x0F), 96 }; 97 98 static int sma1303_startup(struct snd_soc_component *); 99 static int sma1303_shutdown(struct snd_soc_component *); 100 101 static const struct reg_default sma1303_reg_def[] = { 102 { 0x00, 0x80 }, 103 { 0x01, 0x00 }, 104 { 0x02, 0x00 }, 105 { 0x03, 0x11 }, 106 { 0x04, 0x17 }, 107 { 0x09, 0x00 }, 108 { 0x0A, 0x31 }, 109 { 0x0B, 0x98 }, 110 { 0x0C, 0x84 }, 111 { 0x0D, 0x07 }, 112 { 0x0E, 0x3F }, 113 { 0x10, 0x00 }, 114 { 0x11, 0x00 }, 115 { 0x12, 0x00 }, 116 { 0x14, 0x5C }, 117 { 0x15, 0x01 }, 118 { 0x16, 0x0F }, 119 { 0x17, 0x0F }, 120 { 0x18, 0x0F }, 121 { 0x19, 0x00 }, 122 { 0x1A, 0x00 }, 123 { 0x1B, 0x00 }, 124 { 0x23, 0x19 }, 125 { 0x24, 0x00 }, 126 { 0x25, 0x00 }, 127 { 0x26, 0x04 }, 128 { 0x33, 0x00 }, 129 { 0x36, 0x92 }, 130 { 0x37, 0x27 }, 131 { 0x3B, 0x5A }, 132 { 0x3C, 0x20 }, 133 { 0x3D, 0x00 }, 134 { 0x3E, 0x03 }, 135 { 0x3F, 0x0C }, 136 { 0x8B, 0x07 }, 137 { 0x8C, 0x70 }, 138 { 0x8D, 0x8B }, 139 { 0x8E, 0x6F }, 140 { 0x8F, 0x03 }, 141 { 0x90, 0x26 }, 142 { 0x91, 0x42 }, 143 { 0x92, 0xE0 }, 144 { 0x94, 0x35 }, 145 { 0x95, 0x0C }, 146 { 0x96, 0x42 }, 147 { 0x97, 0x95 }, 148 { 0xA0, 0x00 }, 149 { 0xA1, 0x3B }, 150 { 0xA2, 0xC8 }, 151 { 0xA3, 0x28 }, 152 { 0xA4, 0x40 }, 153 { 0xA5, 0x01 }, 154 { 0xA6, 0x41 }, 155 { 0xA7, 0x00 }, 156 }; 157 158 static bool sma1303_readable_register(struct device *dev, unsigned int reg) 159 { 160 bool result; 161 162 if (reg > SMA1303_FF_DEVICE_INDEX) 163 return false; 164 165 switch (reg) { 166 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4: 167 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL: 168 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3: 169 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7: 170 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4: 171 case SMA1303_33_SDM_CTRL ... SMA1303_34_OTP_DATA1: 172 case SMA1303_36_PROTECTION ... SMA1303_38_OTP_TRM0: 173 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2: 174 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL: 175 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4: 176 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON: 177 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2: 178 result = true; 179 break; 180 case SMA1303_FF_DEVICE_INDEX: 181 result = true; 182 break; 183 default: 184 result = false; 185 break; 186 } 187 return result; 188 } 189 190 static bool sma1303_writeable_register(struct device *dev, unsigned int reg) 191 { 192 bool result; 193 194 if (reg > SMA1303_FF_DEVICE_INDEX) 195 return false; 196 197 switch (reg) { 198 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4: 199 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL: 200 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3: 201 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7: 202 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4: 203 case SMA1303_33_SDM_CTRL: 204 case SMA1303_36_PROTECTION ... SMA1303_37_SLOPE_CTRL: 205 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2: 206 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL: 207 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4: 208 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON: 209 result = true; 210 break; 211 default: 212 result = false; 213 break; 214 } 215 return result; 216 } 217 218 static bool sma1303_volatile_register(struct device *dev, unsigned int reg) 219 { 220 bool result; 221 222 switch (reg) { 223 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2: 224 result = true; 225 break; 226 case SMA1303_FF_DEVICE_INDEX: 227 result = true; 228 break; 229 default: 230 result = false; 231 break; 232 } 233 return result; 234 } 235 236 static const DECLARE_TLV_DB_SCALE(sma1303_spk_tlv, -6000, 50, 0); 237 238 static int sma1303_regmap_write(struct sma1303_priv *sma1303, 239 unsigned int reg, unsigned int val) 240 { 241 int ret = 0; 242 int cnt = sma1303->retry_cnt; 243 244 while (cnt--) { 245 ret = regmap_write(sma1303->regmap, reg, val); 246 if (ret < 0) { 247 dev_err(sma1303->dev, 248 "Failed to write [0x%02X]\n", reg); 249 } else 250 break; 251 } 252 return ret; 253 } 254 255 static int sma1303_regmap_update_bits(struct sma1303_priv *sma1303, 256 unsigned int reg, unsigned int mask, unsigned int val, bool *change) 257 { 258 int ret = 0; 259 int cnt = sma1303->retry_cnt; 260 261 while (cnt--) { 262 ret = regmap_update_bits_check(sma1303->regmap, reg, 263 mask, val, change); 264 if (ret < 0) { 265 dev_err(sma1303->dev, 266 "Failed to update [0x%02X]\n", reg); 267 } else 268 break; 269 } 270 return ret; 271 } 272 273 static int sma1303_regmap_read(struct sma1303_priv *sma1303, 274 unsigned int reg, unsigned int *val) 275 { 276 int ret = 0; 277 int cnt = sma1303->retry_cnt; 278 279 while (cnt--) { 280 ret = regmap_read(sma1303->regmap, reg, val); 281 if (ret < 0) { 282 dev_err(sma1303->dev, 283 "Failed to read [0x%02X]\n", reg); 284 } else 285 break; 286 } 287 return ret; 288 } 289 290 static const char * const sma1303_aif_in_source_text[] = { 291 "Mono", "Left", "Right"}; 292 static const char * const sma1303_aif_out_source_text[] = { 293 "Disable", "After_FmtC", "After_Mixer", "After_DSP", "After_Post", 294 "Clk_PLL", "Clk_OSC"}; 295 296 static const struct soc_enum sma1303_aif_in_source_enum = 297 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_in_source_text), 298 sma1303_aif_in_source_text); 299 static const struct soc_enum sma1303_aif_out_source_enum = 300 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_out_source_text), 301 sma1303_aif_out_source_text); 302 303 static int sma1303_force_mute_get(struct snd_kcontrol *kcontrol, 304 struct snd_ctl_elem_value *ucontrol) 305 { 306 struct snd_soc_component *component = 307 snd_soc_kcontrol_component(kcontrol); 308 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 309 310 ucontrol->value.integer.value[0] = (int)sma1303->force_mute_status; 311 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__, 312 sma1303->force_mute_status ? "ON" : "OFF"); 313 314 return 0; 315 } 316 317 static int sma1303_force_mute_put(struct snd_kcontrol *kcontrol, 318 struct snd_ctl_elem_value *ucontrol) 319 { 320 struct snd_soc_component *component = 321 snd_soc_kcontrol_component(kcontrol); 322 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 323 bool change = false, val = (bool)ucontrol->value.integer.value[0]; 324 325 if (sma1303->force_mute_status == val) 326 change = false; 327 else { 328 change = true; 329 sma1303->force_mute_status = val; 330 } 331 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__, 332 sma1303->force_mute_status ? "ON" : "OFF"); 333 334 return change; 335 } 336 337 static int sma1303_postscaler_get(struct snd_kcontrol *kcontrol, 338 struct snd_ctl_elem_value *ucontrol) 339 { 340 struct snd_soc_component *component = 341 snd_soc_kcontrol_component(kcontrol); 342 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 343 int val, ret; 344 345 ret = sma1303_regmap_read(sma1303, SMA1303_90_POSTSCALER, &val); 346 if (ret < 0) 347 return -EINVAL; 348 349 ucontrol->value.integer.value[0] = (val & 0x7E) >> 1; 350 351 return 0; 352 } 353 354 static int sma1303_postscaler_put(struct snd_kcontrol *kcontrol, 355 struct snd_ctl_elem_value *ucontrol) 356 { 357 struct snd_soc_component *component = 358 snd_soc_kcontrol_component(kcontrol); 359 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 360 int ret, val = (int)ucontrol->value.integer.value[0]; 361 bool change; 362 363 ret = sma1303_regmap_update_bits(sma1303, 364 SMA1303_90_POSTSCALER, 0x7E, (val << 1), &change); 365 if (ret < 0) 366 return -EINVAL; 367 368 return change; 369 } 370 371 static int sma1303_startup(struct snd_soc_component *component) 372 { 373 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 374 bool change = false, temp = false; 375 376 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL, 377 SMA1303_PLL_PD2_MASK, SMA1303_PLL_OPERATION2, &temp); 378 if (temp == true) 379 change = true; 380 381 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL, 382 SMA1303_POWER_MASK, SMA1303_POWER_ON, &temp); 383 if (temp == true) 384 change = true; 385 386 if (sma1303->amp_mode == SMA1303_MONO) { 387 sma1303_regmap_update_bits(sma1303, 388 SMA1303_10_SYSTEM_CTRL1, 389 SMA1303_SPK_MODE_MASK, 390 SMA1303_SPK_MONO, 391 &temp); 392 if (temp == true) 393 change = true; 394 395 } else { 396 sma1303_regmap_update_bits(sma1303, 397 SMA1303_10_SYSTEM_CTRL1, 398 SMA1303_SPK_MODE_MASK, 399 SMA1303_SPK_STEREO, 400 &temp); 401 if (temp == true) 402 change = true; 403 } 404 405 if (sma1303->check_fault_status) { 406 if (sma1303->check_fault_period > 0) 407 queue_delayed_work(system_freezable_wq, 408 &sma1303->check_fault_work, 409 sma1303->check_fault_period * HZ); 410 else 411 queue_delayed_work(system_freezable_wq, 412 &sma1303->check_fault_work, 413 CHECK_PERIOD_TIME * HZ); 414 } 415 416 sma1303->amp_power_status = true; 417 418 return change; 419 } 420 421 static int sma1303_shutdown(struct snd_soc_component *component) 422 { 423 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 424 bool change = false, temp = false; 425 426 cancel_delayed_work_sync(&sma1303->check_fault_work); 427 428 sma1303_regmap_update_bits(sma1303, SMA1303_10_SYSTEM_CTRL1, 429 SMA1303_SPK_MODE_MASK, SMA1303_SPK_OFF, &temp); 430 if (temp == true) 431 change = true; 432 433 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL, 434 SMA1303_POWER_MASK, SMA1303_POWER_OFF, &temp); 435 if (temp == true) 436 change = true; 437 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL, 438 SMA1303_PLL_PD2_MASK, SMA1303_PLL_PD2, &temp); 439 if (temp == true) 440 change = true; 441 442 sma1303->amp_power_status = false; 443 444 return change; 445 } 446 447 static int sma1303_aif_in_event(struct snd_soc_dapm_widget *w, 448 struct snd_kcontrol *kcontrol, int event) 449 { 450 struct snd_soc_component *component = 451 snd_soc_dapm_to_component(w->dapm); 452 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 453 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 454 int ret = 0; 455 bool change = false, temp = false; 456 457 switch (event) { 458 case SND_SOC_DAPM_PRE_PMU: 459 switch (mux) { 460 case 0: 461 ret += sma1303_regmap_update_bits(sma1303, 462 SMA1303_11_SYSTEM_CTRL2, 463 SMA1303_MONOMIX_MASK, 464 SMA1303_MONOMIX_ON, 465 &change); 466 sma1303->amp_mode = SMA1303_MONO; 467 break; 468 case 1: 469 ret += sma1303_regmap_update_bits(sma1303, 470 SMA1303_11_SYSTEM_CTRL2, 471 SMA1303_MONOMIX_MASK, 472 SMA1303_MONOMIX_OFF, 473 &temp); 474 if (temp == true) 475 change = true; 476 ret += sma1303_regmap_update_bits(sma1303, 477 SMA1303_11_SYSTEM_CTRL2, 478 SMA1303_LR_DATA_SW_MASK, 479 SMA1303_LR_DATA_SW_NORMAL, 480 &temp); 481 if (temp == true) 482 change = true; 483 sma1303->amp_mode = SMA1303_STEREO; 484 break; 485 case 2: 486 ret += sma1303_regmap_update_bits(sma1303, 487 SMA1303_11_SYSTEM_CTRL2, 488 SMA1303_MONOMIX_MASK, 489 SMA1303_MONOMIX_OFF, 490 &temp); 491 if (temp == true) 492 change = true; 493 ret += sma1303_regmap_update_bits(sma1303, 494 SMA1303_11_SYSTEM_CTRL2, 495 SMA1303_LR_DATA_SW_MASK, 496 SMA1303_LR_DATA_SW_NORMAL, 497 &temp); 498 if (temp == true) 499 change = true; 500 sma1303->amp_mode = SMA1303_STEREO; 501 break; 502 default: 503 dev_err(sma1303->dev, "%s : Invald value (%d)\n", 504 __func__, mux); 505 return -EINVAL; 506 } 507 508 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__, 509 sma1303_aif_in_source_text[mux]); 510 break; 511 } 512 if (ret < 0) 513 return -EINVAL; 514 return change; 515 } 516 517 static int sma1303_aif_out_event(struct snd_soc_dapm_widget *w, 518 struct snd_kcontrol *kcontrol, int event) 519 { 520 struct snd_soc_component *component = 521 snd_soc_dapm_to_component(w->dapm); 522 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 523 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 524 int ret = 0; 525 bool change = false, temp = false; 526 527 switch (event) { 528 case SND_SOC_DAPM_PRE_PMU: 529 switch (mux) { 530 case 0: 531 ret += sma1303_regmap_update_bits(sma1303, 532 SMA1303_A3_TOP_MAN2, 533 SMA1303_TEST_CLKO_EN_MASK, 534 SMA1303_NORMAL_SDO, 535 &temp); 536 if (temp == true) 537 change = true; 538 ret += sma1303_regmap_update_bits(sma1303, 539 SMA1303_09_OUTPUT_CTRL, 540 SMA1303_PORT_OUT_SEL_MASK, 541 SMA1303_OUT_SEL_DISABLE, 542 &temp); 543 if (temp == true) 544 change = true; 545 break; 546 case 1: 547 ret += sma1303_regmap_update_bits(sma1303, 548 SMA1303_A3_TOP_MAN2, 549 SMA1303_TEST_CLKO_EN_MASK, 550 SMA1303_NORMAL_SDO, 551 &temp); 552 if (temp == true) 553 change = true; 554 ret += sma1303_regmap_update_bits(sma1303, 555 SMA1303_09_OUTPUT_CTRL, 556 SMA1303_PORT_OUT_SEL_MASK, 557 SMA1303_FORMAT_CONVERTER, 558 &temp); 559 if (temp == true) 560 change = true; 561 break; 562 case 2: 563 ret += sma1303_regmap_update_bits(sma1303, 564 SMA1303_A3_TOP_MAN2, 565 SMA1303_TEST_CLKO_EN_MASK, 566 SMA1303_NORMAL_SDO, 567 &temp); 568 if (temp == true) 569 change = true; 570 ret += sma1303_regmap_update_bits(sma1303, 571 SMA1303_09_OUTPUT_CTRL, 572 SMA1303_PORT_OUT_SEL_MASK, 573 SMA1303_MIXER_OUTPUT, 574 &temp); 575 if (temp == true) 576 change = true; 577 break; 578 case 3: 579 ret += sma1303_regmap_update_bits(sma1303, 580 SMA1303_A3_TOP_MAN2, 581 SMA1303_TEST_CLKO_EN_MASK, 582 SMA1303_NORMAL_SDO, 583 &temp); 584 if (temp == true) 585 change = true; 586 ret += sma1303_regmap_update_bits(sma1303, 587 SMA1303_09_OUTPUT_CTRL, 588 SMA1303_PORT_OUT_SEL_MASK, 589 SMA1303_SPEAKER_PATH, 590 &temp); 591 if (temp == true) 592 change = true; 593 break; 594 case 4: 595 ret += sma1303_regmap_update_bits(sma1303, 596 SMA1303_A3_TOP_MAN2, 597 SMA1303_TEST_CLKO_EN_MASK, 598 SMA1303_NORMAL_SDO, 599 &temp); 600 if (temp == true) 601 change = true; 602 ret += sma1303_regmap_update_bits(sma1303, 603 SMA1303_09_OUTPUT_CTRL, 604 SMA1303_PORT_OUT_SEL_MASK, 605 SMA1303_POSTSCALER_OUTPUT, 606 &temp); 607 if (temp == true) 608 change = true; 609 break; 610 case 5: 611 ret += sma1303_regmap_update_bits(sma1303, 612 SMA1303_A3_TOP_MAN2, 613 SMA1303_TEST_CLKO_EN_MASK, 614 SMA1303_CLK_OUT_SDO, 615 &temp); 616 if (temp == true) 617 change = true; 618 ret += sma1303_regmap_update_bits(sma1303, 619 SMA1303_A3_TOP_MAN2, 620 SMA1303_MON_OSC_PLL_MASK, 621 SMA1303_PLL_SDO, 622 &temp); 623 if (temp == true) 624 change = true; 625 break; 626 case 6: 627 ret += sma1303_regmap_update_bits(sma1303, 628 SMA1303_A3_TOP_MAN2, 629 SMA1303_TEST_CLKO_EN_MASK, 630 SMA1303_CLK_OUT_SDO, 631 &temp); 632 if (temp == true) 633 change = true; 634 ret += sma1303_regmap_update_bits(sma1303, 635 SMA1303_A3_TOP_MAN2, 636 SMA1303_MON_OSC_PLL_MASK, 637 SMA1303_OSC_SDO, 638 &temp); 639 if (temp == true) 640 change = true; 641 break; 642 default: 643 dev_err(sma1303->dev, "%s : Invald value (%d)\n", 644 __func__, mux); 645 return -EINVAL; 646 } 647 648 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__, 649 sma1303_aif_out_source_text[mux]); 650 break; 651 } 652 if (ret < 0) 653 return -EINVAL; 654 return change; 655 } 656 657 static int sma1303_sdo_event(struct snd_soc_dapm_widget *w, 658 struct snd_kcontrol *kcontrol, int event) 659 { 660 struct snd_soc_component *component = 661 snd_soc_dapm_to_component(w->dapm); 662 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 663 int ret = 0; 664 bool change = false, temp = false; 665 666 switch (event) { 667 case SND_SOC_DAPM_PRE_PMU: 668 dev_dbg(sma1303->dev, 669 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__); 670 ret += sma1303_regmap_update_bits(sma1303, 671 SMA1303_09_OUTPUT_CTRL, 672 SMA1303_PORT_CONFIG_MASK, 673 SMA1303_OUTPUT_PORT_ENABLE, 674 &temp); 675 if (temp == true) 676 change = true; 677 ret += sma1303_regmap_update_bits(sma1303, 678 SMA1303_A3_TOP_MAN2, 679 SMA1303_SDO_OUTPUT_MASK, 680 SMA1303_NORMAL_OUT, 681 &temp); 682 if (temp == true) 683 change = true; 684 break; 685 case SND_SOC_DAPM_POST_PMD: 686 dev_dbg(sma1303->dev, 687 "%s : SND_SOC_DAPM_POST_PMD\n", __func__); 688 ret += sma1303_regmap_update_bits(sma1303, 689 SMA1303_09_OUTPUT_CTRL, 690 SMA1303_PORT_CONFIG_MASK, 691 SMA1303_INPUT_PORT_ONLY, 692 &temp); 693 if (temp == true) 694 change = true; 695 ret += sma1303_regmap_update_bits(sma1303, 696 SMA1303_A3_TOP_MAN2, 697 SMA1303_SDO_OUTPUT_MASK, 698 SMA1303_HIGH_Z_OUT, 699 &temp); 700 if (temp == true) 701 change = true; 702 break; 703 } 704 if (ret < 0) 705 return -EINVAL; 706 return change; 707 } 708 709 static int sma1303_post_scaler_event(struct snd_soc_dapm_widget *w, 710 struct snd_kcontrol *kcontrol, int event) 711 { 712 struct snd_soc_component *component = 713 snd_soc_dapm_to_component(w->dapm); 714 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 715 int ret = 0; 716 bool change = false; 717 718 switch (event) { 719 case SND_SOC_DAPM_PRE_PMU: 720 dev_dbg(sma1303->dev, 721 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__); 722 ret += sma1303_regmap_update_bits(sma1303, 723 SMA1303_90_POSTSCALER, 724 SMA1303_BYP_POST_MASK, 725 SMA1303_EN_POST_SCALER, 726 &change); 727 break; 728 case SND_SOC_DAPM_POST_PMD: 729 dev_dbg(sma1303->dev, 730 "%s : SND_SOC_DAPM_POST_PMD\n", __func__); 731 ret += sma1303_regmap_update_bits(sma1303, 732 SMA1303_90_POSTSCALER, 733 SMA1303_BYP_POST_MASK, 734 SMA1303_BYP_POST_SCALER, 735 &change); 736 break; 737 } 738 if (ret < 0) 739 return -EINVAL; 740 return change; 741 } 742 743 static int sma1303_power_event(struct snd_soc_dapm_widget *w, 744 struct snd_kcontrol *kcontrol, int event) 745 { 746 struct snd_soc_component *component = 747 snd_soc_dapm_to_component(w->dapm); 748 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 749 int ret = 0; 750 751 switch (event) { 752 case SND_SOC_DAPM_POST_PMU: 753 dev_dbg(sma1303->dev, 754 "%s : SND_SOC_DAPM_POST_PMU\n", __func__); 755 ret = sma1303_startup(component); 756 break; 757 case SND_SOC_DAPM_PRE_PMD: 758 dev_dbg(sma1303->dev, 759 "%s : SND_SOC_DAPM_PRE_PMD\n", __func__); 760 ret = sma1303_shutdown(component); 761 break; 762 } 763 return ret; 764 } 765 766 static const struct snd_kcontrol_new sma1303_aif_in_source_control = 767 SOC_DAPM_ENUM("AIF IN Source", sma1303_aif_in_source_enum); 768 static const struct snd_kcontrol_new sma1303_aif_out_source_control = 769 SOC_DAPM_ENUM("AIF OUT Source", sma1303_aif_out_source_enum); 770 static const struct snd_kcontrol_new sma1303_sdo_control = 771 SOC_DAPM_SINGLE_VIRT("Switch", 1); 772 static const struct snd_kcontrol_new sma1303_post_scaler_control = 773 SOC_DAPM_SINGLE_VIRT("Switch", 1); 774 static const struct snd_kcontrol_new sma1303_enable_control = 775 SOC_DAPM_SINGLE_VIRT("Switch", 1); 776 777 static const struct snd_kcontrol_new sma1303_snd_controls[] = { 778 SOC_SINGLE_TLV("Speaker Volume", SMA1303_0A_SPK_VOL, 779 0, 167, 1, sma1303_spk_tlv), 780 SOC_SINGLE_BOOL_EXT("Force Mute Switch", 0, 781 sma1303_force_mute_get, sma1303_force_mute_put), 782 SOC_SINGLE_EXT("Postscaler Gain", SMA1303_90_POSTSCALER, 1, 0x30, 0, 783 sma1303_postscaler_get, sma1303_postscaler_put), 784 }; 785 786 static const struct snd_soc_dapm_widget sma1303_dapm_widgets[] = { 787 /* platform domain */ 788 SND_SOC_DAPM_OUTPUT("SPK"), 789 SND_SOC_DAPM_INPUT("SDO"), 790 791 /* path domain */ 792 SND_SOC_DAPM_MUX_E("AIF IN Source", SND_SOC_NOPM, 0, 0, 793 &sma1303_aif_in_source_control, 794 sma1303_aif_in_event, 795 SND_SOC_DAPM_PRE_PMU), 796 SND_SOC_DAPM_MUX_E("AIF OUT Source", SND_SOC_NOPM, 0, 0, 797 &sma1303_aif_out_source_control, 798 sma1303_aif_out_event, 799 SND_SOC_DAPM_PRE_PMU), 800 SND_SOC_DAPM_SWITCH_E("SDO Enable", SND_SOC_NOPM, 0, 0, 801 &sma1303_sdo_control, 802 sma1303_sdo_event, 803 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 804 SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0), 805 SND_SOC_DAPM_SWITCH_E("Post Scaler", SND_SOC_NOPM, 0, 1, 806 &sma1303_post_scaler_control, 807 sma1303_post_scaler_event, 808 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 809 SND_SOC_DAPM_OUT_DRV_E("AMP Power", SND_SOC_NOPM, 0, 0, NULL, 0, 810 sma1303_power_event, 811 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 812 SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, 813 &sma1303_enable_control), 814 815 /* stream domain */ 816 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 817 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 818 }; 819 820 static const struct snd_soc_dapm_route sma1303_audio_map[] = { 821 /* Playback */ 822 {"AIF IN Source", "Mono", "AIF IN"}, 823 {"AIF IN Source", "Left", "AIF IN"}, 824 {"AIF IN Source", "Right", "AIF IN"}, 825 826 {"SDO Enable", "Switch", "AIF IN"}, 827 {"AIF OUT Source", "Disable", "SDO Enable"}, 828 {"AIF OUT Source", "After_FmtC", "SDO Enable"}, 829 {"AIF OUT Source", "After_Mixer", "SDO Enable"}, 830 {"AIF OUT Source", "After_DSP", "SDO Enable"}, 831 {"AIF OUT Source", "After_Post", "SDO Enable"}, 832 {"AIF OUT Source", "Clk_PLL", "SDO Enable"}, 833 {"AIF OUT Source", "Clk_OSC", "SDO Enable"}, 834 835 {"Entry", NULL, "AIF OUT Source"}, 836 {"Entry", NULL, "AIF IN Source"}, 837 838 {"Post Scaler", "Switch", "Entry"}, 839 {"AMP Power", NULL, "Entry"}, 840 {"AMP Power", NULL, "Entry"}, 841 842 {"AMP Enable", "Switch", "AMP Power"}, 843 {"SPK", NULL, "AMP Enable"}, 844 845 /* Capture */ 846 {"AIF OUT", NULL, "AMP Enable"}, 847 }; 848 849 static int sma1303_setup_pll(struct snd_soc_component *component, 850 unsigned int bclk) 851 { 852 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 853 854 int i = 0, ret = 0; 855 856 dev_dbg(component->dev, "%s : BCLK = %dHz\n", 857 __func__, bclk); 858 859 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_MCLK) { 860 dev_dbg(component->dev, "%s : MCLK is not supported\n", 861 __func__); 862 } else if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) { 863 for (i = 0; i < sma1303->num_of_pll_matches; i++) { 864 if (sma1303->pll_matches[i].input_clk == bclk) 865 break; 866 } 867 if (i == sma1303->num_of_pll_matches) { 868 dev_dbg(component->dev, "%s : No matching value between pll table and SCK\n", 869 __func__); 870 return -EINVAL; 871 } 872 873 ret += sma1303_regmap_update_bits(sma1303, 874 SMA1303_A2_TOP_MAN1, 875 SMA1303_PLL_PD_MASK|SMA1303_PLL_REF_CLK_MASK, 876 SMA1303_PLL_OPERATION|SMA1303_PLL_SCK, 877 NULL); 878 } 879 880 ret += sma1303_regmap_write(sma1303, 881 SMA1303_8B_PLL_POST_N, 882 sma1303->pll_matches[i].post_n); 883 884 ret += sma1303_regmap_write(sma1303, 885 SMA1303_8C_PLL_N, 886 sma1303->pll_matches[i].n); 887 888 ret += sma1303_regmap_write(sma1303, 889 SMA1303_8D_PLL_A_SETTING, 890 sma1303->pll_matches[i].vco); 891 892 ret += sma1303_regmap_write(sma1303, 893 SMA1303_8F_PLL_P_CP, 894 sma1303->pll_matches[i].p_cp); 895 if (ret < 0) 896 return -EINVAL; 897 898 return 0; 899 } 900 901 static int sma1303_dai_hw_params_amp(struct snd_pcm_substream *substream, 902 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 903 { 904 struct snd_soc_component *component = dai->component; 905 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 906 unsigned int bclk = 0; 907 int ret = 0; 908 909 if (sma1303->format == SND_SOC_DAIFMT_DSP_A) 910 bclk = params_rate(params) * sma1303->frame_size; 911 else 912 bclk = params_rate(params) * params_physical_width(params) 913 * params_channels(params); 914 915 dev_dbg(component->dev, 916 "%s : rate = %d : bit size = %d : channel = %d\n", 917 __func__, params_rate(params), params_width(params), 918 params_channels(params)); 919 920 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 921 922 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_MCLK 923 || sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) { 924 925 if (sma1303->last_bclk != bclk) { 926 sma1303_setup_pll(component, bclk); 927 sma1303->last_bclk = bclk; 928 } 929 } 930 931 switch (params_rate(params)) { 932 case 8000: 933 case 12000: 934 case 16000: 935 case 24000: 936 case 32000: 937 case 44100: 938 case 48000: 939 case 96000: 940 ret += sma1303_regmap_update_bits(sma1303, 941 SMA1303_A2_TOP_MAN1, 942 SMA1303_DAC_DN_CONV_MASK, 943 SMA1303_DAC_DN_CONV_DISABLE, 944 NULL); 945 946 ret += sma1303_regmap_update_bits(sma1303, 947 SMA1303_01_INPUT1_CTRL1, 948 SMA1303_LEFTPOL_MASK, 949 SMA1303_LOW_FIRST_CH, 950 NULL); 951 break; 952 953 case 192000: 954 ret += sma1303_regmap_update_bits(sma1303, 955 SMA1303_A2_TOP_MAN1, 956 SMA1303_DAC_DN_CONV_MASK, 957 SMA1303_DAC_DN_CONV_ENABLE, 958 NULL); 959 960 ret += sma1303_regmap_update_bits(sma1303, 961 SMA1303_01_INPUT1_CTRL1, 962 SMA1303_LEFTPOL_MASK, 963 SMA1303_HIGH_FIRST_CH, 964 NULL); 965 break; 966 967 default: 968 dev_err(component->dev, "%s not support rate : %d\n", 969 __func__, params_rate(params)); 970 971 return -EINVAL; 972 } 973 974 } else { 975 976 switch (params_format(params)) { 977 978 case SNDRV_PCM_FORMAT_S16_LE: 979 dev_dbg(component->dev, 980 "%s set format SNDRV_PCM_FORMAT_S16_LE\n", 981 __func__); 982 ret += sma1303_regmap_update_bits(sma1303, 983 SMA1303_A4_TOP_MAN3, 984 SMA1303_SCK_RATE_MASK, 985 SMA1303_SCK_32FS, 986 NULL); 987 break; 988 989 case SNDRV_PCM_FORMAT_S24_LE: 990 dev_dbg(component->dev, 991 "%s set format SNDRV_PCM_FORMAT_S24_LE\n", 992 __func__); 993 ret += sma1303_regmap_update_bits(sma1303, 994 SMA1303_A4_TOP_MAN3, 995 SMA1303_SCK_RATE_MASK, 996 SMA1303_SCK_64FS, 997 NULL); 998 break; 999 case SNDRV_PCM_FORMAT_S32_LE: 1000 dev_dbg(component->dev, 1001 "%s set format SNDRV_PCM_FORMAT_S32_LE\n", 1002 __func__); 1003 ret += sma1303_regmap_update_bits(sma1303, 1004 SMA1303_A4_TOP_MAN3, 1005 SMA1303_SCK_RATE_MASK, 1006 SMA1303_SCK_64FS, 1007 NULL); 1008 break; 1009 default: 1010 dev_err(component->dev, 1011 "%s not support data bit : %d\n", __func__, 1012 params_format(params)); 1013 return -EINVAL; 1014 } 1015 } 1016 1017 switch (sma1303->format) { 1018 case SND_SOC_DAIFMT_I2S: 1019 ret += sma1303_regmap_update_bits(sma1303, 1020 SMA1303_01_INPUT1_CTRL1, 1021 SMA1303_I2S_MODE_MASK, 1022 SMA1303_STANDARD_I2S, 1023 NULL); 1024 ret += sma1303_regmap_update_bits(sma1303, 1025 SMA1303_A4_TOP_MAN3, 1026 SMA1303_O_FORMAT_MASK, 1027 SMA1303_O_FMT_I2S, 1028 NULL); 1029 break; 1030 case SND_SOC_DAIFMT_LEFT_J: 1031 ret += sma1303_regmap_update_bits(sma1303, 1032 SMA1303_01_INPUT1_CTRL1, 1033 SMA1303_I2S_MODE_MASK, 1034 SMA1303_LJ, 1035 NULL); 1036 ret += sma1303_regmap_update_bits(sma1303, 1037 SMA1303_A4_TOP_MAN3, 1038 SMA1303_O_FORMAT_MASK, 1039 SMA1303_O_FMT_LJ, 1040 NULL); 1041 break; 1042 case SND_SOC_DAIFMT_RIGHT_J: 1043 switch (params_width(params)) { 1044 case 16: 1045 ret += sma1303_regmap_update_bits(sma1303, 1046 SMA1303_01_INPUT1_CTRL1, 1047 SMA1303_I2S_MODE_MASK, 1048 SMA1303_RJ_16BIT, 1049 NULL); 1050 break; 1051 case 24: 1052 case 32: 1053 ret += sma1303_regmap_update_bits(sma1303, 1054 SMA1303_01_INPUT1_CTRL1, 1055 SMA1303_I2S_MODE_MASK, 1056 SMA1303_RJ_24BIT, 1057 NULL); 1058 break; 1059 } 1060 break; 1061 case SND_SOC_DAIFMT_DSP_A: 1062 ret += sma1303_regmap_update_bits(sma1303, 1063 SMA1303_01_INPUT1_CTRL1, 1064 SMA1303_I2S_MODE_MASK, 1065 SMA1303_STANDARD_I2S, 1066 NULL); 1067 ret += sma1303_regmap_update_bits(sma1303, 1068 SMA1303_A4_TOP_MAN3, 1069 SMA1303_O_FORMAT_MASK, 1070 SMA1303_O_FMT_TDM, 1071 NULL); 1072 break; 1073 } 1074 1075 switch (params_width(params)) { 1076 case 16: 1077 case 24: 1078 case 32: 1079 break; 1080 default: 1081 dev_err(component->dev, 1082 "%s not support data bit : %d\n", __func__, 1083 params_format(params)); 1084 return -EINVAL; 1085 } 1086 if (ret < 0) 1087 return -EINVAL; 1088 1089 return 0; 1090 } 1091 1092 static int sma1303_dai_set_sysclk_amp(struct snd_soc_dai *dai, 1093 int clk_id, unsigned int freq, int dir) 1094 { 1095 struct snd_soc_component *component = dai->component; 1096 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1097 1098 switch (clk_id) { 1099 case SMA1303_EXTERNAL_CLOCK_19_2: 1100 break; 1101 case SMA1303_EXTERNAL_CLOCK_24_576: 1102 break; 1103 case SMA1303_PLL_CLKIN_MCLK: 1104 break; 1105 case SMA1303_PLL_CLKIN_BCLK: 1106 break; 1107 default: 1108 dev_err(component->dev, "Invalid clk id: %d\n", clk_id); 1109 return -EINVAL; 1110 } 1111 sma1303->sys_clk_id = clk_id; 1112 return 0; 1113 } 1114 1115 static int sma1303_dai_mute(struct snd_soc_dai *dai, int mute, int stream) 1116 { 1117 struct snd_soc_component *component = dai->component; 1118 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1119 int ret = 0; 1120 1121 if (stream == SNDRV_PCM_STREAM_CAPTURE) 1122 return ret; 1123 1124 if (mute) { 1125 dev_dbg(component->dev, "%s : %s\n", __func__, "MUTE"); 1126 1127 ret += sma1303_regmap_update_bits(sma1303, 1128 SMA1303_0E_MUTE_VOL_CTRL, 1129 SMA1303_SPK_MUTE_MASK, 1130 SMA1303_SPK_MUTE, 1131 NULL); 1132 1133 /* Need to wait time for mute slope */ 1134 msleep(55); 1135 } else { 1136 if (!sma1303->force_mute_status) { 1137 dev_dbg(component->dev, "%s : %s\n", 1138 __func__, "UNMUTE"); 1139 ret += sma1303_regmap_update_bits(sma1303, 1140 SMA1303_0E_MUTE_VOL_CTRL, 1141 SMA1303_SPK_MUTE_MASK, 1142 SMA1303_SPK_UNMUTE, 1143 NULL); 1144 } else { 1145 dev_dbg(sma1303->dev, 1146 "%s : FORCE MUTE!!!\n", __func__); 1147 } 1148 } 1149 1150 if (ret < 0) 1151 return -EINVAL; 1152 return 0; 1153 } 1154 1155 static int sma1303_dai_set_fmt_amp(struct snd_soc_dai *dai, 1156 unsigned int fmt) 1157 { 1158 struct snd_soc_component *component = dai->component; 1159 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1160 int ret = 0; 1161 1162 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1163 1164 case SND_SOC_DAIFMT_CBC_CFC: 1165 dev_dbg(component->dev, 1166 "%s : %s\n", __func__, "I2S/TDM Device mode"); 1167 ret += sma1303_regmap_update_bits(sma1303, 1168 SMA1303_01_INPUT1_CTRL1, 1169 SMA1303_CONTROLLER_DEVICE_MASK, 1170 SMA1303_DEVICE_MODE, 1171 NULL); 1172 break; 1173 1174 case SND_SOC_DAIFMT_CBP_CFP: 1175 dev_dbg(component->dev, 1176 "%s : %s\n", __func__, "I2S/TDM Controller mode"); 1177 ret += sma1303_regmap_update_bits(sma1303, 1178 SMA1303_01_INPUT1_CTRL1, 1179 SMA1303_CONTROLLER_DEVICE_MASK, 1180 SMA1303_CONTROLLER_MODE, 1181 NULL); 1182 break; 1183 1184 default: 1185 dev_err(component->dev, 1186 "Unsupported Controller/Device : 0x%x\n", fmt); 1187 return -EINVAL; 1188 } 1189 1190 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1191 1192 case SND_SOC_DAIFMT_I2S: 1193 case SND_SOC_DAIFMT_RIGHT_J: 1194 case SND_SOC_DAIFMT_LEFT_J: 1195 case SND_SOC_DAIFMT_DSP_A: 1196 case SND_SOC_DAIFMT_DSP_B: 1197 sma1303->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1198 break; 1199 default: 1200 dev_err(component->dev, 1201 "Unsupported Audio Interface Format : 0x%x\n", fmt); 1202 return -EINVAL; 1203 } 1204 1205 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1206 1207 case SND_SOC_DAIFMT_IB_NF: 1208 dev_dbg(component->dev, "%s : %s\n", 1209 __func__, "Invert BCLK + Normal Frame"); 1210 ret += sma1303_regmap_update_bits(sma1303, 1211 SMA1303_01_INPUT1_CTRL1, 1212 SMA1303_SCK_RISING_MASK, 1213 SMA1303_SCK_RISING_EDGE, 1214 NULL); 1215 break; 1216 case SND_SOC_DAIFMT_IB_IF: 1217 dev_dbg(component->dev, "%s : %s\n", 1218 __func__, "Invert BCLK + Invert Frame"); 1219 ret += sma1303_regmap_update_bits(sma1303, 1220 SMA1303_01_INPUT1_CTRL1, 1221 SMA1303_LEFTPOL_MASK|SMA1303_SCK_RISING_MASK, 1222 SMA1303_HIGH_FIRST_CH|SMA1303_SCK_RISING_EDGE, 1223 NULL); 1224 break; 1225 case SND_SOC_DAIFMT_NB_IF: 1226 dev_dbg(component->dev, "%s : %s\n", 1227 __func__, "Normal BCLK + Invert Frame"); 1228 ret += sma1303_regmap_update_bits(sma1303, 1229 SMA1303_01_INPUT1_CTRL1, 1230 SMA1303_LEFTPOL_MASK, 1231 SMA1303_HIGH_FIRST_CH, 1232 NULL); 1233 break; 1234 case SND_SOC_DAIFMT_NB_NF: 1235 dev_dbg(component->dev, "%s : %s\n", 1236 __func__, "Normal BCLK + Normal Frame"); 1237 break; 1238 default: 1239 dev_err(component->dev, 1240 "Unsupported Bit & Frameclock : 0x%x\n", fmt); 1241 return -EINVAL; 1242 } 1243 1244 if (ret < 0) 1245 return -EINVAL; 1246 return 0; 1247 } 1248 1249 static int sma1303_dai_set_tdm_slot(struct snd_soc_dai *dai, 1250 unsigned int tx_mask, unsigned int rx_mask, 1251 int slots, int slot_width) 1252 { 1253 struct snd_soc_component *component = dai->component; 1254 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1255 int ret = 0; 1256 1257 dev_dbg(component->dev, "%s : slots = %d, slot_width - %d\n", 1258 __func__, slots, slot_width); 1259 1260 sma1303->frame_size = slot_width * slots; 1261 1262 ret += sma1303_regmap_update_bits(sma1303, 1263 SMA1303_A4_TOP_MAN3, 1264 SMA1303_O_FORMAT_MASK, 1265 SMA1303_O_FMT_TDM, 1266 NULL); 1267 1268 switch (slot_width) { 1269 case 16: 1270 ret += sma1303_regmap_update_bits(sma1303, 1271 SMA1303_A6_TDM2, 1272 SMA1303_TDM_DL_MASK, 1273 SMA1303_TDM_DL_16, 1274 NULL); 1275 break; 1276 case 32: 1277 ret += sma1303_regmap_update_bits(sma1303, 1278 SMA1303_A6_TDM2, 1279 SMA1303_TDM_DL_MASK, 1280 SMA1303_TDM_DL_32, 1281 NULL); 1282 break; 1283 default: 1284 dev_err(component->dev, "%s not support TDM %d slot_width\n", 1285 __func__, slot_width); 1286 break; 1287 } 1288 1289 switch (slots) { 1290 case 4: 1291 ret += sma1303_regmap_update_bits(sma1303, 1292 SMA1303_A6_TDM2, 1293 SMA1303_TDM_N_SLOT_MASK, 1294 SMA1303_TDM_N_SLOT_4, 1295 NULL); 1296 break; 1297 case 8: 1298 ret += sma1303_regmap_update_bits(sma1303, 1299 SMA1303_A6_TDM2, 1300 SMA1303_TDM_N_SLOT_MASK, 1301 SMA1303_TDM_N_SLOT_8, 1302 NULL); 1303 break; 1304 default: 1305 dev_err(component->dev, "%s not support TDM %d slots\n", 1306 __func__, slots); 1307 break; 1308 } 1309 1310 if (sma1303->tdm_slot_rx < slots) 1311 ret += sma1303_regmap_update_bits(sma1303, 1312 SMA1303_A5_TDM1, 1313 SMA1303_TDM_SLOT1_RX_POS_MASK, 1314 (sma1303->tdm_slot_rx) << 3, 1315 NULL); 1316 else 1317 dev_err(component->dev, "%s Incorrect tdm-slot-rx %d set\n", 1318 __func__, sma1303->tdm_slot_rx); 1319 1320 ret += sma1303_regmap_update_bits(sma1303, 1321 SMA1303_A5_TDM1, 1322 SMA1303_TDM_CLK_POL_MASK, 1323 SMA1303_TDM_CLK_POL_RISE, 1324 NULL); 1325 1326 ret += sma1303_regmap_update_bits(sma1303, 1327 SMA1303_A5_TDM1, 1328 SMA1303_TDM_TX_MODE_MASK, 1329 SMA1303_TDM_TX_MONO, 1330 NULL); 1331 1332 if (sma1303->tdm_slot_tx < slots) 1333 ret += sma1303_regmap_update_bits(sma1303, 1334 SMA1303_A6_TDM2, 1335 SMA1303_TDM_SLOT1_TX_POS_MASK, 1336 (sma1303->tdm_slot_tx) << 3, 1337 NULL); 1338 else 1339 dev_err(component->dev, "%s Incorrect tdm-slot-tx %d set\n", 1340 __func__, sma1303->tdm_slot_tx); 1341 1342 if (ret < 0) 1343 return -EINVAL; 1344 return 0; 1345 } 1346 1347 static const struct snd_soc_dai_ops sma1303_dai_ops_amp = { 1348 .set_sysclk = sma1303_dai_set_sysclk_amp, 1349 .set_fmt = sma1303_dai_set_fmt_amp, 1350 .hw_params = sma1303_dai_hw_params_amp, 1351 .mute_stream = sma1303_dai_mute, 1352 .set_tdm_slot = sma1303_dai_set_tdm_slot, 1353 }; 1354 1355 #define SMA1303_RATES SNDRV_PCM_RATE_8000_192000 1356 #define SMA1303_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1357 SNDRV_PCM_FMTBIT_S32_LE) 1358 1359 static struct snd_soc_dai_driver sma1303_dai[] = { 1360 { 1361 .name = "sma1303-amplifier", 1362 .id = 0, 1363 .playback = { 1364 .stream_name = "Playback", 1365 .channels_min = 1, 1366 .channels_max = 2, 1367 .rates = SMA1303_RATES, 1368 .formats = SMA1303_FORMATS, 1369 }, 1370 .capture = { 1371 .stream_name = "Capture", 1372 .channels_min = 1, 1373 .channels_max = 2, 1374 .rates = SMA1303_RATES, 1375 .formats = SMA1303_FORMATS, 1376 }, 1377 .ops = &sma1303_dai_ops_amp, 1378 }, 1379 }; 1380 1381 static void sma1303_check_fault_worker(struct work_struct *work) 1382 { 1383 struct sma1303_priv *sma1303 = 1384 container_of(work, struct sma1303_priv, check_fault_work.work); 1385 int ret = 0; 1386 unsigned int over_temp, ocp_val, uvlo_val; 1387 1388 if (sma1303->tsdw_cnt) 1389 ret = sma1303_regmap_read(sma1303, 1390 SMA1303_0A_SPK_VOL, &sma1303->cur_vol); 1391 else 1392 ret = sma1303_regmap_read(sma1303, 1393 SMA1303_0A_SPK_VOL, &sma1303->init_vol); 1394 1395 if (ret != 0) { 1396 dev_err(sma1303->dev, 1397 "failed to read SMA1303_0A_SPK_VOL : %d\n", ret); 1398 return; 1399 } 1400 1401 ret = sma1303_regmap_read(sma1303, SMA1303_FA_STATUS1, &over_temp); 1402 if (ret != 0) { 1403 dev_err(sma1303->dev, 1404 "failed to read SMA1303_FA_STATUS1 : %d\n", ret); 1405 return; 1406 } 1407 1408 ret = sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &ocp_val); 1409 if (ret != 0) { 1410 dev_err(sma1303->dev, 1411 "failed to read SMA1303_FB_STATUS2 : %d\n", ret); 1412 return; 1413 } 1414 1415 ret = sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &uvlo_val); 1416 if (ret != 0) { 1417 dev_err(sma1303->dev, 1418 "failed to read SMA1303_FF_DEVICE_INDEX : %d\n", ret); 1419 return; 1420 } 1421 1422 if (~over_temp & SMA1303_OT1_OK_STATUS) { 1423 dev_crit(sma1303->dev, 1424 "%s : OT1(Over Temperature Level 1)\n", __func__); 1425 1426 if ((sma1303->cur_vol + 6) <= 0xFF) 1427 sma1303_regmap_write(sma1303, 1428 SMA1303_0A_SPK_VOL, sma1303->cur_vol + 6); 1429 1430 sma1303->tsdw_cnt++; 1431 } else if (sma1303->tsdw_cnt) { 1432 sma1303_regmap_write(sma1303, 1433 SMA1303_0A_SPK_VOL, sma1303->init_vol); 1434 sma1303->tsdw_cnt = 0; 1435 sma1303->cur_vol = sma1303->init_vol; 1436 } 1437 1438 if (~over_temp & SMA1303_OT2_OK_STATUS) { 1439 dev_crit(sma1303->dev, 1440 "%s : OT2(Over Temperature Level 2)\n", __func__); 1441 } 1442 if (ocp_val & SMA1303_OCP_SPK_STATUS) { 1443 dev_crit(sma1303->dev, 1444 "%s : OCP_SPK(Over Current Protect SPK)\n", __func__); 1445 } 1446 if (ocp_val & SMA1303_OCP_BST_STATUS) { 1447 dev_crit(sma1303->dev, 1448 "%s : OCP_BST(Over Current Protect Boost)\n", __func__); 1449 } 1450 if ((ocp_val & SMA1303_CLK_MON_STATUS) && (sma1303->amp_power_status)) { 1451 dev_crit(sma1303->dev, 1452 "%s : CLK_FAULT(No clock input)\n", __func__); 1453 } 1454 if (uvlo_val & SMA1303_UVLO_BST_STATUS) { 1455 dev_crit(sma1303->dev, 1456 "%s : UVLO(Under Voltage Lock Out)\n", __func__); 1457 } 1458 1459 if ((over_temp != sma1303->last_over_temp) || 1460 (ocp_val != sma1303->last_ocp_val)) { 1461 1462 dev_crit(sma1303->dev, "Please check AMP status"); 1463 dev_dbg(sma1303->dev, "STATUS1=0x%02X : STATUS2=0x%02X\n", 1464 over_temp, ocp_val); 1465 sma1303->last_over_temp = over_temp; 1466 sma1303->last_ocp_val = ocp_val; 1467 } 1468 1469 if (sma1303->check_fault_status) { 1470 if (sma1303->check_fault_period > 0) 1471 queue_delayed_work(system_freezable_wq, 1472 &sma1303->check_fault_work, 1473 sma1303->check_fault_period * HZ); 1474 else 1475 queue_delayed_work(system_freezable_wq, 1476 &sma1303->check_fault_work, 1477 CHECK_PERIOD_TIME * HZ); 1478 } 1479 1480 if (!(~over_temp & SMA1303_OT1_OK_STATUS) 1481 && !(~over_temp & SMA1303_OT2_OK_STATUS) 1482 && !(ocp_val & SMA1303_OCP_SPK_STATUS) 1483 && !(ocp_val & SMA1303_OCP_BST_STATUS) 1484 && !(ocp_val & SMA1303_CLK_MON_STATUS) 1485 && !(uvlo_val & SMA1303_UVLO_BST_STATUS)) { 1486 } 1487 } 1488 1489 static int sma1303_probe(struct snd_soc_component *component) 1490 { 1491 struct snd_soc_dapm_context *dapm = 1492 snd_soc_component_get_dapm(component); 1493 1494 snd_soc_dapm_sync(dapm); 1495 1496 return 0; 1497 } 1498 1499 static void sma1303_remove(struct snd_soc_component *component) 1500 { 1501 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1502 1503 cancel_delayed_work_sync(&sma1303->check_fault_work); 1504 } 1505 1506 static const struct snd_soc_component_driver sma1303_component = { 1507 .probe = sma1303_probe, 1508 .remove = sma1303_remove, 1509 .controls = sma1303_snd_controls, 1510 .num_controls = ARRAY_SIZE(sma1303_snd_controls), 1511 .dapm_widgets = sma1303_dapm_widgets, 1512 .num_dapm_widgets = ARRAY_SIZE(sma1303_dapm_widgets), 1513 .dapm_routes = sma1303_audio_map, 1514 .num_dapm_routes = ARRAY_SIZE(sma1303_audio_map), 1515 }; 1516 1517 const struct regmap_config sma_i2c_regmap = { 1518 .reg_bits = 8, 1519 .val_bits = 8, 1520 1521 .max_register = SMA1303_FF_DEVICE_INDEX, 1522 .readable_reg = sma1303_readable_register, 1523 .writeable_reg = sma1303_writeable_register, 1524 .volatile_reg = sma1303_volatile_register, 1525 1526 .cache_type = REGCACHE_NONE, 1527 .reg_defaults = sma1303_reg_def, 1528 .num_reg_defaults = ARRAY_SIZE(sma1303_reg_def), 1529 }; 1530 1531 static ssize_t check_fault_period_show(struct device *dev, 1532 struct device_attribute *devattr, char *buf) 1533 { 1534 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1535 1536 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_period); 1537 } 1538 1539 static ssize_t check_fault_period_store(struct device *dev, 1540 struct device_attribute *devattr, const char *buf, size_t count) 1541 { 1542 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1543 int ret; 1544 1545 ret = kstrtol(buf, 10, &sma1303->check_fault_period); 1546 1547 if (ret) 1548 return -EINVAL; 1549 1550 return (ssize_t)count; 1551 } 1552 1553 static DEVICE_ATTR_RW(check_fault_period); 1554 1555 static ssize_t check_fault_status_show(struct device *dev, 1556 struct device_attribute *devattr, char *buf) 1557 { 1558 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1559 1560 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_status); 1561 } 1562 1563 static ssize_t check_fault_status_store(struct device *dev, 1564 struct device_attribute *devattr, const char *buf, size_t count) 1565 { 1566 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1567 int ret; 1568 1569 ret = kstrtol(buf, 10, &sma1303->check_fault_status); 1570 1571 if (ret) 1572 return -EINVAL; 1573 1574 if (sma1303->check_fault_status) { 1575 if (sma1303->check_fault_period > 0) 1576 queue_delayed_work(system_freezable_wq, 1577 &sma1303->check_fault_work, 1578 sma1303->check_fault_period * HZ); 1579 else 1580 queue_delayed_work(system_freezable_wq, 1581 &sma1303->check_fault_work, 1582 CHECK_PERIOD_TIME * HZ); 1583 } 1584 1585 return (ssize_t)count; 1586 } 1587 1588 static DEVICE_ATTR_RW(check_fault_status); 1589 1590 static struct attribute *sma1303_attr[] = { 1591 &dev_attr_check_fault_period.attr, 1592 &dev_attr_check_fault_status.attr, 1593 NULL, 1594 }; 1595 1596 static struct attribute_group sma1303_attr_group = { 1597 .attrs = sma1303_attr, 1598 }; 1599 1600 static int sma1303_i2c_probe(struct i2c_client *client, 1601 const struct i2c_device_id *id) 1602 { 1603 struct sma1303_priv *sma1303; 1604 struct device_node *np = client->dev.of_node; 1605 int ret, i = 0; 1606 u32 value = 0; 1607 unsigned int device_info, status, otp_stat; 1608 1609 sma1303 = devm_kzalloc(&client->dev, 1610 sizeof(struct sma1303_priv), GFP_KERNEL); 1611 if (!sma1303) 1612 return -ENOMEM; 1613 sma1303->dev = &client->dev; 1614 1615 sma1303->regmap = devm_regmap_init_i2c(client, &sma_i2c_regmap); 1616 if (IS_ERR(sma1303->regmap)) { 1617 ret = PTR_ERR(sma1303->regmap); 1618 dev_err(&client->dev, 1619 "Failed to allocate register map: %d\n", ret); 1620 1621 return ret; 1622 } 1623 1624 if (np) { 1625 if (!of_property_read_u32(np, "i2c-retry", &value)) { 1626 if (value > 50 || value <= 0) { 1627 sma1303->retry_cnt = SMA1303_I2C_RETRY_COUNT; 1628 dev_dbg(&client->dev, "%s : %s\n", __func__, 1629 "i2c-retry out of range (up to 50)"); 1630 } else { 1631 sma1303->retry_cnt = value; 1632 dev_dbg(&client->dev, "%s : %s = %u\n", 1633 __func__, "i2c-retry count", value); 1634 } 1635 } else { 1636 dev_dbg(&client->dev, "%s : %s = %d\n", __func__, 1637 "i2c-retry count", SMA1303_I2C_RETRY_COUNT); 1638 sma1303->retry_cnt = SMA1303_I2C_RETRY_COUNT; 1639 } 1640 if (!of_property_read_u32(np, "tdm-slot-rx", &value)) { 1641 dev_dbg(&client->dev, 1642 "tdm slot rx is '%d' from DT\n", value); 1643 sma1303->tdm_slot_rx = value; 1644 } else { 1645 dev_dbg(&client->dev, 1646 "Default setting of tdm slot rx is '0'\n"); 1647 sma1303->tdm_slot_rx = 0; 1648 } 1649 if (!of_property_read_u32(np, "tdm-slot-tx", &value)) { 1650 dev_dbg(&client->dev, 1651 "tdm slot tx is '%u' from DT\n", value); 1652 sma1303->tdm_slot_tx = value; 1653 } else { 1654 dev_dbg(&client->dev, 1655 "Default setting of tdm slot tx is '0'\n"); 1656 sma1303->tdm_slot_tx = 0; 1657 } 1658 if (!of_property_read_u32(np, "sys-clk-id", &value)) { 1659 switch (value) { 1660 case SMA1303_EXTERNAL_CLOCK_19_2: 1661 case SMA1303_EXTERNAL_CLOCK_24_576: 1662 case SMA1303_PLL_CLKIN_MCLK: 1663 dev_dbg(&client->dev, "MCLK is not supported\n"); 1664 break; 1665 case SMA1303_PLL_CLKIN_BCLK: 1666 dev_dbg(&client->dev, 1667 "Take an BCLK(SCK) and covert it to an internal PLL for use\n"); 1668 break; 1669 default: 1670 dev_err(&client->dev, 1671 "Invalid sys-clk-id: %u\n", value); 1672 return -EINVAL; 1673 } 1674 sma1303->sys_clk_id = value; 1675 } else { 1676 dev_dbg(&client->dev, "Use the internal PLL clock by default\n"); 1677 sma1303->sys_clk_id = SMA1303_PLL_CLKIN_BCLK; 1678 } 1679 } else { 1680 dev_err(&client->dev, 1681 "device node initialization error\n"); 1682 devm_kfree(&client->dev, sma1303); 1683 return -ENODEV; 1684 } 1685 1686 ret = sma1303_regmap_read(sma1303, 1687 SMA1303_FF_DEVICE_INDEX, &device_info); 1688 1689 if ((ret != 0) || ((device_info & 0xF8) != SMA1303_DEVICE_ID)) { 1690 dev_err(&client->dev, "device initialization error (%d 0x%02X)", 1691 ret, device_info); 1692 } 1693 dev_dbg(&client->dev, "chip version 0x%02X\n", device_info); 1694 1695 ret += sma1303_regmap_update_bits(sma1303, 1696 SMA1303_00_SYSTEM_CTRL, 1697 SMA1303_RESETBYI2C_MASK, SMA1303_RESETBYI2C_RESET, 1698 NULL); 1699 1700 ret += sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &status); 1701 sma1303->rev_num = status & SMA1303_REV_NUM_STATUS; 1702 if (sma1303->rev_num == SMA1303_REV_NUM_TV0) 1703 dev_dbg(&client->dev, "SMA1303 Trimming Version 0\n"); 1704 else if (sma1303->rev_num == SMA1303_REV_NUM_TV1) 1705 dev_dbg(&client->dev, "SMA1303 Trimming Version 1\n"); 1706 1707 ret += sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &otp_stat); 1708 if (ret < 0) 1709 dev_err(&client->dev, 1710 "failed to read, register: %02X, ret: %d\n", 1711 SMA1303_FF_DEVICE_INDEX, ret); 1712 1713 if (((sma1303->rev_num == SMA1303_REV_NUM_TV0) && 1714 ((otp_stat & 0x0E) == SMA1303_OTP_STAT_OK_0)) || 1715 ((sma1303->rev_num != SMA1303_REV_NUM_TV0) && 1716 ((otp_stat & 0x0C) == SMA1303_OTP_STAT_OK_1))) 1717 dev_dbg(&client->dev, "SMA1303 OTP Status Successful\n"); 1718 else 1719 dev_dbg(&client->dev, "SMA1303 OTP Status Fail\n"); 1720 1721 for (i = 0; i < (unsigned int)ARRAY_SIZE(sma1303_reg_def); i++) 1722 ret += sma1303_regmap_write(sma1303, 1723 sma1303_reg_def[i].reg, 1724 sma1303_reg_def[i].def); 1725 1726 sma1303->amp_mode = SMA1303_MONO; 1727 sma1303->amp_power_status = false; 1728 sma1303->check_fault_period = CHECK_PERIOD_TIME; 1729 sma1303->check_fault_status = true; 1730 sma1303->force_mute_status = false; 1731 sma1303->init_vol = 0x31; 1732 sma1303->cur_vol = sma1303->init_vol; 1733 sma1303->last_bclk = 0; 1734 sma1303->last_ocp_val = 0x08; 1735 sma1303->last_over_temp = 0xC0; 1736 sma1303->tsdw_cnt = 0; 1737 1738 sma1303->dev = &client->dev; 1739 sma1303->kobj = &client->dev.kobj; 1740 1741 INIT_DELAYED_WORK(&sma1303->check_fault_work, 1742 sma1303_check_fault_worker); 1743 1744 i2c_set_clientdata(client, sma1303); 1745 1746 sma1303->pll_matches = sma1303_pll_matches; 1747 sma1303->num_of_pll_matches = 1748 ARRAY_SIZE(sma1303_pll_matches); 1749 1750 ret = devm_snd_soc_register_component(&client->dev, 1751 &sma1303_component, sma1303_dai, 1); 1752 if (ret) { 1753 dev_err(&client->dev, "Failed to register component"); 1754 1755 return ret; 1756 } 1757 1758 sma1303->attr_grp = &sma1303_attr_group; 1759 ret = sysfs_create_group(sma1303->kobj, sma1303->attr_grp); 1760 if (ret) { 1761 dev_err(&client->dev, 1762 "failed to create attribute group [%d]\n", ret); 1763 sma1303->attr_grp = NULL; 1764 } 1765 1766 return ret; 1767 } 1768 1769 static void sma1303_i2c_remove(struct i2c_client *client) 1770 { 1771 struct sma1303_priv *sma1303 = 1772 (struct sma1303_priv *) i2c_get_clientdata(client); 1773 1774 cancel_delayed_work_sync(&sma1303->check_fault_work); 1775 } 1776 1777 static const struct i2c_device_id sma1303_i2c_id[] = { 1778 {"sma1303", 0}, 1779 {} 1780 }; 1781 MODULE_DEVICE_TABLE(i2c, sma1303_i2c_id); 1782 1783 static const struct of_device_id sma1303_of_match[] = { 1784 { .compatible = "irondevice,sma1303", }, 1785 { } 1786 }; 1787 MODULE_DEVICE_TABLE(of, sma1303_of_match); 1788 1789 static struct i2c_driver sma1303_i2c_driver = { 1790 .driver = { 1791 .name = "sma1303", 1792 .of_match_table = sma1303_of_match, 1793 }, 1794 .probe = sma1303_i2c_probe, 1795 .remove = sma1303_i2c_remove, 1796 .id_table = sma1303_i2c_id, 1797 }; 1798 1799 module_i2c_driver(sma1303_i2c_driver); 1800 1801 MODULE_DESCRIPTION("ALSA SoC SMA1303 driver"); 1802 MODULE_AUTHOR("Gyuhwa Park, <gyuhwa.park@irondevice.com>"); 1803 MODULE_AUTHOR("Kiseok Jo, <kiseok.jo@irondevice.com>"); 1804 MODULE_LICENSE("GPL v2"); 1805