1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // 3 // sma1303.c -- sma1303 ALSA SoC Audio driver 4 // 5 // Copyright 2023 Iron Device Corporation 6 // 7 // Auther: Gyuhwa Park <gyuhwa.park@irondevice.com> 8 // Kiseok Jo <kiseok.jo@irondevice.com> 9 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/regmap.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <linux/of_device.h> 25 #include <linux/slab.h> 26 #include <asm/div64.h> 27 28 #include "sma1303.h" 29 30 #define CHECK_PERIOD_TIME 1 /* sec per HZ */ 31 #define MAX_CONTROL_NAME 48 32 33 #define PLL_MATCH(_input_clk_name, _output_clk_name, _input_clk,\ 34 _post_n, _n, _vco, _p_cp)\ 35 {\ 36 .input_clk_name = _input_clk_name,\ 37 .output_clk_name = _output_clk_name,\ 38 .input_clk = _input_clk,\ 39 .post_n = _post_n,\ 40 .n = _n,\ 41 .vco = _vco,\ 42 .p_cp = _p_cp,\ 43 } 44 45 enum sma1303_type { 46 SMA1303, 47 }; 48 49 struct sma1303_pll_match { 50 char *input_clk_name; 51 char *output_clk_name; 52 unsigned int input_clk; 53 unsigned int post_n; 54 unsigned int n; 55 unsigned int vco; 56 unsigned int p_cp; 57 }; 58 59 struct sma1303_priv { 60 enum sma1303_type devtype; 61 struct attribute_group *attr_grp; 62 struct delayed_work check_fault_work; 63 struct device *dev; 64 struct kobject *kobj; 65 struct regmap *regmap; 66 struct sma1303_pll_match *pll_matches; 67 bool amp_power_status; 68 bool force_mute_status; 69 int num_of_pll_matches; 70 int retry_cnt; 71 unsigned int amp_mode; 72 unsigned int cur_vol; 73 unsigned int format; 74 unsigned int frame_size; 75 unsigned int init_vol; 76 unsigned int last_bclk; 77 unsigned int last_ocp_val; 78 unsigned int last_over_temp; 79 unsigned int rev_num; 80 unsigned int sys_clk_id; 81 unsigned int tdm_slot_rx; 82 unsigned int tdm_slot_tx; 83 unsigned int tsdw_cnt; 84 long check_fault_period; 85 long check_fault_status; 86 }; 87 88 static struct sma1303_pll_match sma1303_pll_matches[] = { 89 PLL_MATCH("1.411MHz", "24.595MHz", 1411200, 0x07, 0xF4, 0x8B, 0x03), 90 PLL_MATCH("1.536MHz", "24.576MHz", 1536000, 0x07, 0xE0, 0x8B, 0x03), 91 PLL_MATCH("3.072MHz", "24.576MHz", 3072000, 0x07, 0x70, 0x8B, 0x03), 92 PLL_MATCH("6.144MHz", "24.576MHz", 6144000, 0x07, 0x70, 0x8B, 0x07), 93 PLL_MATCH("12.288MHz", "24.576MHz", 12288000, 0x07, 0x70, 0x8B, 0x0B), 94 PLL_MATCH("19.2MHz", "24.343MHz", 19200000, 0x07, 0x47, 0x8B, 0x0A), 95 PLL_MATCH("24.576MHz", "24.576MHz", 24576000, 0x07, 0x70, 0x8B, 0x0F), 96 }; 97 98 static int sma1303_startup(struct snd_soc_component *); 99 static int sma1303_shutdown(struct snd_soc_component *); 100 101 static const struct reg_default sma1303_reg_def[] = { 102 { 0x00, 0x80 }, 103 { 0x01, 0x00 }, 104 { 0x02, 0x00 }, 105 { 0x03, 0x11 }, 106 { 0x04, 0x17 }, 107 { 0x09, 0x00 }, 108 { 0x0A, 0x31 }, 109 { 0x0B, 0x98 }, 110 { 0x0C, 0x84 }, 111 { 0x0D, 0x07 }, 112 { 0x0E, 0x3F }, 113 { 0x10, 0x00 }, 114 { 0x11, 0x00 }, 115 { 0x12, 0x00 }, 116 { 0x14, 0x5C }, 117 { 0x15, 0x01 }, 118 { 0x16, 0x0F }, 119 { 0x17, 0x0F }, 120 { 0x18, 0x0F }, 121 { 0x19, 0x00 }, 122 { 0x1A, 0x00 }, 123 { 0x1B, 0x00 }, 124 { 0x23, 0x19 }, 125 { 0x24, 0x00 }, 126 { 0x25, 0x00 }, 127 { 0x26, 0x04 }, 128 { 0x33, 0x00 }, 129 { 0x36, 0x92 }, 130 { 0x37, 0x27 }, 131 { 0x3B, 0x5A }, 132 { 0x3C, 0x20 }, 133 { 0x3D, 0x00 }, 134 { 0x3E, 0x03 }, 135 { 0x3F, 0x0C }, 136 { 0x8B, 0x07 }, 137 { 0x8C, 0x70 }, 138 { 0x8D, 0x8B }, 139 { 0x8E, 0x6F }, 140 { 0x8F, 0x03 }, 141 { 0x90, 0x26 }, 142 { 0x91, 0x42 }, 143 { 0x92, 0xE0 }, 144 { 0x94, 0x35 }, 145 { 0x95, 0x0C }, 146 { 0x96, 0x42 }, 147 { 0x97, 0x95 }, 148 { 0xA0, 0x00 }, 149 { 0xA1, 0x3B }, 150 { 0xA2, 0xC8 }, 151 { 0xA3, 0x28 }, 152 { 0xA4, 0x40 }, 153 { 0xA5, 0x01 }, 154 { 0xA6, 0x41 }, 155 { 0xA7, 0x00 }, 156 }; 157 158 static bool sma1303_readable_register(struct device *dev, unsigned int reg) 159 { 160 bool result; 161 162 if (reg > SMA1303_FF_DEVICE_INDEX) 163 return false; 164 165 switch (reg) { 166 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4: 167 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL: 168 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3: 169 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7: 170 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4: 171 case SMA1303_33_SDM_CTRL ... SMA1303_34_OTP_DATA1: 172 case SMA1303_36_PROTECTION ... SMA1303_38_OTP_TRM0: 173 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2: 174 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL: 175 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4: 176 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON: 177 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2: 178 result = true; 179 break; 180 case SMA1303_FF_DEVICE_INDEX: 181 result = true; 182 break; 183 default: 184 result = false; 185 break; 186 } 187 return result; 188 } 189 190 static bool sma1303_writeable_register(struct device *dev, unsigned int reg) 191 { 192 bool result; 193 194 if (reg > SMA1303_FF_DEVICE_INDEX) 195 return false; 196 197 switch (reg) { 198 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4: 199 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL: 200 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3: 201 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7: 202 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4: 203 case SMA1303_33_SDM_CTRL: 204 case SMA1303_36_PROTECTION ... SMA1303_37_SLOPE_CTRL: 205 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2: 206 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL: 207 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4: 208 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON: 209 result = true; 210 break; 211 default: 212 result = false; 213 break; 214 } 215 return result; 216 } 217 218 static bool sma1303_volatile_register(struct device *dev, unsigned int reg) 219 { 220 bool result; 221 222 switch (reg) { 223 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2: 224 result = true; 225 break; 226 case SMA1303_FF_DEVICE_INDEX: 227 result = true; 228 break; 229 default: 230 result = false; 231 break; 232 } 233 return result; 234 } 235 236 static const DECLARE_TLV_DB_SCALE(sma1303_spk_tlv, -6000, 50, 0); 237 238 static int sma1303_regmap_write(struct sma1303_priv *sma1303, 239 unsigned int reg, unsigned int val) 240 { 241 int ret = 0; 242 int cnt = sma1303->retry_cnt; 243 244 while (cnt--) { 245 ret = regmap_write(sma1303->regmap, reg, val); 246 if (ret < 0) { 247 dev_err(sma1303->dev, 248 "Failed to write [0x%02X]\n", reg); 249 } else 250 break; 251 } 252 return ret; 253 } 254 255 static int sma1303_regmap_update_bits(struct sma1303_priv *sma1303, 256 unsigned int reg, unsigned int mask, unsigned int val, bool *change) 257 { 258 int ret = 0; 259 int cnt = sma1303->retry_cnt; 260 261 while (cnt--) { 262 ret = regmap_update_bits_check(sma1303->regmap, reg, 263 mask, val, change); 264 if (ret < 0) { 265 dev_err(sma1303->dev, 266 "Failed to update [0x%02X]\n", reg); 267 } else 268 break; 269 } 270 return ret; 271 } 272 273 static int sma1303_regmap_read(struct sma1303_priv *sma1303, 274 unsigned int reg, unsigned int *val) 275 { 276 int ret = 0; 277 int cnt = sma1303->retry_cnt; 278 279 while (cnt--) { 280 ret = regmap_read(sma1303->regmap, reg, val); 281 if (ret < 0) { 282 dev_err(sma1303->dev, 283 "Failed to read [0x%02X]\n", reg); 284 } else 285 break; 286 } 287 return ret; 288 } 289 290 static const char * const sma1303_aif_in_source_text[] = { 291 "Mono", "Left", "Right"}; 292 static const char * const sma1303_aif_out_source_text[] = { 293 "Disable", "After_FmtC", "After_Mixer", "After_DSP", "After_Post", 294 "Clk_PLL", "Clk_OSC"}; 295 static const char * const sma1303_tdm_slot_text[] = { 296 "Slot0", "Slot1", "Slot2", "Slot3", 297 "Slot4", "Slot5", "Slot6", "Slot7"}; 298 299 static const struct soc_enum sma1303_aif_in_source_enum = 300 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_in_source_text), 301 sma1303_aif_in_source_text); 302 static const struct soc_enum sma1303_aif_out_source_enum = 303 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_out_source_text), 304 sma1303_aif_out_source_text); 305 static const struct soc_enum sma1303_tdm_slot_enum = 306 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_tdm_slot_text), 307 sma1303_tdm_slot_text); 308 309 static int sma1303_force_mute_get(struct snd_kcontrol *kcontrol, 310 struct snd_ctl_elem_value *ucontrol) 311 { 312 struct snd_soc_component *component = 313 snd_soc_kcontrol_component(kcontrol); 314 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 315 316 ucontrol->value.integer.value[0] = (int)sma1303->force_mute_status; 317 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__, 318 sma1303->force_mute_status ? "ON" : "OFF"); 319 320 return 0; 321 } 322 323 static int sma1303_force_mute_put(struct snd_kcontrol *kcontrol, 324 struct snd_ctl_elem_value *ucontrol) 325 { 326 struct snd_soc_component *component = 327 snd_soc_kcontrol_component(kcontrol); 328 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 329 bool change = false, val = (bool)ucontrol->value.integer.value[0]; 330 331 if (sma1303->force_mute_status == val) 332 change = false; 333 else { 334 change = true; 335 sma1303->force_mute_status = val; 336 } 337 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__, 338 sma1303->force_mute_status ? "ON" : "OFF"); 339 340 return change; 341 } 342 343 static int sma1303_postscaler_get(struct snd_kcontrol *kcontrol, 344 struct snd_ctl_elem_value *ucontrol) 345 { 346 struct snd_soc_component *component = 347 snd_soc_kcontrol_component(kcontrol); 348 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 349 int val, ret; 350 351 ret = sma1303_regmap_read(sma1303, SMA1303_90_POSTSCALER, &val); 352 if (ret < 0) 353 return -EINVAL; 354 355 ucontrol->value.integer.value[0] = (val & 0x7E) >> 1; 356 357 return 0; 358 } 359 360 static int sma1303_postscaler_put(struct snd_kcontrol *kcontrol, 361 struct snd_ctl_elem_value *ucontrol) 362 { 363 struct snd_soc_component *component = 364 snd_soc_kcontrol_component(kcontrol); 365 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 366 int ret, val = (int)ucontrol->value.integer.value[0]; 367 bool change; 368 369 ret = sma1303_regmap_update_bits(sma1303, 370 SMA1303_90_POSTSCALER, 0x7E, (val << 1), &change); 371 if (ret < 0) 372 return -EINVAL; 373 374 return change; 375 } 376 377 static int sma1303_tdm_slot_rx_get(struct snd_kcontrol *kcontrol, 378 struct snd_ctl_elem_value *ucontrol) 379 { 380 struct snd_soc_component *component = 381 snd_soc_kcontrol_component(kcontrol); 382 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 383 int val, ret; 384 385 ret = sma1303_regmap_read(sma1303, SMA1303_A5_TDM1, &val); 386 if (ret < 0) 387 return -EINVAL; 388 389 ucontrol->value.integer.value[0] = (val & 0x38) >> 3; 390 sma1303->tdm_slot_rx = ucontrol->value.integer.value[0]; 391 392 return 0; 393 } 394 395 static int sma1303_tdm_slot_rx_put(struct snd_kcontrol *kcontrol, 396 struct snd_ctl_elem_value *ucontrol) 397 { 398 struct snd_soc_component *component = 399 snd_soc_kcontrol_component(kcontrol); 400 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 401 int ret, val = (int)ucontrol->value.integer.value[0]; 402 bool change; 403 404 ret = sma1303_regmap_update_bits(sma1303, 405 SMA1303_A5_TDM1, 0x38, (val << 3), &change); 406 if (ret < 0) 407 return -EINVAL; 408 409 return change; 410 } 411 412 static int sma1303_tdm_slot_tx_get(struct snd_kcontrol *kcontrol, 413 struct snd_ctl_elem_value *ucontrol) 414 { 415 struct snd_soc_component *component = 416 snd_soc_kcontrol_component(kcontrol); 417 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 418 int val, ret; 419 420 ret = sma1303_regmap_read(sma1303, SMA1303_A6_TDM2, &val); 421 if (ret < 0) 422 return -EINVAL; 423 424 ucontrol->value.integer.value[0] = (val & 0x38) >> 3; 425 sma1303->tdm_slot_tx = ucontrol->value.integer.value[0]; 426 427 return 0; 428 } 429 430 static int sma1303_tdm_slot_tx_put(struct snd_kcontrol *kcontrol, 431 struct snd_ctl_elem_value *ucontrol) 432 { 433 struct snd_soc_component *component = 434 snd_soc_kcontrol_component(kcontrol); 435 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 436 int ret, val = (int)ucontrol->value.integer.value[0]; 437 bool change; 438 439 ret = sma1303_regmap_update_bits(sma1303, 440 SMA1303_A6_TDM2, 0x38, (val << 3), &change); 441 if (ret < 0) 442 return -EINVAL; 443 444 return change; 445 } 446 447 static int sma1303_startup(struct snd_soc_component *component) 448 { 449 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 450 bool change = false, temp = false; 451 452 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL, 453 SMA1303_PLL_PD2_MASK, SMA1303_PLL_OPERATION2, &temp); 454 if (temp == true) 455 change = true; 456 457 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL, 458 SMA1303_POWER_MASK, SMA1303_POWER_ON, &temp); 459 if (temp == true) 460 change = true; 461 462 if (sma1303->amp_mode == SMA1303_MONO) { 463 sma1303_regmap_update_bits(sma1303, 464 SMA1303_10_SYSTEM_CTRL1, 465 SMA1303_SPK_MODE_MASK, 466 SMA1303_SPK_MONO, 467 &temp); 468 if (temp == true) 469 change = true; 470 471 } else { 472 sma1303_regmap_update_bits(sma1303, 473 SMA1303_10_SYSTEM_CTRL1, 474 SMA1303_SPK_MODE_MASK, 475 SMA1303_SPK_STEREO, 476 &temp); 477 if (temp == true) 478 change = true; 479 } 480 481 if (sma1303->check_fault_status) { 482 if (sma1303->check_fault_period > 0) 483 queue_delayed_work(system_freezable_wq, 484 &sma1303->check_fault_work, 485 sma1303->check_fault_period * HZ); 486 else 487 queue_delayed_work(system_freezable_wq, 488 &sma1303->check_fault_work, 489 CHECK_PERIOD_TIME * HZ); 490 } 491 492 sma1303->amp_power_status = true; 493 494 return change; 495 } 496 497 static int sma1303_shutdown(struct snd_soc_component *component) 498 { 499 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 500 bool change = false, temp = false; 501 502 cancel_delayed_work_sync(&sma1303->check_fault_work); 503 504 sma1303_regmap_update_bits(sma1303, SMA1303_10_SYSTEM_CTRL1, 505 SMA1303_SPK_MODE_MASK, SMA1303_SPK_OFF, &temp); 506 if (temp == true) 507 change = true; 508 509 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL, 510 SMA1303_POWER_MASK, SMA1303_POWER_OFF, &temp); 511 if (temp == true) 512 change = true; 513 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL, 514 SMA1303_PLL_PD2_MASK, SMA1303_PLL_PD2, &temp); 515 if (temp == true) 516 change = true; 517 518 sma1303->amp_power_status = false; 519 520 return change; 521 } 522 523 static int sma1303_aif_in_event(struct snd_soc_dapm_widget *w, 524 struct snd_kcontrol *kcontrol, int event) 525 { 526 struct snd_soc_component *component = 527 snd_soc_dapm_to_component(w->dapm); 528 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 529 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 530 int ret = 0; 531 bool change = false, temp = false; 532 533 switch (event) { 534 case SND_SOC_DAPM_PRE_PMU: 535 switch (mux) { 536 case 0: 537 ret += sma1303_regmap_update_bits(sma1303, 538 SMA1303_11_SYSTEM_CTRL2, 539 SMA1303_MONOMIX_MASK, 540 SMA1303_MONOMIX_ON, 541 &change); 542 sma1303->amp_mode = SMA1303_MONO; 543 break; 544 case 1: 545 ret += sma1303_regmap_update_bits(sma1303, 546 SMA1303_11_SYSTEM_CTRL2, 547 SMA1303_MONOMIX_MASK, 548 SMA1303_MONOMIX_OFF, 549 &temp); 550 if (temp == true) 551 change = true; 552 ret += sma1303_regmap_update_bits(sma1303, 553 SMA1303_11_SYSTEM_CTRL2, 554 SMA1303_LR_DATA_SW_MASK, 555 SMA1303_LR_DATA_SW_NORMAL, 556 &temp); 557 if (temp == true) 558 change = true; 559 sma1303->amp_mode = SMA1303_STEREO; 560 break; 561 case 2: 562 ret += sma1303_regmap_update_bits(sma1303, 563 SMA1303_11_SYSTEM_CTRL2, 564 SMA1303_MONOMIX_MASK, 565 SMA1303_MONOMIX_OFF, 566 &temp); 567 if (temp == true) 568 change = true; 569 ret += sma1303_regmap_update_bits(sma1303, 570 SMA1303_11_SYSTEM_CTRL2, 571 SMA1303_LR_DATA_SW_MASK, 572 SMA1303_LR_DATA_SW_NORMAL, 573 &temp); 574 if (temp == true) 575 change = true; 576 sma1303->amp_mode = SMA1303_STEREO; 577 break; 578 default: 579 dev_err(sma1303->dev, "%s : Invalid value (%d)\n", 580 __func__, mux); 581 return -EINVAL; 582 } 583 584 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__, 585 sma1303_aif_in_source_text[mux]); 586 break; 587 } 588 if (ret < 0) 589 return -EINVAL; 590 return change; 591 } 592 593 static int sma1303_aif_out_event(struct snd_soc_dapm_widget *w, 594 struct snd_kcontrol *kcontrol, int event) 595 { 596 struct snd_soc_component *component = 597 snd_soc_dapm_to_component(w->dapm); 598 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 599 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 600 int ret = 0; 601 bool change = false, temp = false; 602 603 switch (event) { 604 case SND_SOC_DAPM_PRE_PMU: 605 switch (mux) { 606 case 0: 607 ret += sma1303_regmap_update_bits(sma1303, 608 SMA1303_A3_TOP_MAN2, 609 SMA1303_TEST_CLKO_EN_MASK, 610 SMA1303_NORMAL_SDO, 611 &temp); 612 if (temp == true) 613 change = true; 614 ret += sma1303_regmap_update_bits(sma1303, 615 SMA1303_09_OUTPUT_CTRL, 616 SMA1303_PORT_OUT_SEL_MASK, 617 SMA1303_OUT_SEL_DISABLE, 618 &temp); 619 if (temp == true) 620 change = true; 621 break; 622 case 1: 623 ret += sma1303_regmap_update_bits(sma1303, 624 SMA1303_A3_TOP_MAN2, 625 SMA1303_TEST_CLKO_EN_MASK, 626 SMA1303_NORMAL_SDO, 627 &temp); 628 if (temp == true) 629 change = true; 630 ret += sma1303_regmap_update_bits(sma1303, 631 SMA1303_09_OUTPUT_CTRL, 632 SMA1303_PORT_OUT_SEL_MASK, 633 SMA1303_FORMAT_CONVERTER, 634 &temp); 635 if (temp == true) 636 change = true; 637 break; 638 case 2: 639 ret += sma1303_regmap_update_bits(sma1303, 640 SMA1303_A3_TOP_MAN2, 641 SMA1303_TEST_CLKO_EN_MASK, 642 SMA1303_NORMAL_SDO, 643 &temp); 644 if (temp == true) 645 change = true; 646 ret += sma1303_regmap_update_bits(sma1303, 647 SMA1303_09_OUTPUT_CTRL, 648 SMA1303_PORT_OUT_SEL_MASK, 649 SMA1303_MIXER_OUTPUT, 650 &temp); 651 if (temp == true) 652 change = true; 653 break; 654 case 3: 655 ret += sma1303_regmap_update_bits(sma1303, 656 SMA1303_A3_TOP_MAN2, 657 SMA1303_TEST_CLKO_EN_MASK, 658 SMA1303_NORMAL_SDO, 659 &temp); 660 if (temp == true) 661 change = true; 662 ret += sma1303_regmap_update_bits(sma1303, 663 SMA1303_09_OUTPUT_CTRL, 664 SMA1303_PORT_OUT_SEL_MASK, 665 SMA1303_SPEAKER_PATH, 666 &temp); 667 if (temp == true) 668 change = true; 669 break; 670 case 4: 671 ret += sma1303_regmap_update_bits(sma1303, 672 SMA1303_A3_TOP_MAN2, 673 SMA1303_TEST_CLKO_EN_MASK, 674 SMA1303_NORMAL_SDO, 675 &temp); 676 if (temp == true) 677 change = true; 678 ret += sma1303_regmap_update_bits(sma1303, 679 SMA1303_09_OUTPUT_CTRL, 680 SMA1303_PORT_OUT_SEL_MASK, 681 SMA1303_POSTSCALER_OUTPUT, 682 &temp); 683 if (temp == true) 684 change = true; 685 break; 686 case 5: 687 ret += sma1303_regmap_update_bits(sma1303, 688 SMA1303_A3_TOP_MAN2, 689 SMA1303_TEST_CLKO_EN_MASK, 690 SMA1303_CLK_OUT_SDO, 691 &temp); 692 if (temp == true) 693 change = true; 694 ret += sma1303_regmap_update_bits(sma1303, 695 SMA1303_A3_TOP_MAN2, 696 SMA1303_MON_OSC_PLL_MASK, 697 SMA1303_PLL_SDO, 698 &temp); 699 if (temp == true) 700 change = true; 701 break; 702 case 6: 703 ret += sma1303_regmap_update_bits(sma1303, 704 SMA1303_A3_TOP_MAN2, 705 SMA1303_TEST_CLKO_EN_MASK, 706 SMA1303_CLK_OUT_SDO, 707 &temp); 708 if (temp == true) 709 change = true; 710 ret += sma1303_regmap_update_bits(sma1303, 711 SMA1303_A3_TOP_MAN2, 712 SMA1303_MON_OSC_PLL_MASK, 713 SMA1303_OSC_SDO, 714 &temp); 715 if (temp == true) 716 change = true; 717 break; 718 default: 719 dev_err(sma1303->dev, "%s : Invalid value (%d)\n", 720 __func__, mux); 721 return -EINVAL; 722 } 723 724 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__, 725 sma1303_aif_out_source_text[mux]); 726 break; 727 } 728 if (ret < 0) 729 return -EINVAL; 730 return change; 731 } 732 733 static int sma1303_sdo_event(struct snd_soc_dapm_widget *w, 734 struct snd_kcontrol *kcontrol, int event) 735 { 736 struct snd_soc_component *component = 737 snd_soc_dapm_to_component(w->dapm); 738 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 739 int ret = 0; 740 bool change = false, temp = false; 741 742 switch (event) { 743 case SND_SOC_DAPM_PRE_PMU: 744 dev_dbg(sma1303->dev, 745 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__); 746 ret += sma1303_regmap_update_bits(sma1303, 747 SMA1303_09_OUTPUT_CTRL, 748 SMA1303_PORT_CONFIG_MASK, 749 SMA1303_OUTPUT_PORT_ENABLE, 750 &temp); 751 if (temp == true) 752 change = true; 753 ret += sma1303_regmap_update_bits(sma1303, 754 SMA1303_A3_TOP_MAN2, 755 SMA1303_SDO_OUTPUT_MASK, 756 SMA1303_NORMAL_OUT, 757 &temp); 758 if (temp == true) 759 change = true; 760 break; 761 case SND_SOC_DAPM_POST_PMD: 762 dev_dbg(sma1303->dev, 763 "%s : SND_SOC_DAPM_POST_PMD\n", __func__); 764 ret += sma1303_regmap_update_bits(sma1303, 765 SMA1303_09_OUTPUT_CTRL, 766 SMA1303_PORT_CONFIG_MASK, 767 SMA1303_INPUT_PORT_ONLY, 768 &temp); 769 if (temp == true) 770 change = true; 771 ret += sma1303_regmap_update_bits(sma1303, 772 SMA1303_A3_TOP_MAN2, 773 SMA1303_SDO_OUTPUT_MASK, 774 SMA1303_HIGH_Z_OUT, 775 &temp); 776 if (temp == true) 777 change = true; 778 break; 779 } 780 if (ret < 0) 781 return -EINVAL; 782 return change; 783 } 784 785 static int sma1303_post_scaler_event(struct snd_soc_dapm_widget *w, 786 struct snd_kcontrol *kcontrol, int event) 787 { 788 struct snd_soc_component *component = 789 snd_soc_dapm_to_component(w->dapm); 790 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 791 int ret = 0; 792 bool change = false; 793 794 switch (event) { 795 case SND_SOC_DAPM_PRE_PMU: 796 dev_dbg(sma1303->dev, 797 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__); 798 ret += sma1303_regmap_update_bits(sma1303, 799 SMA1303_90_POSTSCALER, 800 SMA1303_BYP_POST_MASK, 801 SMA1303_EN_POST_SCALER, 802 &change); 803 break; 804 case SND_SOC_DAPM_POST_PMD: 805 dev_dbg(sma1303->dev, 806 "%s : SND_SOC_DAPM_POST_PMD\n", __func__); 807 ret += sma1303_regmap_update_bits(sma1303, 808 SMA1303_90_POSTSCALER, 809 SMA1303_BYP_POST_MASK, 810 SMA1303_BYP_POST_SCALER, 811 &change); 812 break; 813 } 814 if (ret < 0) 815 return -EINVAL; 816 return change; 817 } 818 819 static int sma1303_power_event(struct snd_soc_dapm_widget *w, 820 struct snd_kcontrol *kcontrol, int event) 821 { 822 struct snd_soc_component *component = 823 snd_soc_dapm_to_component(w->dapm); 824 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 825 int ret = 0; 826 827 switch (event) { 828 case SND_SOC_DAPM_POST_PMU: 829 dev_dbg(sma1303->dev, 830 "%s : SND_SOC_DAPM_POST_PMU\n", __func__); 831 ret = sma1303_startup(component); 832 break; 833 case SND_SOC_DAPM_PRE_PMD: 834 dev_dbg(sma1303->dev, 835 "%s : SND_SOC_DAPM_PRE_PMD\n", __func__); 836 ret = sma1303_shutdown(component); 837 break; 838 } 839 return ret; 840 } 841 842 static const struct snd_kcontrol_new sma1303_aif_in_source_control = 843 SOC_DAPM_ENUM("AIF IN Source", sma1303_aif_in_source_enum); 844 static const struct snd_kcontrol_new sma1303_aif_out_source_control = 845 SOC_DAPM_ENUM("AIF OUT Source", sma1303_aif_out_source_enum); 846 static const struct snd_kcontrol_new sma1303_sdo_control = 847 SOC_DAPM_SINGLE_VIRT("Switch", 1); 848 static const struct snd_kcontrol_new sma1303_post_scaler_control = 849 SOC_DAPM_SINGLE_VIRT("Switch", 1); 850 static const struct snd_kcontrol_new sma1303_enable_control = 851 SOC_DAPM_SINGLE_VIRT("Switch", 1); 852 853 static const struct snd_kcontrol_new sma1303_snd_controls[] = { 854 SOC_SINGLE_TLV("Speaker Volume", SMA1303_0A_SPK_VOL, 855 0, 167, 1, sma1303_spk_tlv), 856 SOC_SINGLE_BOOL_EXT("Force Mute Switch", 0, 857 sma1303_force_mute_get, sma1303_force_mute_put), 858 SOC_SINGLE_EXT("Postscaler Gain", SMA1303_90_POSTSCALER, 1, 0x30, 0, 859 sma1303_postscaler_get, sma1303_postscaler_put), 860 SOC_ENUM_EXT("TDM RX Slot Position", sma1303_tdm_slot_enum, 861 sma1303_tdm_slot_rx_get, sma1303_tdm_slot_rx_put), 862 SOC_ENUM_EXT("TDM TX Slot Position", sma1303_tdm_slot_enum, 863 sma1303_tdm_slot_tx_get, sma1303_tdm_slot_tx_put), 864 }; 865 866 static const struct snd_soc_dapm_widget sma1303_dapm_widgets[] = { 867 /* platform domain */ 868 SND_SOC_DAPM_OUTPUT("SPK"), 869 SND_SOC_DAPM_INPUT("SDO"), 870 871 /* path domain */ 872 SND_SOC_DAPM_MUX_E("AIF IN Source", SND_SOC_NOPM, 0, 0, 873 &sma1303_aif_in_source_control, 874 sma1303_aif_in_event, 875 SND_SOC_DAPM_PRE_PMU), 876 SND_SOC_DAPM_MUX_E("AIF OUT Source", SND_SOC_NOPM, 0, 0, 877 &sma1303_aif_out_source_control, 878 sma1303_aif_out_event, 879 SND_SOC_DAPM_PRE_PMU), 880 SND_SOC_DAPM_SWITCH_E("SDO Enable", SND_SOC_NOPM, 0, 0, 881 &sma1303_sdo_control, 882 sma1303_sdo_event, 883 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 884 SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0), 885 SND_SOC_DAPM_SWITCH_E("Post Scaler", SND_SOC_NOPM, 0, 1, 886 &sma1303_post_scaler_control, 887 sma1303_post_scaler_event, 888 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 889 SND_SOC_DAPM_OUT_DRV_E("AMP Power", SND_SOC_NOPM, 0, 0, NULL, 0, 890 sma1303_power_event, 891 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 892 SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, 893 &sma1303_enable_control), 894 895 /* stream domain */ 896 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 897 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 898 }; 899 900 static const struct snd_soc_dapm_route sma1303_audio_map[] = { 901 /* Playback */ 902 {"AIF IN Source", "Mono", "AIF IN"}, 903 {"AIF IN Source", "Left", "AIF IN"}, 904 {"AIF IN Source", "Right", "AIF IN"}, 905 906 {"SDO Enable", "Switch", "AIF IN"}, 907 {"AIF OUT Source", "Disable", "SDO Enable"}, 908 {"AIF OUT Source", "After_FmtC", "SDO Enable"}, 909 {"AIF OUT Source", "After_Mixer", "SDO Enable"}, 910 {"AIF OUT Source", "After_DSP", "SDO Enable"}, 911 {"AIF OUT Source", "After_Post", "SDO Enable"}, 912 {"AIF OUT Source", "Clk_PLL", "SDO Enable"}, 913 {"AIF OUT Source", "Clk_OSC", "SDO Enable"}, 914 915 {"Entry", NULL, "AIF OUT Source"}, 916 {"Entry", NULL, "AIF IN Source"}, 917 918 {"Post Scaler", "Switch", "Entry"}, 919 {"AMP Power", NULL, "Entry"}, 920 {"AMP Power", NULL, "Entry"}, 921 922 {"AMP Enable", "Switch", "AMP Power"}, 923 {"SPK", NULL, "AMP Enable"}, 924 925 /* Capture */ 926 {"AIF OUT", NULL, "AMP Enable"}, 927 }; 928 929 static int sma1303_setup_pll(struct snd_soc_component *component, 930 unsigned int bclk) 931 { 932 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 933 934 int i = 0, ret = 0; 935 936 dev_dbg(component->dev, "%s : BCLK = %dHz\n", 937 __func__, bclk); 938 939 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_MCLK) { 940 dev_dbg(component->dev, "%s : MCLK is not supported\n", 941 __func__); 942 } else if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) { 943 for (i = 0; i < sma1303->num_of_pll_matches; i++) { 944 if (sma1303->pll_matches[i].input_clk == bclk) 945 break; 946 } 947 if (i == sma1303->num_of_pll_matches) { 948 dev_dbg(component->dev, "%s : No matching value between pll table and SCK\n", 949 __func__); 950 return -EINVAL; 951 } 952 953 ret += sma1303_regmap_update_bits(sma1303, 954 SMA1303_A2_TOP_MAN1, 955 SMA1303_PLL_PD_MASK|SMA1303_PLL_REF_CLK_MASK, 956 SMA1303_PLL_OPERATION|SMA1303_PLL_SCK, 957 NULL); 958 } 959 960 ret += sma1303_regmap_write(sma1303, 961 SMA1303_8B_PLL_POST_N, 962 sma1303->pll_matches[i].post_n); 963 964 ret += sma1303_regmap_write(sma1303, 965 SMA1303_8C_PLL_N, 966 sma1303->pll_matches[i].n); 967 968 ret += sma1303_regmap_write(sma1303, 969 SMA1303_8D_PLL_A_SETTING, 970 sma1303->pll_matches[i].vco); 971 972 ret += sma1303_regmap_write(sma1303, 973 SMA1303_8F_PLL_P_CP, 974 sma1303->pll_matches[i].p_cp); 975 if (ret < 0) 976 return -EINVAL; 977 978 return 0; 979 } 980 981 static int sma1303_dai_hw_params_amp(struct snd_pcm_substream *substream, 982 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 983 { 984 struct snd_soc_component *component = dai->component; 985 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 986 unsigned int bclk = 0; 987 int ret = 0; 988 989 if (sma1303->format == SND_SOC_DAIFMT_DSP_A) 990 bclk = params_rate(params) * sma1303->frame_size; 991 else 992 bclk = params_rate(params) * params_physical_width(params) 993 * params_channels(params); 994 995 dev_dbg(component->dev, 996 "%s : rate = %d : bit size = %d : channel = %d\n", 997 __func__, params_rate(params), params_width(params), 998 params_channels(params)); 999 1000 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1001 1002 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_MCLK 1003 || sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) { 1004 1005 if (sma1303->last_bclk != bclk) { 1006 sma1303_setup_pll(component, bclk); 1007 sma1303->last_bclk = bclk; 1008 } 1009 } 1010 1011 switch (params_rate(params)) { 1012 case 8000: 1013 case 12000: 1014 case 16000: 1015 case 24000: 1016 case 32000: 1017 case 44100: 1018 case 48000: 1019 case 96000: 1020 ret += sma1303_regmap_update_bits(sma1303, 1021 SMA1303_A2_TOP_MAN1, 1022 SMA1303_DAC_DN_CONV_MASK, 1023 SMA1303_DAC_DN_CONV_DISABLE, 1024 NULL); 1025 1026 ret += sma1303_regmap_update_bits(sma1303, 1027 SMA1303_01_INPUT1_CTRL1, 1028 SMA1303_LEFTPOL_MASK, 1029 SMA1303_LOW_FIRST_CH, 1030 NULL); 1031 break; 1032 1033 case 192000: 1034 ret += sma1303_regmap_update_bits(sma1303, 1035 SMA1303_A2_TOP_MAN1, 1036 SMA1303_DAC_DN_CONV_MASK, 1037 SMA1303_DAC_DN_CONV_ENABLE, 1038 NULL); 1039 1040 ret += sma1303_regmap_update_bits(sma1303, 1041 SMA1303_01_INPUT1_CTRL1, 1042 SMA1303_LEFTPOL_MASK, 1043 SMA1303_HIGH_FIRST_CH, 1044 NULL); 1045 break; 1046 1047 default: 1048 dev_err(component->dev, "%s not support rate : %d\n", 1049 __func__, params_rate(params)); 1050 1051 return -EINVAL; 1052 } 1053 1054 } else { 1055 1056 switch (params_format(params)) { 1057 1058 case SNDRV_PCM_FORMAT_S16_LE: 1059 dev_dbg(component->dev, 1060 "%s set format SNDRV_PCM_FORMAT_S16_LE\n", 1061 __func__); 1062 ret += sma1303_regmap_update_bits(sma1303, 1063 SMA1303_A4_TOP_MAN3, 1064 SMA1303_SCK_RATE_MASK, 1065 SMA1303_SCK_32FS, 1066 NULL); 1067 break; 1068 1069 case SNDRV_PCM_FORMAT_S24_LE: 1070 dev_dbg(component->dev, 1071 "%s set format SNDRV_PCM_FORMAT_S24_LE\n", 1072 __func__); 1073 ret += sma1303_regmap_update_bits(sma1303, 1074 SMA1303_A4_TOP_MAN3, 1075 SMA1303_SCK_RATE_MASK, 1076 SMA1303_SCK_64FS, 1077 NULL); 1078 break; 1079 case SNDRV_PCM_FORMAT_S32_LE: 1080 dev_dbg(component->dev, 1081 "%s set format SNDRV_PCM_FORMAT_S32_LE\n", 1082 __func__); 1083 ret += sma1303_regmap_update_bits(sma1303, 1084 SMA1303_A4_TOP_MAN3, 1085 SMA1303_SCK_RATE_MASK, 1086 SMA1303_SCK_64FS, 1087 NULL); 1088 break; 1089 default: 1090 dev_err(component->dev, 1091 "%s not support data bit : %d\n", __func__, 1092 params_format(params)); 1093 return -EINVAL; 1094 } 1095 } 1096 1097 switch (sma1303->format) { 1098 case SND_SOC_DAIFMT_I2S: 1099 ret += sma1303_regmap_update_bits(sma1303, 1100 SMA1303_01_INPUT1_CTRL1, 1101 SMA1303_I2S_MODE_MASK, 1102 SMA1303_STANDARD_I2S, 1103 NULL); 1104 ret += sma1303_regmap_update_bits(sma1303, 1105 SMA1303_A4_TOP_MAN3, 1106 SMA1303_O_FORMAT_MASK, 1107 SMA1303_O_FMT_I2S, 1108 NULL); 1109 break; 1110 case SND_SOC_DAIFMT_LEFT_J: 1111 ret += sma1303_regmap_update_bits(sma1303, 1112 SMA1303_01_INPUT1_CTRL1, 1113 SMA1303_I2S_MODE_MASK, 1114 SMA1303_LJ, 1115 NULL); 1116 ret += sma1303_regmap_update_bits(sma1303, 1117 SMA1303_A4_TOP_MAN3, 1118 SMA1303_O_FORMAT_MASK, 1119 SMA1303_O_FMT_LJ, 1120 NULL); 1121 break; 1122 case SND_SOC_DAIFMT_RIGHT_J: 1123 switch (params_width(params)) { 1124 case 16: 1125 ret += sma1303_regmap_update_bits(sma1303, 1126 SMA1303_01_INPUT1_CTRL1, 1127 SMA1303_I2S_MODE_MASK, 1128 SMA1303_RJ_16BIT, 1129 NULL); 1130 break; 1131 case 24: 1132 case 32: 1133 ret += sma1303_regmap_update_bits(sma1303, 1134 SMA1303_01_INPUT1_CTRL1, 1135 SMA1303_I2S_MODE_MASK, 1136 SMA1303_RJ_24BIT, 1137 NULL); 1138 break; 1139 } 1140 break; 1141 case SND_SOC_DAIFMT_DSP_A: 1142 ret += sma1303_regmap_update_bits(sma1303, 1143 SMA1303_01_INPUT1_CTRL1, 1144 SMA1303_I2S_MODE_MASK, 1145 SMA1303_STANDARD_I2S, 1146 NULL); 1147 ret += sma1303_regmap_update_bits(sma1303, 1148 SMA1303_A4_TOP_MAN3, 1149 SMA1303_O_FORMAT_MASK, 1150 SMA1303_O_FMT_TDM, 1151 NULL); 1152 break; 1153 } 1154 1155 switch (params_width(params)) { 1156 case 16: 1157 case 24: 1158 case 32: 1159 break; 1160 default: 1161 dev_err(component->dev, 1162 "%s not support data bit : %d\n", __func__, 1163 params_format(params)); 1164 return -EINVAL; 1165 } 1166 if (ret < 0) 1167 return -EINVAL; 1168 1169 return 0; 1170 } 1171 1172 static int sma1303_dai_set_sysclk_amp(struct snd_soc_dai *dai, 1173 int clk_id, unsigned int freq, int dir) 1174 { 1175 struct snd_soc_component *component = dai->component; 1176 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1177 1178 switch (clk_id) { 1179 case SMA1303_EXTERNAL_CLOCK_19_2: 1180 break; 1181 case SMA1303_EXTERNAL_CLOCK_24_576: 1182 break; 1183 case SMA1303_PLL_CLKIN_MCLK: 1184 break; 1185 case SMA1303_PLL_CLKIN_BCLK: 1186 break; 1187 default: 1188 dev_err(component->dev, "Invalid clk id: %d\n", clk_id); 1189 return -EINVAL; 1190 } 1191 sma1303->sys_clk_id = clk_id; 1192 return 0; 1193 } 1194 1195 static int sma1303_dai_mute(struct snd_soc_dai *dai, int mute, int stream) 1196 { 1197 struct snd_soc_component *component = dai->component; 1198 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1199 int ret = 0; 1200 1201 if (stream == SNDRV_PCM_STREAM_CAPTURE) 1202 return ret; 1203 1204 if (mute) { 1205 dev_dbg(component->dev, "%s : %s\n", __func__, "MUTE"); 1206 1207 ret += sma1303_regmap_update_bits(sma1303, 1208 SMA1303_0E_MUTE_VOL_CTRL, 1209 SMA1303_SPK_MUTE_MASK, 1210 SMA1303_SPK_MUTE, 1211 NULL); 1212 1213 /* Need to wait time for mute slope */ 1214 msleep(55); 1215 } else { 1216 if (!sma1303->force_mute_status) { 1217 dev_dbg(component->dev, "%s : %s\n", 1218 __func__, "UNMUTE"); 1219 ret += sma1303_regmap_update_bits(sma1303, 1220 SMA1303_0E_MUTE_VOL_CTRL, 1221 SMA1303_SPK_MUTE_MASK, 1222 SMA1303_SPK_UNMUTE, 1223 NULL); 1224 } else { 1225 dev_dbg(sma1303->dev, 1226 "%s : FORCE MUTE!!!\n", __func__); 1227 } 1228 } 1229 1230 if (ret < 0) 1231 return -EINVAL; 1232 return 0; 1233 } 1234 1235 static int sma1303_dai_set_fmt_amp(struct snd_soc_dai *dai, 1236 unsigned int fmt) 1237 { 1238 struct snd_soc_component *component = dai->component; 1239 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1240 int ret = 0; 1241 1242 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1243 1244 case SND_SOC_DAIFMT_CBC_CFC: 1245 dev_dbg(component->dev, 1246 "%s : %s\n", __func__, "I2S/TDM Device mode"); 1247 ret += sma1303_regmap_update_bits(sma1303, 1248 SMA1303_01_INPUT1_CTRL1, 1249 SMA1303_CONTROLLER_DEVICE_MASK, 1250 SMA1303_DEVICE_MODE, 1251 NULL); 1252 break; 1253 1254 case SND_SOC_DAIFMT_CBP_CFP: 1255 dev_dbg(component->dev, 1256 "%s : %s\n", __func__, "I2S/TDM Controller mode"); 1257 ret += sma1303_regmap_update_bits(sma1303, 1258 SMA1303_01_INPUT1_CTRL1, 1259 SMA1303_CONTROLLER_DEVICE_MASK, 1260 SMA1303_CONTROLLER_MODE, 1261 NULL); 1262 break; 1263 1264 default: 1265 dev_err(component->dev, 1266 "Unsupported Controller/Device : 0x%x\n", fmt); 1267 return -EINVAL; 1268 } 1269 1270 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1271 1272 case SND_SOC_DAIFMT_I2S: 1273 case SND_SOC_DAIFMT_RIGHT_J: 1274 case SND_SOC_DAIFMT_LEFT_J: 1275 case SND_SOC_DAIFMT_DSP_A: 1276 case SND_SOC_DAIFMT_DSP_B: 1277 sma1303->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1278 break; 1279 default: 1280 dev_err(component->dev, 1281 "Unsupported Audio Interface Format : 0x%x\n", fmt); 1282 return -EINVAL; 1283 } 1284 1285 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1286 1287 case SND_SOC_DAIFMT_IB_NF: 1288 dev_dbg(component->dev, "%s : %s\n", 1289 __func__, "Invert BCLK + Normal Frame"); 1290 ret += sma1303_regmap_update_bits(sma1303, 1291 SMA1303_01_INPUT1_CTRL1, 1292 SMA1303_SCK_RISING_MASK, 1293 SMA1303_SCK_RISING_EDGE, 1294 NULL); 1295 break; 1296 case SND_SOC_DAIFMT_IB_IF: 1297 dev_dbg(component->dev, "%s : %s\n", 1298 __func__, "Invert BCLK + Invert Frame"); 1299 ret += sma1303_regmap_update_bits(sma1303, 1300 SMA1303_01_INPUT1_CTRL1, 1301 SMA1303_LEFTPOL_MASK|SMA1303_SCK_RISING_MASK, 1302 SMA1303_HIGH_FIRST_CH|SMA1303_SCK_RISING_EDGE, 1303 NULL); 1304 break; 1305 case SND_SOC_DAIFMT_NB_IF: 1306 dev_dbg(component->dev, "%s : %s\n", 1307 __func__, "Normal BCLK + Invert Frame"); 1308 ret += sma1303_regmap_update_bits(sma1303, 1309 SMA1303_01_INPUT1_CTRL1, 1310 SMA1303_LEFTPOL_MASK, 1311 SMA1303_HIGH_FIRST_CH, 1312 NULL); 1313 break; 1314 case SND_SOC_DAIFMT_NB_NF: 1315 dev_dbg(component->dev, "%s : %s\n", 1316 __func__, "Normal BCLK + Normal Frame"); 1317 break; 1318 default: 1319 dev_err(component->dev, 1320 "Unsupported Bit & Frameclock : 0x%x\n", fmt); 1321 return -EINVAL; 1322 } 1323 1324 if (ret < 0) 1325 return -EINVAL; 1326 return 0; 1327 } 1328 1329 static int sma1303_dai_set_tdm_slot(struct snd_soc_dai *dai, 1330 unsigned int tx_mask, unsigned int rx_mask, 1331 int slots, int slot_width) 1332 { 1333 struct snd_soc_component *component = dai->component; 1334 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1335 int ret = 0; 1336 1337 dev_dbg(component->dev, "%s : slots = %d, slot_width - %d\n", 1338 __func__, slots, slot_width); 1339 1340 sma1303->frame_size = slot_width * slots; 1341 1342 ret += sma1303_regmap_update_bits(sma1303, 1343 SMA1303_A4_TOP_MAN3, 1344 SMA1303_O_FORMAT_MASK, 1345 SMA1303_O_FMT_TDM, 1346 NULL); 1347 1348 switch (slot_width) { 1349 case 16: 1350 ret += sma1303_regmap_update_bits(sma1303, 1351 SMA1303_A6_TDM2, 1352 SMA1303_TDM_DL_MASK, 1353 SMA1303_TDM_DL_16, 1354 NULL); 1355 break; 1356 case 32: 1357 ret += sma1303_regmap_update_bits(sma1303, 1358 SMA1303_A6_TDM2, 1359 SMA1303_TDM_DL_MASK, 1360 SMA1303_TDM_DL_32, 1361 NULL); 1362 break; 1363 default: 1364 dev_err(component->dev, "%s not support TDM %d slot_width\n", 1365 __func__, slot_width); 1366 break; 1367 } 1368 1369 switch (slots) { 1370 case 4: 1371 ret += sma1303_regmap_update_bits(sma1303, 1372 SMA1303_A6_TDM2, 1373 SMA1303_TDM_N_SLOT_MASK, 1374 SMA1303_TDM_N_SLOT_4, 1375 NULL); 1376 break; 1377 case 8: 1378 ret += sma1303_regmap_update_bits(sma1303, 1379 SMA1303_A6_TDM2, 1380 SMA1303_TDM_N_SLOT_MASK, 1381 SMA1303_TDM_N_SLOT_8, 1382 NULL); 1383 break; 1384 default: 1385 dev_err(component->dev, "%s not support TDM %d slots\n", 1386 __func__, slots); 1387 break; 1388 } 1389 1390 if (sma1303->tdm_slot_rx < slots) 1391 ret += sma1303_regmap_update_bits(sma1303, 1392 SMA1303_A5_TDM1, 1393 SMA1303_TDM_SLOT1_RX_POS_MASK, 1394 (sma1303->tdm_slot_rx) << 3, 1395 NULL); 1396 else 1397 dev_err(component->dev, "%s Incorrect tdm-slot-rx %d set\n", 1398 __func__, sma1303->tdm_slot_rx); 1399 1400 ret += sma1303_regmap_update_bits(sma1303, 1401 SMA1303_A5_TDM1, 1402 SMA1303_TDM_CLK_POL_MASK, 1403 SMA1303_TDM_CLK_POL_RISE, 1404 NULL); 1405 1406 ret += sma1303_regmap_update_bits(sma1303, 1407 SMA1303_A5_TDM1, 1408 SMA1303_TDM_TX_MODE_MASK, 1409 SMA1303_TDM_TX_MONO, 1410 NULL); 1411 1412 if (sma1303->tdm_slot_tx < slots) 1413 ret += sma1303_regmap_update_bits(sma1303, 1414 SMA1303_A6_TDM2, 1415 SMA1303_TDM_SLOT1_TX_POS_MASK, 1416 (sma1303->tdm_slot_tx) << 3, 1417 NULL); 1418 else 1419 dev_err(component->dev, "%s Incorrect tdm-slot-tx %d set\n", 1420 __func__, sma1303->tdm_slot_tx); 1421 1422 if (ret < 0) 1423 return -EINVAL; 1424 return 0; 1425 } 1426 1427 static const struct snd_soc_dai_ops sma1303_dai_ops_amp = { 1428 .set_sysclk = sma1303_dai_set_sysclk_amp, 1429 .set_fmt = sma1303_dai_set_fmt_amp, 1430 .hw_params = sma1303_dai_hw_params_amp, 1431 .mute_stream = sma1303_dai_mute, 1432 .set_tdm_slot = sma1303_dai_set_tdm_slot, 1433 }; 1434 1435 #define SMA1303_RATES SNDRV_PCM_RATE_8000_192000 1436 #define SMA1303_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1437 SNDRV_PCM_FMTBIT_S32_LE) 1438 1439 static struct snd_soc_dai_driver sma1303_dai[] = { 1440 { 1441 .name = "sma1303-amplifier", 1442 .id = 0, 1443 .playback = { 1444 .stream_name = "Playback", 1445 .channels_min = 1, 1446 .channels_max = 2, 1447 .rates = SMA1303_RATES, 1448 .formats = SMA1303_FORMATS, 1449 }, 1450 .capture = { 1451 .stream_name = "Capture", 1452 .channels_min = 1, 1453 .channels_max = 2, 1454 .rates = SMA1303_RATES, 1455 .formats = SMA1303_FORMATS, 1456 }, 1457 .ops = &sma1303_dai_ops_amp, 1458 }, 1459 }; 1460 1461 static void sma1303_check_fault_worker(struct work_struct *work) 1462 { 1463 struct sma1303_priv *sma1303 = 1464 container_of(work, struct sma1303_priv, check_fault_work.work); 1465 int ret = 0; 1466 unsigned int over_temp, ocp_val, uvlo_val; 1467 1468 if (sma1303->tsdw_cnt) 1469 ret = sma1303_regmap_read(sma1303, 1470 SMA1303_0A_SPK_VOL, &sma1303->cur_vol); 1471 else 1472 ret = sma1303_regmap_read(sma1303, 1473 SMA1303_0A_SPK_VOL, &sma1303->init_vol); 1474 1475 if (ret != 0) { 1476 dev_err(sma1303->dev, 1477 "failed to read SMA1303_0A_SPK_VOL : %d\n", ret); 1478 return; 1479 } 1480 1481 ret = sma1303_regmap_read(sma1303, SMA1303_FA_STATUS1, &over_temp); 1482 if (ret != 0) { 1483 dev_err(sma1303->dev, 1484 "failed to read SMA1303_FA_STATUS1 : %d\n", ret); 1485 return; 1486 } 1487 1488 ret = sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &ocp_val); 1489 if (ret != 0) { 1490 dev_err(sma1303->dev, 1491 "failed to read SMA1303_FB_STATUS2 : %d\n", ret); 1492 return; 1493 } 1494 1495 ret = sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &uvlo_val); 1496 if (ret != 0) { 1497 dev_err(sma1303->dev, 1498 "failed to read SMA1303_FF_DEVICE_INDEX : %d\n", ret); 1499 return; 1500 } 1501 1502 if (~over_temp & SMA1303_OT1_OK_STATUS) { 1503 dev_crit(sma1303->dev, 1504 "%s : OT1(Over Temperature Level 1)\n", __func__); 1505 1506 if ((sma1303->cur_vol + 6) <= 0xFF) 1507 sma1303_regmap_write(sma1303, 1508 SMA1303_0A_SPK_VOL, sma1303->cur_vol + 6); 1509 1510 sma1303->tsdw_cnt++; 1511 } else if (sma1303->tsdw_cnt) { 1512 sma1303_regmap_write(sma1303, 1513 SMA1303_0A_SPK_VOL, sma1303->init_vol); 1514 sma1303->tsdw_cnt = 0; 1515 sma1303->cur_vol = sma1303->init_vol; 1516 } 1517 1518 if (~over_temp & SMA1303_OT2_OK_STATUS) { 1519 dev_crit(sma1303->dev, 1520 "%s : OT2(Over Temperature Level 2)\n", __func__); 1521 } 1522 if (ocp_val & SMA1303_OCP_SPK_STATUS) { 1523 dev_crit(sma1303->dev, 1524 "%s : OCP_SPK(Over Current Protect SPK)\n", __func__); 1525 } 1526 if (ocp_val & SMA1303_OCP_BST_STATUS) { 1527 dev_crit(sma1303->dev, 1528 "%s : OCP_BST(Over Current Protect Boost)\n", __func__); 1529 } 1530 if ((ocp_val & SMA1303_CLK_MON_STATUS) && (sma1303->amp_power_status)) { 1531 dev_crit(sma1303->dev, 1532 "%s : CLK_FAULT(No clock input)\n", __func__); 1533 } 1534 if (uvlo_val & SMA1303_UVLO_BST_STATUS) { 1535 dev_crit(sma1303->dev, 1536 "%s : UVLO(Under Voltage Lock Out)\n", __func__); 1537 } 1538 1539 if ((over_temp != sma1303->last_over_temp) || 1540 (ocp_val != sma1303->last_ocp_val)) { 1541 1542 dev_crit(sma1303->dev, "Please check AMP status"); 1543 dev_dbg(sma1303->dev, "STATUS1=0x%02X : STATUS2=0x%02X\n", 1544 over_temp, ocp_val); 1545 sma1303->last_over_temp = over_temp; 1546 sma1303->last_ocp_val = ocp_val; 1547 } 1548 1549 if (sma1303->check_fault_status) { 1550 if (sma1303->check_fault_period > 0) 1551 queue_delayed_work(system_freezable_wq, 1552 &sma1303->check_fault_work, 1553 sma1303->check_fault_period * HZ); 1554 else 1555 queue_delayed_work(system_freezable_wq, 1556 &sma1303->check_fault_work, 1557 CHECK_PERIOD_TIME * HZ); 1558 } 1559 1560 if (!(~over_temp & SMA1303_OT1_OK_STATUS) 1561 && !(~over_temp & SMA1303_OT2_OK_STATUS) 1562 && !(ocp_val & SMA1303_OCP_SPK_STATUS) 1563 && !(ocp_val & SMA1303_OCP_BST_STATUS) 1564 && !(ocp_val & SMA1303_CLK_MON_STATUS) 1565 && !(uvlo_val & SMA1303_UVLO_BST_STATUS)) { 1566 } 1567 } 1568 1569 static int sma1303_probe(struct snd_soc_component *component) 1570 { 1571 struct snd_soc_dapm_context *dapm = 1572 snd_soc_component_get_dapm(component); 1573 1574 snd_soc_dapm_sync(dapm); 1575 1576 return 0; 1577 } 1578 1579 static void sma1303_remove(struct snd_soc_component *component) 1580 { 1581 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1582 1583 cancel_delayed_work_sync(&sma1303->check_fault_work); 1584 } 1585 1586 static const struct snd_soc_component_driver sma1303_component = { 1587 .probe = sma1303_probe, 1588 .remove = sma1303_remove, 1589 .controls = sma1303_snd_controls, 1590 .num_controls = ARRAY_SIZE(sma1303_snd_controls), 1591 .dapm_widgets = sma1303_dapm_widgets, 1592 .num_dapm_widgets = ARRAY_SIZE(sma1303_dapm_widgets), 1593 .dapm_routes = sma1303_audio_map, 1594 .num_dapm_routes = ARRAY_SIZE(sma1303_audio_map), 1595 }; 1596 1597 const struct regmap_config sma_i2c_regmap = { 1598 .reg_bits = 8, 1599 .val_bits = 8, 1600 1601 .max_register = SMA1303_FF_DEVICE_INDEX, 1602 .readable_reg = sma1303_readable_register, 1603 .writeable_reg = sma1303_writeable_register, 1604 .volatile_reg = sma1303_volatile_register, 1605 1606 .cache_type = REGCACHE_NONE, 1607 .reg_defaults = sma1303_reg_def, 1608 .num_reg_defaults = ARRAY_SIZE(sma1303_reg_def), 1609 }; 1610 1611 static ssize_t check_fault_period_show(struct device *dev, 1612 struct device_attribute *devattr, char *buf) 1613 { 1614 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1615 1616 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_period); 1617 } 1618 1619 static ssize_t check_fault_period_store(struct device *dev, 1620 struct device_attribute *devattr, const char *buf, size_t count) 1621 { 1622 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1623 int ret; 1624 1625 ret = kstrtol(buf, 10, &sma1303->check_fault_period); 1626 1627 if (ret) 1628 return -EINVAL; 1629 1630 return (ssize_t)count; 1631 } 1632 1633 static DEVICE_ATTR_RW(check_fault_period); 1634 1635 static ssize_t check_fault_status_show(struct device *dev, 1636 struct device_attribute *devattr, char *buf) 1637 { 1638 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1639 1640 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_status); 1641 } 1642 1643 static ssize_t check_fault_status_store(struct device *dev, 1644 struct device_attribute *devattr, const char *buf, size_t count) 1645 { 1646 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1647 int ret; 1648 1649 ret = kstrtol(buf, 10, &sma1303->check_fault_status); 1650 1651 if (ret) 1652 return -EINVAL; 1653 1654 if (sma1303->check_fault_status) { 1655 if (sma1303->check_fault_period > 0) 1656 queue_delayed_work(system_freezable_wq, 1657 &sma1303->check_fault_work, 1658 sma1303->check_fault_period * HZ); 1659 else 1660 queue_delayed_work(system_freezable_wq, 1661 &sma1303->check_fault_work, 1662 CHECK_PERIOD_TIME * HZ); 1663 } 1664 1665 return (ssize_t)count; 1666 } 1667 1668 static DEVICE_ATTR_RW(check_fault_status); 1669 1670 static struct attribute *sma1303_attr[] = { 1671 &dev_attr_check_fault_period.attr, 1672 &dev_attr_check_fault_status.attr, 1673 NULL, 1674 }; 1675 1676 static struct attribute_group sma1303_attr_group = { 1677 .attrs = sma1303_attr, 1678 }; 1679 1680 static int sma1303_i2c_probe(struct i2c_client *client) 1681 { 1682 struct sma1303_priv *sma1303; 1683 struct device_node *np = client->dev.of_node; 1684 int ret, i = 0; 1685 u32 value = 0; 1686 unsigned int device_info, status, otp_stat; 1687 1688 sma1303 = devm_kzalloc(&client->dev, 1689 sizeof(struct sma1303_priv), GFP_KERNEL); 1690 if (!sma1303) 1691 return -ENOMEM; 1692 sma1303->dev = &client->dev; 1693 1694 sma1303->regmap = devm_regmap_init_i2c(client, &sma_i2c_regmap); 1695 if (IS_ERR(sma1303->regmap)) { 1696 ret = PTR_ERR(sma1303->regmap); 1697 dev_err(&client->dev, 1698 "Failed to allocate register map: %d\n", ret); 1699 1700 return ret; 1701 } 1702 1703 if (np) { 1704 if (!of_property_read_u32(np, "sys-clk-id", &value)) { 1705 switch (value) { 1706 case SMA1303_EXTERNAL_CLOCK_19_2: 1707 case SMA1303_EXTERNAL_CLOCK_24_576: 1708 case SMA1303_PLL_CLKIN_MCLK: 1709 dev_dbg(&client->dev, "MCLK is not supported\n"); 1710 break; 1711 case SMA1303_PLL_CLKIN_BCLK: 1712 dev_dbg(&client->dev, 1713 "Take an BCLK(SCK) and covert it to an internal PLL for use\n"); 1714 break; 1715 default: 1716 dev_err(&client->dev, 1717 "Invalid sys-clk-id: %u\n", value); 1718 return -EINVAL; 1719 } 1720 sma1303->sys_clk_id = value; 1721 } else { 1722 dev_dbg(&client->dev, "Use the internal PLL clock by default\n"); 1723 sma1303->sys_clk_id = SMA1303_PLL_CLKIN_BCLK; 1724 } 1725 } else { 1726 dev_err(&client->dev, 1727 "device node initialization error\n"); 1728 devm_kfree(&client->dev, sma1303); 1729 return -ENODEV; 1730 } 1731 1732 ret = sma1303_regmap_read(sma1303, 1733 SMA1303_FF_DEVICE_INDEX, &device_info); 1734 1735 if ((ret != 0) || ((device_info & 0xF8) != SMA1303_DEVICE_ID)) { 1736 dev_err(&client->dev, "device initialization error (%d 0x%02X)", 1737 ret, device_info); 1738 } 1739 dev_dbg(&client->dev, "chip version 0x%02X\n", device_info); 1740 1741 ret += sma1303_regmap_update_bits(sma1303, 1742 SMA1303_00_SYSTEM_CTRL, 1743 SMA1303_RESETBYI2C_MASK, SMA1303_RESETBYI2C_RESET, 1744 NULL); 1745 1746 ret += sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &status); 1747 sma1303->rev_num = status & SMA1303_REV_NUM_STATUS; 1748 if (sma1303->rev_num == SMA1303_REV_NUM_TV0) 1749 dev_dbg(&client->dev, "SMA1303 Trimming Version 0\n"); 1750 else if (sma1303->rev_num == SMA1303_REV_NUM_TV1) 1751 dev_dbg(&client->dev, "SMA1303 Trimming Version 1\n"); 1752 1753 ret += sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &otp_stat); 1754 if (ret < 0) 1755 dev_err(&client->dev, 1756 "failed to read, register: %02X, ret: %d\n", 1757 SMA1303_FF_DEVICE_INDEX, ret); 1758 1759 if (((sma1303->rev_num == SMA1303_REV_NUM_TV0) && 1760 ((otp_stat & 0x0E) == SMA1303_OTP_STAT_OK_0)) || 1761 ((sma1303->rev_num != SMA1303_REV_NUM_TV0) && 1762 ((otp_stat & 0x0C) == SMA1303_OTP_STAT_OK_1))) 1763 dev_dbg(&client->dev, "SMA1303 OTP Status Successful\n"); 1764 else 1765 dev_dbg(&client->dev, "SMA1303 OTP Status Fail\n"); 1766 1767 for (i = 0; i < (unsigned int)ARRAY_SIZE(sma1303_reg_def); i++) 1768 ret += sma1303_regmap_write(sma1303, 1769 sma1303_reg_def[i].reg, 1770 sma1303_reg_def[i].def); 1771 1772 sma1303->amp_mode = SMA1303_MONO; 1773 sma1303->amp_power_status = false; 1774 sma1303->check_fault_period = CHECK_PERIOD_TIME; 1775 sma1303->check_fault_status = true; 1776 sma1303->force_mute_status = false; 1777 sma1303->init_vol = 0x31; 1778 sma1303->cur_vol = sma1303->init_vol; 1779 sma1303->last_bclk = 0; 1780 sma1303->last_ocp_val = 0x08; 1781 sma1303->last_over_temp = 0xC0; 1782 sma1303->tsdw_cnt = 0; 1783 sma1303->retry_cnt = SMA1303_I2C_RETRY_COUNT; 1784 sma1303->tdm_slot_rx = 0; 1785 sma1303->tdm_slot_tx = 0; 1786 1787 sma1303->dev = &client->dev; 1788 sma1303->kobj = &client->dev.kobj; 1789 1790 INIT_DELAYED_WORK(&sma1303->check_fault_work, 1791 sma1303_check_fault_worker); 1792 1793 i2c_set_clientdata(client, sma1303); 1794 1795 sma1303->pll_matches = sma1303_pll_matches; 1796 sma1303->num_of_pll_matches = 1797 ARRAY_SIZE(sma1303_pll_matches); 1798 1799 ret = devm_snd_soc_register_component(&client->dev, 1800 &sma1303_component, sma1303_dai, 1); 1801 if (ret) { 1802 dev_err(&client->dev, "Failed to register component"); 1803 1804 return ret; 1805 } 1806 1807 sma1303->attr_grp = &sma1303_attr_group; 1808 ret = sysfs_create_group(sma1303->kobj, sma1303->attr_grp); 1809 if (ret) { 1810 dev_err(&client->dev, 1811 "failed to create attribute group [%d]\n", ret); 1812 sma1303->attr_grp = NULL; 1813 } 1814 1815 return ret; 1816 } 1817 1818 static void sma1303_i2c_remove(struct i2c_client *client) 1819 { 1820 struct sma1303_priv *sma1303 = 1821 (struct sma1303_priv *) i2c_get_clientdata(client); 1822 1823 cancel_delayed_work_sync(&sma1303->check_fault_work); 1824 } 1825 1826 static const struct i2c_device_id sma1303_i2c_id[] = { 1827 {"sma1303", 0}, 1828 {} 1829 }; 1830 MODULE_DEVICE_TABLE(i2c, sma1303_i2c_id); 1831 1832 static const struct of_device_id sma1303_of_match[] = { 1833 { .compatible = "irondevice,sma1303", }, 1834 { } 1835 }; 1836 MODULE_DEVICE_TABLE(of, sma1303_of_match); 1837 1838 static struct i2c_driver sma1303_i2c_driver = { 1839 .driver = { 1840 .name = "sma1303", 1841 .of_match_table = sma1303_of_match, 1842 }, 1843 .probe_new = sma1303_i2c_probe, 1844 .remove = sma1303_i2c_remove, 1845 .id_table = sma1303_i2c_id, 1846 }; 1847 1848 module_i2c_driver(sma1303_i2c_driver); 1849 1850 MODULE_DESCRIPTION("ALSA SoC SMA1303 driver"); 1851 MODULE_AUTHOR("Gyuhwa Park, <gyuhwa.park@irondevice.com>"); 1852 MODULE_AUTHOR("Kiseok Jo, <kiseok.jo@irondevice.com>"); 1853 MODULE_LICENSE("GPL v2"); 1854