1 // SPDX-License-Identifier: GPL-2.0-or-later 2 // 3 // sma1303.c -- sma1303 ALSA SoC Audio driver 4 // 5 // Copyright 2023 Iron Device Corporation 6 // 7 // Auther: Gyuhwa Park <gyuhwa.park@irondevice.com> 8 // Kiseok Jo <kiseok.jo@irondevice.com> 9 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <linux/slab.h> 26 #include <asm/div64.h> 27 28 #include "sma1303.h" 29 30 #define CHECK_PERIOD_TIME 1 /* sec per HZ */ 31 #define MAX_CONTROL_NAME 48 32 33 #define PLL_MATCH(_input_clk_name, _output_clk_name, _input_clk,\ 34 _post_n, _n, _vco, _p_cp)\ 35 {\ 36 .input_clk_name = _input_clk_name,\ 37 .output_clk_name = _output_clk_name,\ 38 .input_clk = _input_clk,\ 39 .post_n = _post_n,\ 40 .n = _n,\ 41 .vco = _vco,\ 42 .p_cp = _p_cp,\ 43 } 44 45 enum sma1303_type { 46 SMA1303, 47 }; 48 49 struct sma1303_pll_match { 50 char *input_clk_name; 51 char *output_clk_name; 52 unsigned int input_clk; 53 unsigned int post_n; 54 unsigned int n; 55 unsigned int vco; 56 unsigned int p_cp; 57 }; 58 59 struct sma1303_priv { 60 enum sma1303_type devtype; 61 struct attribute_group *attr_grp; 62 struct delayed_work check_fault_work; 63 struct device *dev; 64 struct kobject *kobj; 65 struct regmap *regmap; 66 struct sma1303_pll_match *pll_matches; 67 bool amp_power_status; 68 bool force_mute_status; 69 int num_of_pll_matches; 70 int retry_cnt; 71 unsigned int amp_mode; 72 unsigned int cur_vol; 73 unsigned int format; 74 unsigned int frame_size; 75 unsigned int init_vol; 76 unsigned int last_bclk; 77 unsigned int last_ocp_val; 78 unsigned int last_over_temp; 79 unsigned int rev_num; 80 unsigned int sys_clk_id; 81 unsigned int tdm_slot_rx; 82 unsigned int tdm_slot_tx; 83 unsigned int tsdw_cnt; 84 long check_fault_period; 85 long check_fault_status; 86 }; 87 88 static struct sma1303_pll_match sma1303_pll_matches[] = { 89 PLL_MATCH("1.411MHz", "24.595MHz", 1411200, 0x07, 0xF4, 0x8B, 0x03), 90 PLL_MATCH("1.536MHz", "24.576MHz", 1536000, 0x07, 0xE0, 0x8B, 0x03), 91 PLL_MATCH("3.072MHz", "24.576MHz", 3072000, 0x07, 0x70, 0x8B, 0x03), 92 PLL_MATCH("6.144MHz", "24.576MHz", 6144000, 0x07, 0x70, 0x8B, 0x07), 93 PLL_MATCH("12.288MHz", "24.576MHz", 12288000, 0x07, 0x70, 0x8B, 0x0B), 94 PLL_MATCH("19.2MHz", "24.343MHz", 19200000, 0x07, 0x47, 0x8B, 0x0A), 95 PLL_MATCH("24.576MHz", "24.576MHz", 24576000, 0x07, 0x70, 0x8B, 0x0F), 96 }; 97 98 static int sma1303_startup(struct snd_soc_component *); 99 static int sma1303_shutdown(struct snd_soc_component *); 100 101 static const struct reg_default sma1303_reg_def[] = { 102 { 0x00, 0x80 }, 103 { 0x01, 0x00 }, 104 { 0x02, 0x00 }, 105 { 0x03, 0x11 }, 106 { 0x04, 0x17 }, 107 { 0x09, 0x00 }, 108 { 0x0A, 0x31 }, 109 { 0x0B, 0x98 }, 110 { 0x0C, 0x84 }, 111 { 0x0D, 0x07 }, 112 { 0x0E, 0x3F }, 113 { 0x10, 0x00 }, 114 { 0x11, 0x00 }, 115 { 0x12, 0x00 }, 116 { 0x14, 0x5C }, 117 { 0x15, 0x01 }, 118 { 0x16, 0x0F }, 119 { 0x17, 0x0F }, 120 { 0x18, 0x0F }, 121 { 0x19, 0x00 }, 122 { 0x1A, 0x00 }, 123 { 0x1B, 0x00 }, 124 { 0x23, 0x19 }, 125 { 0x24, 0x00 }, 126 { 0x25, 0x00 }, 127 { 0x26, 0x04 }, 128 { 0x33, 0x00 }, 129 { 0x36, 0x92 }, 130 { 0x37, 0x27 }, 131 { 0x3B, 0x5A }, 132 { 0x3C, 0x20 }, 133 { 0x3D, 0x00 }, 134 { 0x3E, 0x03 }, 135 { 0x3F, 0x0C }, 136 { 0x8B, 0x07 }, 137 { 0x8C, 0x70 }, 138 { 0x8D, 0x8B }, 139 { 0x8E, 0x6F }, 140 { 0x8F, 0x03 }, 141 { 0x90, 0x26 }, 142 { 0x91, 0x42 }, 143 { 0x92, 0xE0 }, 144 { 0x94, 0x35 }, 145 { 0x95, 0x0C }, 146 { 0x96, 0x42 }, 147 { 0x97, 0x95 }, 148 { 0xA0, 0x00 }, 149 { 0xA1, 0x3B }, 150 { 0xA2, 0xC8 }, 151 { 0xA3, 0x28 }, 152 { 0xA4, 0x40 }, 153 { 0xA5, 0x01 }, 154 { 0xA6, 0x41 }, 155 { 0xA7, 0x00 }, 156 }; 157 158 static bool sma1303_readable_register(struct device *dev, unsigned int reg) 159 { 160 bool result; 161 162 if (reg > SMA1303_FF_DEVICE_INDEX) 163 return false; 164 165 switch (reg) { 166 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4: 167 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL: 168 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3: 169 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7: 170 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4: 171 case SMA1303_33_SDM_CTRL ... SMA1303_34_OTP_DATA1: 172 case SMA1303_36_PROTECTION ... SMA1303_38_OTP_TRM0: 173 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2: 174 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL: 175 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4: 176 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON: 177 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2: 178 result = true; 179 break; 180 case SMA1303_FF_DEVICE_INDEX: 181 result = true; 182 break; 183 default: 184 result = false; 185 break; 186 } 187 return result; 188 } 189 190 static bool sma1303_writeable_register(struct device *dev, unsigned int reg) 191 { 192 bool result; 193 194 if (reg > SMA1303_FF_DEVICE_INDEX) 195 return false; 196 197 switch (reg) { 198 case SMA1303_00_SYSTEM_CTRL ... SMA1303_04_INPUT1_CTRL4: 199 case SMA1303_09_OUTPUT_CTRL ... SMA1303_0E_MUTE_VOL_CTRL: 200 case SMA1303_10_SYSTEM_CTRL1 ... SMA1303_12_SYSTEM_CTRL3: 201 case SMA1303_14_MODULATOR ... SMA1303_1B_BASS_SPK7: 202 case SMA1303_23_COMP_LIM1 ... SMA1303_26_COMP_LIM4: 203 case SMA1303_33_SDM_CTRL: 204 case SMA1303_36_PROTECTION ... SMA1303_37_SLOPE_CTRL: 205 case SMA1303_3B_TEST1 ... SMA1303_3F_ATEST2: 206 case SMA1303_8B_PLL_POST_N ... SMA1303_92_FDPEC_CTRL: 207 case SMA1303_94_BOOST_CTRL1 ... SMA1303_97_BOOST_CTRL4: 208 case SMA1303_A0_PAD_CTRL0 ... SMA1303_A7_CLK_MON: 209 result = true; 210 break; 211 default: 212 result = false; 213 break; 214 } 215 return result; 216 } 217 218 static bool sma1303_volatile_register(struct device *dev, unsigned int reg) 219 { 220 bool result; 221 222 switch (reg) { 223 case SMA1303_FA_STATUS1 ... SMA1303_FB_STATUS2: 224 result = true; 225 break; 226 case SMA1303_FF_DEVICE_INDEX: 227 result = true; 228 break; 229 default: 230 result = false; 231 break; 232 } 233 return result; 234 } 235 236 static const DECLARE_TLV_DB_SCALE(sma1303_spk_tlv, -6000, 50, 0); 237 238 static int sma1303_regmap_write(struct sma1303_priv *sma1303, 239 unsigned int reg, unsigned int val) 240 { 241 int ret = 0; 242 int cnt = sma1303->retry_cnt; 243 244 while (cnt--) { 245 ret = regmap_write(sma1303->regmap, reg, val); 246 if (ret < 0) { 247 dev_err(sma1303->dev, 248 "Failed to write [0x%02X]\n", reg); 249 } else 250 break; 251 } 252 return ret; 253 } 254 255 static int sma1303_regmap_update_bits(struct sma1303_priv *sma1303, 256 unsigned int reg, unsigned int mask, unsigned int val, bool *change) 257 { 258 int ret = 0; 259 int cnt = sma1303->retry_cnt; 260 261 while (cnt--) { 262 ret = regmap_update_bits_check(sma1303->regmap, reg, 263 mask, val, change); 264 if (ret < 0) { 265 dev_err(sma1303->dev, 266 "Failed to update [0x%02X]\n", reg); 267 } else 268 break; 269 } 270 return ret; 271 } 272 273 static int sma1303_regmap_read(struct sma1303_priv *sma1303, 274 unsigned int reg, unsigned int *val) 275 { 276 int ret = 0; 277 int cnt = sma1303->retry_cnt; 278 279 while (cnt--) { 280 ret = regmap_read(sma1303->regmap, reg, val); 281 if (ret < 0) { 282 dev_err(sma1303->dev, 283 "Failed to read [0x%02X]\n", reg); 284 } else 285 break; 286 } 287 return ret; 288 } 289 290 static const char * const sma1303_aif_in_source_text[] = { 291 "Mono", "Left", "Right"}; 292 static const char * const sma1303_aif_out_source_text[] = { 293 "Disable", "After_FmtC", "After_Mixer", "After_DSP", "After_Post", 294 "Clk_PLL", "Clk_OSC"}; 295 static const char * const sma1303_tdm_slot_text[] = { 296 "Slot0", "Slot1", "Slot2", "Slot3", 297 "Slot4", "Slot5", "Slot6", "Slot7"}; 298 299 static const struct soc_enum sma1303_aif_in_source_enum = 300 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_in_source_text), 301 sma1303_aif_in_source_text); 302 static const struct soc_enum sma1303_aif_out_source_enum = 303 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_aif_out_source_text), 304 sma1303_aif_out_source_text); 305 static const struct soc_enum sma1303_tdm_slot_enum = 306 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sma1303_tdm_slot_text), 307 sma1303_tdm_slot_text); 308 309 static int sma1303_force_mute_get(struct snd_kcontrol *kcontrol, 310 struct snd_ctl_elem_value *ucontrol) 311 { 312 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 313 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 314 315 ucontrol->value.integer.value[0] = (int)sma1303->force_mute_status; 316 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__, 317 sma1303->force_mute_status ? "ON" : "OFF"); 318 319 return 0; 320 } 321 322 static int sma1303_force_mute_put(struct snd_kcontrol *kcontrol, 323 struct snd_ctl_elem_value *ucontrol) 324 { 325 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 326 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 327 bool change = false, val = (bool)ucontrol->value.integer.value[0]; 328 329 if (sma1303->force_mute_status == val) 330 change = false; 331 else { 332 change = true; 333 sma1303->force_mute_status = val; 334 } 335 dev_dbg(sma1303->dev, "%s : Force Mute %s\n", __func__, 336 sma1303->force_mute_status ? "ON" : "OFF"); 337 338 return change; 339 } 340 341 static int sma1303_postscaler_get(struct snd_kcontrol *kcontrol, 342 struct snd_ctl_elem_value *ucontrol) 343 { 344 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 345 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 346 int val, ret; 347 348 ret = sma1303_regmap_read(sma1303, SMA1303_90_POSTSCALER, &val); 349 if (ret < 0) 350 return -EINVAL; 351 352 ucontrol->value.integer.value[0] = (val & 0x7E) >> 1; 353 354 return 0; 355 } 356 357 static int sma1303_postscaler_put(struct snd_kcontrol *kcontrol, 358 struct snd_ctl_elem_value *ucontrol) 359 { 360 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 361 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 362 int ret, val = (int)ucontrol->value.integer.value[0]; 363 bool change; 364 365 ret = sma1303_regmap_update_bits(sma1303, 366 SMA1303_90_POSTSCALER, 0x7E, (val << 1), &change); 367 if (ret < 0) 368 return -EINVAL; 369 370 return change; 371 } 372 373 static int sma1303_tdm_slot_rx_get(struct snd_kcontrol *kcontrol, 374 struct snd_ctl_elem_value *ucontrol) 375 { 376 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 377 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 378 int val, ret; 379 380 ret = sma1303_regmap_read(sma1303, SMA1303_A5_TDM1, &val); 381 if (ret < 0) 382 return -EINVAL; 383 384 ucontrol->value.integer.value[0] = (val & 0x38) >> 3; 385 sma1303->tdm_slot_rx = ucontrol->value.integer.value[0]; 386 387 return 0; 388 } 389 390 static int sma1303_tdm_slot_rx_put(struct snd_kcontrol *kcontrol, 391 struct snd_ctl_elem_value *ucontrol) 392 { 393 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 394 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 395 int ret, val = (int)ucontrol->value.integer.value[0]; 396 bool change; 397 398 ret = sma1303_regmap_update_bits(sma1303, 399 SMA1303_A5_TDM1, 0x38, (val << 3), &change); 400 if (ret < 0) 401 return -EINVAL; 402 403 return change; 404 } 405 406 static int sma1303_tdm_slot_tx_get(struct snd_kcontrol *kcontrol, 407 struct snd_ctl_elem_value *ucontrol) 408 { 409 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 410 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 411 int val, ret; 412 413 ret = sma1303_regmap_read(sma1303, SMA1303_A6_TDM2, &val); 414 if (ret < 0) 415 return -EINVAL; 416 417 ucontrol->value.integer.value[0] = (val & 0x38) >> 3; 418 sma1303->tdm_slot_tx = ucontrol->value.integer.value[0]; 419 420 return 0; 421 } 422 423 static int sma1303_tdm_slot_tx_put(struct snd_kcontrol *kcontrol, 424 struct snd_ctl_elem_value *ucontrol) 425 { 426 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 427 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 428 int ret, val = (int)ucontrol->value.integer.value[0]; 429 bool change; 430 431 ret = sma1303_regmap_update_bits(sma1303, 432 SMA1303_A6_TDM2, 0x38, (val << 3), &change); 433 if (ret < 0) 434 return -EINVAL; 435 436 return change; 437 } 438 439 static int sma1303_startup(struct snd_soc_component *component) 440 { 441 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 442 bool change = false, temp = false; 443 444 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL, 445 SMA1303_PLL_PD2_MASK, SMA1303_PLL_OPERATION2, &temp); 446 if (temp == true) 447 change = true; 448 449 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL, 450 SMA1303_POWER_MASK, SMA1303_POWER_ON, &temp); 451 if (temp == true) 452 change = true; 453 454 if (sma1303->amp_mode == SMA1303_MONO) { 455 sma1303_regmap_update_bits(sma1303, 456 SMA1303_10_SYSTEM_CTRL1, 457 SMA1303_SPK_MODE_MASK, 458 SMA1303_SPK_MONO, 459 &temp); 460 if (temp == true) 461 change = true; 462 463 } else { 464 sma1303_regmap_update_bits(sma1303, 465 SMA1303_10_SYSTEM_CTRL1, 466 SMA1303_SPK_MODE_MASK, 467 SMA1303_SPK_STEREO, 468 &temp); 469 if (temp == true) 470 change = true; 471 } 472 473 if (sma1303->check_fault_status) { 474 if (sma1303->check_fault_period > 0) 475 queue_delayed_work(system_freezable_wq, 476 &sma1303->check_fault_work, 477 sma1303->check_fault_period * HZ); 478 else 479 queue_delayed_work(system_freezable_wq, 480 &sma1303->check_fault_work, 481 CHECK_PERIOD_TIME * HZ); 482 } 483 484 sma1303->amp_power_status = true; 485 486 return change; 487 } 488 489 static int sma1303_shutdown(struct snd_soc_component *component) 490 { 491 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 492 bool change = false, temp = false; 493 494 cancel_delayed_work_sync(&sma1303->check_fault_work); 495 496 sma1303_regmap_update_bits(sma1303, SMA1303_10_SYSTEM_CTRL1, 497 SMA1303_SPK_MODE_MASK, SMA1303_SPK_OFF, &temp); 498 if (temp == true) 499 change = true; 500 501 sma1303_regmap_update_bits(sma1303, SMA1303_00_SYSTEM_CTRL, 502 SMA1303_POWER_MASK, SMA1303_POWER_OFF, &temp); 503 if (temp == true) 504 change = true; 505 sma1303_regmap_update_bits(sma1303, SMA1303_8E_PLL_CTRL, 506 SMA1303_PLL_PD2_MASK, SMA1303_PLL_PD2, &temp); 507 if (temp == true) 508 change = true; 509 510 sma1303->amp_power_status = false; 511 512 return change; 513 } 514 515 static int sma1303_aif_in_event(struct snd_soc_dapm_widget *w, 516 struct snd_kcontrol *kcontrol, int event) 517 { 518 struct snd_soc_component *component = 519 snd_soc_dapm_to_component(w->dapm); 520 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 521 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 522 int ret = 0; 523 bool change = false, temp = false; 524 525 switch (event) { 526 case SND_SOC_DAPM_PRE_PMU: 527 switch (mux) { 528 case 0: 529 ret += sma1303_regmap_update_bits(sma1303, 530 SMA1303_11_SYSTEM_CTRL2, 531 SMA1303_MONOMIX_MASK, 532 SMA1303_MONOMIX_ON, 533 &change); 534 sma1303->amp_mode = SMA1303_MONO; 535 break; 536 case 1: 537 ret += sma1303_regmap_update_bits(sma1303, 538 SMA1303_11_SYSTEM_CTRL2, 539 SMA1303_MONOMIX_MASK, 540 SMA1303_MONOMIX_OFF, 541 &temp); 542 if (temp == true) 543 change = true; 544 ret += sma1303_regmap_update_bits(sma1303, 545 SMA1303_11_SYSTEM_CTRL2, 546 SMA1303_LR_DATA_SW_MASK, 547 SMA1303_LR_DATA_SW_NORMAL, 548 &temp); 549 if (temp == true) 550 change = true; 551 sma1303->amp_mode = SMA1303_STEREO; 552 break; 553 case 2: 554 ret += sma1303_regmap_update_bits(sma1303, 555 SMA1303_11_SYSTEM_CTRL2, 556 SMA1303_MONOMIX_MASK, 557 SMA1303_MONOMIX_OFF, 558 &temp); 559 if (temp == true) 560 change = true; 561 ret += sma1303_regmap_update_bits(sma1303, 562 SMA1303_11_SYSTEM_CTRL2, 563 SMA1303_LR_DATA_SW_MASK, 564 SMA1303_LR_DATA_SW_SWAP, 565 &temp); 566 if (temp == true) 567 change = true; 568 sma1303->amp_mode = SMA1303_STEREO; 569 break; 570 default: 571 dev_err(sma1303->dev, "%s : Invalid value (%d)\n", 572 __func__, mux); 573 return -EINVAL; 574 } 575 576 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__, 577 sma1303_aif_in_source_text[mux]); 578 break; 579 } 580 if (ret < 0) 581 return -EINVAL; 582 return change; 583 } 584 585 static int sma1303_aif_out_event(struct snd_soc_dapm_widget *w, 586 struct snd_kcontrol *kcontrol, int event) 587 { 588 struct snd_soc_component *component = 589 snd_soc_dapm_to_component(w->dapm); 590 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 591 unsigned int mux = snd_soc_dapm_kcontrol_get_value(w->kcontrols[0]); 592 int ret = 0; 593 bool change = false, temp = false; 594 595 switch (event) { 596 case SND_SOC_DAPM_PRE_PMU: 597 switch (mux) { 598 case 0: 599 ret += sma1303_regmap_update_bits(sma1303, 600 SMA1303_A3_TOP_MAN2, 601 SMA1303_TEST_CLKO_EN_MASK, 602 SMA1303_NORMAL_SDO, 603 &temp); 604 if (temp == true) 605 change = true; 606 ret += sma1303_regmap_update_bits(sma1303, 607 SMA1303_09_OUTPUT_CTRL, 608 SMA1303_PORT_OUT_SEL_MASK, 609 SMA1303_OUT_SEL_DISABLE, 610 &temp); 611 if (temp == true) 612 change = true; 613 break; 614 case 1: 615 ret += sma1303_regmap_update_bits(sma1303, 616 SMA1303_A3_TOP_MAN2, 617 SMA1303_TEST_CLKO_EN_MASK, 618 SMA1303_NORMAL_SDO, 619 &temp); 620 if (temp == true) 621 change = true; 622 ret += sma1303_regmap_update_bits(sma1303, 623 SMA1303_09_OUTPUT_CTRL, 624 SMA1303_PORT_OUT_SEL_MASK, 625 SMA1303_FORMAT_CONVERTER, 626 &temp); 627 if (temp == true) 628 change = true; 629 break; 630 case 2: 631 ret += sma1303_regmap_update_bits(sma1303, 632 SMA1303_A3_TOP_MAN2, 633 SMA1303_TEST_CLKO_EN_MASK, 634 SMA1303_NORMAL_SDO, 635 &temp); 636 if (temp == true) 637 change = true; 638 ret += sma1303_regmap_update_bits(sma1303, 639 SMA1303_09_OUTPUT_CTRL, 640 SMA1303_PORT_OUT_SEL_MASK, 641 SMA1303_MIXER_OUTPUT, 642 &temp); 643 if (temp == true) 644 change = true; 645 break; 646 case 3: 647 ret += sma1303_regmap_update_bits(sma1303, 648 SMA1303_A3_TOP_MAN2, 649 SMA1303_TEST_CLKO_EN_MASK, 650 SMA1303_NORMAL_SDO, 651 &temp); 652 if (temp == true) 653 change = true; 654 ret += sma1303_regmap_update_bits(sma1303, 655 SMA1303_09_OUTPUT_CTRL, 656 SMA1303_PORT_OUT_SEL_MASK, 657 SMA1303_SPEAKER_PATH, 658 &temp); 659 if (temp == true) 660 change = true; 661 break; 662 case 4: 663 ret += sma1303_regmap_update_bits(sma1303, 664 SMA1303_A3_TOP_MAN2, 665 SMA1303_TEST_CLKO_EN_MASK, 666 SMA1303_NORMAL_SDO, 667 &temp); 668 if (temp == true) 669 change = true; 670 ret += sma1303_regmap_update_bits(sma1303, 671 SMA1303_09_OUTPUT_CTRL, 672 SMA1303_PORT_OUT_SEL_MASK, 673 SMA1303_POSTSCALER_OUTPUT, 674 &temp); 675 if (temp == true) 676 change = true; 677 break; 678 case 5: 679 ret += sma1303_regmap_update_bits(sma1303, 680 SMA1303_A3_TOP_MAN2, 681 SMA1303_TEST_CLKO_EN_MASK, 682 SMA1303_CLK_OUT_SDO, 683 &temp); 684 if (temp == true) 685 change = true; 686 ret += sma1303_regmap_update_bits(sma1303, 687 SMA1303_A3_TOP_MAN2, 688 SMA1303_MON_OSC_PLL_MASK, 689 SMA1303_PLL_SDO, 690 &temp); 691 if (temp == true) 692 change = true; 693 break; 694 case 6: 695 ret += sma1303_regmap_update_bits(sma1303, 696 SMA1303_A3_TOP_MAN2, 697 SMA1303_TEST_CLKO_EN_MASK, 698 SMA1303_CLK_OUT_SDO, 699 &temp); 700 if (temp == true) 701 change = true; 702 ret += sma1303_regmap_update_bits(sma1303, 703 SMA1303_A3_TOP_MAN2, 704 SMA1303_MON_OSC_PLL_MASK, 705 SMA1303_OSC_SDO, 706 &temp); 707 if (temp == true) 708 change = true; 709 break; 710 default: 711 dev_err(sma1303->dev, "%s : Invalid value (%d)\n", 712 __func__, mux); 713 return -EINVAL; 714 } 715 716 dev_dbg(sma1303->dev, "%s : Source : %s\n", __func__, 717 sma1303_aif_out_source_text[mux]); 718 break; 719 } 720 if (ret < 0) 721 return -EINVAL; 722 return change; 723 } 724 725 static int sma1303_sdo_event(struct snd_soc_dapm_widget *w, 726 struct snd_kcontrol *kcontrol, int event) 727 { 728 struct snd_soc_component *component = 729 snd_soc_dapm_to_component(w->dapm); 730 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 731 int ret = 0; 732 bool change = false, temp = false; 733 734 switch (event) { 735 case SND_SOC_DAPM_PRE_PMU: 736 dev_dbg(sma1303->dev, 737 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__); 738 ret += sma1303_regmap_update_bits(sma1303, 739 SMA1303_09_OUTPUT_CTRL, 740 SMA1303_PORT_CONFIG_MASK, 741 SMA1303_OUTPUT_PORT_ENABLE, 742 &temp); 743 if (temp == true) 744 change = true; 745 ret += sma1303_regmap_update_bits(sma1303, 746 SMA1303_A3_TOP_MAN2, 747 SMA1303_SDO_OUTPUT_MASK, 748 SMA1303_NORMAL_OUT, 749 &temp); 750 if (temp == true) 751 change = true; 752 break; 753 case SND_SOC_DAPM_POST_PMD: 754 dev_dbg(sma1303->dev, 755 "%s : SND_SOC_DAPM_POST_PMD\n", __func__); 756 ret += sma1303_regmap_update_bits(sma1303, 757 SMA1303_09_OUTPUT_CTRL, 758 SMA1303_PORT_CONFIG_MASK, 759 SMA1303_INPUT_PORT_ONLY, 760 &temp); 761 if (temp == true) 762 change = true; 763 ret += sma1303_regmap_update_bits(sma1303, 764 SMA1303_A3_TOP_MAN2, 765 SMA1303_SDO_OUTPUT_MASK, 766 SMA1303_HIGH_Z_OUT, 767 &temp); 768 if (temp == true) 769 change = true; 770 break; 771 } 772 if (ret < 0) 773 return -EINVAL; 774 return change; 775 } 776 777 static int sma1303_post_scaler_event(struct snd_soc_dapm_widget *w, 778 struct snd_kcontrol *kcontrol, int event) 779 { 780 struct snd_soc_component *component = 781 snd_soc_dapm_to_component(w->dapm); 782 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 783 int ret = 0; 784 bool change = false; 785 786 switch (event) { 787 case SND_SOC_DAPM_PRE_PMU: 788 dev_dbg(sma1303->dev, 789 "%s : SND_SOC_DAPM_PRE_PMU\n", __func__); 790 ret += sma1303_regmap_update_bits(sma1303, 791 SMA1303_90_POSTSCALER, 792 SMA1303_BYP_POST_MASK, 793 SMA1303_EN_POST_SCALER, 794 &change); 795 break; 796 case SND_SOC_DAPM_POST_PMD: 797 dev_dbg(sma1303->dev, 798 "%s : SND_SOC_DAPM_POST_PMD\n", __func__); 799 ret += sma1303_regmap_update_bits(sma1303, 800 SMA1303_90_POSTSCALER, 801 SMA1303_BYP_POST_MASK, 802 SMA1303_BYP_POST_SCALER, 803 &change); 804 break; 805 } 806 if (ret < 0) 807 return -EINVAL; 808 return change; 809 } 810 811 static int sma1303_power_event(struct snd_soc_dapm_widget *w, 812 struct snd_kcontrol *kcontrol, int event) 813 { 814 struct snd_soc_component *component = 815 snd_soc_dapm_to_component(w->dapm); 816 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 817 int ret = 0; 818 819 switch (event) { 820 case SND_SOC_DAPM_POST_PMU: 821 dev_dbg(sma1303->dev, 822 "%s : SND_SOC_DAPM_POST_PMU\n", __func__); 823 ret = sma1303_startup(component); 824 break; 825 case SND_SOC_DAPM_PRE_PMD: 826 dev_dbg(sma1303->dev, 827 "%s : SND_SOC_DAPM_PRE_PMD\n", __func__); 828 ret = sma1303_shutdown(component); 829 break; 830 } 831 return ret; 832 } 833 834 static const struct snd_kcontrol_new sma1303_aif_in_source_control = 835 SOC_DAPM_ENUM("AIF IN Source", sma1303_aif_in_source_enum); 836 static const struct snd_kcontrol_new sma1303_aif_out_source_control = 837 SOC_DAPM_ENUM("AIF OUT Source", sma1303_aif_out_source_enum); 838 static const struct snd_kcontrol_new sma1303_sdo_control = 839 SOC_DAPM_SINGLE_VIRT("Switch", 1); 840 static const struct snd_kcontrol_new sma1303_post_scaler_control = 841 SOC_DAPM_SINGLE_VIRT("Switch", 1); 842 static const struct snd_kcontrol_new sma1303_enable_control = 843 SOC_DAPM_SINGLE_VIRT("Switch", 1); 844 845 static const struct snd_kcontrol_new sma1303_snd_controls[] = { 846 SOC_SINGLE_TLV("Speaker Volume", SMA1303_0A_SPK_VOL, 847 0, 167, 1, sma1303_spk_tlv), 848 SOC_SINGLE_BOOL_EXT("Force Mute Switch", 0, 849 sma1303_force_mute_get, sma1303_force_mute_put), 850 SOC_SINGLE_EXT("Postscaler Gain", SMA1303_90_POSTSCALER, 1, 0x30, 0, 851 sma1303_postscaler_get, sma1303_postscaler_put), 852 SOC_ENUM_EXT("TDM RX Slot Position", sma1303_tdm_slot_enum, 853 sma1303_tdm_slot_rx_get, sma1303_tdm_slot_rx_put), 854 SOC_ENUM_EXT("TDM TX Slot Position", sma1303_tdm_slot_enum, 855 sma1303_tdm_slot_tx_get, sma1303_tdm_slot_tx_put), 856 }; 857 858 static const struct snd_soc_dapm_widget sma1303_dapm_widgets[] = { 859 /* platform domain */ 860 SND_SOC_DAPM_OUTPUT("SPK"), 861 SND_SOC_DAPM_INPUT("SDO"), 862 863 /* path domain */ 864 SND_SOC_DAPM_MUX_E("AIF IN Source", SND_SOC_NOPM, 0, 0, 865 &sma1303_aif_in_source_control, 866 sma1303_aif_in_event, 867 SND_SOC_DAPM_PRE_PMU), 868 SND_SOC_DAPM_MUX_E("AIF OUT Source", SND_SOC_NOPM, 0, 0, 869 &sma1303_aif_out_source_control, 870 sma1303_aif_out_event, 871 SND_SOC_DAPM_PRE_PMU), 872 SND_SOC_DAPM_SWITCH_E("SDO Enable", SND_SOC_NOPM, 0, 0, 873 &sma1303_sdo_control, 874 sma1303_sdo_event, 875 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 876 SND_SOC_DAPM_MIXER("Entry", SND_SOC_NOPM, 0, 0, NULL, 0), 877 SND_SOC_DAPM_SWITCH_E("Post Scaler", SND_SOC_NOPM, 0, 1, 878 &sma1303_post_scaler_control, 879 sma1303_post_scaler_event, 880 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 881 SND_SOC_DAPM_OUT_DRV_E("AMP Power", SND_SOC_NOPM, 0, 0, NULL, 0, 882 sma1303_power_event, 883 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 884 SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, 885 &sma1303_enable_control), 886 887 /* stream domain */ 888 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 889 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 890 }; 891 892 static const struct snd_soc_dapm_route sma1303_audio_map[] = { 893 /* Playback */ 894 {"AIF IN Source", "Mono", "AIF IN"}, 895 {"AIF IN Source", "Left", "AIF IN"}, 896 {"AIF IN Source", "Right", "AIF IN"}, 897 898 {"SDO Enable", "Switch", "AIF IN"}, 899 {"AIF OUT Source", "Disable", "SDO Enable"}, 900 {"AIF OUT Source", "After_FmtC", "SDO Enable"}, 901 {"AIF OUT Source", "After_Mixer", "SDO Enable"}, 902 {"AIF OUT Source", "After_DSP", "SDO Enable"}, 903 {"AIF OUT Source", "After_Post", "SDO Enable"}, 904 {"AIF OUT Source", "Clk_PLL", "SDO Enable"}, 905 {"AIF OUT Source", "Clk_OSC", "SDO Enable"}, 906 907 {"Entry", NULL, "AIF OUT Source"}, 908 {"Entry", NULL, "AIF IN Source"}, 909 910 {"Post Scaler", "Switch", "Entry"}, 911 {"AMP Power", NULL, "Entry"}, 912 {"AMP Power", NULL, "Entry"}, 913 914 {"AMP Enable", "Switch", "AMP Power"}, 915 {"SPK", NULL, "AMP Enable"}, 916 917 /* Capture */ 918 {"AIF OUT", NULL, "AMP Enable"}, 919 }; 920 921 static int sma1303_setup_pll(struct snd_soc_component *component, 922 unsigned int bclk) 923 { 924 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 925 926 int i = 0, ret = 0; 927 928 dev_dbg(component->dev, "%s : BCLK = %dHz\n", 929 __func__, bclk); 930 931 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_MCLK) { 932 dev_dbg(component->dev, "%s : MCLK is not supported\n", 933 __func__); 934 } else if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) { 935 for (i = 0; i < sma1303->num_of_pll_matches; i++) { 936 if (sma1303->pll_matches[i].input_clk == bclk) 937 break; 938 } 939 if (i == sma1303->num_of_pll_matches) { 940 dev_dbg(component->dev, "%s : No matching value between pll table and SCK\n", 941 __func__); 942 return -EINVAL; 943 } 944 945 ret += sma1303_regmap_update_bits(sma1303, 946 SMA1303_A2_TOP_MAN1, 947 SMA1303_PLL_PD_MASK|SMA1303_PLL_REF_CLK_MASK, 948 SMA1303_PLL_OPERATION|SMA1303_PLL_SCK, 949 NULL); 950 } 951 952 ret += sma1303_regmap_write(sma1303, 953 SMA1303_8B_PLL_POST_N, 954 sma1303->pll_matches[i].post_n); 955 956 ret += sma1303_regmap_write(sma1303, 957 SMA1303_8C_PLL_N, 958 sma1303->pll_matches[i].n); 959 960 ret += sma1303_regmap_write(sma1303, 961 SMA1303_8D_PLL_A_SETTING, 962 sma1303->pll_matches[i].vco); 963 964 ret += sma1303_regmap_write(sma1303, 965 SMA1303_8F_PLL_P_CP, 966 sma1303->pll_matches[i].p_cp); 967 if (ret < 0) 968 return -EINVAL; 969 970 return 0; 971 } 972 973 static int sma1303_dai_hw_params_amp(struct snd_pcm_substream *substream, 974 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 975 { 976 struct snd_soc_component *component = dai->component; 977 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 978 unsigned int bclk = 0; 979 int ret = 0; 980 981 if (sma1303->format == SND_SOC_DAIFMT_DSP_A) 982 bclk = params_rate(params) * sma1303->frame_size; 983 else 984 bclk = params_rate(params) * params_physical_width(params) 985 * params_channels(params); 986 987 dev_dbg(component->dev, 988 "%s : rate = %d : bit size = %d : channel = %d\n", 989 __func__, params_rate(params), params_width(params), 990 params_channels(params)); 991 992 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 993 if (sma1303->sys_clk_id == SMA1303_PLL_CLKIN_BCLK) { 994 if (sma1303->last_bclk != bclk) { 995 sma1303_setup_pll(component, bclk); 996 sma1303->last_bclk = bclk; 997 } 998 } 999 1000 switch (params_rate(params)) { 1001 case 8000: 1002 case 12000: 1003 case 16000: 1004 case 24000: 1005 case 32000: 1006 case 44100: 1007 case 48000: 1008 case 96000: 1009 ret += sma1303_regmap_update_bits(sma1303, 1010 SMA1303_A2_TOP_MAN1, 1011 SMA1303_DAC_DN_CONV_MASK, 1012 SMA1303_DAC_DN_CONV_DISABLE, 1013 NULL); 1014 1015 ret += sma1303_regmap_update_bits(sma1303, 1016 SMA1303_01_INPUT1_CTRL1, 1017 SMA1303_LEFTPOL_MASK, 1018 SMA1303_LOW_FIRST_CH, 1019 NULL); 1020 break; 1021 1022 case 192000: 1023 ret += sma1303_regmap_update_bits(sma1303, 1024 SMA1303_A2_TOP_MAN1, 1025 SMA1303_DAC_DN_CONV_MASK, 1026 SMA1303_DAC_DN_CONV_ENABLE, 1027 NULL); 1028 1029 ret += sma1303_regmap_update_bits(sma1303, 1030 SMA1303_01_INPUT1_CTRL1, 1031 SMA1303_LEFTPOL_MASK, 1032 SMA1303_HIGH_FIRST_CH, 1033 NULL); 1034 break; 1035 1036 default: 1037 dev_err(component->dev, "%s not support rate : %d\n", 1038 __func__, params_rate(params)); 1039 1040 return -EINVAL; 1041 } 1042 1043 } else { 1044 1045 switch (params_format(params)) { 1046 1047 case SNDRV_PCM_FORMAT_S16_LE: 1048 dev_dbg(component->dev, 1049 "%s set format SNDRV_PCM_FORMAT_S16_LE\n", 1050 __func__); 1051 ret += sma1303_regmap_update_bits(sma1303, 1052 SMA1303_A4_TOP_MAN3, 1053 SMA1303_SCK_RATE_MASK, 1054 SMA1303_SCK_32FS, 1055 NULL); 1056 break; 1057 1058 case SNDRV_PCM_FORMAT_S24_LE: 1059 dev_dbg(component->dev, 1060 "%s set format SNDRV_PCM_FORMAT_S24_LE\n", 1061 __func__); 1062 ret += sma1303_regmap_update_bits(sma1303, 1063 SMA1303_A4_TOP_MAN3, 1064 SMA1303_SCK_RATE_MASK, 1065 SMA1303_SCK_64FS, 1066 NULL); 1067 break; 1068 case SNDRV_PCM_FORMAT_S32_LE: 1069 dev_dbg(component->dev, 1070 "%s set format SNDRV_PCM_FORMAT_S32_LE\n", 1071 __func__); 1072 ret += sma1303_regmap_update_bits(sma1303, 1073 SMA1303_A4_TOP_MAN3, 1074 SMA1303_SCK_RATE_MASK, 1075 SMA1303_SCK_64FS, 1076 NULL); 1077 break; 1078 default: 1079 dev_err(component->dev, 1080 "%s not support data bit : %d\n", __func__, 1081 params_format(params)); 1082 return -EINVAL; 1083 } 1084 } 1085 1086 switch (sma1303->format) { 1087 case SND_SOC_DAIFMT_I2S: 1088 ret += sma1303_regmap_update_bits(sma1303, 1089 SMA1303_01_INPUT1_CTRL1, 1090 SMA1303_I2S_MODE_MASK, 1091 SMA1303_STANDARD_I2S, 1092 NULL); 1093 ret += sma1303_regmap_update_bits(sma1303, 1094 SMA1303_A4_TOP_MAN3, 1095 SMA1303_O_FORMAT_MASK, 1096 SMA1303_O_FMT_I2S, 1097 NULL); 1098 break; 1099 case SND_SOC_DAIFMT_LEFT_J: 1100 ret += sma1303_regmap_update_bits(sma1303, 1101 SMA1303_01_INPUT1_CTRL1, 1102 SMA1303_I2S_MODE_MASK, 1103 SMA1303_LJ, 1104 NULL); 1105 ret += sma1303_regmap_update_bits(sma1303, 1106 SMA1303_A4_TOP_MAN3, 1107 SMA1303_O_FORMAT_MASK, 1108 SMA1303_O_FMT_LJ, 1109 NULL); 1110 break; 1111 case SND_SOC_DAIFMT_RIGHT_J: 1112 switch (params_width(params)) { 1113 case 16: 1114 ret += sma1303_regmap_update_bits(sma1303, 1115 SMA1303_01_INPUT1_CTRL1, 1116 SMA1303_I2S_MODE_MASK, 1117 SMA1303_RJ_16BIT, 1118 NULL); 1119 break; 1120 case 24: 1121 case 32: 1122 ret += sma1303_regmap_update_bits(sma1303, 1123 SMA1303_01_INPUT1_CTRL1, 1124 SMA1303_I2S_MODE_MASK, 1125 SMA1303_RJ_24BIT, 1126 NULL); 1127 break; 1128 } 1129 break; 1130 case SND_SOC_DAIFMT_DSP_A: 1131 ret += sma1303_regmap_update_bits(sma1303, 1132 SMA1303_01_INPUT1_CTRL1, 1133 SMA1303_I2S_MODE_MASK, 1134 SMA1303_STANDARD_I2S, 1135 NULL); 1136 ret += sma1303_regmap_update_bits(sma1303, 1137 SMA1303_A4_TOP_MAN3, 1138 SMA1303_O_FORMAT_MASK, 1139 SMA1303_O_FMT_TDM, 1140 NULL); 1141 break; 1142 } 1143 1144 switch (params_width(params)) { 1145 case 16: 1146 case 24: 1147 case 32: 1148 break; 1149 default: 1150 dev_err(component->dev, 1151 "%s not support data bit : %d\n", __func__, 1152 params_format(params)); 1153 return -EINVAL; 1154 } 1155 if (ret < 0) 1156 return -EINVAL; 1157 1158 return 0; 1159 } 1160 1161 static int sma1303_dai_set_sysclk_amp(struct snd_soc_dai *dai, 1162 int clk_id, unsigned int freq, int dir) 1163 { 1164 struct snd_soc_component *component = dai->component; 1165 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1166 1167 switch (clk_id) { 1168 case SMA1303_EXTERNAL_CLOCK_19_2: 1169 break; 1170 case SMA1303_EXTERNAL_CLOCK_24_576: 1171 break; 1172 case SMA1303_PLL_CLKIN_MCLK: 1173 break; 1174 case SMA1303_PLL_CLKIN_BCLK: 1175 break; 1176 default: 1177 dev_err(component->dev, "Invalid clk id: %d\n", clk_id); 1178 return -EINVAL; 1179 } 1180 sma1303->sys_clk_id = clk_id; 1181 return 0; 1182 } 1183 1184 static int sma1303_dai_mute(struct snd_soc_dai *dai, int mute, int stream) 1185 { 1186 struct snd_soc_component *component = dai->component; 1187 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1188 int ret = 0; 1189 1190 if (stream == SNDRV_PCM_STREAM_CAPTURE) 1191 return ret; 1192 1193 if (mute) { 1194 dev_dbg(component->dev, "%s : %s\n", __func__, "MUTE"); 1195 1196 ret += sma1303_regmap_update_bits(sma1303, 1197 SMA1303_0E_MUTE_VOL_CTRL, 1198 SMA1303_SPK_MUTE_MASK, 1199 SMA1303_SPK_MUTE, 1200 NULL); 1201 1202 /* Need to wait time for mute slope */ 1203 msleep(55); 1204 } else { 1205 if (!sma1303->force_mute_status) { 1206 dev_dbg(component->dev, "%s : %s\n", 1207 __func__, "UNMUTE"); 1208 ret += sma1303_regmap_update_bits(sma1303, 1209 SMA1303_0E_MUTE_VOL_CTRL, 1210 SMA1303_SPK_MUTE_MASK, 1211 SMA1303_SPK_UNMUTE, 1212 NULL); 1213 } else { 1214 dev_dbg(sma1303->dev, 1215 "%s : FORCE MUTE!!!\n", __func__); 1216 } 1217 } 1218 1219 if (ret < 0) 1220 return -EINVAL; 1221 return 0; 1222 } 1223 1224 static int sma1303_dai_set_fmt_amp(struct snd_soc_dai *dai, 1225 unsigned int fmt) 1226 { 1227 struct snd_soc_component *component = dai->component; 1228 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1229 int ret = 0; 1230 1231 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1232 1233 case SND_SOC_DAIFMT_CBC_CFC: 1234 dev_dbg(component->dev, 1235 "%s : %s\n", __func__, "I2S/TDM Device mode"); 1236 ret += sma1303_regmap_update_bits(sma1303, 1237 SMA1303_01_INPUT1_CTRL1, 1238 SMA1303_CONTROLLER_DEVICE_MASK, 1239 SMA1303_DEVICE_MODE, 1240 NULL); 1241 break; 1242 1243 case SND_SOC_DAIFMT_CBP_CFP: 1244 dev_dbg(component->dev, 1245 "%s : %s\n", __func__, "I2S/TDM Controller mode"); 1246 ret += sma1303_regmap_update_bits(sma1303, 1247 SMA1303_01_INPUT1_CTRL1, 1248 SMA1303_CONTROLLER_DEVICE_MASK, 1249 SMA1303_CONTROLLER_MODE, 1250 NULL); 1251 break; 1252 1253 default: 1254 dev_err(component->dev, 1255 "Unsupported Controller/Device : 0x%x\n", fmt); 1256 return -EINVAL; 1257 } 1258 1259 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1260 1261 case SND_SOC_DAIFMT_I2S: 1262 case SND_SOC_DAIFMT_RIGHT_J: 1263 case SND_SOC_DAIFMT_LEFT_J: 1264 case SND_SOC_DAIFMT_DSP_A: 1265 case SND_SOC_DAIFMT_DSP_B: 1266 sma1303->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1267 break; 1268 default: 1269 dev_err(component->dev, 1270 "Unsupported Audio Interface Format : 0x%x\n", fmt); 1271 return -EINVAL; 1272 } 1273 1274 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1275 1276 case SND_SOC_DAIFMT_IB_NF: 1277 dev_dbg(component->dev, "%s : %s\n", 1278 __func__, "Invert BCLK + Normal Frame"); 1279 ret += sma1303_regmap_update_bits(sma1303, 1280 SMA1303_01_INPUT1_CTRL1, 1281 SMA1303_SCK_RISING_MASK, 1282 SMA1303_SCK_RISING_EDGE, 1283 NULL); 1284 break; 1285 case SND_SOC_DAIFMT_IB_IF: 1286 dev_dbg(component->dev, "%s : %s\n", 1287 __func__, "Invert BCLK + Invert Frame"); 1288 ret += sma1303_regmap_update_bits(sma1303, 1289 SMA1303_01_INPUT1_CTRL1, 1290 SMA1303_LEFTPOL_MASK|SMA1303_SCK_RISING_MASK, 1291 SMA1303_HIGH_FIRST_CH|SMA1303_SCK_RISING_EDGE, 1292 NULL); 1293 break; 1294 case SND_SOC_DAIFMT_NB_IF: 1295 dev_dbg(component->dev, "%s : %s\n", 1296 __func__, "Normal BCLK + Invert Frame"); 1297 ret += sma1303_regmap_update_bits(sma1303, 1298 SMA1303_01_INPUT1_CTRL1, 1299 SMA1303_LEFTPOL_MASK, 1300 SMA1303_HIGH_FIRST_CH, 1301 NULL); 1302 break; 1303 case SND_SOC_DAIFMT_NB_NF: 1304 dev_dbg(component->dev, "%s : %s\n", 1305 __func__, "Normal BCLK + Normal Frame"); 1306 break; 1307 default: 1308 dev_err(component->dev, 1309 "Unsupported Bit & Frameclock : 0x%x\n", fmt); 1310 return -EINVAL; 1311 } 1312 1313 if (ret < 0) 1314 return -EINVAL; 1315 return 0; 1316 } 1317 1318 static int sma1303_dai_set_tdm_slot(struct snd_soc_dai *dai, 1319 unsigned int tx_mask, unsigned int rx_mask, 1320 int slots, int slot_width) 1321 { 1322 struct snd_soc_component *component = dai->component; 1323 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1324 int ret = 0; 1325 1326 dev_dbg(component->dev, "%s : slots = %d, slot_width - %d\n", 1327 __func__, slots, slot_width); 1328 1329 sma1303->frame_size = slot_width * slots; 1330 1331 ret += sma1303_regmap_update_bits(sma1303, 1332 SMA1303_A4_TOP_MAN3, 1333 SMA1303_O_FORMAT_MASK, 1334 SMA1303_O_FMT_TDM, 1335 NULL); 1336 1337 switch (slot_width) { 1338 case 16: 1339 ret += sma1303_regmap_update_bits(sma1303, 1340 SMA1303_A6_TDM2, 1341 SMA1303_TDM_DL_MASK, 1342 SMA1303_TDM_DL_16, 1343 NULL); 1344 break; 1345 case 32: 1346 ret += sma1303_regmap_update_bits(sma1303, 1347 SMA1303_A6_TDM2, 1348 SMA1303_TDM_DL_MASK, 1349 SMA1303_TDM_DL_32, 1350 NULL); 1351 break; 1352 default: 1353 dev_err(component->dev, "%s not support TDM %d slot_width\n", 1354 __func__, slot_width); 1355 break; 1356 } 1357 1358 switch (slots) { 1359 case 4: 1360 ret += sma1303_regmap_update_bits(sma1303, 1361 SMA1303_A6_TDM2, 1362 SMA1303_TDM_N_SLOT_MASK, 1363 SMA1303_TDM_N_SLOT_4, 1364 NULL); 1365 break; 1366 case 8: 1367 ret += sma1303_regmap_update_bits(sma1303, 1368 SMA1303_A6_TDM2, 1369 SMA1303_TDM_N_SLOT_MASK, 1370 SMA1303_TDM_N_SLOT_8, 1371 NULL); 1372 break; 1373 default: 1374 dev_err(component->dev, "%s not support TDM %d slots\n", 1375 __func__, slots); 1376 break; 1377 } 1378 1379 if (sma1303->tdm_slot_rx < slots) 1380 ret += sma1303_regmap_update_bits(sma1303, 1381 SMA1303_A5_TDM1, 1382 SMA1303_TDM_SLOT1_RX_POS_MASK, 1383 (sma1303->tdm_slot_rx) << 3, 1384 NULL); 1385 else 1386 dev_err(component->dev, "%s Incorrect tdm-slot-rx %d set\n", 1387 __func__, sma1303->tdm_slot_rx); 1388 1389 ret += sma1303_regmap_update_bits(sma1303, 1390 SMA1303_A5_TDM1, 1391 SMA1303_TDM_CLK_POL_MASK, 1392 SMA1303_TDM_CLK_POL_RISE, 1393 NULL); 1394 1395 ret += sma1303_regmap_update_bits(sma1303, 1396 SMA1303_A5_TDM1, 1397 SMA1303_TDM_TX_MODE_MASK, 1398 SMA1303_TDM_TX_MONO, 1399 NULL); 1400 1401 if (sma1303->tdm_slot_tx < slots) 1402 ret += sma1303_regmap_update_bits(sma1303, 1403 SMA1303_A6_TDM2, 1404 SMA1303_TDM_SLOT1_TX_POS_MASK, 1405 (sma1303->tdm_slot_tx) << 3, 1406 NULL); 1407 else 1408 dev_err(component->dev, "%s Incorrect tdm-slot-tx %d set\n", 1409 __func__, sma1303->tdm_slot_tx); 1410 1411 if (ret < 0) 1412 return -EINVAL; 1413 return 0; 1414 } 1415 1416 static const struct snd_soc_dai_ops sma1303_dai_ops_amp = { 1417 .set_sysclk = sma1303_dai_set_sysclk_amp, 1418 .set_fmt = sma1303_dai_set_fmt_amp, 1419 .hw_params = sma1303_dai_hw_params_amp, 1420 .mute_stream = sma1303_dai_mute, 1421 .set_tdm_slot = sma1303_dai_set_tdm_slot, 1422 }; 1423 1424 #define SMA1303_RATES SNDRV_PCM_RATE_8000_192000 1425 #define SMA1303_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1426 SNDRV_PCM_FMTBIT_S32_LE) 1427 1428 static struct snd_soc_dai_driver sma1303_dai[] = { 1429 { 1430 .name = "sma1303-amplifier", 1431 .id = 0, 1432 .playback = { 1433 .stream_name = "Playback", 1434 .channels_min = 1, 1435 .channels_max = 2, 1436 .rates = SMA1303_RATES, 1437 .formats = SMA1303_FORMATS, 1438 }, 1439 .capture = { 1440 .stream_name = "Capture", 1441 .channels_min = 1, 1442 .channels_max = 2, 1443 .rates = SMA1303_RATES, 1444 .formats = SMA1303_FORMATS, 1445 }, 1446 .ops = &sma1303_dai_ops_amp, 1447 }, 1448 }; 1449 1450 static void sma1303_check_fault_worker(struct work_struct *work) 1451 { 1452 struct sma1303_priv *sma1303 = 1453 container_of(work, struct sma1303_priv, check_fault_work.work); 1454 int ret = 0; 1455 unsigned int over_temp, ocp_val, uvlo_val; 1456 1457 if (sma1303->tsdw_cnt) 1458 ret = sma1303_regmap_read(sma1303, 1459 SMA1303_0A_SPK_VOL, &sma1303->cur_vol); 1460 else 1461 ret = sma1303_regmap_read(sma1303, 1462 SMA1303_0A_SPK_VOL, &sma1303->init_vol); 1463 1464 if (ret != 0) { 1465 dev_err(sma1303->dev, 1466 "failed to read SMA1303_0A_SPK_VOL : %d\n", ret); 1467 return; 1468 } 1469 1470 ret = sma1303_regmap_read(sma1303, SMA1303_FA_STATUS1, &over_temp); 1471 if (ret != 0) { 1472 dev_err(sma1303->dev, 1473 "failed to read SMA1303_FA_STATUS1 : %d\n", ret); 1474 return; 1475 } 1476 1477 ret = sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &ocp_val); 1478 if (ret != 0) { 1479 dev_err(sma1303->dev, 1480 "failed to read SMA1303_FB_STATUS2 : %d\n", ret); 1481 return; 1482 } 1483 1484 ret = sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &uvlo_val); 1485 if (ret != 0) { 1486 dev_err(sma1303->dev, 1487 "failed to read SMA1303_FF_DEVICE_INDEX : %d\n", ret); 1488 return; 1489 } 1490 1491 if (~over_temp & SMA1303_OT1_OK_STATUS) { 1492 dev_crit(sma1303->dev, 1493 "%s : OT1(Over Temperature Level 1)\n", __func__); 1494 1495 if ((sma1303->cur_vol + 6) <= 0xFF) 1496 sma1303_regmap_write(sma1303, 1497 SMA1303_0A_SPK_VOL, sma1303->cur_vol + 6); 1498 1499 sma1303->tsdw_cnt++; 1500 } else if (sma1303->tsdw_cnt) { 1501 sma1303_regmap_write(sma1303, 1502 SMA1303_0A_SPK_VOL, sma1303->init_vol); 1503 sma1303->tsdw_cnt = 0; 1504 sma1303->cur_vol = sma1303->init_vol; 1505 } 1506 1507 if (~over_temp & SMA1303_OT2_OK_STATUS) { 1508 dev_crit(sma1303->dev, 1509 "%s : OT2(Over Temperature Level 2)\n", __func__); 1510 } 1511 if (ocp_val & SMA1303_OCP_SPK_STATUS) { 1512 dev_crit(sma1303->dev, 1513 "%s : OCP_SPK(Over Current Protect SPK)\n", __func__); 1514 } 1515 if (ocp_val & SMA1303_OCP_BST_STATUS) { 1516 dev_crit(sma1303->dev, 1517 "%s : OCP_BST(Over Current Protect Boost)\n", __func__); 1518 } 1519 if ((ocp_val & SMA1303_CLK_MON_STATUS) && (sma1303->amp_power_status)) { 1520 dev_crit(sma1303->dev, 1521 "%s : CLK_FAULT(No clock input)\n", __func__); 1522 } 1523 if (uvlo_val & SMA1303_UVLO_BST_STATUS) { 1524 dev_crit(sma1303->dev, 1525 "%s : UVLO(Under Voltage Lock Out)\n", __func__); 1526 } 1527 1528 if ((over_temp != sma1303->last_over_temp) || 1529 (ocp_val != sma1303->last_ocp_val)) { 1530 1531 dev_crit(sma1303->dev, "Please check AMP status"); 1532 dev_dbg(sma1303->dev, "STATUS1=0x%02X : STATUS2=0x%02X\n", 1533 over_temp, ocp_val); 1534 sma1303->last_over_temp = over_temp; 1535 sma1303->last_ocp_val = ocp_val; 1536 } 1537 1538 if (sma1303->check_fault_status) { 1539 if (sma1303->check_fault_period > 0) 1540 queue_delayed_work(system_freezable_wq, 1541 &sma1303->check_fault_work, 1542 sma1303->check_fault_period * HZ); 1543 else 1544 queue_delayed_work(system_freezable_wq, 1545 &sma1303->check_fault_work, 1546 CHECK_PERIOD_TIME * HZ); 1547 } 1548 1549 if (!(~over_temp & SMA1303_OT1_OK_STATUS) 1550 && !(~over_temp & SMA1303_OT2_OK_STATUS) 1551 && !(ocp_val & SMA1303_OCP_SPK_STATUS) 1552 && !(ocp_val & SMA1303_OCP_BST_STATUS) 1553 && !(ocp_val & SMA1303_CLK_MON_STATUS) 1554 && !(uvlo_val & SMA1303_UVLO_BST_STATUS)) { 1555 } 1556 } 1557 1558 static int sma1303_probe(struct snd_soc_component *component) 1559 { 1560 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1561 1562 snd_soc_dapm_sync(dapm); 1563 1564 return 0; 1565 } 1566 1567 static void sma1303_remove(struct snd_soc_component *component) 1568 { 1569 struct sma1303_priv *sma1303 = snd_soc_component_get_drvdata(component); 1570 1571 cancel_delayed_work_sync(&sma1303->check_fault_work); 1572 } 1573 1574 static const struct snd_soc_component_driver sma1303_component = { 1575 .probe = sma1303_probe, 1576 .remove = sma1303_remove, 1577 .controls = sma1303_snd_controls, 1578 .num_controls = ARRAY_SIZE(sma1303_snd_controls), 1579 .dapm_widgets = sma1303_dapm_widgets, 1580 .num_dapm_widgets = ARRAY_SIZE(sma1303_dapm_widgets), 1581 .dapm_routes = sma1303_audio_map, 1582 .num_dapm_routes = ARRAY_SIZE(sma1303_audio_map), 1583 }; 1584 1585 static const struct regmap_config sma_i2c_regmap = { 1586 .reg_bits = 8, 1587 .val_bits = 8, 1588 1589 .max_register = SMA1303_FF_DEVICE_INDEX, 1590 .readable_reg = sma1303_readable_register, 1591 .writeable_reg = sma1303_writeable_register, 1592 .volatile_reg = sma1303_volatile_register, 1593 1594 .cache_type = REGCACHE_NONE, 1595 .reg_defaults = sma1303_reg_def, 1596 .num_reg_defaults = ARRAY_SIZE(sma1303_reg_def), 1597 }; 1598 1599 static ssize_t check_fault_period_show(struct device *dev, 1600 struct device_attribute *devattr, char *buf) 1601 { 1602 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1603 1604 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_period); 1605 } 1606 1607 static ssize_t check_fault_period_store(struct device *dev, 1608 struct device_attribute *devattr, const char *buf, size_t count) 1609 { 1610 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1611 int ret; 1612 1613 ret = kstrtol(buf, 10, &sma1303->check_fault_period); 1614 1615 if (ret) 1616 return -EINVAL; 1617 1618 return (ssize_t)count; 1619 } 1620 1621 static DEVICE_ATTR_RW(check_fault_period); 1622 1623 static ssize_t check_fault_status_show(struct device *dev, 1624 struct device_attribute *devattr, char *buf) 1625 { 1626 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1627 1628 return sysfs_emit(buf, "%ld\n", sma1303->check_fault_status); 1629 } 1630 1631 static ssize_t check_fault_status_store(struct device *dev, 1632 struct device_attribute *devattr, const char *buf, size_t count) 1633 { 1634 struct sma1303_priv *sma1303 = dev_get_drvdata(dev); 1635 int ret; 1636 1637 ret = kstrtol(buf, 10, &sma1303->check_fault_status); 1638 1639 if (ret) 1640 return -EINVAL; 1641 1642 if (sma1303->check_fault_status) { 1643 if (sma1303->check_fault_period > 0) 1644 queue_delayed_work(system_freezable_wq, 1645 &sma1303->check_fault_work, 1646 sma1303->check_fault_period * HZ); 1647 else 1648 queue_delayed_work(system_freezable_wq, 1649 &sma1303->check_fault_work, 1650 CHECK_PERIOD_TIME * HZ); 1651 } 1652 1653 return (ssize_t)count; 1654 } 1655 1656 static DEVICE_ATTR_RW(check_fault_status); 1657 1658 static struct attribute *sma1303_attr[] = { 1659 &dev_attr_check_fault_period.attr, 1660 &dev_attr_check_fault_status.attr, 1661 NULL, 1662 }; 1663 1664 static struct attribute_group sma1303_attr_group = { 1665 .attrs = sma1303_attr, 1666 }; 1667 1668 static int sma1303_i2c_probe(struct i2c_client *client) 1669 { 1670 struct sma1303_priv *sma1303; 1671 int ret, i = 0; 1672 unsigned int device_info, status, otp_stat; 1673 1674 sma1303 = devm_kzalloc(&client->dev, 1675 sizeof(struct sma1303_priv), GFP_KERNEL); 1676 if (!sma1303) 1677 return -ENOMEM; 1678 sma1303->dev = &client->dev; 1679 1680 sma1303->regmap = devm_regmap_init_i2c(client, &sma_i2c_regmap); 1681 if (IS_ERR(sma1303->regmap)) { 1682 ret = PTR_ERR(sma1303->regmap); 1683 dev_err(&client->dev, 1684 "Failed to allocate register map: %d\n", ret); 1685 1686 return ret; 1687 } 1688 1689 ret = sma1303_regmap_read(sma1303, 1690 SMA1303_FF_DEVICE_INDEX, &device_info); 1691 1692 if ((ret != 0) || ((device_info & 0xF8) != SMA1303_DEVICE_ID)) { 1693 dev_err(&client->dev, "device initialization error (%d 0x%02X)", 1694 ret, device_info); 1695 } 1696 dev_dbg(&client->dev, "chip version 0x%02X\n", device_info); 1697 1698 ret += sma1303_regmap_update_bits(sma1303, 1699 SMA1303_00_SYSTEM_CTRL, 1700 SMA1303_RESETBYI2C_MASK, SMA1303_RESETBYI2C_RESET, 1701 NULL); 1702 1703 ret += sma1303_regmap_read(sma1303, SMA1303_FF_DEVICE_INDEX, &status); 1704 sma1303->rev_num = status & SMA1303_REV_NUM_STATUS; 1705 if (sma1303->rev_num == SMA1303_REV_NUM_TV0) 1706 dev_dbg(&client->dev, "SMA1303 Trimming Version 0\n"); 1707 else if (sma1303->rev_num == SMA1303_REV_NUM_TV1) 1708 dev_dbg(&client->dev, "SMA1303 Trimming Version 1\n"); 1709 1710 ret += sma1303_regmap_read(sma1303, SMA1303_FB_STATUS2, &otp_stat); 1711 if (ret < 0) 1712 dev_err(&client->dev, 1713 "failed to read, register: %02X, ret: %d\n", 1714 SMA1303_FF_DEVICE_INDEX, ret); 1715 1716 if (((sma1303->rev_num == SMA1303_REV_NUM_TV0) && 1717 ((otp_stat & 0x0E) == SMA1303_OTP_STAT_OK_0)) || 1718 ((sma1303->rev_num != SMA1303_REV_NUM_TV0) && 1719 ((otp_stat & 0x0C) == SMA1303_OTP_STAT_OK_1))) 1720 dev_dbg(&client->dev, "SMA1303 OTP Status Successful\n"); 1721 else 1722 dev_dbg(&client->dev, "SMA1303 OTP Status Fail\n"); 1723 1724 for (i = 0; i < (unsigned int)ARRAY_SIZE(sma1303_reg_def); i++) 1725 ret += sma1303_regmap_write(sma1303, 1726 sma1303_reg_def[i].reg, 1727 sma1303_reg_def[i].def); 1728 1729 sma1303->amp_mode = SMA1303_MONO; 1730 sma1303->amp_power_status = false; 1731 sma1303->check_fault_period = CHECK_PERIOD_TIME; 1732 sma1303->check_fault_status = true; 1733 sma1303->force_mute_status = false; 1734 sma1303->init_vol = 0x31; 1735 sma1303->cur_vol = sma1303->init_vol; 1736 sma1303->last_bclk = 0; 1737 sma1303->last_ocp_val = 0x08; 1738 sma1303->last_over_temp = 0xC0; 1739 sma1303->tsdw_cnt = 0; 1740 sma1303->retry_cnt = SMA1303_I2C_RETRY_COUNT; 1741 sma1303->tdm_slot_rx = 0; 1742 sma1303->tdm_slot_tx = 0; 1743 sma1303->sys_clk_id = SMA1303_PLL_CLKIN_BCLK; 1744 1745 sma1303->dev = &client->dev; 1746 sma1303->kobj = &client->dev.kobj; 1747 1748 INIT_DELAYED_WORK(&sma1303->check_fault_work, 1749 sma1303_check_fault_worker); 1750 1751 i2c_set_clientdata(client, sma1303); 1752 1753 sma1303->pll_matches = sma1303_pll_matches; 1754 sma1303->num_of_pll_matches = 1755 ARRAY_SIZE(sma1303_pll_matches); 1756 1757 ret = devm_snd_soc_register_component(&client->dev, 1758 &sma1303_component, sma1303_dai, 1); 1759 if (ret) { 1760 dev_err(&client->dev, "Failed to register component"); 1761 1762 return ret; 1763 } 1764 1765 sma1303->attr_grp = &sma1303_attr_group; 1766 ret = sysfs_create_group(sma1303->kobj, sma1303->attr_grp); 1767 if (ret) { 1768 dev_err(&client->dev, 1769 "failed to create attribute group [%d]\n", ret); 1770 sma1303->attr_grp = NULL; 1771 } 1772 1773 return ret; 1774 } 1775 1776 static void sma1303_i2c_remove(struct i2c_client *client) 1777 { 1778 struct sma1303_priv *sma1303 = 1779 (struct sma1303_priv *) i2c_get_clientdata(client); 1780 1781 cancel_delayed_work_sync(&sma1303->check_fault_work); 1782 } 1783 1784 static const struct i2c_device_id sma1303_i2c_id[] = { 1785 {"sma1303"}, 1786 {} 1787 }; 1788 MODULE_DEVICE_TABLE(i2c, sma1303_i2c_id); 1789 1790 static const struct of_device_id sma1303_of_match[] = { 1791 { .compatible = "irondevice,sma1303", }, 1792 { } 1793 }; 1794 MODULE_DEVICE_TABLE(of, sma1303_of_match); 1795 1796 static struct i2c_driver sma1303_i2c_driver = { 1797 .driver = { 1798 .name = "sma1303", 1799 .of_match_table = sma1303_of_match, 1800 }, 1801 .probe = sma1303_i2c_probe, 1802 .remove = sma1303_i2c_remove, 1803 .id_table = sma1303_i2c_id, 1804 }; 1805 1806 module_i2c_driver(sma1303_i2c_driver); 1807 1808 MODULE_DESCRIPTION("ALSA SoC SMA1303 driver"); 1809 MODULE_AUTHOR("Gyuhwa Park, <gyuhwa.park@irondevice.com>"); 1810 MODULE_AUTHOR("Kiseok Jo, <kiseok.jo@irondevice.com>"); 1811 MODULE_LICENSE("GPL v2"); 1812