1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/log2.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/driver.h> 22 #include <linux/regulator/machine.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/of_device.h> 25 #include <sound/core.h> 26 #include <sound/tlv.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 33 #include "sgtl5000.h" 34 35 #define SGTL5000_DAP_REG_OFFSET 0x0100 36 #define SGTL5000_MAX_REG_OFFSET 0x013A 37 38 /* default value of sgtl5000 registers */ 39 static const struct reg_default sgtl5000_reg_defaults[] = { 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 }, 41 { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, 42 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 43 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 44 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, 45 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 46 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 47 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, 48 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 49 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 50 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 }, 51 { SGTL5000_CHIP_REF_CTRL, 0x0000 }, 52 { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, 53 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, 54 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 55 { SGTL5000_CHIP_ANA_POWER, 0x7060 }, 56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, 58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, 59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, 60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, 61 { SGTL5000_DAP_CTRL, 0x0000 }, 62 { SGTL5000_DAP_PEQ, 0x0000 }, 63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, 66 { SGTL5000_DAP_SURROUND, 0x0040 }, 67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 73 { SGTL5000_DAP_MIX_CHAN, 0x0000 }, 74 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 77 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 78 }; 79 80 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 81 enum sgtl5000_regulator_supplies { 82 VDDA, 83 VDDIO, 84 VDDD, 85 SGTL5000_SUPPLY_NUM 86 }; 87 88 /* vddd is optional supply */ 89 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 90 "VDDA", 91 "VDDIO", 92 "VDDD" 93 }; 94 95 #define LDO_CONSUMER_NAME "VDDD_LDO" 96 #define LDO_VOLTAGE 1200000 97 98 static struct regulator_consumer_supply ldo_consumer[] = { 99 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), 100 }; 101 102 static struct regulator_init_data ldo_init_data = { 103 .constraints = { 104 .min_uV = 1200000, 105 .max_uV = 1200000, 106 .valid_modes_mask = REGULATOR_MODE_NORMAL, 107 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 108 }, 109 .num_consumer_supplies = 1, 110 .consumer_supplies = &ldo_consumer[0], 111 }; 112 113 /* 114 * sgtl5000 internal ldo regulator, 115 * enabled when VDDD not provided 116 */ 117 struct ldo_regulator { 118 struct regulator_desc desc; 119 struct regulator_dev *dev; 120 int voltage; 121 void *codec_data; 122 bool enabled; 123 }; 124 125 enum sgtl5000_micbias_resistor { 126 SGTL5000_MICBIAS_OFF = 0, 127 SGTL5000_MICBIAS_2K = 2, 128 SGTL5000_MICBIAS_4K = 4, 129 SGTL5000_MICBIAS_8K = 8, 130 }; 131 132 /* sgtl5000 private structure in codec */ 133 struct sgtl5000_priv { 134 int sysclk; /* sysclk rate */ 135 int master; /* i2s master or not */ 136 int fmt; /* i2s data format */ 137 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 138 struct ldo_regulator *ldo; 139 struct regmap *regmap; 140 struct clk *mclk; 141 int revision; 142 u8 micbias_resistor; 143 u8 micbias_voltage; 144 }; 145 146 /* 147 * mic_bias power on/off share the same register bits with 148 * output impedance of mic bias, when power on mic bias, we 149 * need reclaim it to impedance value. 150 * 0x0 = Powered off 151 * 0x1 = 2Kohm 152 * 0x2 = 4Kohm 153 * 0x3 = 8Kohm 154 */ 155 static int mic_bias_event(struct snd_soc_dapm_widget *w, 156 struct snd_kcontrol *kcontrol, int event) 157 { 158 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(w->codec); 159 160 switch (event) { 161 case SND_SOC_DAPM_POST_PMU: 162 /* change mic bias resistor */ 163 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 164 SGTL5000_BIAS_R_MASK, 165 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 166 break; 167 168 case SND_SOC_DAPM_PRE_PMD: 169 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 170 SGTL5000_BIAS_R_MASK, 0); 171 break; 172 } 173 return 0; 174 } 175 176 /* 177 * As manual described, ADC/DAC only works when VAG powerup, 178 * So enabled VAG before ADC/DAC up. 179 * In power down case, we need wait 400ms when vag fully ramped down. 180 */ 181 static int power_vag_event(struct snd_soc_dapm_widget *w, 182 struct snd_kcontrol *kcontrol, int event) 183 { 184 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 185 186 switch (event) { 187 case SND_SOC_DAPM_POST_PMU: 188 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 189 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 190 break; 191 192 case SND_SOC_DAPM_PRE_PMD: 193 /* 194 * Don't clear VAG_POWERUP, when both DAC and ADC are 195 * operational to prevent inadvertently starving the 196 * other one of them. 197 */ 198 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) & 199 mask) != mask) { 200 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 201 SGTL5000_VAG_POWERUP, 0); 202 msleep(400); 203 } 204 break; 205 default: 206 break; 207 } 208 209 return 0; 210 } 211 212 /* input sources for ADC */ 213 static const char *adc_mux_text[] = { 214 "MIC_IN", "LINE_IN" 215 }; 216 217 static SOC_ENUM_SINGLE_DECL(adc_enum, 218 SGTL5000_CHIP_ANA_CTRL, 2, 219 adc_mux_text); 220 221 static const struct snd_kcontrol_new adc_mux = 222 SOC_DAPM_ENUM("Capture Mux", adc_enum); 223 224 /* input sources for DAC */ 225 static const char *dac_mux_text[] = { 226 "DAC", "LINE_IN" 227 }; 228 229 static SOC_ENUM_SINGLE_DECL(dac_enum, 230 SGTL5000_CHIP_ANA_CTRL, 6, 231 dac_mux_text); 232 233 static const struct snd_kcontrol_new dac_mux = 234 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 235 236 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 237 SND_SOC_DAPM_INPUT("LINE_IN"), 238 SND_SOC_DAPM_INPUT("MIC_IN"), 239 240 SND_SOC_DAPM_OUTPUT("HP_OUT"), 241 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 242 243 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 244 mic_bias_event, 245 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 246 247 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 248 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 249 250 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 251 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 252 253 /* aif for i2s input */ 254 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 255 0, SGTL5000_CHIP_DIG_POWER, 256 0, 0), 257 258 /* aif for i2s output */ 259 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 260 0, SGTL5000_CHIP_DIG_POWER, 261 1, 0), 262 263 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 264 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 265 266 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 267 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 268 }; 269 270 /* routes for sgtl5000 */ 271 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 272 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 273 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 274 275 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 276 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 277 278 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 279 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 280 {"LO", NULL, "DAC"}, /* dac --> line_out */ 281 282 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 283 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 284 285 {"LINE_OUT", NULL, "LO"}, 286 {"HP_OUT", NULL, "HP"}, 287 }; 288 289 /* custom function to fetch info of PCM playback volume */ 290 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 291 struct snd_ctl_elem_info *uinfo) 292 { 293 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 294 uinfo->count = 2; 295 uinfo->value.integer.min = 0; 296 uinfo->value.integer.max = 0xfc - 0x3c; 297 return 0; 298 } 299 300 /* 301 * custom function to get of PCM playback volume 302 * 303 * dac volume register 304 * 15-------------8-7--------------0 305 * | R channel vol | L channel vol | 306 * ------------------------------- 307 * 308 * PCM volume with 0.5017 dB steps from 0 to -90 dB 309 * 310 * register values map to dB 311 * 0x3B and less = Reserved 312 * 0x3C = 0 dB 313 * 0x3D = -0.5 dB 314 * 0xF0 = -90 dB 315 * 0xFC and greater = Muted 316 * 317 * register value map to userspace value 318 * 319 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 320 * ------------------------------ 321 * userspace value 0xc0 0 322 */ 323 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 324 struct snd_ctl_elem_value *ucontrol) 325 { 326 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 327 int reg; 328 int l; 329 int r; 330 331 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 332 333 /* get left channel volume */ 334 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 335 336 /* get right channel volume */ 337 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 338 339 /* make sure value fall in (0x3c,0xfc) */ 340 l = clamp(l, 0x3c, 0xfc); 341 r = clamp(r, 0x3c, 0xfc); 342 343 /* invert it and map to userspace value */ 344 l = 0xfc - l; 345 r = 0xfc - r; 346 347 ucontrol->value.integer.value[0] = l; 348 ucontrol->value.integer.value[1] = r; 349 350 return 0; 351 } 352 353 /* 354 * custom function to put of PCM playback volume 355 * 356 * dac volume register 357 * 15-------------8-7--------------0 358 * | R channel vol | L channel vol | 359 * ------------------------------- 360 * 361 * PCM volume with 0.5017 dB steps from 0 to -90 dB 362 * 363 * register values map to dB 364 * 0x3B and less = Reserved 365 * 0x3C = 0 dB 366 * 0x3D = -0.5 dB 367 * 0xF0 = -90 dB 368 * 0xFC and greater = Muted 369 * 370 * userspace value map to register value 371 * 372 * userspace value 0xc0 0 373 * ------------------------------ 374 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 375 */ 376 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 377 struct snd_ctl_elem_value *ucontrol) 378 { 379 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 380 int reg; 381 int l; 382 int r; 383 384 l = ucontrol->value.integer.value[0]; 385 r = ucontrol->value.integer.value[1]; 386 387 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 388 l = clamp(l, 0, 0xfc - 0x3c); 389 r = clamp(r, 0, 0xfc - 0x3c); 390 391 /* invert it, get the value can be set to register */ 392 l = 0xfc - l; 393 r = 0xfc - r; 394 395 /* shift to get the register value */ 396 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 397 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 398 399 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 400 401 return 0; 402 } 403 404 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 405 406 /* tlv for mic gain, 0db 20db 30db 40db */ 407 static const unsigned int mic_gain_tlv[] = { 408 TLV_DB_RANGE_HEAD(2), 409 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 410 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), 411 }; 412 413 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 414 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 415 416 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 417 /* SOC_DOUBLE_S8_TLV with invert */ 418 { 419 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 420 .name = "PCM Playback Volume", 421 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 422 SNDRV_CTL_ELEM_ACCESS_READWRITE, 423 .info = dac_info_volsw, 424 .get = dac_get_volsw, 425 .put = dac_put_volsw, 426 }, 427 428 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 429 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 430 SGTL5000_CHIP_ANA_ADC_CTRL, 431 8, 1, 0, capture_6db_attenuate), 432 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 433 434 SOC_DOUBLE_TLV("Headphone Playback Volume", 435 SGTL5000_CHIP_ANA_HP_CTRL, 436 0, 8, 437 0x7f, 1, 438 headphone_volume), 439 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 440 5, 1, 0), 441 442 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 443 0, 3, 0, mic_gain_tlv), 444 }; 445 446 /* mute the codec used by alsa core */ 447 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 448 { 449 struct snd_soc_codec *codec = codec_dai->codec; 450 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 451 452 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 453 adcdac_ctrl, mute ? adcdac_ctrl : 0); 454 455 return 0; 456 } 457 458 /* set codec format */ 459 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 460 { 461 struct snd_soc_codec *codec = codec_dai->codec; 462 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 463 u16 i2sctl = 0; 464 465 sgtl5000->master = 0; 466 /* 467 * i2s clock and frame master setting. 468 * ONLY support: 469 * - clock and frame slave, 470 * - clock and frame master 471 */ 472 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 473 case SND_SOC_DAIFMT_CBS_CFS: 474 break; 475 case SND_SOC_DAIFMT_CBM_CFM: 476 i2sctl |= SGTL5000_I2S_MASTER; 477 sgtl5000->master = 1; 478 break; 479 default: 480 return -EINVAL; 481 } 482 483 /* setting i2s data format */ 484 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 485 case SND_SOC_DAIFMT_DSP_A: 486 i2sctl |= SGTL5000_I2S_MODE_PCM; 487 break; 488 case SND_SOC_DAIFMT_DSP_B: 489 i2sctl |= SGTL5000_I2S_MODE_PCM; 490 i2sctl |= SGTL5000_I2S_LRALIGN; 491 break; 492 case SND_SOC_DAIFMT_I2S: 493 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 494 break; 495 case SND_SOC_DAIFMT_RIGHT_J: 496 i2sctl |= SGTL5000_I2S_MODE_RJ; 497 i2sctl |= SGTL5000_I2S_LRPOL; 498 break; 499 case SND_SOC_DAIFMT_LEFT_J: 500 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 501 i2sctl |= SGTL5000_I2S_LRALIGN; 502 break; 503 default: 504 return -EINVAL; 505 } 506 507 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 508 509 /* Clock inversion */ 510 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 511 case SND_SOC_DAIFMT_NB_NF: 512 break; 513 case SND_SOC_DAIFMT_IB_NF: 514 i2sctl |= SGTL5000_I2S_SCLK_INV; 515 break; 516 default: 517 return -EINVAL; 518 } 519 520 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 521 522 return 0; 523 } 524 525 /* set codec sysclk */ 526 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 527 int clk_id, unsigned int freq, int dir) 528 { 529 struct snd_soc_codec *codec = codec_dai->codec; 530 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 531 532 switch (clk_id) { 533 case SGTL5000_SYSCLK: 534 sgtl5000->sysclk = freq; 535 break; 536 default: 537 return -EINVAL; 538 } 539 540 return 0; 541 } 542 543 /* 544 * set clock according to i2s frame clock, 545 * sgtl5000 provides 2 clock sources: 546 * 1. sys_mclk: sample freq can only be configured to 547 * 1/256, 1/384, 1/512 of sys_mclk. 548 * 2. pll: can derive any audio clocks. 549 * 550 * clock setting rules: 551 * 1. in slave mode, only sys_mclk can be used 552 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz 553 * and above. 554 * 3. usage of sys_mclk is preferred over pll to save power. 555 */ 556 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 557 { 558 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 559 int clk_ctl = 0; 560 int sys_fs; /* sample freq */ 561 562 /* 563 * sample freq should be divided by frame clock, 564 * if frame clock is lower than 44.1 kHz, sample freq should be set to 565 * 32 kHz or 44.1 kHz. 566 */ 567 switch (frame_rate) { 568 case 8000: 569 case 16000: 570 sys_fs = 32000; 571 break; 572 case 11025: 573 case 22050: 574 sys_fs = 44100; 575 break; 576 default: 577 sys_fs = frame_rate; 578 break; 579 } 580 581 /* set divided factor of frame clock */ 582 switch (sys_fs / frame_rate) { 583 case 4: 584 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 585 break; 586 case 2: 587 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 588 break; 589 case 1: 590 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 591 break; 592 default: 593 return -EINVAL; 594 } 595 596 /* set the sys_fs according to frame rate */ 597 switch (sys_fs) { 598 case 32000: 599 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 600 break; 601 case 44100: 602 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 603 break; 604 case 48000: 605 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 606 break; 607 case 96000: 608 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 609 break; 610 default: 611 dev_err(codec->dev, "frame rate %d not supported\n", 612 frame_rate); 613 return -EINVAL; 614 } 615 616 /* 617 * calculate the divider of mclk/sample_freq, 618 * factor of freq = 96 kHz can only be 256, since mclk is in the range 619 * of 8 MHz - 27 MHz 620 */ 621 switch (sgtl5000->sysclk / frame_rate) { 622 case 256: 623 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 624 SGTL5000_MCLK_FREQ_SHIFT; 625 break; 626 case 384: 627 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 628 SGTL5000_MCLK_FREQ_SHIFT; 629 break; 630 case 512: 631 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 632 SGTL5000_MCLK_FREQ_SHIFT; 633 break; 634 default: 635 /* if mclk does not satisfy the divider, use pll */ 636 if (sgtl5000->master) { 637 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 638 SGTL5000_MCLK_FREQ_SHIFT; 639 } else { 640 dev_err(codec->dev, 641 "PLL not supported in slave mode\n"); 642 dev_err(codec->dev, "%d ratio is not supported. " 643 "SYS_MCLK needs to be 256, 384 or 512 * fs\n", 644 sgtl5000->sysclk / frame_rate); 645 return -EINVAL; 646 } 647 } 648 649 /* if using pll, please check manual 6.4.2 for detail */ 650 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 651 u64 out, t; 652 int div2; 653 int pll_ctl; 654 unsigned int in, int_div, frac_div; 655 656 if (sgtl5000->sysclk > 17000000) { 657 div2 = 1; 658 in = sgtl5000->sysclk / 2; 659 } else { 660 div2 = 0; 661 in = sgtl5000->sysclk; 662 } 663 if (sys_fs == 44100) 664 out = 180633600; 665 else 666 out = 196608000; 667 t = do_div(out, in); 668 int_div = out; 669 t *= 2048; 670 do_div(t, in); 671 frac_div = t; 672 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 673 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 674 675 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 676 if (div2) 677 snd_soc_update_bits(codec, 678 SGTL5000_CHIP_CLK_TOP_CTRL, 679 SGTL5000_INPUT_FREQ_DIV2, 680 SGTL5000_INPUT_FREQ_DIV2); 681 else 682 snd_soc_update_bits(codec, 683 SGTL5000_CHIP_CLK_TOP_CTRL, 684 SGTL5000_INPUT_FREQ_DIV2, 685 0); 686 687 /* power up pll */ 688 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 689 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 690 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 691 692 /* if using pll, clk_ctrl must be set after pll power up */ 693 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 694 } else { 695 /* otherwise, clk_ctrl must be set before pll power down */ 696 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 697 698 /* power down pll */ 699 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 700 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 701 0); 702 } 703 704 return 0; 705 } 706 707 /* 708 * Set PCM DAI bit size and sample rate. 709 * input: params_rate, params_fmt 710 */ 711 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 712 struct snd_pcm_hw_params *params, 713 struct snd_soc_dai *dai) 714 { 715 struct snd_soc_codec *codec = dai->codec; 716 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 717 int channels = params_channels(params); 718 int i2s_ctl = 0; 719 int stereo; 720 int ret; 721 722 /* sysclk should already set */ 723 if (!sgtl5000->sysclk) { 724 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 725 return -EFAULT; 726 } 727 728 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 729 stereo = SGTL5000_DAC_STEREO; 730 else 731 stereo = SGTL5000_ADC_STEREO; 732 733 /* set mono to save power */ 734 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 735 channels == 1 ? 0 : stereo); 736 737 /* set codec clock base on lrclk */ 738 ret = sgtl5000_set_clock(codec, params_rate(params)); 739 if (ret) 740 return ret; 741 742 /* set i2s data format */ 743 switch (params_width(params)) { 744 case 16: 745 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 746 return -EINVAL; 747 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 748 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 749 SGTL5000_I2S_SCLKFREQ_SHIFT; 750 break; 751 case 20: 752 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 753 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 754 SGTL5000_I2S_SCLKFREQ_SHIFT; 755 break; 756 case 24: 757 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 758 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 759 SGTL5000_I2S_SCLKFREQ_SHIFT; 760 break; 761 case 32: 762 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 763 return -EINVAL; 764 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 765 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 766 SGTL5000_I2S_SCLKFREQ_SHIFT; 767 break; 768 default: 769 return -EINVAL; 770 } 771 772 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 773 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 774 i2s_ctl); 775 776 return 0; 777 } 778 779 #ifdef CONFIG_REGULATOR 780 static int ldo_regulator_is_enabled(struct regulator_dev *dev) 781 { 782 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 783 784 return ldo->enabled; 785 } 786 787 static int ldo_regulator_enable(struct regulator_dev *dev) 788 { 789 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 790 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 791 int reg; 792 793 if (ldo_regulator_is_enabled(dev)) 794 return 0; 795 796 /* set regulator value firstly */ 797 reg = (1600 - ldo->voltage / 1000) / 50; 798 reg = clamp(reg, 0x0, 0xf); 799 800 /* amend the voltage value, unit: uV */ 801 ldo->voltage = (1600 - reg * 50) * 1000; 802 803 /* set voltage to register */ 804 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 805 SGTL5000_LINREG_VDDD_MASK, reg); 806 807 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 808 SGTL5000_LINEREG_D_POWERUP, 809 SGTL5000_LINEREG_D_POWERUP); 810 811 /* when internal ldo is enabled, simple digital power can be disabled */ 812 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 813 SGTL5000_LINREG_SIMPLE_POWERUP, 814 0); 815 816 ldo->enabled = 1; 817 return 0; 818 } 819 820 static int ldo_regulator_disable(struct regulator_dev *dev) 821 { 822 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 823 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 824 825 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 826 SGTL5000_LINEREG_D_POWERUP, 827 0); 828 829 /* clear voltage info */ 830 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 831 SGTL5000_LINREG_VDDD_MASK, 0); 832 833 ldo->enabled = 0; 834 835 return 0; 836 } 837 838 static int ldo_regulator_get_voltage(struct regulator_dev *dev) 839 { 840 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 841 842 return ldo->voltage; 843 } 844 845 static struct regulator_ops ldo_regulator_ops = { 846 .is_enabled = ldo_regulator_is_enabled, 847 .enable = ldo_regulator_enable, 848 .disable = ldo_regulator_disable, 849 .get_voltage = ldo_regulator_get_voltage, 850 }; 851 852 static int ldo_regulator_register(struct snd_soc_codec *codec, 853 struct regulator_init_data *init_data, 854 int voltage) 855 { 856 struct ldo_regulator *ldo; 857 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 858 struct regulator_config config = { }; 859 860 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); 861 862 if (!ldo) 863 return -ENOMEM; 864 865 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); 866 if (!ldo->desc.name) { 867 kfree(ldo); 868 dev_err(codec->dev, "failed to allocate decs name memory\n"); 869 return -ENOMEM; 870 } 871 872 ldo->desc.type = REGULATOR_VOLTAGE; 873 ldo->desc.owner = THIS_MODULE; 874 ldo->desc.ops = &ldo_regulator_ops; 875 ldo->desc.n_voltages = 1; 876 877 ldo->codec_data = codec; 878 ldo->voltage = voltage; 879 880 config.dev = codec->dev; 881 config.driver_data = ldo; 882 config.init_data = init_data; 883 884 ldo->dev = regulator_register(&ldo->desc, &config); 885 if (IS_ERR(ldo->dev)) { 886 int ret = PTR_ERR(ldo->dev); 887 888 dev_err(codec->dev, "failed to register regulator\n"); 889 kfree(ldo->desc.name); 890 kfree(ldo); 891 892 return ret; 893 } 894 sgtl5000->ldo = ldo; 895 896 return 0; 897 } 898 899 static int ldo_regulator_remove(struct snd_soc_codec *codec) 900 { 901 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 902 struct ldo_regulator *ldo = sgtl5000->ldo; 903 904 if (!ldo) 905 return 0; 906 907 regulator_unregister(ldo->dev); 908 kfree(ldo->desc.name); 909 kfree(ldo); 910 911 return 0; 912 } 913 #else 914 static int ldo_regulator_register(struct snd_soc_codec *codec, 915 struct regulator_init_data *init_data, 916 int voltage) 917 { 918 dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); 919 return -EINVAL; 920 } 921 922 static int ldo_regulator_remove(struct snd_soc_codec *codec) 923 { 924 return 0; 925 } 926 #endif 927 928 /* 929 * set dac bias 930 * common state changes: 931 * startup: 932 * off --> standby --> prepare --> on 933 * standby --> prepare --> on 934 * 935 * stop: 936 * on --> prepare --> standby 937 */ 938 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 939 enum snd_soc_bias_level level) 940 { 941 int ret; 942 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 943 944 switch (level) { 945 case SND_SOC_BIAS_ON: 946 case SND_SOC_BIAS_PREPARE: 947 break; 948 case SND_SOC_BIAS_STANDBY: 949 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 950 ret = regulator_bulk_enable( 951 ARRAY_SIZE(sgtl5000->supplies), 952 sgtl5000->supplies); 953 if (ret) 954 return ret; 955 udelay(10); 956 957 regcache_cache_only(sgtl5000->regmap, false); 958 959 ret = regcache_sync(sgtl5000->regmap); 960 if (ret != 0) { 961 dev_err(codec->dev, 962 "Failed to restore cache: %d\n", ret); 963 964 regcache_cache_only(sgtl5000->regmap, true); 965 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 966 sgtl5000->supplies); 967 968 return ret; 969 } 970 } 971 972 break; 973 case SND_SOC_BIAS_OFF: 974 regcache_cache_only(sgtl5000->regmap, true); 975 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 976 sgtl5000->supplies); 977 break; 978 } 979 980 codec->dapm.bias_level = level; 981 return 0; 982 } 983 984 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 985 SNDRV_PCM_FMTBIT_S20_3LE |\ 986 SNDRV_PCM_FMTBIT_S24_LE |\ 987 SNDRV_PCM_FMTBIT_S32_LE) 988 989 static const struct snd_soc_dai_ops sgtl5000_ops = { 990 .hw_params = sgtl5000_pcm_hw_params, 991 .digital_mute = sgtl5000_digital_mute, 992 .set_fmt = sgtl5000_set_dai_fmt, 993 .set_sysclk = sgtl5000_set_dai_sysclk, 994 }; 995 996 static struct snd_soc_dai_driver sgtl5000_dai = { 997 .name = "sgtl5000", 998 .playback = { 999 .stream_name = "Playback", 1000 .channels_min = 1, 1001 .channels_max = 2, 1002 /* 1003 * only support 8~48K + 96K, 1004 * TODO modify hw_param to support more 1005 */ 1006 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 1007 .formats = SGTL5000_FORMATS, 1008 }, 1009 .capture = { 1010 .stream_name = "Capture", 1011 .channels_min = 1, 1012 .channels_max = 2, 1013 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 1014 .formats = SGTL5000_FORMATS, 1015 }, 1016 .ops = &sgtl5000_ops, 1017 .symmetric_rates = 1, 1018 }; 1019 1020 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 1021 { 1022 switch (reg) { 1023 case SGTL5000_CHIP_ID: 1024 case SGTL5000_CHIP_ADCDAC_CTRL: 1025 case SGTL5000_CHIP_ANA_STATUS: 1026 return true; 1027 } 1028 1029 return false; 1030 } 1031 1032 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 1033 { 1034 switch (reg) { 1035 case SGTL5000_CHIP_ID: 1036 case SGTL5000_CHIP_DIG_POWER: 1037 case SGTL5000_CHIP_CLK_CTRL: 1038 case SGTL5000_CHIP_I2S_CTRL: 1039 case SGTL5000_CHIP_SSS_CTRL: 1040 case SGTL5000_CHIP_ADCDAC_CTRL: 1041 case SGTL5000_CHIP_DAC_VOL: 1042 case SGTL5000_CHIP_PAD_STRENGTH: 1043 case SGTL5000_CHIP_ANA_ADC_CTRL: 1044 case SGTL5000_CHIP_ANA_HP_CTRL: 1045 case SGTL5000_CHIP_ANA_CTRL: 1046 case SGTL5000_CHIP_LINREG_CTRL: 1047 case SGTL5000_CHIP_REF_CTRL: 1048 case SGTL5000_CHIP_MIC_CTRL: 1049 case SGTL5000_CHIP_LINE_OUT_CTRL: 1050 case SGTL5000_CHIP_LINE_OUT_VOL: 1051 case SGTL5000_CHIP_ANA_POWER: 1052 case SGTL5000_CHIP_PLL_CTRL: 1053 case SGTL5000_CHIP_CLK_TOP_CTRL: 1054 case SGTL5000_CHIP_ANA_STATUS: 1055 case SGTL5000_CHIP_SHORT_CTRL: 1056 case SGTL5000_CHIP_ANA_TEST2: 1057 case SGTL5000_DAP_CTRL: 1058 case SGTL5000_DAP_PEQ: 1059 case SGTL5000_DAP_BASS_ENHANCE: 1060 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 1061 case SGTL5000_DAP_AUDIO_EQ: 1062 case SGTL5000_DAP_SURROUND: 1063 case SGTL5000_DAP_FLT_COEF_ACCESS: 1064 case SGTL5000_DAP_COEF_WR_B0_MSB: 1065 case SGTL5000_DAP_COEF_WR_B0_LSB: 1066 case SGTL5000_DAP_EQ_BASS_BAND0: 1067 case SGTL5000_DAP_EQ_BASS_BAND1: 1068 case SGTL5000_DAP_EQ_BASS_BAND2: 1069 case SGTL5000_DAP_EQ_BASS_BAND3: 1070 case SGTL5000_DAP_EQ_BASS_BAND4: 1071 case SGTL5000_DAP_MAIN_CHAN: 1072 case SGTL5000_DAP_MIX_CHAN: 1073 case SGTL5000_DAP_AVC_CTRL: 1074 case SGTL5000_DAP_AVC_THRESHOLD: 1075 case SGTL5000_DAP_AVC_ATTACK: 1076 case SGTL5000_DAP_AVC_DECAY: 1077 case SGTL5000_DAP_COEF_WR_B1_MSB: 1078 case SGTL5000_DAP_COEF_WR_B1_LSB: 1079 case SGTL5000_DAP_COEF_WR_B2_MSB: 1080 case SGTL5000_DAP_COEF_WR_B2_LSB: 1081 case SGTL5000_DAP_COEF_WR_A1_MSB: 1082 case SGTL5000_DAP_COEF_WR_A1_LSB: 1083 case SGTL5000_DAP_COEF_WR_A2_MSB: 1084 case SGTL5000_DAP_COEF_WR_A2_LSB: 1085 return true; 1086 1087 default: 1088 return false; 1089 } 1090 } 1091 1092 /* 1093 * sgtl5000 has 3 internal power supplies: 1094 * 1. VAG, normally set to vdda/2 1095 * 2. charge pump, set to different value 1096 * according to voltage of vdda and vddio 1097 * 3. line out VAG, normally set to vddio/2 1098 * 1099 * and should be set according to: 1100 * 1. vddd provided by external or not 1101 * 2. vdda and vddio voltage value. > 3.1v or not 1102 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. 1103 */ 1104 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1105 { 1106 int vddd; 1107 int vdda; 1108 int vddio; 1109 u16 ana_pwr; 1110 u16 lreg_ctrl; 1111 int vag; 1112 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1113 1114 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1115 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1116 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); 1117 1118 vdda = vdda / 1000; 1119 vddio = vddio / 1000; 1120 vddd = vddd / 1000; 1121 1122 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1123 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1124 1125 return -EINVAL; 1126 } 1127 1128 /* according to datasheet, maximum voltage of supplies */ 1129 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1130 dev_err(codec->dev, 1131 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1132 vdda, vddio, vddd); 1133 1134 return -EINVAL; 1135 } 1136 1137 /* reset value */ 1138 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1139 ana_pwr |= SGTL5000_DAC_STEREO | 1140 SGTL5000_ADC_STEREO | 1141 SGTL5000_REFTOP_POWERUP; 1142 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1143 1144 if (vddio < 3100 && vdda < 3100) { 1145 /* enable internal oscillator used for charge pump */ 1146 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1147 SGTL5000_INT_OSC_EN, 1148 SGTL5000_INT_OSC_EN); 1149 /* Enable VDDC charge pump */ 1150 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1151 } else if (vddio >= 3100 && vdda >= 3100) { 1152 /* 1153 * if vddio and vddd > 3.1v, 1154 * charge pump should be clean before set ana_pwr 1155 */ 1156 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1157 SGTL5000_VDDC_CHRGPMP_POWERUP, 0); 1158 1159 /* VDDC use VDDIO rail */ 1160 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1161 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1162 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1163 } 1164 1165 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1166 1167 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1168 1169 /* set voltage to register */ 1170 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 1171 SGTL5000_LINREG_VDDD_MASK, 0x8); 1172 1173 /* 1174 * if vddd linear reg has been enabled, 1175 * simple digital supply should be clear to get 1176 * proper VDDD voltage. 1177 */ 1178 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) 1179 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1180 SGTL5000_LINREG_SIMPLE_POWERUP, 1181 0); 1182 else 1183 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1184 SGTL5000_LINREG_SIMPLE_POWERUP | 1185 SGTL5000_STARTUP_POWERUP, 1186 0); 1187 1188 /* 1189 * set ADC/DAC VAG to vdda / 2, 1190 * should stay in range (0.8v, 1.575v) 1191 */ 1192 vag = vdda / 2; 1193 if (vag <= SGTL5000_ANA_GND_BASE) 1194 vag = 0; 1195 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1196 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1197 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1198 else 1199 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1200 1201 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1202 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1203 1204 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1205 vag = vddio / 2; 1206 if (vag <= SGTL5000_LINE_OUT_GND_BASE) 1207 vag = 0; 1208 else if (vag >= SGTL5000_LINE_OUT_GND_BASE + 1209 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1210 vag = SGTL5000_LINE_OUT_GND_MAX; 1211 else 1212 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / 1213 SGTL5000_LINE_OUT_GND_STP; 1214 1215 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1216 SGTL5000_LINE_OUT_CURRENT_MASK | 1217 SGTL5000_LINE_OUT_GND_MASK, 1218 vag << SGTL5000_LINE_OUT_GND_SHIFT | 1219 SGTL5000_LINE_OUT_CURRENT_360u << 1220 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1221 1222 return 0; 1223 } 1224 1225 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) 1226 { 1227 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1228 int ret; 1229 1230 /* set internal ldo to 1.2v */ 1231 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); 1232 if (ret) { 1233 dev_err(codec->dev, 1234 "Failed to register vddd internal supplies: %d\n", ret); 1235 return ret; 1236 } 1237 1238 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; 1239 1240 dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); 1241 return 0; 1242 } 1243 1244 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) 1245 { 1246 int ret; 1247 int i; 1248 int external_vddd = 0; 1249 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1250 struct regulator *vddd; 1251 1252 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1253 sgtl5000->supplies[i].supply = supply_names[i]; 1254 1255 /* External VDDD only works before revision 0x11 */ 1256 if (sgtl5000->revision < 0x11) { 1257 vddd = regulator_get_optional(codec->dev, "VDDD"); 1258 if (IS_ERR(vddd)) { 1259 /* See if it's just not registered yet */ 1260 if (PTR_ERR(vddd) == -EPROBE_DEFER) 1261 return -EPROBE_DEFER; 1262 } else { 1263 external_vddd = 1; 1264 regulator_put(vddd); 1265 } 1266 } 1267 1268 if (!external_vddd) { 1269 ret = sgtl5000_replace_vddd_with_ldo(codec); 1270 if (ret) 1271 return ret; 1272 } 1273 1274 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1275 sgtl5000->supplies); 1276 if (ret) 1277 goto err_ldo_remove; 1278 1279 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1280 sgtl5000->supplies); 1281 if (ret) 1282 goto err_regulator_free; 1283 1284 /* wait for all power rails bring up */ 1285 udelay(10); 1286 1287 return 0; 1288 1289 err_regulator_free: 1290 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1291 sgtl5000->supplies); 1292 err_ldo_remove: 1293 if (!external_vddd) 1294 ldo_regulator_remove(codec); 1295 return ret; 1296 1297 } 1298 1299 static int sgtl5000_probe(struct snd_soc_codec *codec) 1300 { 1301 int ret; 1302 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1303 1304 ret = sgtl5000_enable_regulators(codec); 1305 if (ret) 1306 return ret; 1307 1308 /* power up sgtl5000 */ 1309 ret = sgtl5000_set_power_regs(codec); 1310 if (ret) 1311 goto err; 1312 1313 /* enable small pop, introduce 400ms delay in turning off */ 1314 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1315 SGTL5000_SMALL_POP, 1); 1316 1317 /* disable short cut detector */ 1318 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1319 1320 /* 1321 * set i2s as default input of sound switch 1322 * TODO: add sound switch to control and dapm widge. 1323 */ 1324 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1325 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1326 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1327 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1328 1329 /* enable dac volume ramp by default */ 1330 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1331 SGTL5000_DAC_VOL_RAMP_EN | 1332 SGTL5000_DAC_MUTE_RIGHT | 1333 SGTL5000_DAC_MUTE_LEFT); 1334 1335 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1336 1337 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1338 SGTL5000_HP_ZCD_EN | 1339 SGTL5000_ADC_ZCD_EN); 1340 1341 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1342 SGTL5000_BIAS_R_MASK, 1343 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 1344 1345 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1346 SGTL5000_BIAS_R_MASK, 1347 sgtl5000->micbias_voltage << SGTL5000_BIAS_R_SHIFT); 1348 /* 1349 * disable DAP 1350 * TODO: 1351 * Enable DAP in kcontrol and dapm. 1352 */ 1353 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1354 1355 return 0; 1356 1357 err: 1358 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1359 sgtl5000->supplies); 1360 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1361 sgtl5000->supplies); 1362 ldo_regulator_remove(codec); 1363 1364 return ret; 1365 } 1366 1367 static int sgtl5000_remove(struct snd_soc_codec *codec) 1368 { 1369 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1370 1371 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1372 sgtl5000->supplies); 1373 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1374 sgtl5000->supplies); 1375 ldo_regulator_remove(codec); 1376 1377 return 0; 1378 } 1379 1380 static struct snd_soc_codec_driver sgtl5000_driver = { 1381 .probe = sgtl5000_probe, 1382 .remove = sgtl5000_remove, 1383 .set_bias_level = sgtl5000_set_bias_level, 1384 .suspend_bias_off = true, 1385 .controls = sgtl5000_snd_controls, 1386 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1387 .dapm_widgets = sgtl5000_dapm_widgets, 1388 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1389 .dapm_routes = sgtl5000_dapm_routes, 1390 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1391 }; 1392 1393 static const struct regmap_config sgtl5000_regmap = { 1394 .reg_bits = 16, 1395 .val_bits = 16, 1396 .reg_stride = 2, 1397 1398 .max_register = SGTL5000_MAX_REG_OFFSET, 1399 .volatile_reg = sgtl5000_volatile, 1400 .readable_reg = sgtl5000_readable, 1401 1402 .cache_type = REGCACHE_RBTREE, 1403 .reg_defaults = sgtl5000_reg_defaults, 1404 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1405 }; 1406 1407 /* 1408 * Write all the default values from sgtl5000_reg_defaults[] array into the 1409 * sgtl5000 registers, to make sure we always start with the sane registers 1410 * values as stated in the datasheet. 1411 * 1412 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1413 * we follow this approach to guarantee we always start from the default values 1414 * and avoid problems like, not being able to probe after an audio playback 1415 * followed by a system reset or a 'reboot' command in Linux 1416 */ 1417 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000) 1418 { 1419 int i, ret, val, index; 1420 1421 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1422 val = sgtl5000_reg_defaults[i].def; 1423 index = sgtl5000_reg_defaults[i].reg; 1424 ret = regmap_write(sgtl5000->regmap, index, val); 1425 if (ret) 1426 return ret; 1427 } 1428 1429 return 0; 1430 } 1431 1432 static int sgtl5000_i2c_probe(struct i2c_client *client, 1433 const struct i2c_device_id *id) 1434 { 1435 struct sgtl5000_priv *sgtl5000; 1436 int ret, reg, rev; 1437 struct device_node *np = client->dev.of_node; 1438 u32 value; 1439 1440 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); 1441 if (!sgtl5000) 1442 return -ENOMEM; 1443 1444 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1445 if (IS_ERR(sgtl5000->regmap)) { 1446 ret = PTR_ERR(sgtl5000->regmap); 1447 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1448 return ret; 1449 } 1450 1451 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1452 if (IS_ERR(sgtl5000->mclk)) { 1453 ret = PTR_ERR(sgtl5000->mclk); 1454 dev_err(&client->dev, "Failed to get mclock: %d\n", ret); 1455 /* Defer the probe to see if the clk will be provided later */ 1456 if (ret == -ENOENT) 1457 return -EPROBE_DEFER; 1458 return ret; 1459 } 1460 1461 ret = clk_prepare_enable(sgtl5000->mclk); 1462 if (ret) 1463 return ret; 1464 1465 /* read chip information */ 1466 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1467 if (ret) 1468 goto disable_clk; 1469 1470 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1471 SGTL5000_PARTID_PART_ID) { 1472 dev_err(&client->dev, 1473 "Device with ID register %x is not a sgtl5000\n", reg); 1474 ret = -ENODEV; 1475 goto disable_clk; 1476 } 1477 1478 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1479 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1480 sgtl5000->revision = rev; 1481 1482 if (np) { 1483 if (!of_property_read_u32(np, 1484 "micbias-resistor-k-ohms", &value)) { 1485 switch (value) { 1486 case SGTL5000_MICBIAS_OFF: 1487 sgtl5000->micbias_resistor = 0; 1488 break; 1489 case SGTL5000_MICBIAS_2K: 1490 sgtl5000->micbias_resistor = 1; 1491 break; 1492 case SGTL5000_MICBIAS_4K: 1493 sgtl5000->micbias_resistor = 2; 1494 break; 1495 case SGTL5000_MICBIAS_8K: 1496 sgtl5000->micbias_resistor = 3; 1497 break; 1498 default: 1499 sgtl5000->micbias_resistor = 2; 1500 dev_err(&client->dev, 1501 "Unsuitable MicBias resistor\n"); 1502 } 1503 } else { 1504 /* default is 4Kohms */ 1505 sgtl5000->micbias_resistor = 2; 1506 } 1507 if (!of_property_read_u32(np, 1508 "micbias-voltage-m-volts", &value)) { 1509 /* 1250mV => 0 */ 1510 /* steps of 250mV */ 1511 if ((value >= 1250) && (value <= 3000)) 1512 sgtl5000->micbias_voltage = (value / 250) - 5; 1513 else { 1514 sgtl5000->micbias_voltage = 0; 1515 dev_err(&client->dev, 1516 "Unsuitable MicBias resistor\n"); 1517 } 1518 } else { 1519 sgtl5000->micbias_voltage = 0; 1520 } 1521 } 1522 1523 i2c_set_clientdata(client, sgtl5000); 1524 1525 /* Ensure sgtl5000 will start with sane register values */ 1526 ret = sgtl5000_fill_defaults(sgtl5000); 1527 if (ret) 1528 goto disable_clk; 1529 1530 ret = snd_soc_register_codec(&client->dev, 1531 &sgtl5000_driver, &sgtl5000_dai, 1); 1532 if (ret) 1533 goto disable_clk; 1534 1535 return 0; 1536 1537 disable_clk: 1538 clk_disable_unprepare(sgtl5000->mclk); 1539 return ret; 1540 } 1541 1542 static int sgtl5000_i2c_remove(struct i2c_client *client) 1543 { 1544 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1545 1546 snd_soc_unregister_codec(&client->dev); 1547 clk_disable_unprepare(sgtl5000->mclk); 1548 return 0; 1549 } 1550 1551 static const struct i2c_device_id sgtl5000_id[] = { 1552 {"sgtl5000", 0}, 1553 {}, 1554 }; 1555 1556 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1557 1558 static const struct of_device_id sgtl5000_dt_ids[] = { 1559 { .compatible = "fsl,sgtl5000", }, 1560 { /* sentinel */ } 1561 }; 1562 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1563 1564 static struct i2c_driver sgtl5000_i2c_driver = { 1565 .driver = { 1566 .name = "sgtl5000", 1567 .owner = THIS_MODULE, 1568 .of_match_table = sgtl5000_dt_ids, 1569 }, 1570 .probe = sgtl5000_i2c_probe, 1571 .remove = sgtl5000_i2c_remove, 1572 .id_table = sgtl5000_id, 1573 }; 1574 1575 module_i2c_driver(sgtl5000_i2c_driver); 1576 1577 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1578 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1579 MODULE_LICENSE("GPL"); 1580