1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/log2.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/driver.h> 22 #include <linux/regulator/machine.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/of_device.h> 25 #include <sound/core.h> 26 #include <sound/tlv.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 33 #include "sgtl5000.h" 34 35 #define SGTL5000_DAP_REG_OFFSET 0x0100 36 #define SGTL5000_MAX_REG_OFFSET 0x013A 37 38 /* default value of sgtl5000 registers */ 39 static const struct reg_default sgtl5000_reg_defaults[] = { 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 }, 41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, 44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, 47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 49 { SGTL5000_CHIP_REF_CTRL, 0x0000 }, 50 { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, 51 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, 52 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 53 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 54 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, 55 { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, 56 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, 57 { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, 58 { SGTL5000_DAP_CTRL, 0x0000 }, 59 { SGTL5000_DAP_PEQ, 0x0000 }, 60 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 61 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 62 { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, 63 { SGTL5000_DAP_SURROUND, 0x0040 }, 64 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 65 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 66 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 67 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 68 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 69 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 70 { SGTL5000_DAP_MIX_CHAN, 0x0000 }, 71 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 72 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 73 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 74 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 75 }; 76 77 /* AVC: Threshold dB -> register: pre-calculated values */ 78 static const u16 avc_thr_db2reg[97] = { 79 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068, 80 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F, 81 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414, 82 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172, 83 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083, 84 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E, 85 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010, 86 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005, 87 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002, 88 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; 90 91 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 92 enum sgtl5000_regulator_supplies { 93 VDDA, 94 VDDIO, 95 VDDD, 96 SGTL5000_SUPPLY_NUM 97 }; 98 99 /* vddd is optional supply */ 100 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 101 "VDDA", 102 "VDDIO", 103 "VDDD" 104 }; 105 106 #define LDO_VOLTAGE 1200000 107 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50) 108 109 enum sgtl5000_micbias_resistor { 110 SGTL5000_MICBIAS_OFF = 0, 111 SGTL5000_MICBIAS_2K = 2, 112 SGTL5000_MICBIAS_4K = 4, 113 SGTL5000_MICBIAS_8K = 8, 114 }; 115 116 enum { 117 I2S_LRCLK_STRENGTH_DISABLE, 118 I2S_LRCLK_STRENGTH_LOW, 119 I2S_LRCLK_STRENGTH_MEDIUM, 120 I2S_LRCLK_STRENGTH_HIGH, 121 }; 122 123 /* sgtl5000 private structure in codec */ 124 struct sgtl5000_priv { 125 int sysclk; /* sysclk rate */ 126 int master; /* i2s master or not */ 127 int fmt; /* i2s data format */ 128 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 129 int num_supplies; 130 struct regmap *regmap; 131 struct clk *mclk; 132 int revision; 133 u8 micbias_resistor; 134 u8 micbias_voltage; 135 u8 lrclk_strength; 136 }; 137 138 /* 139 * mic_bias power on/off share the same register bits with 140 * output impedance of mic bias, when power on mic bias, we 141 * need reclaim it to impedance value. 142 * 0x0 = Powered off 143 * 0x1 = 2Kohm 144 * 0x2 = 4Kohm 145 * 0x3 = 8Kohm 146 */ 147 static int mic_bias_event(struct snd_soc_dapm_widget *w, 148 struct snd_kcontrol *kcontrol, int event) 149 { 150 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 151 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 152 153 switch (event) { 154 case SND_SOC_DAPM_POST_PMU: 155 /* change mic bias resistor */ 156 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 157 SGTL5000_BIAS_R_MASK, 158 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 159 break; 160 161 case SND_SOC_DAPM_PRE_PMD: 162 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 163 SGTL5000_BIAS_R_MASK, 0); 164 break; 165 } 166 return 0; 167 } 168 169 /* 170 * As manual described, ADC/DAC only works when VAG powerup, 171 * So enabled VAG before ADC/DAC up. 172 * In power down case, we need wait 400ms when vag fully ramped down. 173 */ 174 static int power_vag_event(struct snd_soc_dapm_widget *w, 175 struct snd_kcontrol *kcontrol, int event) 176 { 177 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 178 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 179 180 switch (event) { 181 case SND_SOC_DAPM_POST_PMU: 182 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 183 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 184 msleep(400); 185 break; 186 187 case SND_SOC_DAPM_PRE_PMD: 188 /* 189 * Don't clear VAG_POWERUP, when both DAC and ADC are 190 * operational to prevent inadvertently starving the 191 * other one of them. 192 */ 193 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) & 194 mask) != mask) { 195 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 196 SGTL5000_VAG_POWERUP, 0); 197 msleep(400); 198 } 199 break; 200 default: 201 break; 202 } 203 204 return 0; 205 } 206 207 /* input sources for ADC */ 208 static const char *adc_mux_text[] = { 209 "MIC_IN", "LINE_IN" 210 }; 211 212 static SOC_ENUM_SINGLE_DECL(adc_enum, 213 SGTL5000_CHIP_ANA_CTRL, 2, 214 adc_mux_text); 215 216 static const struct snd_kcontrol_new adc_mux = 217 SOC_DAPM_ENUM("Capture Mux", adc_enum); 218 219 /* input sources for DAC */ 220 static const char *dac_mux_text[] = { 221 "DAC", "LINE_IN" 222 }; 223 224 static SOC_ENUM_SINGLE_DECL(dac_enum, 225 SGTL5000_CHIP_ANA_CTRL, 6, 226 dac_mux_text); 227 228 static const struct snd_kcontrol_new dac_mux = 229 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 230 231 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 232 SND_SOC_DAPM_INPUT("LINE_IN"), 233 SND_SOC_DAPM_INPUT("MIC_IN"), 234 235 SND_SOC_DAPM_OUTPUT("HP_OUT"), 236 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 237 238 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 239 mic_bias_event, 240 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 241 242 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 243 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 244 245 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 246 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 247 248 /* aif for i2s input */ 249 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 250 0, SGTL5000_CHIP_DIG_POWER, 251 0, 0), 252 253 /* aif for i2s output */ 254 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 255 0, SGTL5000_CHIP_DIG_POWER, 256 1, 0), 257 258 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 259 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 260 261 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 262 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 263 }; 264 265 /* routes for sgtl5000 */ 266 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 267 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 268 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 269 270 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 271 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 272 273 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 274 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 275 {"LO", NULL, "DAC"}, /* dac --> line_out */ 276 277 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 278 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 279 280 {"LINE_OUT", NULL, "LO"}, 281 {"HP_OUT", NULL, "HP"}, 282 }; 283 284 /* custom function to fetch info of PCM playback volume */ 285 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 286 struct snd_ctl_elem_info *uinfo) 287 { 288 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 289 uinfo->count = 2; 290 uinfo->value.integer.min = 0; 291 uinfo->value.integer.max = 0xfc - 0x3c; 292 return 0; 293 } 294 295 /* 296 * custom function to get of PCM playback volume 297 * 298 * dac volume register 299 * 15-------------8-7--------------0 300 * | R channel vol | L channel vol | 301 * ------------------------------- 302 * 303 * PCM volume with 0.5017 dB steps from 0 to -90 dB 304 * 305 * register values map to dB 306 * 0x3B and less = Reserved 307 * 0x3C = 0 dB 308 * 0x3D = -0.5 dB 309 * 0xF0 = -90 dB 310 * 0xFC and greater = Muted 311 * 312 * register value map to userspace value 313 * 314 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 315 * ------------------------------ 316 * userspace value 0xc0 0 317 */ 318 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 319 struct snd_ctl_elem_value *ucontrol) 320 { 321 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 322 int reg; 323 int l; 324 int r; 325 326 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 327 328 /* get left channel volume */ 329 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 330 331 /* get right channel volume */ 332 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 333 334 /* make sure value fall in (0x3c,0xfc) */ 335 l = clamp(l, 0x3c, 0xfc); 336 r = clamp(r, 0x3c, 0xfc); 337 338 /* invert it and map to userspace value */ 339 l = 0xfc - l; 340 r = 0xfc - r; 341 342 ucontrol->value.integer.value[0] = l; 343 ucontrol->value.integer.value[1] = r; 344 345 return 0; 346 } 347 348 /* 349 * custom function to put of PCM playback volume 350 * 351 * dac volume register 352 * 15-------------8-7--------------0 353 * | R channel vol | L channel vol | 354 * ------------------------------- 355 * 356 * PCM volume with 0.5017 dB steps from 0 to -90 dB 357 * 358 * register values map to dB 359 * 0x3B and less = Reserved 360 * 0x3C = 0 dB 361 * 0x3D = -0.5 dB 362 * 0xF0 = -90 dB 363 * 0xFC and greater = Muted 364 * 365 * userspace value map to register value 366 * 367 * userspace value 0xc0 0 368 * ------------------------------ 369 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 370 */ 371 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 372 struct snd_ctl_elem_value *ucontrol) 373 { 374 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 375 int reg; 376 int l; 377 int r; 378 379 l = ucontrol->value.integer.value[0]; 380 r = ucontrol->value.integer.value[1]; 381 382 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 383 l = clamp(l, 0, 0xfc - 0x3c); 384 r = clamp(r, 0, 0xfc - 0x3c); 385 386 /* invert it, get the value can be set to register */ 387 l = 0xfc - l; 388 r = 0xfc - r; 389 390 /* shift to get the register value */ 391 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 392 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 393 394 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 395 396 return 0; 397 } 398 399 /* 400 * custom function to get AVC threshold 401 * 402 * The threshold dB is calculated by rearranging the calculation from the 403 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==> 404 * dB = ( fls(register_value) - 14.347 ) * 6.02 405 * 406 * As this calculation is expensive and the threshold dB values may not exeed 407 * 0 to 96 we use pre-calculated values. 408 */ 409 static int avc_get_threshold(struct snd_kcontrol *kcontrol, 410 struct snd_ctl_elem_value *ucontrol) 411 { 412 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 413 int db, i; 414 u16 reg = snd_soc_read(codec, SGTL5000_DAP_AVC_THRESHOLD); 415 416 /* register value 0 => -96dB */ 417 if (!reg) { 418 ucontrol->value.integer.value[0] = 96; 419 ucontrol->value.integer.value[1] = 96; 420 return 0; 421 } 422 423 /* get dB from register value (rounded down) */ 424 for (i = 0; avc_thr_db2reg[i] > reg; i++) 425 ; 426 db = i; 427 428 ucontrol->value.integer.value[0] = db; 429 ucontrol->value.integer.value[1] = db; 430 431 return 0; 432 } 433 434 /* 435 * custom function to put AVC threshold 436 * 437 * The register value is calculated by following formula: 438 * register_value = 10^(dB/20) * 0.636 * 2^15 439 * As this calculation is expensive and the threshold dB values may not exeed 440 * 0 to 96 we use pre-calculated values. 441 */ 442 static int avc_put_threshold(struct snd_kcontrol *kcontrol, 443 struct snd_ctl_elem_value *ucontrol) 444 { 445 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 446 int db; 447 u16 reg; 448 449 db = (int)ucontrol->value.integer.value[0]; 450 if (db < 0 || db > 96) 451 return -EINVAL; 452 reg = avc_thr_db2reg[db]; 453 snd_soc_write(codec, SGTL5000_DAP_AVC_THRESHOLD, reg); 454 455 return 0; 456 } 457 458 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 459 460 /* tlv for mic gain, 0db 20db 30db 40db */ 461 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv, 462 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 463 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0) 464 ); 465 466 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 467 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 468 469 /* tlv for lineout volume, 31 steps of .5db each */ 470 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0); 471 472 /* tlv for dap avc max gain, 0db, 6db, 12db */ 473 static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0); 474 475 /* tlv for dap avc threshold, */ 476 static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600); 477 478 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 479 /* SOC_DOUBLE_S8_TLV with invert */ 480 { 481 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 482 .name = "PCM Playback Volume", 483 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 484 SNDRV_CTL_ELEM_ACCESS_READWRITE, 485 .info = dac_info_volsw, 486 .get = dac_get_volsw, 487 .put = dac_put_volsw, 488 }, 489 490 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 491 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 492 SGTL5000_CHIP_ANA_ADC_CTRL, 493 8, 1, 0, capture_6db_attenuate), 494 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 495 496 SOC_DOUBLE_TLV("Headphone Playback Volume", 497 SGTL5000_CHIP_ANA_HP_CTRL, 498 0, 8, 499 0x7f, 1, 500 headphone_volume), 501 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL, 502 4, 1, 1), 503 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 504 5, 1, 0), 505 506 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 507 0, 3, 0, mic_gain_tlv), 508 509 SOC_DOUBLE_TLV("Lineout Playback Volume", 510 SGTL5000_CHIP_LINE_OUT_VOL, 511 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT, 512 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT, 513 0x1f, 1, 514 lineout_volume), 515 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1), 516 517 /* Automatic Volume Control (DAP AVC) */ 518 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0), 519 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0), 520 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0, 521 avc_max_gain), 522 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0), 523 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD, 524 0, 96, 0, avc_get_threshold, avc_put_threshold, 525 avc_threshold), 526 }; 527 528 /* mute the codec used by alsa core */ 529 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 530 { 531 struct snd_soc_codec *codec = codec_dai->codec; 532 u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP; 533 534 /* 535 * During 'digital mute' do not mute DAC 536 * because LINE_IN would be muted aswell. We want to mute 537 * only I2S block - this can be done by powering it off 538 */ 539 snd_soc_update_bits(codec, SGTL5000_CHIP_DIG_POWER, 540 i2s_pwr, mute ? 0 : i2s_pwr); 541 542 return 0; 543 } 544 545 /* set codec format */ 546 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 547 { 548 struct snd_soc_codec *codec = codec_dai->codec; 549 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 550 u16 i2sctl = 0; 551 552 sgtl5000->master = 0; 553 /* 554 * i2s clock and frame master setting. 555 * ONLY support: 556 * - clock and frame slave, 557 * - clock and frame master 558 */ 559 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 560 case SND_SOC_DAIFMT_CBS_CFS: 561 break; 562 case SND_SOC_DAIFMT_CBM_CFM: 563 i2sctl |= SGTL5000_I2S_MASTER; 564 sgtl5000->master = 1; 565 break; 566 default: 567 return -EINVAL; 568 } 569 570 /* setting i2s data format */ 571 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 572 case SND_SOC_DAIFMT_DSP_A: 573 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 574 break; 575 case SND_SOC_DAIFMT_DSP_B: 576 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 577 i2sctl |= SGTL5000_I2S_LRALIGN; 578 break; 579 case SND_SOC_DAIFMT_I2S: 580 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 581 break; 582 case SND_SOC_DAIFMT_RIGHT_J: 583 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT; 584 i2sctl |= SGTL5000_I2S_LRPOL; 585 break; 586 case SND_SOC_DAIFMT_LEFT_J: 587 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 588 i2sctl |= SGTL5000_I2S_LRALIGN; 589 break; 590 default: 591 return -EINVAL; 592 } 593 594 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 595 596 /* Clock inversion */ 597 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 598 case SND_SOC_DAIFMT_NB_NF: 599 break; 600 case SND_SOC_DAIFMT_IB_NF: 601 i2sctl |= SGTL5000_I2S_SCLK_INV; 602 break; 603 default: 604 return -EINVAL; 605 } 606 607 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 608 609 return 0; 610 } 611 612 /* set codec sysclk */ 613 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 614 int clk_id, unsigned int freq, int dir) 615 { 616 struct snd_soc_codec *codec = codec_dai->codec; 617 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 618 619 switch (clk_id) { 620 case SGTL5000_SYSCLK: 621 sgtl5000->sysclk = freq; 622 break; 623 default: 624 return -EINVAL; 625 } 626 627 return 0; 628 } 629 630 /* 631 * set clock according to i2s frame clock, 632 * sgtl5000 provides 2 clock sources: 633 * 1. sys_mclk: sample freq can only be configured to 634 * 1/256, 1/384, 1/512 of sys_mclk. 635 * 2. pll: can derive any audio clocks. 636 * 637 * clock setting rules: 638 * 1. in slave mode, only sys_mclk can be used 639 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz 640 * and above. 641 * 3. usage of sys_mclk is preferred over pll to save power. 642 */ 643 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 644 { 645 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 646 int clk_ctl = 0; 647 int sys_fs; /* sample freq */ 648 649 /* 650 * sample freq should be divided by frame clock, 651 * if frame clock is lower than 44.1 kHz, sample freq should be set to 652 * 32 kHz or 44.1 kHz. 653 */ 654 switch (frame_rate) { 655 case 8000: 656 case 16000: 657 sys_fs = 32000; 658 break; 659 case 11025: 660 case 22050: 661 sys_fs = 44100; 662 break; 663 default: 664 sys_fs = frame_rate; 665 break; 666 } 667 668 /* set divided factor of frame clock */ 669 switch (sys_fs / frame_rate) { 670 case 4: 671 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 672 break; 673 case 2: 674 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 675 break; 676 case 1: 677 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 678 break; 679 default: 680 return -EINVAL; 681 } 682 683 /* set the sys_fs according to frame rate */ 684 switch (sys_fs) { 685 case 32000: 686 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 687 break; 688 case 44100: 689 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 690 break; 691 case 48000: 692 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 693 break; 694 case 96000: 695 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 696 break; 697 default: 698 dev_err(codec->dev, "frame rate %d not supported\n", 699 frame_rate); 700 return -EINVAL; 701 } 702 703 /* 704 * calculate the divider of mclk/sample_freq, 705 * factor of freq = 96 kHz can only be 256, since mclk is in the range 706 * of 8 MHz - 27 MHz 707 */ 708 switch (sgtl5000->sysclk / frame_rate) { 709 case 256: 710 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 711 SGTL5000_MCLK_FREQ_SHIFT; 712 break; 713 case 384: 714 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 715 SGTL5000_MCLK_FREQ_SHIFT; 716 break; 717 case 512: 718 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 719 SGTL5000_MCLK_FREQ_SHIFT; 720 break; 721 default: 722 /* if mclk does not satisfy the divider, use pll */ 723 if (sgtl5000->master) { 724 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 725 SGTL5000_MCLK_FREQ_SHIFT; 726 } else { 727 dev_err(codec->dev, 728 "PLL not supported in slave mode\n"); 729 dev_err(codec->dev, "%d ratio is not supported. " 730 "SYS_MCLK needs to be 256, 384 or 512 * fs\n", 731 sgtl5000->sysclk / frame_rate); 732 return -EINVAL; 733 } 734 } 735 736 /* if using pll, please check manual 6.4.2 for detail */ 737 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 738 u64 out, t; 739 int div2; 740 int pll_ctl; 741 unsigned int in, int_div, frac_div; 742 743 if (sgtl5000->sysclk > 17000000) { 744 div2 = 1; 745 in = sgtl5000->sysclk / 2; 746 } else { 747 div2 = 0; 748 in = sgtl5000->sysclk; 749 } 750 if (sys_fs == 44100) 751 out = 180633600; 752 else 753 out = 196608000; 754 t = do_div(out, in); 755 int_div = out; 756 t *= 2048; 757 do_div(t, in); 758 frac_div = t; 759 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 760 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 761 762 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 763 if (div2) 764 snd_soc_update_bits(codec, 765 SGTL5000_CHIP_CLK_TOP_CTRL, 766 SGTL5000_INPUT_FREQ_DIV2, 767 SGTL5000_INPUT_FREQ_DIV2); 768 else 769 snd_soc_update_bits(codec, 770 SGTL5000_CHIP_CLK_TOP_CTRL, 771 SGTL5000_INPUT_FREQ_DIV2, 772 0); 773 774 /* power up pll */ 775 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 776 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 777 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 778 779 /* if using pll, clk_ctrl must be set after pll power up */ 780 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 781 } else { 782 /* otherwise, clk_ctrl must be set before pll power down */ 783 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 784 785 /* power down pll */ 786 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 787 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 788 0); 789 } 790 791 return 0; 792 } 793 794 /* 795 * Set PCM DAI bit size and sample rate. 796 * input: params_rate, params_fmt 797 */ 798 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 799 struct snd_pcm_hw_params *params, 800 struct snd_soc_dai *dai) 801 { 802 struct snd_soc_codec *codec = dai->codec; 803 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 804 int channels = params_channels(params); 805 int i2s_ctl = 0; 806 int stereo; 807 int ret; 808 809 /* sysclk should already set */ 810 if (!sgtl5000->sysclk) { 811 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 812 return -EFAULT; 813 } 814 815 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 816 stereo = SGTL5000_DAC_STEREO; 817 else 818 stereo = SGTL5000_ADC_STEREO; 819 820 /* set mono to save power */ 821 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 822 channels == 1 ? 0 : stereo); 823 824 /* set codec clock base on lrclk */ 825 ret = sgtl5000_set_clock(codec, params_rate(params)); 826 if (ret) 827 return ret; 828 829 /* set i2s data format */ 830 switch (params_width(params)) { 831 case 16: 832 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 833 return -EINVAL; 834 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 835 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 836 SGTL5000_I2S_SCLKFREQ_SHIFT; 837 break; 838 case 20: 839 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 840 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 841 SGTL5000_I2S_SCLKFREQ_SHIFT; 842 break; 843 case 24: 844 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 845 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 846 SGTL5000_I2S_SCLKFREQ_SHIFT; 847 break; 848 case 32: 849 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 850 return -EINVAL; 851 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 852 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 853 SGTL5000_I2S_SCLKFREQ_SHIFT; 854 break; 855 default: 856 return -EINVAL; 857 } 858 859 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 860 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 861 i2s_ctl); 862 863 return 0; 864 } 865 866 /* 867 * set dac bias 868 * common state changes: 869 * startup: 870 * off --> standby --> prepare --> on 871 * standby --> prepare --> on 872 * 873 * stop: 874 * on --> prepare --> standby 875 */ 876 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 877 enum snd_soc_bias_level level) 878 { 879 struct sgtl5000_priv *sgtl = snd_soc_codec_get_drvdata(codec); 880 int ret; 881 882 switch (level) { 883 case SND_SOC_BIAS_ON: 884 case SND_SOC_BIAS_PREPARE: 885 case SND_SOC_BIAS_STANDBY: 886 regcache_cache_only(sgtl->regmap, false); 887 ret = regcache_sync(sgtl->regmap); 888 if (ret) { 889 regcache_cache_only(sgtl->regmap, true); 890 return ret; 891 } 892 893 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 894 SGTL5000_REFTOP_POWERUP, 895 SGTL5000_REFTOP_POWERUP); 896 break; 897 case SND_SOC_BIAS_OFF: 898 regcache_cache_only(sgtl->regmap, true); 899 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 900 SGTL5000_REFTOP_POWERUP, 0); 901 break; 902 } 903 904 return 0; 905 } 906 907 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 908 SNDRV_PCM_FMTBIT_S20_3LE |\ 909 SNDRV_PCM_FMTBIT_S24_LE |\ 910 SNDRV_PCM_FMTBIT_S32_LE) 911 912 static const struct snd_soc_dai_ops sgtl5000_ops = { 913 .hw_params = sgtl5000_pcm_hw_params, 914 .digital_mute = sgtl5000_digital_mute, 915 .set_fmt = sgtl5000_set_dai_fmt, 916 .set_sysclk = sgtl5000_set_dai_sysclk, 917 }; 918 919 static struct snd_soc_dai_driver sgtl5000_dai = { 920 .name = "sgtl5000", 921 .playback = { 922 .stream_name = "Playback", 923 .channels_min = 1, 924 .channels_max = 2, 925 /* 926 * only support 8~48K + 96K, 927 * TODO modify hw_param to support more 928 */ 929 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 930 .formats = SGTL5000_FORMATS, 931 }, 932 .capture = { 933 .stream_name = "Capture", 934 .channels_min = 1, 935 .channels_max = 2, 936 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 937 .formats = SGTL5000_FORMATS, 938 }, 939 .ops = &sgtl5000_ops, 940 .symmetric_rates = 1, 941 }; 942 943 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 944 { 945 switch (reg) { 946 case SGTL5000_CHIP_ID: 947 case SGTL5000_CHIP_ADCDAC_CTRL: 948 case SGTL5000_CHIP_ANA_STATUS: 949 return true; 950 } 951 952 return false; 953 } 954 955 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 956 { 957 switch (reg) { 958 case SGTL5000_CHIP_ID: 959 case SGTL5000_CHIP_DIG_POWER: 960 case SGTL5000_CHIP_CLK_CTRL: 961 case SGTL5000_CHIP_I2S_CTRL: 962 case SGTL5000_CHIP_SSS_CTRL: 963 case SGTL5000_CHIP_ADCDAC_CTRL: 964 case SGTL5000_CHIP_DAC_VOL: 965 case SGTL5000_CHIP_PAD_STRENGTH: 966 case SGTL5000_CHIP_ANA_ADC_CTRL: 967 case SGTL5000_CHIP_ANA_HP_CTRL: 968 case SGTL5000_CHIP_ANA_CTRL: 969 case SGTL5000_CHIP_LINREG_CTRL: 970 case SGTL5000_CHIP_REF_CTRL: 971 case SGTL5000_CHIP_MIC_CTRL: 972 case SGTL5000_CHIP_LINE_OUT_CTRL: 973 case SGTL5000_CHIP_LINE_OUT_VOL: 974 case SGTL5000_CHIP_ANA_POWER: 975 case SGTL5000_CHIP_PLL_CTRL: 976 case SGTL5000_CHIP_CLK_TOP_CTRL: 977 case SGTL5000_CHIP_ANA_STATUS: 978 case SGTL5000_CHIP_SHORT_CTRL: 979 case SGTL5000_CHIP_ANA_TEST2: 980 case SGTL5000_DAP_CTRL: 981 case SGTL5000_DAP_PEQ: 982 case SGTL5000_DAP_BASS_ENHANCE: 983 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 984 case SGTL5000_DAP_AUDIO_EQ: 985 case SGTL5000_DAP_SURROUND: 986 case SGTL5000_DAP_FLT_COEF_ACCESS: 987 case SGTL5000_DAP_COEF_WR_B0_MSB: 988 case SGTL5000_DAP_COEF_WR_B0_LSB: 989 case SGTL5000_DAP_EQ_BASS_BAND0: 990 case SGTL5000_DAP_EQ_BASS_BAND1: 991 case SGTL5000_DAP_EQ_BASS_BAND2: 992 case SGTL5000_DAP_EQ_BASS_BAND3: 993 case SGTL5000_DAP_EQ_BASS_BAND4: 994 case SGTL5000_DAP_MAIN_CHAN: 995 case SGTL5000_DAP_MIX_CHAN: 996 case SGTL5000_DAP_AVC_CTRL: 997 case SGTL5000_DAP_AVC_THRESHOLD: 998 case SGTL5000_DAP_AVC_ATTACK: 999 case SGTL5000_DAP_AVC_DECAY: 1000 case SGTL5000_DAP_COEF_WR_B1_MSB: 1001 case SGTL5000_DAP_COEF_WR_B1_LSB: 1002 case SGTL5000_DAP_COEF_WR_B2_MSB: 1003 case SGTL5000_DAP_COEF_WR_B2_LSB: 1004 case SGTL5000_DAP_COEF_WR_A1_MSB: 1005 case SGTL5000_DAP_COEF_WR_A1_LSB: 1006 case SGTL5000_DAP_COEF_WR_A2_MSB: 1007 case SGTL5000_DAP_COEF_WR_A2_LSB: 1008 return true; 1009 1010 default: 1011 return false; 1012 } 1013 } 1014 1015 /* 1016 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results 1017 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL 1018 * The calculatation was done for all possible register values which 1019 * is the array index and the following formula: 10^((idx−15)/40) * 100 1020 */ 1021 static const u8 vol_quot_table[] = { 1022 42, 45, 47, 50, 53, 56, 60, 63, 1023 67, 71, 75, 79, 84, 89, 94, 100, 1024 106, 112, 119, 126, 133, 141, 150, 158, 1025 168, 178, 188, 200, 211, 224, 237, 251 1026 }; 1027 1028 /* 1029 * sgtl5000 has 3 internal power supplies: 1030 * 1. VAG, normally set to vdda/2 1031 * 2. charge pump, set to different value 1032 * according to voltage of vdda and vddio 1033 * 3. line out VAG, normally set to vddio/2 1034 * 1035 * and should be set according to: 1036 * 1. vddd provided by external or not 1037 * 2. vdda and vddio voltage value. > 3.1v or not 1038 */ 1039 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1040 { 1041 int vddd; 1042 int vdda; 1043 int vddio; 1044 u16 ana_pwr; 1045 u16 lreg_ctrl; 1046 int vag; 1047 int lo_vag; 1048 int vol_quot; 1049 int lo_vol; 1050 size_t i; 1051 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1052 1053 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1054 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1055 vddd = (sgtl5000->num_supplies > VDDD) 1056 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer) 1057 : LDO_VOLTAGE; 1058 1059 vdda = vdda / 1000; 1060 vddio = vddio / 1000; 1061 vddd = vddd / 1000; 1062 1063 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1064 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1065 1066 return -EINVAL; 1067 } 1068 1069 /* according to datasheet, maximum voltage of supplies */ 1070 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1071 dev_err(codec->dev, 1072 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1073 vdda, vddio, vddd); 1074 1075 return -EINVAL; 1076 } 1077 1078 /* reset value */ 1079 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1080 ana_pwr |= SGTL5000_DAC_STEREO | 1081 SGTL5000_ADC_STEREO | 1082 SGTL5000_REFTOP_POWERUP; 1083 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1084 1085 if (vddio < 3100 && vdda < 3100) { 1086 /* enable internal oscillator used for charge pump */ 1087 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1088 SGTL5000_INT_OSC_EN, 1089 SGTL5000_INT_OSC_EN); 1090 /* Enable VDDC charge pump */ 1091 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1092 } else if (vddio >= 3100 && vdda >= 3100) { 1093 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP; 1094 /* VDDC use VDDIO rail */ 1095 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1096 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1097 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1098 } 1099 1100 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1101 1102 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1103 1104 /* 1105 * set ADC/DAC VAG to vdda / 2, 1106 * should stay in range (0.8v, 1.575v) 1107 */ 1108 vag = vdda / 2; 1109 if (vag <= SGTL5000_ANA_GND_BASE) 1110 vag = 0; 1111 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1112 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1113 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1114 else 1115 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1116 1117 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1118 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1119 1120 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1121 lo_vag = vddio / 2; 1122 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE) 1123 lo_vag = 0; 1124 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE + 1125 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1126 lo_vag = SGTL5000_LINE_OUT_GND_MAX; 1127 else 1128 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) / 1129 SGTL5000_LINE_OUT_GND_STP; 1130 1131 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1132 SGTL5000_LINE_OUT_CURRENT_MASK | 1133 SGTL5000_LINE_OUT_GND_MASK, 1134 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT | 1135 SGTL5000_LINE_OUT_CURRENT_360u << 1136 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1137 1138 /* 1139 * Set lineout output level in range (0..31) 1140 * the same value is used for right and left channel 1141 * 1142 * Searching for a suitable index solving this formula: 1143 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15 1144 */ 1145 vol_quot = (vag * 100) / lo_vag; 1146 lo_vol = 0; 1147 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) { 1148 if (vol_quot >= vol_quot_table[i]) 1149 lo_vol = i; 1150 else 1151 break; 1152 } 1153 1154 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL, 1155 SGTL5000_LINE_OUT_VOL_RIGHT_MASK | 1156 SGTL5000_LINE_OUT_VOL_LEFT_MASK, 1157 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT | 1158 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT); 1159 1160 return 0; 1161 } 1162 1163 static int sgtl5000_enable_regulators(struct i2c_client *client) 1164 { 1165 int ret; 1166 int i; 1167 int external_vddd = 0; 1168 struct regulator *vddd; 1169 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1170 1171 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1172 sgtl5000->supplies[i].supply = supply_names[i]; 1173 1174 vddd = regulator_get_optional(&client->dev, "VDDD"); 1175 if (IS_ERR(vddd)) { 1176 /* See if it's just not registered yet */ 1177 if (PTR_ERR(vddd) == -EPROBE_DEFER) 1178 return -EPROBE_DEFER; 1179 } else { 1180 external_vddd = 1; 1181 regulator_put(vddd); 1182 } 1183 1184 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies) 1185 - 1 + external_vddd; 1186 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies, 1187 sgtl5000->supplies); 1188 if (ret) 1189 return ret; 1190 1191 ret = regulator_bulk_enable(sgtl5000->num_supplies, 1192 sgtl5000->supplies); 1193 if (!ret) 1194 usleep_range(10, 20); 1195 else 1196 regulator_bulk_free(sgtl5000->num_supplies, 1197 sgtl5000->supplies); 1198 1199 return ret; 1200 } 1201 1202 static int sgtl5000_probe(struct snd_soc_codec *codec) 1203 { 1204 int ret; 1205 u16 reg; 1206 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1207 1208 /* power up sgtl5000 */ 1209 ret = sgtl5000_set_power_regs(codec); 1210 if (ret) 1211 goto err; 1212 1213 /* enable small pop, introduce 400ms delay in turning off */ 1214 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1215 SGTL5000_SMALL_POP, 1); 1216 1217 /* disable short cut detector */ 1218 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1219 1220 /* 1221 * set i2s as default input of sound switch 1222 * TODO: add sound switch to control and dapm widge. 1223 */ 1224 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1225 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1226 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1227 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1228 1229 /* enable dac volume ramp by default */ 1230 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1231 SGTL5000_DAC_VOL_RAMP_EN | 1232 SGTL5000_DAC_MUTE_RIGHT | 1233 SGTL5000_DAC_MUTE_LEFT); 1234 1235 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f); 1236 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, reg); 1237 1238 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1239 SGTL5000_HP_ZCD_EN | 1240 SGTL5000_ADC_ZCD_EN); 1241 1242 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1243 SGTL5000_BIAS_R_MASK, 1244 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 1245 1246 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1247 SGTL5000_BIAS_VOLT_MASK, 1248 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT); 1249 /* 1250 * disable DAP 1251 * TODO: 1252 * Enable DAP in kcontrol and dapm. 1253 */ 1254 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1255 1256 /* Unmute DAC after start */ 1257 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1258 SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0); 1259 1260 return 0; 1261 1262 err: 1263 return ret; 1264 } 1265 1266 static int sgtl5000_remove(struct snd_soc_codec *codec) 1267 { 1268 return 0; 1269 } 1270 1271 static const struct snd_soc_codec_driver sgtl5000_driver = { 1272 .probe = sgtl5000_probe, 1273 .remove = sgtl5000_remove, 1274 .set_bias_level = sgtl5000_set_bias_level, 1275 .suspend_bias_off = true, 1276 .component_driver = { 1277 .controls = sgtl5000_snd_controls, 1278 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1279 .dapm_widgets = sgtl5000_dapm_widgets, 1280 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1281 .dapm_routes = sgtl5000_dapm_routes, 1282 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1283 }, 1284 }; 1285 1286 static const struct regmap_config sgtl5000_regmap = { 1287 .reg_bits = 16, 1288 .val_bits = 16, 1289 .reg_stride = 2, 1290 1291 .max_register = SGTL5000_MAX_REG_OFFSET, 1292 .volatile_reg = sgtl5000_volatile, 1293 .readable_reg = sgtl5000_readable, 1294 1295 .cache_type = REGCACHE_RBTREE, 1296 .reg_defaults = sgtl5000_reg_defaults, 1297 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1298 }; 1299 1300 /* 1301 * Write all the default values from sgtl5000_reg_defaults[] array into the 1302 * sgtl5000 registers, to make sure we always start with the sane registers 1303 * values as stated in the datasheet. 1304 * 1305 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1306 * we follow this approach to guarantee we always start from the default values 1307 * and avoid problems like, not being able to probe after an audio playback 1308 * followed by a system reset or a 'reboot' command in Linux 1309 */ 1310 static void sgtl5000_fill_defaults(struct i2c_client *client) 1311 { 1312 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1313 int i, ret, val, index; 1314 1315 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1316 val = sgtl5000_reg_defaults[i].def; 1317 index = sgtl5000_reg_defaults[i].reg; 1318 ret = regmap_write(sgtl5000->regmap, index, val); 1319 if (ret) 1320 dev_err(&client->dev, 1321 "%s: error %d setting reg 0x%02x to 0x%04x\n", 1322 __func__, ret, index, val); 1323 } 1324 } 1325 1326 static int sgtl5000_i2c_probe(struct i2c_client *client, 1327 const struct i2c_device_id *id) 1328 { 1329 struct sgtl5000_priv *sgtl5000; 1330 int ret, reg, rev; 1331 struct device_node *np = client->dev.of_node; 1332 u32 value; 1333 u16 ana_pwr; 1334 1335 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); 1336 if (!sgtl5000) 1337 return -ENOMEM; 1338 1339 i2c_set_clientdata(client, sgtl5000); 1340 1341 ret = sgtl5000_enable_regulators(client); 1342 if (ret) 1343 return ret; 1344 1345 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1346 if (IS_ERR(sgtl5000->regmap)) { 1347 ret = PTR_ERR(sgtl5000->regmap); 1348 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1349 goto disable_regs; 1350 } 1351 1352 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1353 if (IS_ERR(sgtl5000->mclk)) { 1354 ret = PTR_ERR(sgtl5000->mclk); 1355 /* Defer the probe to see if the clk will be provided later */ 1356 if (ret == -ENOENT) 1357 ret = -EPROBE_DEFER; 1358 1359 if (ret != -EPROBE_DEFER) 1360 dev_err(&client->dev, "Failed to get mclock: %d\n", 1361 ret); 1362 goto disable_regs; 1363 } 1364 1365 ret = clk_prepare_enable(sgtl5000->mclk); 1366 if (ret) { 1367 dev_err(&client->dev, "Error enabling clock %d\n", ret); 1368 goto disable_regs; 1369 } 1370 1371 /* Need 8 clocks before I2C accesses */ 1372 udelay(1); 1373 1374 /* read chip information */ 1375 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1376 if (ret) { 1377 dev_err(&client->dev, "Error reading chip id %d\n", ret); 1378 goto disable_clk; 1379 } 1380 1381 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1382 SGTL5000_PARTID_PART_ID) { 1383 dev_err(&client->dev, 1384 "Device with ID register %x is not a sgtl5000\n", reg); 1385 ret = -ENODEV; 1386 goto disable_clk; 1387 } 1388 1389 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1390 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1391 sgtl5000->revision = rev; 1392 1393 /* reconfigure the clocks in case we're using the PLL */ 1394 ret = regmap_write(sgtl5000->regmap, 1395 SGTL5000_CHIP_CLK_CTRL, 1396 SGTL5000_CHIP_CLK_CTRL_DEFAULT); 1397 if (ret) 1398 dev_err(&client->dev, 1399 "Error %d initializing CHIP_CLK_CTRL\n", ret); 1400 1401 /* Follow section 2.2.1.1 of AN3663 */ 1402 ana_pwr = SGTL5000_ANA_POWER_DEFAULT; 1403 if (sgtl5000->num_supplies <= VDDD) { 1404 /* internal VDDD at 1.2V */ 1405 ret = regmap_update_bits(sgtl5000->regmap, 1406 SGTL5000_CHIP_LINREG_CTRL, 1407 SGTL5000_LINREG_VDDD_MASK, 1408 LINREG_VDDD); 1409 if (ret) 1410 dev_err(&client->dev, 1411 "Error %d setting LINREG_VDDD\n", ret); 1412 1413 ana_pwr |= SGTL5000_LINEREG_D_POWERUP; 1414 dev_info(&client->dev, 1415 "Using internal LDO instead of VDDD: check ER1 erratum\n"); 1416 } else { 1417 /* using external LDO for VDDD 1418 * Clear startup powerup and simple powerup 1419 * bits to save power 1420 */ 1421 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP 1422 | SGTL5000_LINREG_SIMPLE_POWERUP); 1423 dev_dbg(&client->dev, "Using external VDDD\n"); 1424 } 1425 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1426 if (ret) 1427 dev_err(&client->dev, 1428 "Error %d setting CHIP_ANA_POWER to %04x\n", 1429 ret, ana_pwr); 1430 1431 if (np) { 1432 if (!of_property_read_u32(np, 1433 "micbias-resistor-k-ohms", &value)) { 1434 switch (value) { 1435 case SGTL5000_MICBIAS_OFF: 1436 sgtl5000->micbias_resistor = 0; 1437 break; 1438 case SGTL5000_MICBIAS_2K: 1439 sgtl5000->micbias_resistor = 1; 1440 break; 1441 case SGTL5000_MICBIAS_4K: 1442 sgtl5000->micbias_resistor = 2; 1443 break; 1444 case SGTL5000_MICBIAS_8K: 1445 sgtl5000->micbias_resistor = 3; 1446 break; 1447 default: 1448 sgtl5000->micbias_resistor = 2; 1449 dev_err(&client->dev, 1450 "Unsuitable MicBias resistor\n"); 1451 } 1452 } else { 1453 /* default is 4Kohms */ 1454 sgtl5000->micbias_resistor = 2; 1455 } 1456 if (!of_property_read_u32(np, 1457 "micbias-voltage-m-volts", &value)) { 1458 /* 1250mV => 0 */ 1459 /* steps of 250mV */ 1460 if ((value >= 1250) && (value <= 3000)) 1461 sgtl5000->micbias_voltage = (value / 250) - 5; 1462 else { 1463 sgtl5000->micbias_voltage = 0; 1464 dev_err(&client->dev, 1465 "Unsuitable MicBias voltage\n"); 1466 } 1467 } else { 1468 sgtl5000->micbias_voltage = 0; 1469 } 1470 } 1471 1472 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW; 1473 if (!of_property_read_u32(np, "lrclk-strength", &value)) { 1474 if (value > I2S_LRCLK_STRENGTH_HIGH) 1475 value = I2S_LRCLK_STRENGTH_LOW; 1476 sgtl5000->lrclk_strength = value; 1477 } 1478 1479 /* Ensure sgtl5000 will start with sane register values */ 1480 sgtl5000_fill_defaults(client); 1481 1482 ret = snd_soc_register_codec(&client->dev, 1483 &sgtl5000_driver, &sgtl5000_dai, 1); 1484 if (ret) 1485 goto disable_clk; 1486 1487 return 0; 1488 1489 disable_clk: 1490 clk_disable_unprepare(sgtl5000->mclk); 1491 1492 disable_regs: 1493 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); 1494 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); 1495 1496 return ret; 1497 } 1498 1499 static int sgtl5000_i2c_remove(struct i2c_client *client) 1500 { 1501 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1502 1503 snd_soc_unregister_codec(&client->dev); 1504 clk_disable_unprepare(sgtl5000->mclk); 1505 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); 1506 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); 1507 1508 return 0; 1509 } 1510 1511 static const struct i2c_device_id sgtl5000_id[] = { 1512 {"sgtl5000", 0}, 1513 {}, 1514 }; 1515 1516 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1517 1518 static const struct of_device_id sgtl5000_dt_ids[] = { 1519 { .compatible = "fsl,sgtl5000", }, 1520 { /* sentinel */ } 1521 }; 1522 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1523 1524 static struct i2c_driver sgtl5000_i2c_driver = { 1525 .driver = { 1526 .name = "sgtl5000", 1527 .of_match_table = sgtl5000_dt_ids, 1528 }, 1529 .probe = sgtl5000_i2c_probe, 1530 .remove = sgtl5000_i2c_remove, 1531 .id_table = sgtl5000_id, 1532 }; 1533 1534 module_i2c_driver(sgtl5000_i2c_driver); 1535 1536 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1537 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1538 MODULE_LICENSE("GPL"); 1539