1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2023 Richtek Technology Corp. 4 // 5 // Author: ChiYuan Huang <cy_huang@richtek.com> 6 // 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/property.h> 17 #include <linux/regmap.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 #include <sound/tlv.h> 21 22 #define RTQ9128_REG_SDI_SEL 0x00 23 #define RTQ9128_REG_SDO_SEL 0x01 24 #define RTQ9128_REG_I2S_OPT 0x02 25 #define RTQ9128_REG_MISC 0x03 26 #define RTQ9128_REG_STATE_CTRL 0x04 27 #define RTQ9128_REG_PLLTRI_GEN1 0x05 28 #define RTQ9128_REG_PLLTRI_GEN2 0x06 29 #define RTQ9128_REG_PWM_SS_OPT 0x07 30 #define RTQ9128_REG_DSP_EN 0x08 31 #define RTQ9128_REG_TDM_TX_CH1 0x21 32 #define RTQ9128_REG_TDM_RX_CH1 0x25 33 #define RTQ9128_REG_MS_VOL 0x30 34 #define RTQ9128_REG_CH1_VOL 0x31 35 #define RTQ9128_REG_CH2_VOL 0x32 36 #define RTQ9128_REG_CH3_VOL 0x33 37 #define RTQ9128_REG_CH4_VOL 0x34 38 #define RTQ9128_REG_PROT_OPT 0x71 39 #define RTQ9128_REG_EFUSE_DATA 0xE0 40 #define RTQ9128_REG_VENDOR_ID 0xF9 41 42 #define RTQ9154_REG_CH1_VOL 0x34 43 #define RTQ9154_REG_CH2_VOL 0x33 44 #define RTQ9154_REG_CH3_VOL 0x32 45 #define RTQ9154_REG_CH4_VOL 0x31 46 #define RTQ9154_REG_AUTOULQM 0xAD 47 48 #define RTQ9128_CHSTAT_VAL_MASK GENMASK(1, 0) 49 #define RTQ9128_DOLEN_MASK GENMASK(7, 6) 50 #define RTQ9128_TDMSRCIN_MASK GENMASK(5, 4) 51 #define RTQ9128_AUDBIT_MASK GENMASK(5, 4) 52 #define RTQ9128_AUDFMT_MASK GENMASK(3, 0) 53 #define RTQ9128_MSMUTE_MASK BIT(0) 54 #define RTQ9128_DIE_CHECK_MASK GENMASK(4, 0) 55 #define RTQ9128_VENDOR_ID_MASK GENMASK(19, 8) 56 #define RTQ9128_MODEL_ID_MASK GENMASK(7, 4) 57 58 #define RTQ9128_SOFT_RESET_VAL 0x80 59 #define RTQ9128_VENDOR_ID_VAL 0x470 60 #define RTQ9128_ALLCH_HIZ_VAL 0x55 61 #define RTQ9128_ALLCH_ULQM_VAL 0xFF 62 #define RTQ9128_TKA470B_VAL 0 63 #define RTQ9128_RTQ9128DH_VAL 0x0F 64 #define RTQ9128_RTQ9128DL_VAL 0x10 65 #define RTQ9154_MODEL_ID 0x08 66 67 #define RTQ9154_AUTOULQM_VAL 0x82 68 69 enum rtq9128_chip_model { 70 CHIP_MODEL_RTQ9128 = 0, 71 CHIP_MODEL_RTQ9154, 72 CHIP_MODEL_MAX 73 }; 74 75 struct rtq9128_data { 76 struct gpio_desc *enable; 77 unsigned int daifmt; 78 int tdm_slots; 79 int tdm_slot_width; 80 bool tdm_input_data2_select; 81 enum rtq9128_chip_model chip_model; 82 }; 83 84 struct rtq9128_init_reg { 85 unsigned int reg; 86 unsigned int val; 87 }; 88 89 static int rtq9128_get_reg_size(unsigned int reg) 90 { 91 switch (reg) { 92 case 0x5C ... 0x6F: 93 case 0x98 ... 0x9F: 94 case 0xC0 ... 0xC3: 95 case 0xC8 ... 0xCF: 96 case 0xDF ... 0xE5: 97 case 0xF9: 98 return 4; 99 case 0x40 ... 0x4F: 100 return 3; 101 case 0x30 ... 0x35: 102 case 0x8C ... 0x97: 103 case 0xC4 ... 0xC7: 104 case 0xD7 ... 0xDA: 105 return 2; 106 default: 107 return 1; 108 } 109 } 110 111 static int rtq9128_i2c_write(void *context, const void *data, size_t count) 112 { 113 struct device *dev = context; 114 struct i2c_client *i2c = to_i2c_client(dev); 115 u8 reg = *(u8 *)data; 116 int rg_size; 117 118 if (count != 5) { 119 dev_err(dev, "Invalid write for data length (%d)\n", (int)count); 120 return -EINVAL; 121 } 122 123 rg_size = rtq9128_get_reg_size(reg); 124 return i2c_smbus_write_i2c_block_data(i2c, reg, rg_size, data + count - rg_size); 125 } 126 127 static int rtq9128_i2c_read(void *context, const void *reg_buf, size_t reg_size, void *val_buf, 128 size_t val_size) 129 { 130 struct device *dev = context; 131 struct i2c_client *i2c = to_i2c_client(dev); 132 u8 reg = *(u8 *)reg_buf; 133 u8 data_tmp[4] = {}; 134 int rg_size, ret; 135 136 if (reg_size != 1 || val_size != 4) { 137 dev_err(dev, "Invalid read for reg_size (%d) or val_size (%d)\n", (int)reg_size, 138 (int)val_size); 139 return -EINVAL; 140 } 141 142 rg_size = rtq9128_get_reg_size(reg); 143 ret = i2c_smbus_read_i2c_block_data(i2c, reg, rg_size, data_tmp); 144 if (ret < 0) 145 return ret; 146 else if (ret != rg_size) 147 return -EIO; 148 149 memset(val_buf, 0, val_size - rg_size); 150 memcpy(val_buf + val_size - rg_size, data_tmp, rg_size); 151 152 return 0; 153 } 154 155 static const struct regmap_bus rtq9128_regmap_bus = { 156 .write = rtq9128_i2c_write, 157 .read = rtq9128_i2c_read, 158 .max_raw_read = 4, 159 .max_raw_write = 4, 160 }; 161 162 static bool rtq9128_is_readable_reg(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case 0x00 ... 0x2B: 166 case 0x30 ... 0x35: 167 case 0x40 ... 0x56: 168 case 0x5C ... 0x76: 169 case 0x80 ... 0xAD: 170 case 0xB0 ... 0xBA: 171 case 0xC0 ... 0xE5: 172 case 0xF0 ... 0xFB: 173 return true; 174 default: 175 return false; 176 } 177 } 178 179 static bool rtq9128_is_writeable_reg(struct device *dev, unsigned int reg) 180 { 181 switch (reg) { 182 case 0x00 ... 0x1F: 183 case 0x21 ... 0x2B: 184 case 0x30 ... 0x35: 185 case 0x40 ... 0x56: 186 case 0x5C ... 0x76: 187 case 0x80 ... 0x8B: 188 case 0xA0 ... 0xAD: 189 case 0xB0 ... 0xBA: 190 case 0xC0: 191 case 0xD0 ... 0xDE: 192 case 0xE0 ... 0xE5: 193 case 0xF0 ... 0xF3: 194 case 0xF6 ... 0xF8: 195 case 0xFA ... 0xFB: 196 return true; 197 default: 198 return false; 199 } 200 } 201 202 static bool rtq9128_is_volatile_reg(struct device *dev, unsigned int reg) 203 { 204 switch (reg) { 205 case 0x0F ... 0x17: 206 case 0x20: 207 case 0x53: 208 case 0x55: 209 case 0x5C ... 0x6F: 210 case 0x8C ... 0x9F: 211 case 0xC0 ... 0xCF: 212 case 0xDF: 213 case 0xF0 ... 0xF1: 214 case 0xF4 ... 0xF5: 215 return true; 216 default: 217 return false; 218 } 219 } 220 221 static const struct regmap_config rtq9128_regmap_config = { 222 .name = "rtq9128", 223 .reg_bits = 8, 224 .val_bits = 32, 225 .val_format_endian = REGMAP_ENDIAN_BIG, 226 .cache_type = REGCACHE_MAPLE, 227 228 .readable_reg = rtq9128_is_readable_reg, 229 .writeable_reg = rtq9128_is_writeable_reg, 230 .volatile_reg = rtq9128_is_volatile_reg, 231 .num_reg_defaults_raw = RTQ9128_REG_VENDOR_ID + 1, 232 }; 233 234 static const DECLARE_TLV_DB_SCALE(dig_tlv, -10375, 25, 0); 235 236 static const DECLARE_TLV_DB_RANGE(spkgain_tlv, 237 0, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), 238 4, 5, TLV_DB_SCALE_ITEM(1500, 300, 0), 239 ); 240 241 static const char * const source_select_text[] = { "CH1", "CH2", "CH3", "CH4" }; 242 static const char * const pwmfreq_select_text[] = { "8fs", "10fs", "40fs", "44fs", "48fs" }; 243 static const char * const phase_select_text[] = { 244 "0 degree", "45 degree", "90 degree", "135 degree", 245 "180 degree", "225 degree", "270 degree", "315 degree", 246 }; 247 static const char * const dvdduv_select_text[] = { "1P4V", "1P5V", "2P1V", "2P3V" }; 248 249 static const struct soc_enum rtq9128_ch1_si_enum = 250 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 6, ARRAY_SIZE(source_select_text), source_select_text); 251 static const struct soc_enum rtq9128_ch2_si_enum = 252 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 4, ARRAY_SIZE(source_select_text), source_select_text); 253 static const struct soc_enum rtq9128_ch3_si_enum = 254 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 2, ARRAY_SIZE(source_select_text), source_select_text); 255 static const struct soc_enum rtq9128_ch4_si_enum = 256 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 0, ARRAY_SIZE(source_select_text), source_select_text); 257 static const struct soc_enum rtq9128_pwm_freq_enum = 258 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 4, ARRAY_SIZE(pwmfreq_select_text), 259 pwmfreq_select_text); 260 static const struct soc_enum rtq9128_out2_phase_enum = 261 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 0, ARRAY_SIZE(phase_select_text), 262 phase_select_text); 263 static const struct soc_enum rtq9128_out3_phase_enum = 264 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 4, ARRAY_SIZE(phase_select_text), 265 phase_select_text); 266 static const struct soc_enum rtq9128_out4_phase_enum = 267 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 0, ARRAY_SIZE(phase_select_text), 268 phase_select_text); 269 270 static const struct soc_enum rtq9154_ch1_si_enum = 271 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 0, ARRAY_SIZE(source_select_text), 272 source_select_text); 273 static const struct soc_enum rtq9154_ch2_si_enum = 274 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 2, ARRAY_SIZE(source_select_text), 275 source_select_text); 276 static const struct soc_enum rtq9154_ch3_si_enum = 277 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 4, ARRAY_SIZE(source_select_text), 278 source_select_text); 279 static const struct soc_enum rtq9154_ch4_si_enum = 280 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 6, ARRAY_SIZE(source_select_text), 281 source_select_text); 282 static const struct soc_enum rtq9154_out1_phase_enum = 283 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 0, ARRAY_SIZE(phase_select_text), 284 phase_select_text); 285 static const struct soc_enum rtq9154_out2_phase_enum = 286 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 4, ARRAY_SIZE(phase_select_text), 287 phase_select_text); 288 static const struct soc_enum rtq9154_out3_phase_enum = 289 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 0, ARRAY_SIZE(phase_select_text), 290 phase_select_text); 291 292 /* 293 * In general usage, DVDD could be 1P8V, 3P0V or 3P3V. 294 * This DVDD undervoltage protection is to prevent from the abnormal power 295 * lose case while the amplifier is operating. Due to the different DVDD 296 * application, treat this threshold as a user choosable option. 297 */ 298 static const struct soc_enum rtq9128_dvdduv_select_enum = 299 SOC_ENUM_SINGLE(RTQ9128_REG_PROT_OPT, 6, ARRAY_SIZE(dvdduv_select_text), 300 dvdduv_select_text); 301 302 static const struct snd_kcontrol_new rtq9128_snd_ctrls[] = { 303 SOC_SINGLE_TLV("MS Volume", RTQ9128_REG_MS_VOL, 2, 511, 1, dig_tlv), 304 SOC_SINGLE_TLV("CH1 Volume", RTQ9128_REG_CH1_VOL, 2, 511, 1, dig_tlv), 305 SOC_SINGLE_TLV("CH2 Volume", RTQ9128_REG_CH2_VOL, 2, 511, 1, dig_tlv), 306 SOC_SINGLE_TLV("CH3 Volume", RTQ9128_REG_CH3_VOL, 2, 511, 1, dig_tlv), 307 SOC_SINGLE_TLV("CH4 Volume", RTQ9128_REG_CH4_VOL, 2, 511, 1, dig_tlv), 308 SOC_SINGLE_TLV("SPK Gain Volume", RTQ9128_REG_MISC, 0, 5, 0, spkgain_tlv), 309 SOC_SINGLE("PBTL12 Switch", RTQ9128_REG_MISC, 5, 1, 0), 310 SOC_SINGLE("PBTL34 Switch", RTQ9128_REG_MISC, 4, 1, 0), 311 SOC_SINGLE("Spread Spectrum Switch", RTQ9128_REG_PWM_SS_OPT, 7, 1, 0), 312 SOC_SINGLE("SDO Select", RTQ9128_REG_SDO_SEL, 0, 15, 0), 313 SOC_ENUM("CH1 SI Select", rtq9128_ch1_si_enum), 314 SOC_ENUM("CH2 SI Select", rtq9128_ch2_si_enum), 315 SOC_ENUM("CH3 SI Select", rtq9128_ch3_si_enum), 316 SOC_ENUM("CH4 SI Select", rtq9128_ch4_si_enum), 317 SOC_ENUM("PWM FREQ Select", rtq9128_pwm_freq_enum), 318 SOC_ENUM("OUT2 Phase Select", rtq9128_out2_phase_enum), 319 SOC_ENUM("OUT3 Phase Select", rtq9128_out3_phase_enum), 320 SOC_ENUM("OUT4 Phase Select", rtq9128_out4_phase_enum), 321 SOC_ENUM("DVDD UV Threshold Select", rtq9128_dvdduv_select_enum), 322 }; 323 324 static const struct snd_kcontrol_new rtq9154_snd_ctrls[] = { 325 SOC_SINGLE_TLV("MS Volume", RTQ9128_REG_MS_VOL, 2, 511, 1, dig_tlv), 326 SOC_SINGLE_TLV("CH1 Volume", RTQ9154_REG_CH1_VOL, 2, 511, 1, dig_tlv), 327 SOC_SINGLE_TLV("CH2 Volume", RTQ9154_REG_CH2_VOL, 2, 511, 1, dig_tlv), 328 SOC_SINGLE_TLV("CH3 Volume", RTQ9154_REG_CH3_VOL, 2, 511, 1, dig_tlv), 329 SOC_SINGLE_TLV("CH4 Volume", RTQ9154_REG_CH4_VOL, 2, 511, 1, dig_tlv), 330 SOC_SINGLE_TLV("SPK Gain Volume", RTQ9128_REG_MISC, 0, 5, 0, spkgain_tlv), 331 SOC_SINGLE("PBTL12 Switch", RTQ9128_REG_MISC, 4, 1, 0), 332 SOC_SINGLE("PBTL34 Switch", RTQ9128_REG_MISC, 5, 1, 0), 333 SOC_SINGLE("Spread Spectrum Switch", RTQ9128_REG_PWM_SS_OPT, 7, 1, 0), 334 SOC_SINGLE("SDO Select", RTQ9128_REG_SDO_SEL, 0, 15, 0), 335 SOC_ENUM("CH1 SI Select", rtq9154_ch1_si_enum), 336 SOC_ENUM("CH2 SI Select", rtq9154_ch2_si_enum), 337 SOC_ENUM("CH3 SI Select", rtq9154_ch3_si_enum), 338 SOC_ENUM("CH4 SI Select", rtq9154_ch4_si_enum), 339 SOC_ENUM("PWM FREQ Select", rtq9128_pwm_freq_enum), 340 SOC_ENUM("OUT1 Phase Select", rtq9154_out1_phase_enum), 341 SOC_ENUM("OUT2 Phase Select", rtq9154_out2_phase_enum), 342 SOC_ENUM("OUT3 Phase Select", rtq9154_out3_phase_enum), 343 SOC_ENUM("DVDD UV Threshold Select", rtq9128_dvdduv_select_enum), 344 }; 345 346 static int rtq9128_dac_power_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, 347 int event) 348 { 349 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 350 struct rtq9128_data *data = snd_soc_component_get_drvdata(comp); 351 unsigned int shift, mask; 352 int ret; 353 354 dev_dbg(comp->dev, "%s: %s event %d\n", __func__, w->name, event); 355 356 if (snd_soc_dapm_widget_name_cmp(w, "DAC1") == 0) 357 shift = 6; 358 else if (snd_soc_dapm_widget_name_cmp(w, "DAC2") == 0) 359 shift = 4; 360 else if (snd_soc_dapm_widget_name_cmp(w, "DAC3") == 0) 361 shift = 2; 362 else 363 shift = 0; 364 365 /* Compared to RTQ9128, RTQ9154 use the reverse order for DACx bitfield location */ 366 if (data->chip_model == CHIP_MODEL_RTQ9154) 367 shift = 6 - shift; 368 369 mask = RTQ9128_CHSTAT_VAL_MASK << shift; 370 371 /* Turn channel state to Normal or HiZ */ 372 ret = snd_soc_component_write_field(comp, RTQ9128_REG_STATE_CTRL, mask, 373 event != SND_SOC_DAPM_POST_PMU); 374 if (ret < 0) 375 return ret; 376 377 /* 378 * For each channel turns on, HW will trigger DC load detect and DC 379 * offset calibration, the time is needed for all the actions done. 380 */ 381 if (event == SND_SOC_DAPM_POST_PMU) 382 msleep(25); 383 384 return 0; 385 } 386 387 static const struct snd_soc_dapm_widget rtq9128_dapm_widgets[] = { 388 SND_SOC_DAPM_DAC_E("DAC1", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 389 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 390 SND_SOC_DAPM_DAC_E("DAC2", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 391 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 392 SND_SOC_DAPM_DAC_E("DAC3", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 393 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 394 SND_SOC_DAPM_DAC_E("DAC4", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 395 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 396 SND_SOC_DAPM_OUTPUT("OUT1"), 397 SND_SOC_DAPM_OUTPUT("OUT2"), 398 SND_SOC_DAPM_OUTPUT("OUT3"), 399 SND_SOC_DAPM_OUTPUT("OUT4"), 400 }; 401 402 static const struct snd_soc_dapm_route rtq9128_dapm_routes[] = { 403 { "DAC1", NULL, "Playback" }, 404 { "DAC2", NULL, "Playback" }, 405 { "DAC3", NULL, "Playback" }, 406 { "DAC4", NULL, "Playback" }, 407 { "OUT1", NULL, "DAC1" }, 408 { "OUT2", NULL, "DAC2" }, 409 { "OUT3", NULL, "DAC3" }, 410 { "OUT4", NULL, "DAC4" }, 411 { "Capture", NULL, "DAC1" }, 412 { "Capture", NULL, "DAC2" }, 413 { "Capture", NULL, "DAC3" }, 414 { "Capture", NULL, "DAC4" }, 415 }; 416 417 static const struct rtq9128_init_reg rtq9128_tka470b_tables[] = { 418 { 0xA0, 0xEF }, 419 { 0x0D, 0x00 }, 420 { 0x03, 0x45 }, 421 { 0x05, 0x31 }, 422 { 0x06, 0x23 }, 423 { 0x70, 0x11 }, 424 { 0x75, 0x1F }, 425 { 0xB6, 0x03 }, 426 { 0xB9, 0x03 }, 427 { 0xB8, 0x03 }, 428 { 0xC1, 0xFF }, 429 { 0xF8, 0x72 }, 430 { 0x30, 0x180 }, 431 }; 432 433 static const struct rtq9128_init_reg rtq9128_dh_tables[] = { 434 { 0x0F, 0x00 }, 435 { 0x03, 0x4D }, 436 { 0xB2, 0xFF }, 437 { 0xB3, 0xFF }, 438 { 0x30, 0x180 }, 439 { 0x8A, 0x55 }, 440 { 0x72, 0x00 }, 441 { 0xB1, 0xE3 }, 442 }; 443 444 static const struct rtq9128_init_reg rtq9128_dl_tables[] = { 445 { 0x0F, 0x00 }, 446 { 0x03, 0x4D }, 447 { 0x30, 0x180 }, 448 { 0x8A, 0x55 }, 449 { 0x72, 0x00 }, 450 { 0xB1, 0xE3 }, 451 }; 452 453 static int rtq9128_component_probe(struct snd_soc_component *comp) 454 { 455 struct rtq9128_data *data = snd_soc_component_get_drvdata(comp); 456 const struct rtq9128_init_reg *table, *curr; 457 size_t table_size; 458 unsigned int val; 459 int i, ret; 460 461 ret = pm_runtime_resume_and_get(comp->dev); 462 if (ret < 0) { 463 dev_err(comp->dev, "Failed to resume device (%d)\n", ret); 464 return ret; 465 } 466 467 val = snd_soc_component_read(comp, RTQ9128_REG_EFUSE_DATA); 468 469 switch (FIELD_GET(RTQ9128_DIE_CHECK_MASK, val)) { 470 case RTQ9128_TKA470B_VAL: 471 table = rtq9128_tka470b_tables; 472 table_size = ARRAY_SIZE(rtq9128_tka470b_tables); 473 break; 474 case RTQ9128_RTQ9128DH_VAL: 475 table = rtq9128_dh_tables; 476 table_size = ARRAY_SIZE(rtq9128_dh_tables); 477 break; 478 default: 479 table = rtq9128_dl_tables; 480 table_size = ARRAY_SIZE(rtq9128_dl_tables); 481 break; 482 } 483 484 for (i = 0, curr = table; i < table_size; i++, curr++) { 485 ret = snd_soc_component_write(comp, curr->reg, curr->val); 486 if (ret < 0) 487 return ret; 488 } 489 490 491 if (data->chip_model == CHIP_MODEL_RTQ9154) { 492 /* Enable RTQ9154 Specific AUTO ULQM feature */ 493 ret = snd_soc_component_write(comp, RTQ9154_REG_AUTOULQM, RTQ9154_AUTOULQM_VAL); 494 if (ret < 0) 495 return ret; 496 } 497 498 pm_runtime_mark_last_busy(comp->dev); 499 pm_runtime_put(comp->dev); 500 501 return 0; 502 } 503 504 static const struct snd_soc_component_driver rtq9128_comp_driver = { 505 .probe = rtq9128_component_probe, 506 .controls = rtq9128_snd_ctrls, 507 .num_controls = ARRAY_SIZE(rtq9128_snd_ctrls), 508 .dapm_widgets = rtq9128_dapm_widgets, 509 .num_dapm_widgets = ARRAY_SIZE(rtq9128_dapm_widgets), 510 .dapm_routes = rtq9128_dapm_routes, 511 .num_dapm_routes = ARRAY_SIZE(rtq9128_dapm_routes), 512 .use_pmdown_time = 1, 513 .endianness = 1, 514 }; 515 516 static const struct snd_soc_component_driver rtq9154_comp_driver = { 517 .probe = rtq9128_component_probe, 518 .controls = rtq9154_snd_ctrls, 519 .num_controls = ARRAY_SIZE(rtq9154_snd_ctrls), 520 .dapm_widgets = rtq9128_dapm_widgets, 521 .num_dapm_widgets = ARRAY_SIZE(rtq9128_dapm_widgets), 522 .dapm_routes = rtq9128_dapm_routes, 523 .num_dapm_routes = ARRAY_SIZE(rtq9128_dapm_routes), 524 .use_pmdown_time = 1, 525 .endianness = 1, 526 }; 527 528 static int rtq9128_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 529 { 530 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 531 struct device *dev = dai->dev; 532 533 dev_dbg(dev, "%s: fmt 0x%8x\n", __func__, fmt); 534 535 /* Only support bitclock & framesync as consumer */ 536 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_BC_FC) { 537 dev_err(dev, "Only support BCK and LRCK as consumer\n"); 538 return -EINVAL; 539 } 540 541 /* Store here and will be used in runtime hw_params for DAI format setting */ 542 data->daifmt = fmt; 543 544 return 0; 545 } 546 547 static int rtq9128_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 548 unsigned int rx_mask, int slots, int slot_width) 549 { 550 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 551 struct snd_soc_component *comp = dai->component; 552 struct device *dev = dai->dev; 553 unsigned int mask, start_loc, srcin_select; 554 int i, frame_length, ret; 555 556 dev_dbg(dev, "%s: slot %d slot_width %d, tx/rx mask 0x%x 0x%x\n", __func__, slots, 557 slot_width, tx_mask, rx_mask); 558 559 if (slots <= 0 || slot_width <= 0 || slot_width % 8) { 560 dev_err(dev, "Invalid slot numbers (%d) or width (%d)\n", slots, slot_width); 561 return -EINVAL; 562 } 563 564 /* HW supported maximum frame length 512 */ 565 frame_length = slots * slot_width; 566 if (frame_length > 512) { 567 dev_err(dev, "frame length exceed the maximum (%d)\n", frame_length); 568 return -EINVAL; 569 } 570 571 if (!rx_mask || hweight_long(tx_mask) > slots || hweight_long(rx_mask) > slots || 572 fls(tx_mask) > slots || fls(rx_mask) > slots) { 573 dev_err(dev, "Invalid tx/rx mask (0x%x/0x%x)\n", tx_mask, rx_mask); 574 return -EINVAL; 575 } 576 577 for (mask = tx_mask, i = 0; i < 4 && mask; i++) { 578 start_loc = (ffs(mask) - 1) * slot_width / 8; 579 mask &= ~BIT(ffs(mask) - 1); 580 581 ret = snd_soc_component_write(comp, RTQ9128_REG_TDM_TX_CH1 + i, start_loc); 582 if (ret < 0) { 583 dev_err(dev, "Failed to assign tx_loc %d (%d)\n", i, ret); 584 return ret; 585 } 586 } 587 588 for (mask = rx_mask, i = 0; i < 4 && mask; i++) { 589 start_loc = (ffs(mask) - 1) * slot_width / 8; 590 mask &= ~BIT(ffs(mask) - 1); 591 592 ret = snd_soc_component_write(comp, RTQ9128_REG_TDM_RX_CH1 + i, start_loc); 593 if (ret < 0) { 594 dev_err(dev, "Failed to assign rx_loc %d (%d)\n", i, ret); 595 return ret; 596 } 597 } 598 599 srcin_select = data->tdm_input_data2_select ? RTQ9128_TDMSRCIN_MASK : 0; 600 ret = snd_soc_component_update_bits(comp, RTQ9128_REG_SDO_SEL, RTQ9128_TDMSRCIN_MASK, 601 srcin_select); 602 if (ret < 0) { 603 dev_err(dev, "Failed to configure TDM source input select\n"); 604 return ret; 605 } 606 607 data->tdm_slots = slots; 608 data->tdm_slot_width = slot_width; 609 610 return 0; 611 } 612 613 static int rtq9128_dai_hw_params(struct snd_pcm_substream *stream, struct snd_pcm_hw_params *param, 614 struct snd_soc_dai *dai) 615 { 616 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 617 unsigned int width, slot_width, bitrate, audbit, dolen; 618 struct snd_soc_component *comp = dai->component; 619 struct device *dev = dai->dev; 620 unsigned int fmtval, audfmt; 621 int ret; 622 623 dev_dbg(dev, "%s: width %d\n", __func__, params_width(param)); 624 625 fmtval = FIELD_GET(SND_SOC_DAIFMT_FORMAT_MASK, data->daifmt); 626 if (data->tdm_slots && fmtval != SND_SOC_DAIFMT_DSP_A && fmtval != SND_SOC_DAIFMT_DSP_B) { 627 dev_err(dev, "TDM is used, format only support DSP_A or DSP_B\n"); 628 return -EINVAL; 629 } 630 631 switch (fmtval) { 632 case SND_SOC_DAIFMT_I2S: 633 audfmt = 8; 634 break; 635 case SND_SOC_DAIFMT_LEFT_J: 636 audfmt = 9; 637 break; 638 case SND_SOC_DAIFMT_RIGHT_J: 639 audfmt = 10; 640 break; 641 case SND_SOC_DAIFMT_DSP_A: 642 audfmt = data->tdm_slots ? 12 : 11; 643 break; 644 case SND_SOC_DAIFMT_DSP_B: 645 audfmt = data->tdm_slots ? 4 : 3; 646 break; 647 default: 648 dev_err(dev, "Unsupported format 0x%8x\n", fmtval); 649 return -EINVAL; 650 } 651 652 switch (width = params_width(param)) { 653 case 16: 654 audbit = 0; 655 break; 656 case 18: 657 audbit = 1; 658 break; 659 case 20: 660 audbit = 2; 661 break; 662 case 24: 663 case 32: 664 audbit = 3; 665 break; 666 default: 667 dev_err(dev, "Unsupported width (%d)\n", width); 668 return -EINVAL; 669 } 670 671 slot_width = params_physical_width(param); 672 673 if (data->tdm_slots) { 674 if (slot_width > data->tdm_slot_width) { 675 dev_err(dev, "slot width is larger than TDM slot width\n"); 676 return -EINVAL; 677 } 678 679 /* Check BCK not exceed the maximum supported rate 24.576MHz */ 680 bitrate = data->tdm_slots * data->tdm_slot_width * params_rate(param); 681 if (bitrate > 24576000) { 682 dev_err(dev, "bitrate exceed the maximum (%d)\n", bitrate); 683 return -EINVAL; 684 } 685 686 /* If TDM is used, configure slot width as TDM slot witdh */ 687 slot_width = data->tdm_slot_width; 688 } 689 690 switch (slot_width) { 691 case 16: 692 dolen = 0; 693 break; 694 case 24: 695 dolen = 1; 696 break; 697 case 32: 698 dolen = 2; 699 break; 700 default: 701 dev_err(dev, "Unsupported slot width (%d)\n", slot_width); 702 return -EINVAL; 703 } 704 705 ret = snd_soc_component_write_field(comp, RTQ9128_REG_I2S_OPT, RTQ9128_AUDFMT_MASK, audfmt); 706 if (ret < 0) 707 return ret; 708 709 ret = snd_soc_component_write_field(comp, RTQ9128_REG_I2S_OPT, RTQ9128_AUDBIT_MASK, audbit); 710 if (ret < 0) 711 return ret; 712 713 ret = snd_soc_component_write_field(comp, RTQ9128_REG_SDO_SEL, RTQ9128_DOLEN_MASK, dolen); 714 return ret < 0 ? ret : 0; 715 } 716 717 static int rtq9128_dai_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 718 { 719 struct snd_soc_component *comp = dai->component; 720 struct device *dev = dai->dev; 721 int ret; 722 723 dev_dbg(dev, "%s: mute (%d), stream (%d)\n", __func__, mute, stream); 724 725 ret = snd_soc_component_write_field(comp, RTQ9128_REG_DSP_EN, RTQ9128_MSMUTE_MASK, 726 mute ? 1 : 0); 727 return ret < 0 ? ret : 0; 728 } 729 730 static const struct snd_soc_dai_ops rtq9128_dai_ops = { 731 .set_fmt = rtq9128_dai_set_fmt, 732 .set_tdm_slot = rtq9128_dai_set_tdm_slot, 733 .hw_params = rtq9128_dai_hw_params, 734 .mute_stream = rtq9128_dai_mute_stream, 735 .no_capture_mute = 1, 736 }; 737 738 #define RTQ9128_FMTS_MASK (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE |\ 739 SNDRV_PCM_FMTBIT_S20_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 740 SNDRV_PCM_FMTBIT_S32_LE) 741 742 static struct snd_soc_dai_driver rtq9128_dai = { 743 .name = "rtq9128-aif", 744 .playback = { 745 .stream_name = "Playback", 746 .rates = SNDRV_PCM_RATE_8000_192000, 747 .formats = RTQ9128_FMTS_MASK, 748 .channels_min = 1, 749 .channels_max = 4, 750 }, 751 .capture = { 752 .stream_name = "Capture", 753 .rates = SNDRV_PCM_RATE_8000_192000, 754 .formats = RTQ9128_FMTS_MASK, 755 .channels_min = 1, 756 .channels_max = 4, 757 }, 758 .ops = &rtq9128_dai_ops, 759 .symmetric_rate = 1, 760 .symmetric_sample_bits = 1, 761 }; 762 763 static int rtq9128_probe(struct i2c_client *i2c) 764 { 765 struct device *dev = &i2c->dev; 766 struct rtq9128_data *data; 767 struct regmap *regmap; 768 unsigned int veninfo, venid, chip_model; 769 const struct snd_soc_component_driver *comp_drv; 770 int ret; 771 772 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 773 if (!data) 774 return -ENOMEM; 775 776 data->enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); 777 if (IS_ERR(data->enable)) 778 return dev_err_probe(dev, PTR_ERR(data->enable), "Failed to get 'enable' gpio\n"); 779 else if (data->enable) 780 usleep_range(10000, 11000); 781 782 data->tdm_input_data2_select = device_property_read_bool(dev, 783 "richtek,tdm-input-data2-select"); 784 785 i2c_set_clientdata(i2c, data); 786 787 /* 788 * Due to the bad design to combine SOFT_RESET bit with other function, 789 * directly use generic i2c API to trigger SOFT_RESET. 790 */ 791 ret = i2c_smbus_write_byte_data(i2c, RTQ9128_REG_MISC, RTQ9128_SOFT_RESET_VAL); 792 if (ret) 793 return dev_err_probe(dev, ret, "Failed to trigger software reset\n"); 794 795 /* After trigger soft reset, have to wait 10ms for digital reset done */ 796 usleep_range(10000, 11000); 797 798 regmap = devm_regmap_init(dev, &rtq9128_regmap_bus, dev, &rtq9128_regmap_config); 799 if (IS_ERR(regmap)) 800 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n"); 801 802 ret = regmap_read(regmap, RTQ9128_REG_VENDOR_ID, &veninfo); 803 if (ret) 804 return dev_err_probe(dev, ret, "Failed to get vendor id\n"); 805 806 venid = FIELD_GET(RTQ9128_VENDOR_ID_MASK, veninfo); 807 if (venid != RTQ9128_VENDOR_ID_VAL) 808 return dev_err_probe(dev, -ENODEV, "Vendor ID not match (0x%x)\n", venid); 809 810 chip_model = FIELD_GET(RTQ9128_MODEL_ID_MASK, veninfo); 811 switch (chip_model) { 812 case RTQ9154_MODEL_ID: 813 data->chip_model = CHIP_MODEL_RTQ9154; 814 comp_drv = &rtq9154_comp_driver; 815 break; 816 default: 817 data->chip_model = CHIP_MODEL_RTQ9128; 818 comp_drv = &rtq9128_comp_driver; 819 break; 820 } 821 822 pm_runtime_set_active(dev); 823 pm_runtime_mark_last_busy(dev); 824 ret = devm_pm_runtime_enable(dev); 825 if (ret) 826 return dev_err_probe(dev, ret, "Failed to enable pm runtime\n"); 827 828 return devm_snd_soc_register_component(dev, comp_drv, &rtq9128_dai, 1); 829 } 830 831 static int rtq9128_pm_runtime_suspend(struct device *dev) 832 { 833 struct rtq9128_data *data = dev_get_drvdata(dev); 834 struct regmap *regmap = dev_get_regmap(dev, NULL); 835 836 /* If 'enable' gpio not specified, change all channels to ultra low quiescent */ 837 if (!data->enable) 838 return regmap_write(regmap, RTQ9128_REG_STATE_CTRL, RTQ9128_ALLCH_ULQM_VAL); 839 840 gpiod_set_value_cansleep(data->enable, 0); 841 842 regcache_cache_only(regmap, true); 843 regcache_mark_dirty(regmap); 844 845 return 0; 846 } 847 848 static int rtq9128_pm_runtime_resume(struct device *dev) 849 { 850 struct rtq9128_data *data = dev_get_drvdata(dev); 851 struct regmap *regmap = dev_get_regmap(dev, NULL); 852 853 /* If 'enable' gpio not specified, change all channels to default Hi-Z */ 854 if (!data->enable) 855 return regmap_write(regmap, RTQ9128_REG_STATE_CTRL, RTQ9128_ALLCH_HIZ_VAL); 856 857 gpiod_set_value_cansleep(data->enable, 1); 858 859 /* Wait digital block to be ready */ 860 usleep_range(10000, 11000); 861 862 regcache_cache_only(regmap, false); 863 return regcache_sync(regmap); 864 } 865 866 static const struct dev_pm_ops rtq9128_pm_ops = { 867 RUNTIME_PM_OPS(rtq9128_pm_runtime_suspend, rtq9128_pm_runtime_resume, NULL) 868 }; 869 870 static const struct of_device_id rtq9128_device_table[] = { 871 { .compatible = "richtek,rtq9128" }, 872 {} 873 }; 874 MODULE_DEVICE_TABLE(of, rtq9128_device_table); 875 876 static struct i2c_driver rtq9128_driver = { 877 .driver = { 878 .name = "rtq9128", 879 .of_match_table = rtq9128_device_table, 880 .pm = pm_ptr(&rtq9128_pm_ops), 881 }, 882 .probe = rtq9128_probe, 883 }; 884 module_i2c_driver(rtq9128_driver); 885 886 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>"); 887 MODULE_DESCRIPTION("RTQ9128 4CH Audio Amplifier Driver"); 888 MODULE_LICENSE("GPL"); 889