1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2023 Richtek Technology Corp. 4 // 5 // Author: ChiYuan Huang <cy_huang@richtek.com> 6 // 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/kernel.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #define RTQ9128_REG_SDI_SEL 0x00 24 #define RTQ9128_REG_SDO_SEL 0x01 25 #define RTQ9128_REG_I2S_OPT 0x02 26 #define RTQ9128_REG_MISC 0x03 27 #define RTQ9128_REG_STATE_CTRL 0x04 28 #define RTQ9128_REG_PLLTRI_GEN1 0x05 29 #define RTQ9128_REG_PLLTRI_GEN2 0x06 30 #define RTQ9128_REG_PWM_SS_OPT 0x07 31 #define RTQ9128_REG_DSP_EN 0x08 32 #define RTQ9128_REG_TDM_TX_CH1 0x21 33 #define RTQ9128_REG_TDM_RX_CH1 0x25 34 #define RTQ9128_REG_MS_VOL 0x30 35 #define RTQ9128_REG_CH1_VOL 0x31 36 #define RTQ9128_REG_CH2_VOL 0x32 37 #define RTQ9128_REG_CH3_VOL 0x33 38 #define RTQ9128_REG_CH4_VOL 0x34 39 #define RTQ9128_REG_PROT_OPT 0x71 40 #define RTQ9128_REG_EFUSE_DATA 0xE0 41 #define RTQ9128_REG_VENDOR_ID 0xF9 42 43 #define RTQ9154_REG_CH1_VOL 0x34 44 #define RTQ9154_REG_CH2_VOL 0x33 45 #define RTQ9154_REG_CH3_VOL 0x32 46 #define RTQ9154_REG_CH4_VOL 0x31 47 #define RTQ9154_REG_AUTOULQM 0xAD 48 49 #define RTQ9128_CHSTAT_VAL_MASK GENMASK(1, 0) 50 #define RTQ9128_DOLEN_MASK GENMASK(7, 6) 51 #define RTQ9128_TDMSRCIN_MASK GENMASK(5, 4) 52 #define RTQ9128_AUDBIT_MASK GENMASK(5, 4) 53 #define RTQ9128_AUDFMT_MASK GENMASK(3, 0) 54 #define RTQ9128_MSMUTE_MASK BIT(0) 55 #define RTQ9128_DIE_CHECK_MASK GENMASK(4, 0) 56 #define RTQ9128_VENDOR_ID_MASK GENMASK(19, 8) 57 #define RTQ9128_MODEL_ID_MASK GENMASK(7, 4) 58 59 #define RTQ9128_SOFT_RESET_VAL 0x80 60 #define RTQ9128_VENDOR_ID_VAL 0x470 61 #define RTQ9128_ALLCH_HIZ_VAL 0x55 62 #define RTQ9128_ALLCH_ULQM_VAL 0xFF 63 #define RTQ9128_TKA470B_VAL 0 64 #define RTQ9128_RTQ9128DH_VAL 0x0F 65 #define RTQ9128_RTQ9128DL_VAL 0x10 66 #define RTQ9154_MODEL_ID 0x08 67 68 #define RTQ9154_AUTOULQM_VAL 0x82 69 70 enum rtq9128_chip_model { 71 CHIP_MODEL_RTQ9128 = 0, 72 CHIP_MODEL_RTQ9154, 73 CHIP_MODEL_MAX 74 }; 75 76 struct rtq9128_data { 77 struct gpio_desc *enable; 78 unsigned int daifmt; 79 int tdm_slots; 80 int tdm_slot_width; 81 bool tdm_input_data2_select; 82 enum rtq9128_chip_model chip_model; 83 }; 84 85 struct rtq9128_init_reg { 86 unsigned int reg; 87 unsigned int val; 88 }; 89 90 static int rtq9128_get_reg_size(unsigned int reg) 91 { 92 switch (reg) { 93 case 0x5C ... 0x6F: 94 case 0x98 ... 0x9F: 95 case 0xC0 ... 0xC3: 96 case 0xC8 ... 0xCF: 97 case 0xDF ... 0xE5: 98 case 0xF9: 99 return 4; 100 case 0x40 ... 0x4F: 101 return 3; 102 case 0x30 ... 0x35: 103 case 0x8C ... 0x97: 104 case 0xC4 ... 0xC7: 105 case 0xD7 ... 0xDA: 106 return 2; 107 default: 108 return 1; 109 } 110 } 111 112 static int rtq9128_i2c_write(void *context, const void *data, size_t count) 113 { 114 struct device *dev = context; 115 struct i2c_client *i2c = to_i2c_client(dev); 116 u8 reg = *(u8 *)data; 117 int rg_size; 118 119 if (count != 5) { 120 dev_err(dev, "Invalid write for data length (%d)\n", (int)count); 121 return -EINVAL; 122 } 123 124 rg_size = rtq9128_get_reg_size(reg); 125 return i2c_smbus_write_i2c_block_data(i2c, reg, rg_size, data + count - rg_size); 126 } 127 128 static int rtq9128_i2c_read(void *context, const void *reg_buf, size_t reg_size, void *val_buf, 129 size_t val_size) 130 { 131 struct device *dev = context; 132 struct i2c_client *i2c = to_i2c_client(dev); 133 u8 reg = *(u8 *)reg_buf; 134 u8 data_tmp[4] = {}; 135 int rg_size, ret; 136 137 if (reg_size != 1 || val_size != 4) { 138 dev_err(dev, "Invalid read for reg_size (%d) or val_size (%d)\n", (int)reg_size, 139 (int)val_size); 140 return -EINVAL; 141 } 142 143 rg_size = rtq9128_get_reg_size(reg); 144 ret = i2c_smbus_read_i2c_block_data(i2c, reg, rg_size, data_tmp); 145 if (ret < 0) 146 return ret; 147 else if (ret != rg_size) 148 return -EIO; 149 150 memset(val_buf, 0, val_size - rg_size); 151 memcpy(val_buf + val_size - rg_size, data_tmp, rg_size); 152 153 return 0; 154 } 155 156 static const struct regmap_bus rtq9128_regmap_bus = { 157 .write = rtq9128_i2c_write, 158 .read = rtq9128_i2c_read, 159 .max_raw_read = 4, 160 .max_raw_write = 4, 161 }; 162 163 static bool rtq9128_is_readable_reg(struct device *dev, unsigned int reg) 164 { 165 switch (reg) { 166 case 0x00 ... 0x2B: 167 case 0x30 ... 0x35: 168 case 0x40 ... 0x56: 169 case 0x5C ... 0x76: 170 case 0x80 ... 0xAD: 171 case 0xB0 ... 0xBA: 172 case 0xC0 ... 0xE5: 173 case 0xF0 ... 0xFB: 174 return true; 175 default: 176 return false; 177 } 178 } 179 180 static bool rtq9128_is_writeable_reg(struct device *dev, unsigned int reg) 181 { 182 switch (reg) { 183 case 0x00 ... 0x1F: 184 case 0x21 ... 0x2B: 185 case 0x30 ... 0x35: 186 case 0x40 ... 0x56: 187 case 0x5C ... 0x76: 188 case 0x80 ... 0x8B: 189 case 0xA0 ... 0xAD: 190 case 0xB0 ... 0xBA: 191 case 0xC0: 192 case 0xD0 ... 0xDE: 193 case 0xE0 ... 0xE5: 194 case 0xF0 ... 0xF3: 195 case 0xF6 ... 0xF8: 196 case 0xFA ... 0xFB: 197 return true; 198 default: 199 return false; 200 } 201 } 202 203 static bool rtq9128_is_volatile_reg(struct device *dev, unsigned int reg) 204 { 205 switch (reg) { 206 case 0x0F ... 0x17: 207 case 0x20: 208 case 0x53: 209 case 0x55: 210 case 0x5C ... 0x6F: 211 case 0x8C ... 0x9F: 212 case 0xC0 ... 0xCF: 213 case 0xDF: 214 case 0xF0 ... 0xF1: 215 case 0xF4 ... 0xF5: 216 return true; 217 default: 218 return false; 219 } 220 } 221 222 static const struct regmap_config rtq9128_regmap_config = { 223 .name = "rtq9128", 224 .reg_bits = 8, 225 .val_bits = 32, 226 .val_format_endian = REGMAP_ENDIAN_BIG, 227 .cache_type = REGCACHE_MAPLE, 228 229 .readable_reg = rtq9128_is_readable_reg, 230 .writeable_reg = rtq9128_is_writeable_reg, 231 .volatile_reg = rtq9128_is_volatile_reg, 232 .num_reg_defaults_raw = RTQ9128_REG_VENDOR_ID + 1, 233 }; 234 235 static const DECLARE_TLV_DB_SCALE(dig_tlv, -10375, 25, 0); 236 237 static const DECLARE_TLV_DB_RANGE(spkgain_tlv, 238 0, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), 239 4, 5, TLV_DB_SCALE_ITEM(1500, 300, 0), 240 ); 241 242 static const char * const source_select_text[] = { "CH1", "CH2", "CH3", "CH4" }; 243 static const char * const pwmfreq_select_text[] = { "8fs", "10fs", "40fs", "44fs", "48fs" }; 244 static const char * const phase_select_text[] = { 245 "0 degree", "45 degree", "90 degree", "135 degree", 246 "180 degree", "225 degree", "270 degree", "315 degree", 247 }; 248 static const char * const dvdduv_select_text[] = { "1P4V", "1P5V", "2P1V", "2P3V" }; 249 250 static const struct soc_enum rtq9128_ch1_si_enum = 251 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 6, ARRAY_SIZE(source_select_text), source_select_text); 252 static const struct soc_enum rtq9128_ch2_si_enum = 253 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 4, ARRAY_SIZE(source_select_text), source_select_text); 254 static const struct soc_enum rtq9128_ch3_si_enum = 255 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 2, ARRAY_SIZE(source_select_text), source_select_text); 256 static const struct soc_enum rtq9128_ch4_si_enum = 257 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 0, ARRAY_SIZE(source_select_text), source_select_text); 258 static const struct soc_enum rtq9128_pwm_freq_enum = 259 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 4, ARRAY_SIZE(pwmfreq_select_text), 260 pwmfreq_select_text); 261 static const struct soc_enum rtq9128_out2_phase_enum = 262 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 0, ARRAY_SIZE(phase_select_text), 263 phase_select_text); 264 static const struct soc_enum rtq9128_out3_phase_enum = 265 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 4, ARRAY_SIZE(phase_select_text), 266 phase_select_text); 267 static const struct soc_enum rtq9128_out4_phase_enum = 268 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 0, ARRAY_SIZE(phase_select_text), 269 phase_select_text); 270 271 static const struct soc_enum rtq9154_ch1_si_enum = 272 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 0, ARRAY_SIZE(source_select_text), 273 source_select_text); 274 static const struct soc_enum rtq9154_ch2_si_enum = 275 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 2, ARRAY_SIZE(source_select_text), 276 source_select_text); 277 static const struct soc_enum rtq9154_ch3_si_enum = 278 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 4, ARRAY_SIZE(source_select_text), 279 source_select_text); 280 static const struct soc_enum rtq9154_ch4_si_enum = 281 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 6, ARRAY_SIZE(source_select_text), 282 source_select_text); 283 static const struct soc_enum rtq9154_out1_phase_enum = 284 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 0, ARRAY_SIZE(phase_select_text), 285 phase_select_text); 286 static const struct soc_enum rtq9154_out2_phase_enum = 287 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 4, ARRAY_SIZE(phase_select_text), 288 phase_select_text); 289 static const struct soc_enum rtq9154_out3_phase_enum = 290 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 0, ARRAY_SIZE(phase_select_text), 291 phase_select_text); 292 293 /* 294 * In general usage, DVDD could be 1P8V, 3P0V or 3P3V. 295 * This DVDD undervoltage protection is to prevent from the abnormal power 296 * lose case while the amplifier is operating. Due to the different DVDD 297 * application, treat this threshold as a user choosable option. 298 */ 299 static const struct soc_enum rtq9128_dvdduv_select_enum = 300 SOC_ENUM_SINGLE(RTQ9128_REG_PROT_OPT, 6, ARRAY_SIZE(dvdduv_select_text), 301 dvdduv_select_text); 302 303 static const struct snd_kcontrol_new rtq9128_snd_ctrls[] = { 304 SOC_SINGLE_TLV("MS Volume", RTQ9128_REG_MS_VOL, 2, 511, 1, dig_tlv), 305 SOC_SINGLE_TLV("CH1 Volume", RTQ9128_REG_CH1_VOL, 2, 511, 1, dig_tlv), 306 SOC_SINGLE_TLV("CH2 Volume", RTQ9128_REG_CH2_VOL, 2, 511, 1, dig_tlv), 307 SOC_SINGLE_TLV("CH3 Volume", RTQ9128_REG_CH3_VOL, 2, 511, 1, dig_tlv), 308 SOC_SINGLE_TLV("CH4 Volume", RTQ9128_REG_CH4_VOL, 2, 511, 1, dig_tlv), 309 SOC_SINGLE_TLV("SPK Gain Volume", RTQ9128_REG_MISC, 0, 5, 0, spkgain_tlv), 310 SOC_SINGLE("PBTL12 Switch", RTQ9128_REG_MISC, 5, 1, 0), 311 SOC_SINGLE("PBTL34 Switch", RTQ9128_REG_MISC, 4, 1, 0), 312 SOC_SINGLE("Spread Spectrum Switch", RTQ9128_REG_PWM_SS_OPT, 7, 1, 0), 313 SOC_SINGLE("SDO Select", RTQ9128_REG_SDO_SEL, 0, 15, 0), 314 SOC_ENUM("CH1 SI Select", rtq9128_ch1_si_enum), 315 SOC_ENUM("CH2 SI Select", rtq9128_ch2_si_enum), 316 SOC_ENUM("CH3 SI Select", rtq9128_ch3_si_enum), 317 SOC_ENUM("CH4 SI Select", rtq9128_ch4_si_enum), 318 SOC_ENUM("PWM FREQ Select", rtq9128_pwm_freq_enum), 319 SOC_ENUM("OUT2 Phase Select", rtq9128_out2_phase_enum), 320 SOC_ENUM("OUT3 Phase Select", rtq9128_out3_phase_enum), 321 SOC_ENUM("OUT4 Phase Select", rtq9128_out4_phase_enum), 322 SOC_ENUM("DVDD UV Threshold Select", rtq9128_dvdduv_select_enum), 323 }; 324 325 static const struct snd_kcontrol_new rtq9154_snd_ctrls[] = { 326 SOC_SINGLE_TLV("MS Volume", RTQ9128_REG_MS_VOL, 2, 511, 1, dig_tlv), 327 SOC_SINGLE_TLV("CH1 Volume", RTQ9154_REG_CH1_VOL, 2, 511, 1, dig_tlv), 328 SOC_SINGLE_TLV("CH2 Volume", RTQ9154_REG_CH2_VOL, 2, 511, 1, dig_tlv), 329 SOC_SINGLE_TLV("CH3 Volume", RTQ9154_REG_CH3_VOL, 2, 511, 1, dig_tlv), 330 SOC_SINGLE_TLV("CH4 Volume", RTQ9154_REG_CH4_VOL, 2, 511, 1, dig_tlv), 331 SOC_SINGLE_TLV("SPK Gain Volume", RTQ9128_REG_MISC, 0, 5, 0, spkgain_tlv), 332 SOC_SINGLE("PBTL12 Switch", RTQ9128_REG_MISC, 4, 1, 0), 333 SOC_SINGLE("PBTL34 Switch", RTQ9128_REG_MISC, 5, 1, 0), 334 SOC_SINGLE("Spread Spectrum Switch", RTQ9128_REG_PWM_SS_OPT, 7, 1, 0), 335 SOC_SINGLE("SDO Select", RTQ9128_REG_SDO_SEL, 0, 15, 0), 336 SOC_ENUM("CH1 SI Select", rtq9154_ch1_si_enum), 337 SOC_ENUM("CH2 SI Select", rtq9154_ch2_si_enum), 338 SOC_ENUM("CH3 SI Select", rtq9154_ch3_si_enum), 339 SOC_ENUM("CH4 SI Select", rtq9154_ch4_si_enum), 340 SOC_ENUM("PWM FREQ Select", rtq9128_pwm_freq_enum), 341 SOC_ENUM("OUT1 Phase Select", rtq9154_out1_phase_enum), 342 SOC_ENUM("OUT2 Phase Select", rtq9154_out2_phase_enum), 343 SOC_ENUM("OUT3 Phase Select", rtq9154_out3_phase_enum), 344 SOC_ENUM("DVDD UV Threshold Select", rtq9128_dvdduv_select_enum), 345 }; 346 347 static int rtq9128_dac_power_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, 348 int event) 349 { 350 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 351 struct rtq9128_data *data = snd_soc_component_get_drvdata(comp); 352 unsigned int shift, mask; 353 int ret; 354 355 dev_dbg(comp->dev, "%s: %s event %d\n", __func__, w->name, event); 356 357 if (snd_soc_dapm_widget_name_cmp(w, "DAC1") == 0) 358 shift = 6; 359 else if (snd_soc_dapm_widget_name_cmp(w, "DAC2") == 0) 360 shift = 4; 361 else if (snd_soc_dapm_widget_name_cmp(w, "DAC3") == 0) 362 shift = 2; 363 else 364 shift = 0; 365 366 /* Compared to RTQ9128, RTQ9154 use the reverse order for DACx bitfield location */ 367 if (data->chip_model == CHIP_MODEL_RTQ9154) 368 shift = 6 - shift; 369 370 mask = RTQ9128_CHSTAT_VAL_MASK << shift; 371 372 /* Turn channel state to Normal or HiZ */ 373 ret = snd_soc_component_write_field(comp, RTQ9128_REG_STATE_CTRL, mask, 374 event != SND_SOC_DAPM_POST_PMU); 375 if (ret < 0) 376 return ret; 377 378 /* 379 * For each channel turns on, HW will trigger DC load detect and DC 380 * offset calibration, the time is needed for all the actions done. 381 */ 382 if (event == SND_SOC_DAPM_POST_PMU) 383 msleep(25); 384 385 return 0; 386 } 387 388 static const struct snd_soc_dapm_widget rtq9128_dapm_widgets[] = { 389 SND_SOC_DAPM_DAC_E("DAC1", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 390 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 391 SND_SOC_DAPM_DAC_E("DAC2", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 392 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 393 SND_SOC_DAPM_DAC_E("DAC3", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 394 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 395 SND_SOC_DAPM_DAC_E("DAC4", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 396 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 397 SND_SOC_DAPM_OUTPUT("OUT1"), 398 SND_SOC_DAPM_OUTPUT("OUT2"), 399 SND_SOC_DAPM_OUTPUT("OUT3"), 400 SND_SOC_DAPM_OUTPUT("OUT4"), 401 }; 402 403 static const struct snd_soc_dapm_route rtq9128_dapm_routes[] = { 404 { "DAC1", NULL, "Playback" }, 405 { "DAC2", NULL, "Playback" }, 406 { "DAC3", NULL, "Playback" }, 407 { "DAC4", NULL, "Playback" }, 408 { "OUT1", NULL, "DAC1" }, 409 { "OUT2", NULL, "DAC2" }, 410 { "OUT3", NULL, "DAC3" }, 411 { "OUT4", NULL, "DAC4" }, 412 { "Capture", NULL, "DAC1" }, 413 { "Capture", NULL, "DAC2" }, 414 { "Capture", NULL, "DAC3" }, 415 { "Capture", NULL, "DAC4" }, 416 }; 417 418 static const struct rtq9128_init_reg rtq9128_tka470b_tables[] = { 419 { 0xA0, 0xEF }, 420 { 0x0D, 0x00 }, 421 { 0x03, 0x45 }, 422 { 0x05, 0x31 }, 423 { 0x06, 0x23 }, 424 { 0x70, 0x11 }, 425 { 0x75, 0x1F }, 426 { 0xB6, 0x03 }, 427 { 0xB9, 0x03 }, 428 { 0xB8, 0x03 }, 429 { 0xC1, 0xFF }, 430 { 0xF8, 0x72 }, 431 { 0x30, 0x180 }, 432 }; 433 434 static const struct rtq9128_init_reg rtq9128_dh_tables[] = { 435 { 0x0F, 0x00 }, 436 { 0x03, 0x4D }, 437 { 0xB2, 0xFF }, 438 { 0xB3, 0xFF }, 439 { 0x30, 0x180 }, 440 { 0x8A, 0x55 }, 441 { 0x72, 0x00 }, 442 { 0xB1, 0xE3 }, 443 }; 444 445 static const struct rtq9128_init_reg rtq9128_dl_tables[] = { 446 { 0x0F, 0x00 }, 447 { 0x03, 0x4D }, 448 { 0x30, 0x180 }, 449 { 0x8A, 0x55 }, 450 { 0x72, 0x00 }, 451 { 0xB1, 0xE3 }, 452 }; 453 454 static int rtq9128_component_probe(struct snd_soc_component *comp) 455 { 456 struct rtq9128_data *data = snd_soc_component_get_drvdata(comp); 457 const struct rtq9128_init_reg *table, *curr; 458 size_t table_size; 459 unsigned int val; 460 int i, ret; 461 462 ret = pm_runtime_resume_and_get(comp->dev); 463 if (ret < 0) { 464 dev_err(comp->dev, "Failed to resume device (%d)\n", ret); 465 return ret; 466 } 467 468 val = snd_soc_component_read(comp, RTQ9128_REG_EFUSE_DATA); 469 470 switch (FIELD_GET(RTQ9128_DIE_CHECK_MASK, val)) { 471 case RTQ9128_TKA470B_VAL: 472 table = rtq9128_tka470b_tables; 473 table_size = ARRAY_SIZE(rtq9128_tka470b_tables); 474 break; 475 case RTQ9128_RTQ9128DH_VAL: 476 table = rtq9128_dh_tables; 477 table_size = ARRAY_SIZE(rtq9128_dh_tables); 478 break; 479 default: 480 table = rtq9128_dl_tables; 481 table_size = ARRAY_SIZE(rtq9128_dl_tables); 482 break; 483 } 484 485 for (i = 0, curr = table; i < table_size; i++, curr++) { 486 ret = snd_soc_component_write(comp, curr->reg, curr->val); 487 if (ret < 0) 488 return ret; 489 } 490 491 492 if (data->chip_model == CHIP_MODEL_RTQ9154) { 493 /* Enable RTQ9154 Specific AUTO ULQM feature */ 494 ret = snd_soc_component_write(comp, RTQ9154_REG_AUTOULQM, RTQ9154_AUTOULQM_VAL); 495 if (ret < 0) 496 return ret; 497 } 498 499 pm_runtime_mark_last_busy(comp->dev); 500 pm_runtime_put(comp->dev); 501 502 return 0; 503 } 504 505 static const struct snd_soc_component_driver rtq9128_comp_driver = { 506 .probe = rtq9128_component_probe, 507 .controls = rtq9128_snd_ctrls, 508 .num_controls = ARRAY_SIZE(rtq9128_snd_ctrls), 509 .dapm_widgets = rtq9128_dapm_widgets, 510 .num_dapm_widgets = ARRAY_SIZE(rtq9128_dapm_widgets), 511 .dapm_routes = rtq9128_dapm_routes, 512 .num_dapm_routes = ARRAY_SIZE(rtq9128_dapm_routes), 513 .use_pmdown_time = 1, 514 .endianness = 1, 515 }; 516 517 static const struct snd_soc_component_driver rtq9154_comp_driver = { 518 .probe = rtq9128_component_probe, 519 .controls = rtq9154_snd_ctrls, 520 .num_controls = ARRAY_SIZE(rtq9154_snd_ctrls), 521 .dapm_widgets = rtq9128_dapm_widgets, 522 .num_dapm_widgets = ARRAY_SIZE(rtq9128_dapm_widgets), 523 .dapm_routes = rtq9128_dapm_routes, 524 .num_dapm_routes = ARRAY_SIZE(rtq9128_dapm_routes), 525 .use_pmdown_time = 1, 526 .endianness = 1, 527 }; 528 529 static int rtq9128_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 530 { 531 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 532 struct device *dev = dai->dev; 533 534 dev_dbg(dev, "%s: fmt 0x%8x\n", __func__, fmt); 535 536 /* Only support bitclock & framesync as consumer */ 537 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_BC_FC) { 538 dev_err(dev, "Only support BCK and LRCK as consumer\n"); 539 return -EINVAL; 540 } 541 542 /* Store here and will be used in runtime hw_params for DAI format setting */ 543 data->daifmt = fmt; 544 545 return 0; 546 } 547 548 static int rtq9128_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 549 unsigned int rx_mask, int slots, int slot_width) 550 { 551 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 552 struct snd_soc_component *comp = dai->component; 553 struct device *dev = dai->dev; 554 unsigned int mask, start_loc, srcin_select; 555 int i, frame_length, ret; 556 557 dev_dbg(dev, "%s: slot %d slot_width %d, tx/rx mask 0x%x 0x%x\n", __func__, slots, 558 slot_width, tx_mask, rx_mask); 559 560 if (slots <= 0 || slot_width <= 0 || slot_width % 8) { 561 dev_err(dev, "Invalid slot numbers (%d) or width (%d)\n", slots, slot_width); 562 return -EINVAL; 563 } 564 565 /* HW supported maximum frame length 512 */ 566 frame_length = slots * slot_width; 567 if (frame_length > 512) { 568 dev_err(dev, "frame length exceed the maximum (%d)\n", frame_length); 569 return -EINVAL; 570 } 571 572 if (!rx_mask || hweight_long(tx_mask) > slots || hweight_long(rx_mask) > slots || 573 fls(tx_mask) > slots || fls(rx_mask) > slots) { 574 dev_err(dev, "Invalid tx/rx mask (0x%x/0x%x)\n", tx_mask, rx_mask); 575 return -EINVAL; 576 } 577 578 for (mask = tx_mask, i = 0; i < 4 && mask; i++) { 579 start_loc = (ffs(mask) - 1) * slot_width / 8; 580 mask &= ~BIT(ffs(mask) - 1); 581 582 ret = snd_soc_component_write(comp, RTQ9128_REG_TDM_TX_CH1 + i, start_loc); 583 if (ret < 0) { 584 dev_err(dev, "Failed to assign tx_loc %d (%d)\n", i, ret); 585 return ret; 586 } 587 } 588 589 for (mask = rx_mask, i = 0; i < 4 && mask; i++) { 590 start_loc = (ffs(mask) - 1) * slot_width / 8; 591 mask &= ~BIT(ffs(mask) - 1); 592 593 ret = snd_soc_component_write(comp, RTQ9128_REG_TDM_RX_CH1 + i, start_loc); 594 if (ret < 0) { 595 dev_err(dev, "Failed to assign rx_loc %d (%d)\n", i, ret); 596 return ret; 597 } 598 } 599 600 srcin_select = data->tdm_input_data2_select ? RTQ9128_TDMSRCIN_MASK : 0; 601 ret = snd_soc_component_update_bits(comp, RTQ9128_REG_SDO_SEL, RTQ9128_TDMSRCIN_MASK, 602 srcin_select); 603 if (ret < 0) { 604 dev_err(dev, "Failed to configure TDM source input select\n"); 605 return ret; 606 } 607 608 data->tdm_slots = slots; 609 data->tdm_slot_width = slot_width; 610 611 return 0; 612 } 613 614 static int rtq9128_dai_hw_params(struct snd_pcm_substream *stream, struct snd_pcm_hw_params *param, 615 struct snd_soc_dai *dai) 616 { 617 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 618 unsigned int width, slot_width, bitrate, audbit, dolen; 619 struct snd_soc_component *comp = dai->component; 620 struct device *dev = dai->dev; 621 unsigned int fmtval, audfmt; 622 int ret; 623 624 dev_dbg(dev, "%s: width %d\n", __func__, params_width(param)); 625 626 fmtval = FIELD_GET(SND_SOC_DAIFMT_FORMAT_MASK, data->daifmt); 627 if (data->tdm_slots && fmtval != SND_SOC_DAIFMT_DSP_A && fmtval != SND_SOC_DAIFMT_DSP_B) { 628 dev_err(dev, "TDM is used, format only support DSP_A or DSP_B\n"); 629 return -EINVAL; 630 } 631 632 switch (fmtval) { 633 case SND_SOC_DAIFMT_I2S: 634 audfmt = 8; 635 break; 636 case SND_SOC_DAIFMT_LEFT_J: 637 audfmt = 9; 638 break; 639 case SND_SOC_DAIFMT_RIGHT_J: 640 audfmt = 10; 641 break; 642 case SND_SOC_DAIFMT_DSP_A: 643 audfmt = data->tdm_slots ? 12 : 11; 644 break; 645 case SND_SOC_DAIFMT_DSP_B: 646 audfmt = data->tdm_slots ? 4 : 3; 647 break; 648 default: 649 dev_err(dev, "Unsupported format 0x%8x\n", fmtval); 650 return -EINVAL; 651 } 652 653 switch (width = params_width(param)) { 654 case 16: 655 audbit = 0; 656 break; 657 case 18: 658 audbit = 1; 659 break; 660 case 20: 661 audbit = 2; 662 break; 663 case 24: 664 case 32: 665 audbit = 3; 666 break; 667 default: 668 dev_err(dev, "Unsupported width (%d)\n", width); 669 return -EINVAL; 670 } 671 672 slot_width = params_physical_width(param); 673 674 if (data->tdm_slots) { 675 if (slot_width > data->tdm_slot_width) { 676 dev_err(dev, "slot width is larger than TDM slot width\n"); 677 return -EINVAL; 678 } 679 680 /* Check BCK not exceed the maximum supported rate 24.576MHz */ 681 bitrate = data->tdm_slots * data->tdm_slot_width * params_rate(param); 682 if (bitrate > 24576000) { 683 dev_err(dev, "bitrate exceed the maximum (%d)\n", bitrate); 684 return -EINVAL; 685 } 686 687 /* If TDM is used, configure slot width as TDM slot witdh */ 688 slot_width = data->tdm_slot_width; 689 } 690 691 switch (slot_width) { 692 case 16: 693 dolen = 0; 694 break; 695 case 24: 696 dolen = 1; 697 break; 698 case 32: 699 dolen = 2; 700 break; 701 default: 702 dev_err(dev, "Unsupported slot width (%d)\n", slot_width); 703 return -EINVAL; 704 } 705 706 ret = snd_soc_component_write_field(comp, RTQ9128_REG_I2S_OPT, RTQ9128_AUDFMT_MASK, audfmt); 707 if (ret < 0) 708 return ret; 709 710 ret = snd_soc_component_write_field(comp, RTQ9128_REG_I2S_OPT, RTQ9128_AUDBIT_MASK, audbit); 711 if (ret < 0) 712 return ret; 713 714 ret = snd_soc_component_write_field(comp, RTQ9128_REG_SDO_SEL, RTQ9128_DOLEN_MASK, dolen); 715 return ret < 0 ? ret : 0; 716 } 717 718 static int rtq9128_dai_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 719 { 720 struct snd_soc_component *comp = dai->component; 721 struct device *dev = dai->dev; 722 int ret; 723 724 dev_dbg(dev, "%s: mute (%d), stream (%d)\n", __func__, mute, stream); 725 726 ret = snd_soc_component_write_field(comp, RTQ9128_REG_DSP_EN, RTQ9128_MSMUTE_MASK, 727 mute ? 1 : 0); 728 return ret < 0 ? ret : 0; 729 } 730 731 static const struct snd_soc_dai_ops rtq9128_dai_ops = { 732 .set_fmt = rtq9128_dai_set_fmt, 733 .set_tdm_slot = rtq9128_dai_set_tdm_slot, 734 .hw_params = rtq9128_dai_hw_params, 735 .mute_stream = rtq9128_dai_mute_stream, 736 .no_capture_mute = 1, 737 }; 738 739 #define RTQ9128_FMTS_MASK (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE |\ 740 SNDRV_PCM_FMTBIT_S20_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 741 SNDRV_PCM_FMTBIT_S32_LE) 742 743 static struct snd_soc_dai_driver rtq9128_dai = { 744 .name = "rtq9128-aif", 745 .playback = { 746 .stream_name = "Playback", 747 .rates = SNDRV_PCM_RATE_8000_192000, 748 .formats = RTQ9128_FMTS_MASK, 749 .channels_min = 1, 750 .channels_max = 4, 751 }, 752 .capture = { 753 .stream_name = "Capture", 754 .rates = SNDRV_PCM_RATE_8000_192000, 755 .formats = RTQ9128_FMTS_MASK, 756 .channels_min = 1, 757 .channels_max = 4, 758 }, 759 .ops = &rtq9128_dai_ops, 760 .symmetric_rate = 1, 761 .symmetric_sample_bits = 1, 762 }; 763 764 static int rtq9128_probe(struct i2c_client *i2c) 765 { 766 struct device *dev = &i2c->dev; 767 struct rtq9128_data *data; 768 struct regmap *regmap; 769 unsigned int veninfo, venid, chip_model; 770 const struct snd_soc_component_driver *comp_drv; 771 int ret; 772 773 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 774 if (!data) 775 return -ENOMEM; 776 777 data->enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); 778 if (IS_ERR(data->enable)) 779 return dev_err_probe(dev, PTR_ERR(data->enable), "Failed to get 'enable' gpio\n"); 780 else if (data->enable) 781 usleep_range(10000, 11000); 782 783 data->tdm_input_data2_select = device_property_read_bool(dev, 784 "richtek,tdm-input-data2-select"); 785 786 i2c_set_clientdata(i2c, data); 787 788 /* 789 * Due to the bad design to combine SOFT_RESET bit with other function, 790 * directly use generic i2c API to trigger SOFT_RESET. 791 */ 792 ret = i2c_smbus_write_byte_data(i2c, RTQ9128_REG_MISC, RTQ9128_SOFT_RESET_VAL); 793 if (ret) 794 return dev_err_probe(dev, ret, "Failed to trigger software reset\n"); 795 796 /* After trigger soft reset, have to wait 10ms for digital reset done */ 797 usleep_range(10000, 11000); 798 799 regmap = devm_regmap_init(dev, &rtq9128_regmap_bus, dev, &rtq9128_regmap_config); 800 if (IS_ERR(regmap)) 801 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n"); 802 803 ret = regmap_read(regmap, RTQ9128_REG_VENDOR_ID, &veninfo); 804 if (ret) 805 return dev_err_probe(dev, ret, "Failed to get vendor id\n"); 806 807 venid = FIELD_GET(RTQ9128_VENDOR_ID_MASK, veninfo); 808 if (venid != RTQ9128_VENDOR_ID_VAL) 809 return dev_err_probe(dev, -ENODEV, "Vendor ID not match (0x%x)\n", venid); 810 811 chip_model = FIELD_GET(RTQ9128_MODEL_ID_MASK, veninfo); 812 switch (chip_model) { 813 case RTQ9154_MODEL_ID: 814 data->chip_model = CHIP_MODEL_RTQ9154; 815 comp_drv = &rtq9154_comp_driver; 816 break; 817 default: 818 data->chip_model = CHIP_MODEL_RTQ9128; 819 comp_drv = &rtq9128_comp_driver; 820 break; 821 } 822 823 pm_runtime_set_active(dev); 824 pm_runtime_mark_last_busy(dev); 825 ret = devm_pm_runtime_enable(dev); 826 if (ret) 827 return dev_err_probe(dev, ret, "Failed to enable pm runtime\n"); 828 829 return devm_snd_soc_register_component(dev, comp_drv, &rtq9128_dai, 1); 830 } 831 832 static int rtq9128_pm_runtime_suspend(struct device *dev) 833 { 834 struct rtq9128_data *data = dev_get_drvdata(dev); 835 struct regmap *regmap = dev_get_regmap(dev, NULL); 836 837 /* If 'enable' gpio not specified, change all channels to ultra low quiescent */ 838 if (!data->enable) 839 return regmap_write(regmap, RTQ9128_REG_STATE_CTRL, RTQ9128_ALLCH_ULQM_VAL); 840 841 gpiod_set_value_cansleep(data->enable, 0); 842 843 regcache_cache_only(regmap, true); 844 regcache_mark_dirty(regmap); 845 846 return 0; 847 } 848 849 static int rtq9128_pm_runtime_resume(struct device *dev) 850 { 851 struct rtq9128_data *data = dev_get_drvdata(dev); 852 struct regmap *regmap = dev_get_regmap(dev, NULL); 853 854 /* If 'enable' gpio not specified, change all channels to default Hi-Z */ 855 if (!data->enable) 856 return regmap_write(regmap, RTQ9128_REG_STATE_CTRL, RTQ9128_ALLCH_HIZ_VAL); 857 858 gpiod_set_value_cansleep(data->enable, 1); 859 860 /* Wait digital block to be ready */ 861 usleep_range(10000, 11000); 862 863 regcache_cache_only(regmap, false); 864 return regcache_sync(regmap); 865 } 866 867 static const struct dev_pm_ops rtq9128_pm_ops = { 868 RUNTIME_PM_OPS(rtq9128_pm_runtime_suspend, rtq9128_pm_runtime_resume, NULL) 869 }; 870 871 static const struct of_device_id rtq9128_device_table[] = { 872 { .compatible = "richtek,rtq9128" }, 873 {} 874 }; 875 MODULE_DEVICE_TABLE(of, rtq9128_device_table); 876 877 static struct i2c_driver rtq9128_driver = { 878 .driver = { 879 .name = "rtq9128", 880 .of_match_table = rtq9128_device_table, 881 .pm = pm_ptr(&rtq9128_pm_ops), 882 }, 883 .probe = rtq9128_probe, 884 }; 885 module_i2c_driver(rtq9128_driver); 886 887 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>"); 888 MODULE_DESCRIPTION("RTQ9128 4CH Audio Amplifier Driver"); 889 MODULE_LICENSE("GPL"); 890