1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2023 Richtek Technology Corp. 4 // 5 // Author: ChiYuan Huang <cy_huang@richtek.com> 6 // 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/kernel.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/tlv.h> 22 23 #define RTQ9128_REG_SDI_SEL 0x00 24 #define RTQ9128_REG_SDO_SEL 0x01 25 #define RTQ9128_REG_I2S_OPT 0x02 26 #define RTQ9128_REG_MISC 0x03 27 #define RTQ9128_REG_STATE_CTRL 0x04 28 #define RTQ9128_REG_PLLTRI_GEN1 0x05 29 #define RTQ9128_REG_PLLTRI_GEN2 0x06 30 #define RTQ9128_REG_PWM_SS_OPT 0x07 31 #define RTQ9128_REG_DSP_EN 0x08 32 #define RTQ9128_REG_TDM_TX_CH1 0x21 33 #define RTQ9128_REG_TDM_RX_CH1 0x25 34 #define RTQ9128_REG_MS_VOL 0x30 35 #define RTQ9128_REG_CH1_VOL 0x31 36 #define RTQ9128_REG_CH2_VOL 0x32 37 #define RTQ9128_REG_CH3_VOL 0x33 38 #define RTQ9128_REG_CH4_VOL 0x34 39 #define RTQ9128_REG_PROT_OPT 0x71 40 #define RTQ9128_REG_EFUSE_DATA 0xE0 41 #define RTQ9128_REG_VENDOR_ID 0xF9 42 43 #define RTQ9128_CHSTAT_VAL_MASK GENMASK(1, 0) 44 #define RTQ9128_DOLEN_MASK GENMASK(7, 6) 45 #define RTQ9128_TDMSRCIN_MASK GENMASK(5, 4) 46 #define RTQ9128_AUDBIT_MASK GENMASK(5, 4) 47 #define RTQ9128_AUDFMT_MASK GENMASK(3, 0) 48 #define RTQ9128_MSMUTE_MASK BIT(0) 49 #define RTQ9128_DIE_CHECK_MASK GENMASK(4, 0) 50 #define RTQ9128_VENDOR_ID_MASK GENMASK(19, 8) 51 52 #define RTQ9128_SOFT_RESET_VAL 0x80 53 #define RTQ9128_VENDOR_ID_VAL 0x470 54 #define RTQ9128_ALLCH_HIZ_VAL 0x55 55 #define RTQ9128_ALLCH_ULQM_VAL 0xFF 56 #define RTQ9128_TKA470B_VAL 0 57 #define RTQ9128_RTQ9128DH_VAL 0x0F 58 #define RTQ9128_RTQ9128DL_VAL 0x10 59 60 struct rtq9128_data { 61 struct gpio_desc *enable; 62 int tdm_slots; 63 int tdm_slot_width; 64 bool tdm_input_data2_select; 65 }; 66 67 struct rtq9128_init_reg { 68 unsigned int reg; 69 unsigned int val; 70 }; 71 72 static int rtq9128_get_reg_size(unsigned int reg) 73 { 74 switch (reg) { 75 case 0x5C ... 0x6F: 76 case 0x98 ... 0x9F: 77 case 0xC0 ... 0xC3: 78 case 0xC8 ... 0xCF: 79 case 0xDF ... 0xE5: 80 case 0xF9: 81 return 4; 82 case 0x40 ... 0x4F: 83 return 3; 84 case 0x30 ... 0x35: 85 case 0x8C ... 0x97: 86 case 0xC4 ... 0xC7: 87 case 0xD7 ... 0xDA: 88 return 2; 89 default: 90 return 1; 91 } 92 } 93 94 static int rtq9128_i2c_write(void *context, const void *data, size_t count) 95 { 96 struct device *dev = context; 97 struct i2c_client *i2c = to_i2c_client(dev); 98 u8 reg = *(u8 *)data; 99 int rg_size; 100 101 if (count != 5) { 102 dev_err(dev, "Invalid write for data length (%d)\n", (int)count); 103 return -EINVAL; 104 } 105 106 rg_size = rtq9128_get_reg_size(reg); 107 return i2c_smbus_write_i2c_block_data(i2c, reg, rg_size, data + count - rg_size); 108 } 109 110 static int rtq9128_i2c_read(void *context, const void *reg_buf, size_t reg_size, void *val_buf, 111 size_t val_size) 112 { 113 struct device *dev = context; 114 struct i2c_client *i2c = to_i2c_client(dev); 115 u8 reg = *(u8 *)reg_buf; 116 u8 data_tmp[4] = {}; 117 int rg_size, ret; 118 119 if (reg_size != 1 || val_size != 4) { 120 dev_err(dev, "Invalid read for reg_size (%d) or val_size (%d)\n", (int)reg_size, 121 (int)val_size); 122 return -EINVAL; 123 } 124 125 rg_size = rtq9128_get_reg_size(reg); 126 ret = i2c_smbus_read_i2c_block_data(i2c, reg, rg_size, data_tmp); 127 if (ret < 0) 128 return ret; 129 else if (ret != rg_size) 130 return -EIO; 131 132 memset(val_buf, 0, val_size - rg_size); 133 memcpy(val_buf + val_size - rg_size, data_tmp, rg_size); 134 135 return 0; 136 } 137 138 static const struct regmap_bus rtq9128_regmap_bus = { 139 .write = rtq9128_i2c_write, 140 .read = rtq9128_i2c_read, 141 .max_raw_read = 4, 142 .max_raw_write = 4, 143 }; 144 145 static bool rtq9128_is_readable_reg(struct device *dev, unsigned int reg) 146 { 147 switch (reg) { 148 case 0x00 ... 0x2B: 149 case 0x30 ... 0x35: 150 case 0x40 ... 0x56: 151 case 0x5C ... 0x76: 152 case 0x80 ... 0xAD: 153 case 0xB0 ... 0xBA: 154 case 0xC0 ... 0xE5: 155 case 0xF0 ... 0xFB: 156 return true; 157 default: 158 return false; 159 } 160 } 161 162 static bool rtq9128_is_writeable_reg(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case 0x00 ... 0x1F: 166 case 0x21 ... 0x2B: 167 case 0x30 ... 0x35: 168 case 0x40 ... 0x56: 169 case 0x5C ... 0x76: 170 case 0x80 ... 0x8B: 171 case 0xA0 ... 0xAD: 172 case 0xB0 ... 0xBA: 173 case 0xC0: 174 case 0xD0 ... 0xDE: 175 case 0xE0 ... 0xE5: 176 case 0xF0 ... 0xF3: 177 case 0xF6 ... 0xF8: 178 case 0xFA ... 0xFB: 179 return true; 180 default: 181 return false; 182 } 183 } 184 185 static bool rtq9128_is_volatile_reg(struct device *dev, unsigned int reg) 186 { 187 switch (reg) { 188 case 0x0F ... 0x17: 189 case 0x20: 190 case 0x53: 191 case 0x55: 192 case 0x5C ... 0x6F: 193 case 0x8C ... 0x9F: 194 case 0xC0 ... 0xCF: 195 case 0xDF: 196 case 0xF0 ... 0xF1: 197 case 0xF4 ... 0xF5: 198 return true; 199 default: 200 return false; 201 } 202 } 203 204 static const struct regmap_config rtq9128_regmap_config = { 205 .name = "rtq9128", 206 .reg_bits = 8, 207 .val_bits = 32, 208 .val_format_endian = REGMAP_ENDIAN_BIG, 209 .cache_type = REGCACHE_MAPLE, 210 211 .readable_reg = rtq9128_is_readable_reg, 212 .writeable_reg = rtq9128_is_writeable_reg, 213 .volatile_reg = rtq9128_is_volatile_reg, 214 .num_reg_defaults_raw = RTQ9128_REG_VENDOR_ID + 1, 215 }; 216 217 static const DECLARE_TLV_DB_SCALE(dig_tlv, -10375, 25, 0); 218 219 static const DECLARE_TLV_DB_RANGE(spkgain_tlv, 220 0, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), 221 4, 5, TLV_DB_SCALE_ITEM(1500, 300, 0), 222 ); 223 224 static const char * const source_select_text[] = { "CH1", "CH2", "CH3", "CH4" }; 225 static const char * const pwmfreq_select_text[] = { "8fs", "10fs", "40fs", "44fs", "48fs" }; 226 static const char * const phase_select_text[] = { 227 "0 degree", "45 degree", "90 degree", "135 degree", 228 "180 degree", "225 degree", "270 degree", "315 degree", 229 }; 230 static const char * const dvdduv_select_text[] = { "1P4V", "1P5V", "2P1V", "2P3V" }; 231 232 static const struct soc_enum rtq9128_ch1_si_enum = 233 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 6, ARRAY_SIZE(source_select_text), source_select_text); 234 static const struct soc_enum rtq9128_ch2_si_enum = 235 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 4, ARRAY_SIZE(source_select_text), source_select_text); 236 static const struct soc_enum rtq9128_ch3_si_enum = 237 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 2, ARRAY_SIZE(source_select_text), source_select_text); 238 static const struct soc_enum rtq9128_ch4_si_enum = 239 SOC_ENUM_SINGLE(RTQ9128_REG_SDI_SEL, 0, ARRAY_SIZE(source_select_text), source_select_text); 240 static const struct soc_enum rtq9128_pwm_freq_enum = 241 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 4, ARRAY_SIZE(pwmfreq_select_text), 242 pwmfreq_select_text); 243 static const struct soc_enum rtq9128_out2_phase_enum = 244 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN1, 0, ARRAY_SIZE(phase_select_text), 245 phase_select_text); 246 static const struct soc_enum rtq9128_out3_phase_enum = 247 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 4, ARRAY_SIZE(phase_select_text), 248 phase_select_text); 249 static const struct soc_enum rtq9128_out4_phase_enum = 250 SOC_ENUM_SINGLE(RTQ9128_REG_PLLTRI_GEN2, 0, ARRAY_SIZE(phase_select_text), 251 phase_select_text); 252 253 /* 254 * In general usage, DVDD could be 1P8V, 3P0V or 3P3V. 255 * This DVDD undervoltage protection is to prevent from the abnormal power 256 * lose case while the amplifier is operating. Due to the different DVDD 257 * application, treat this threshold as a user choosable option. 258 */ 259 static const struct soc_enum rtq9128_dvdduv_select_enum = 260 SOC_ENUM_SINGLE(RTQ9128_REG_PROT_OPT, 6, ARRAY_SIZE(dvdduv_select_text), 261 dvdduv_select_text); 262 263 static const struct snd_kcontrol_new rtq9128_snd_ctrls[] = { 264 SOC_SINGLE_TLV("MS Volume", RTQ9128_REG_MS_VOL, 2, 511, 1, dig_tlv), 265 SOC_SINGLE_TLV("CH1 Volume", RTQ9128_REG_CH1_VOL, 2, 511, 1, dig_tlv), 266 SOC_SINGLE_TLV("CH2 Volume", RTQ9128_REG_CH2_VOL, 2, 511, 1, dig_tlv), 267 SOC_SINGLE_TLV("CH3 Volume", RTQ9128_REG_CH3_VOL, 2, 511, 1, dig_tlv), 268 SOC_SINGLE_TLV("CH4 Volume", RTQ9128_REG_CH4_VOL, 2, 511, 1, dig_tlv), 269 SOC_SINGLE_TLV("SPK Gain Volume", RTQ9128_REG_MISC, 0, 5, 0, spkgain_tlv), 270 SOC_SINGLE("PBTL12 Switch", RTQ9128_REG_MISC, 5, 1, 0), 271 SOC_SINGLE("PBTL34 Switch", RTQ9128_REG_MISC, 4, 1, 0), 272 SOC_SINGLE("Spread Spectrum Switch", RTQ9128_REG_PWM_SS_OPT, 7, 1, 0), 273 SOC_SINGLE("SDO Select", RTQ9128_REG_SDO_SEL, 0, 15, 0), 274 SOC_ENUM("CH1 SI Select", rtq9128_ch1_si_enum), 275 SOC_ENUM("CH2 SI Select", rtq9128_ch2_si_enum), 276 SOC_ENUM("CH3 SI Select", rtq9128_ch3_si_enum), 277 SOC_ENUM("CH4 SI Select", rtq9128_ch4_si_enum), 278 SOC_ENUM("PWM FREQ Select", rtq9128_pwm_freq_enum), 279 SOC_ENUM("OUT2 Phase Select", rtq9128_out2_phase_enum), 280 SOC_ENUM("OUT3 Phase Select", rtq9128_out3_phase_enum), 281 SOC_ENUM("OUT4 Phase Select", rtq9128_out4_phase_enum), 282 SOC_ENUM("DVDD UV Threshold Select", rtq9128_dvdduv_select_enum), 283 }; 284 285 static int rtq9128_dac_power_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, 286 int event) 287 { 288 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 289 unsigned int shift, mask; 290 int ret; 291 292 dev_dbg(comp->dev, "%s: %s event %d\n", __func__, w->name, event); 293 294 if (snd_soc_dapm_widget_name_cmp(w, "DAC1") == 0) 295 shift = 6; 296 else if (snd_soc_dapm_widget_name_cmp(w, "DAC2") == 0) 297 shift = 4; 298 else if (snd_soc_dapm_widget_name_cmp(w, "DAC3") == 0) 299 shift = 2; 300 else 301 shift = 0; 302 303 mask = RTQ9128_CHSTAT_VAL_MASK << shift; 304 305 /* Turn channel state to Normal or HiZ */ 306 ret = snd_soc_component_write_field(comp, RTQ9128_REG_STATE_CTRL, mask, 307 event != SND_SOC_DAPM_POST_PMU); 308 if (ret < 0) 309 return ret; 310 311 /* 312 * For each channel turns on, HW will trigger DC load detect and DC 313 * offset calibration, the time is needed for all the actions done. 314 */ 315 if (event == SND_SOC_DAPM_POST_PMU) 316 msleep(25); 317 318 return 0; 319 } 320 321 static const struct snd_soc_dapm_widget rtq9128_dapm_widgets[] = { 322 SND_SOC_DAPM_DAC_E("DAC1", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 323 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 324 SND_SOC_DAPM_DAC_E("DAC2", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 325 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 326 SND_SOC_DAPM_DAC_E("DAC3", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 327 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 328 SND_SOC_DAPM_DAC_E("DAC4", NULL, SND_SOC_NOPM, 0, 0, rtq9128_dac_power_event, 329 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 330 SND_SOC_DAPM_OUTPUT("OUT1"), 331 SND_SOC_DAPM_OUTPUT("OUT2"), 332 SND_SOC_DAPM_OUTPUT("OUT3"), 333 SND_SOC_DAPM_OUTPUT("OUT4"), 334 }; 335 336 static const struct snd_soc_dapm_route rtq9128_dapm_routes[] = { 337 { "DAC1", NULL, "Playback" }, 338 { "DAC2", NULL, "Playback" }, 339 { "DAC3", NULL, "Playback" }, 340 { "DAC4", NULL, "Playback" }, 341 { "OUT1", NULL, "DAC1" }, 342 { "OUT2", NULL, "DAC2" }, 343 { "OUT3", NULL, "DAC3" }, 344 { "OUT4", NULL, "DAC4" }, 345 { "Capture", NULL, "DAC1" }, 346 { "Capture", NULL, "DAC2" }, 347 { "Capture", NULL, "DAC3" }, 348 { "Capture", NULL, "DAC4" }, 349 }; 350 351 static const struct rtq9128_init_reg rtq9128_tka470b_tables[] = { 352 { 0xA0, 0xEF }, 353 { 0x0D, 0x00 }, 354 { 0x03, 0x05 }, 355 { 0x05, 0x31 }, 356 { 0x06, 0x23 }, 357 { 0x70, 0x11 }, 358 { 0x75, 0x1F }, 359 { 0xB6, 0x03 }, 360 { 0xB9, 0x03 }, 361 { 0xB8, 0x03 }, 362 { 0xC1, 0xFF }, 363 { 0xF8, 0x72 }, 364 { 0x30, 0x180 }, 365 }; 366 367 static const struct rtq9128_init_reg rtq9128_dh_tables[] = { 368 { 0x0F, 0x00 }, 369 { 0x03, 0x0D }, 370 { 0xB2, 0xFF }, 371 { 0xB3, 0xFF }, 372 { 0x30, 0x180 }, 373 { 0x8A, 0x55 }, 374 { 0x72, 0x00 }, 375 { 0xB1, 0xE3 }, 376 }; 377 378 static const struct rtq9128_init_reg rtq9128_dl_tables[] = { 379 { 0x0F, 0x00 }, 380 { 0x03, 0x0D }, 381 { 0x30, 0x180 }, 382 { 0x8A, 0x55 }, 383 { 0x72, 0x00 }, 384 { 0xB1, 0xE3 }, 385 }; 386 387 static int rtq9128_component_probe(struct snd_soc_component *comp) 388 { 389 const struct rtq9128_init_reg *table, *curr; 390 size_t table_size; 391 unsigned int val; 392 int i, ret; 393 394 pm_runtime_resume_and_get(comp->dev); 395 396 val = snd_soc_component_read(comp, RTQ9128_REG_EFUSE_DATA); 397 398 switch (FIELD_GET(RTQ9128_DIE_CHECK_MASK, val)) { 399 case RTQ9128_TKA470B_VAL: 400 table = rtq9128_tka470b_tables; 401 table_size = ARRAY_SIZE(rtq9128_tka470b_tables); 402 break; 403 case RTQ9128_RTQ9128DH_VAL: 404 table = rtq9128_dh_tables; 405 table_size = ARRAY_SIZE(rtq9128_dh_tables); 406 break; 407 default: 408 table = rtq9128_dl_tables; 409 table_size = ARRAY_SIZE(rtq9128_dl_tables); 410 break; 411 } 412 413 for (i = 0, curr = table; i < table_size; i++, curr++) { 414 ret = snd_soc_component_write(comp, curr->reg, curr->val); 415 if (ret < 0) 416 return ret; 417 } 418 419 pm_runtime_mark_last_busy(comp->dev); 420 pm_runtime_put(comp->dev); 421 422 return 0; 423 } 424 425 static const struct snd_soc_component_driver rtq9128_comp_driver = { 426 .probe = rtq9128_component_probe, 427 .controls = rtq9128_snd_ctrls, 428 .num_controls = ARRAY_SIZE(rtq9128_snd_ctrls), 429 .dapm_widgets = rtq9128_dapm_widgets, 430 .num_dapm_widgets = ARRAY_SIZE(rtq9128_dapm_widgets), 431 .dapm_routes = rtq9128_dapm_routes, 432 .num_dapm_routes = ARRAY_SIZE(rtq9128_dapm_routes), 433 .use_pmdown_time = 1, 434 .endianness = 1, 435 }; 436 437 static int rtq9128_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 438 { 439 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 440 struct snd_soc_component *comp = dai->component; 441 struct device *dev = dai->dev; 442 unsigned int audfmt, fmtval; 443 int ret; 444 445 dev_dbg(dev, "%s: fmt 0x%8x\n", __func__, fmt); 446 447 /* Only support bitclock & framesync as consumer */ 448 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_BC_FC) { 449 dev_err(dev, "Only support BCK and LRCK as consumer\n"); 450 return -EINVAL; 451 } 452 453 fmtval = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 454 if (data->tdm_slots && fmtval != SND_SOC_DAIFMT_DSP_A && fmtval != SND_SOC_DAIFMT_DSP_B) { 455 dev_err(dev, "TDM is used, format only support DSP_A or DSP_B\n"); 456 return -EINVAL; 457 } 458 459 switch (fmtval) { 460 case SND_SOC_DAIFMT_I2S: 461 audfmt = 8; 462 break; 463 case SND_SOC_DAIFMT_LEFT_J: 464 audfmt = 9; 465 break; 466 case SND_SOC_DAIFMT_RIGHT_J: 467 audfmt = 10; 468 break; 469 case SND_SOC_DAIFMT_DSP_A: 470 audfmt = data->tdm_slots ? 12 : 11; 471 break; 472 case SND_SOC_DAIFMT_DSP_B: 473 audfmt = data->tdm_slots ? 4 : 3; 474 break; 475 default: 476 dev_err(dev, "Unsupported format 0x%8x\n", fmt); 477 return -EINVAL; 478 } 479 480 ret = snd_soc_component_write_field(comp, RTQ9128_REG_I2S_OPT, RTQ9128_AUDFMT_MASK, audfmt); 481 return ret < 0 ? ret : 0; 482 } 483 484 static int rtq9128_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 485 unsigned int rx_mask, int slots, int slot_width) 486 { 487 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 488 struct snd_soc_component *comp = dai->component; 489 struct device *dev = dai->dev; 490 unsigned int mask, start_loc, srcin_select; 491 int i, frame_length, ret; 492 493 dev_dbg(dev, "%s: slot %d slot_width %d, tx/rx mask 0x%x 0x%x\n", __func__, slots, 494 slot_width, tx_mask, rx_mask); 495 496 if (slots <= 0 || slot_width <= 0 || slot_width % 8) { 497 dev_err(dev, "Invalid slot numbers (%d) or width (%d)\n", slots, slot_width); 498 return -EINVAL; 499 } 500 501 /* HW supported maximum frame length 512 */ 502 frame_length = slots * slot_width; 503 if (frame_length > 512) { 504 dev_err(dev, "frame length exceed the maximum (%d)\n", frame_length); 505 return -EINVAL; 506 } 507 508 if (!rx_mask || hweight_long(tx_mask) > slots || hweight_long(rx_mask) > slots || 509 fls(tx_mask) > slots || fls(rx_mask) > slots) { 510 dev_err(dev, "Invalid tx/rx mask (0x%x/0x%x)\n", tx_mask, rx_mask); 511 return -EINVAL; 512 } 513 514 for (mask = tx_mask, i = 0; i < 4 && mask; i++) { 515 start_loc = (ffs(mask) - 1) * slot_width / 8; 516 mask &= ~BIT(ffs(mask) - 1); 517 518 ret = snd_soc_component_write(comp, RTQ9128_REG_TDM_TX_CH1 + i, start_loc); 519 if (ret < 0) { 520 dev_err(dev, "Failed to assign tx_loc %d (%d)\n", i, ret); 521 return ret; 522 } 523 } 524 525 for (mask = rx_mask, i = 0; i < 4 && mask; i++) { 526 start_loc = (ffs(mask) - 1) * slot_width / 8; 527 mask &= ~BIT(ffs(mask) - 1); 528 529 ret = snd_soc_component_write(comp, RTQ9128_REG_TDM_RX_CH1 + i, start_loc); 530 if (ret < 0) { 531 dev_err(dev, "Failed to assign rx_loc %d (%d)\n", i, ret); 532 return ret; 533 } 534 } 535 536 srcin_select = data->tdm_input_data2_select ? RTQ9128_TDMSRCIN_MASK : 0; 537 ret = snd_soc_component_update_bits(comp, RTQ9128_REG_SDO_SEL, RTQ9128_TDMSRCIN_MASK, 538 srcin_select); 539 if (ret < 0) { 540 dev_err(dev, "Failed to configure TDM source input select\n"); 541 return ret; 542 } 543 544 data->tdm_slots = slots; 545 data->tdm_slot_width = slot_width; 546 547 return 0; 548 } 549 550 static int rtq9128_dai_hw_params(struct snd_pcm_substream *stream, struct snd_pcm_hw_params *param, 551 struct snd_soc_dai *dai) 552 { 553 struct rtq9128_data *data = snd_soc_dai_get_drvdata(dai); 554 unsigned int width, slot_width, bitrate, audbit, dolen; 555 struct snd_soc_component *comp = dai->component; 556 struct device *dev = dai->dev; 557 int ret; 558 559 dev_dbg(dev, "%s: width %d\n", __func__, params_width(param)); 560 561 switch (width = params_width(param)) { 562 case 16: 563 audbit = 0; 564 break; 565 case 18: 566 audbit = 1; 567 break; 568 case 20: 569 audbit = 2; 570 break; 571 case 24: 572 case 32: 573 audbit = 3; 574 break; 575 default: 576 dev_err(dev, "Unsupported width (%d)\n", width); 577 return -EINVAL; 578 } 579 580 slot_width = params_physical_width(param); 581 582 if (data->tdm_slots) { 583 if (slot_width > data->tdm_slot_width) { 584 dev_err(dev, "slot width is larger than TDM slot width\n"); 585 return -EINVAL; 586 } 587 588 /* Check BCK not exceed the maximum supported rate 24.576MHz */ 589 bitrate = data->tdm_slots * data->tdm_slot_width * params_rate(param); 590 if (bitrate > 24576000) { 591 dev_err(dev, "bitrate exceed the maximum (%d)\n", bitrate); 592 return -EINVAL; 593 } 594 595 /* If TDM is used, configure slot width as TDM slot witdh */ 596 slot_width = data->tdm_slot_width; 597 } 598 599 switch (slot_width) { 600 case 16: 601 dolen = 0; 602 break; 603 case 24: 604 dolen = 1; 605 break; 606 case 32: 607 dolen = 2; 608 break; 609 default: 610 dev_err(dev, "Unsupported slot width (%d)\n", slot_width); 611 return -EINVAL; 612 } 613 614 ret = snd_soc_component_write_field(comp, RTQ9128_REG_I2S_OPT, RTQ9128_AUDBIT_MASK, audbit); 615 if (ret < 0) 616 return ret; 617 618 ret = snd_soc_component_write_field(comp, RTQ9128_REG_SDO_SEL, RTQ9128_DOLEN_MASK, dolen); 619 return ret < 0 ? ret : 0; 620 } 621 622 static int rtq9128_dai_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 623 { 624 struct snd_soc_component *comp = dai->component; 625 struct device *dev = dai->dev; 626 int ret; 627 628 dev_dbg(dev, "%s: mute (%d), stream (%d)\n", __func__, mute, stream); 629 630 ret = snd_soc_component_write_field(comp, RTQ9128_REG_DSP_EN, RTQ9128_MSMUTE_MASK, 631 mute ? 1 : 0); 632 return ret < 0 ? ret : 0; 633 } 634 635 static const struct snd_soc_dai_ops rtq9128_dai_ops = { 636 .set_fmt = rtq9128_dai_set_fmt, 637 .set_tdm_slot = rtq9128_dai_set_tdm_slot, 638 .hw_params = rtq9128_dai_hw_params, 639 .mute_stream = rtq9128_dai_mute_stream, 640 .no_capture_mute = 1, 641 }; 642 643 #define RTQ9128_FMTS_MASK (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE |\ 644 SNDRV_PCM_FMTBIT_S20_LE | SNDRV_PCM_FMTBIT_S24_LE |\ 645 SNDRV_PCM_FMTBIT_S32_LE) 646 647 static struct snd_soc_dai_driver rtq9128_dai = { 648 .name = "rtq9128-aif", 649 .playback = { 650 .stream_name = "Playback", 651 .rates = SNDRV_PCM_RATE_8000_192000, 652 .formats = RTQ9128_FMTS_MASK, 653 .channels_min = 1, 654 .channels_max = 4, 655 }, 656 .capture = { 657 .stream_name = "Capture", 658 .rates = SNDRV_PCM_RATE_8000_192000, 659 .formats = RTQ9128_FMTS_MASK, 660 .channels_min = 1, 661 .channels_max = 4, 662 }, 663 .ops = &rtq9128_dai_ops, 664 .symmetric_rate = 1, 665 .symmetric_sample_bits = 1, 666 }; 667 668 static int rtq9128_probe(struct i2c_client *i2c) 669 { 670 struct device *dev = &i2c->dev; 671 struct rtq9128_data *data; 672 struct regmap *regmap; 673 unsigned int venid; 674 int ret; 675 676 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 677 if (!data) 678 return -ENOMEM; 679 680 data->enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH); 681 if (IS_ERR(data->enable)) 682 return dev_err_probe(dev, PTR_ERR(data->enable), "Failed to get 'enable' gpio\n"); 683 else if (data->enable) 684 usleep_range(10000, 11000); 685 686 data->tdm_input_data2_select = device_property_read_bool(dev, 687 "richtek,tdm-input-data2-select"); 688 689 i2c_set_clientdata(i2c, data); 690 691 /* 692 * Due to the bad design to combine SOFT_RESET bit with other function, 693 * directly use generic i2c API to trigger SOFT_RESET. 694 */ 695 ret = i2c_smbus_write_byte_data(i2c, RTQ9128_REG_MISC, RTQ9128_SOFT_RESET_VAL); 696 if (ret) 697 return dev_err_probe(dev, ret, "Failed to trigger software reset\n"); 698 699 /* After trigger soft reset, have to wait 10ms for digital reset done */ 700 usleep_range(10000, 11000); 701 702 regmap = devm_regmap_init(dev, &rtq9128_regmap_bus, dev, &rtq9128_regmap_config); 703 if (IS_ERR(regmap)) 704 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n"); 705 706 ret = regmap_read(regmap, RTQ9128_REG_VENDOR_ID, &venid); 707 if (ret) 708 return dev_err_probe(dev, ret, "Failed to get vendor id\n"); 709 710 venid = FIELD_GET(RTQ9128_VENDOR_ID_MASK, venid); 711 if (venid != RTQ9128_VENDOR_ID_VAL) 712 return dev_err_probe(dev, -ENODEV, "Vendor ID not match (0x%x)\n", venid); 713 714 pm_runtime_set_active(dev); 715 pm_runtime_mark_last_busy(dev); 716 ret = devm_pm_runtime_enable(dev); 717 if (ret) 718 return dev_err_probe(dev, ret, "Failed to enable pm runtime\n"); 719 720 return devm_snd_soc_register_component(dev, &rtq9128_comp_driver, &rtq9128_dai, 1); 721 } 722 723 static int __maybe_unused rtq9128_pm_runtime_suspend(struct device *dev) 724 { 725 struct rtq9128_data *data = dev_get_drvdata(dev); 726 struct regmap *regmap = dev_get_regmap(dev, NULL); 727 728 /* If 'enable' gpio not specified, change all channels to ultra low quiescent */ 729 if (!data->enable) 730 return regmap_write(regmap, RTQ9128_REG_STATE_CTRL, RTQ9128_ALLCH_ULQM_VAL); 731 732 gpiod_set_value_cansleep(data->enable, 0); 733 734 regcache_cache_only(regmap, true); 735 regcache_mark_dirty(regmap); 736 737 return 0; 738 } 739 740 static int __maybe_unused rtq9128_pm_runtime_resume(struct device *dev) 741 { 742 struct rtq9128_data *data = dev_get_drvdata(dev); 743 struct regmap *regmap = dev_get_regmap(dev, NULL); 744 745 /* If 'enable' gpio not specified, change all channels to default Hi-Z */ 746 if (!data->enable) 747 return regmap_write(regmap, RTQ9128_REG_STATE_CTRL, RTQ9128_ALLCH_HIZ_VAL); 748 749 gpiod_set_value_cansleep(data->enable, 1); 750 751 /* Wait digital block to be ready */ 752 usleep_range(10000, 11000); 753 754 regcache_cache_only(regmap, false); 755 return regcache_sync(regmap); 756 } 757 758 static const struct dev_pm_ops __maybe_unused rtq9128_pm_ops = { 759 SET_RUNTIME_PM_OPS(rtq9128_pm_runtime_suspend, rtq9128_pm_runtime_resume, NULL) 760 }; 761 762 static const struct of_device_id rtq9128_device_table[] = { 763 { .compatible = "richtek,rtq9128" }, 764 {} 765 }; 766 MODULE_DEVICE_TABLE(of, rtq9128_device_table); 767 768 static struct i2c_driver rtq9128_driver = { 769 .driver = { 770 .name = "rtq9128", 771 .of_match_table = rtq9128_device_table, 772 .pm = pm_ptr(&rtq9128_pm_ops), 773 }, 774 .probe = rtq9128_probe, 775 }; 776 module_i2c_driver(rtq9128_driver); 777 778 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>"); 779 MODULE_DESCRIPTION("RTQ9128 4CH Audio Amplifier Driver"); 780 MODULE_LICENSE("GPL"); 781