1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver 4 // 5 // Copyright(c) 2023 Realtek Semiconductor Corp. 6 // 7 // 8 9 #include <linux/bitops.h> 10 #include <sound/core.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <sound/initval.h> 14 #include <sound/jack.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <sound/pcm.h> 19 #include <linux/pm_runtime.h> 20 #include <sound/pcm_params.h> 21 #include <linux/soundwire/sdw_registers.h> 22 #include <linux/slab.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "rt722-sdca.h" 27 28 int rt722_sdca_index_write(struct rt722_sdca_priv *rt722, 29 unsigned int nid, unsigned int reg, unsigned int value) 30 { 31 struct regmap *regmap = rt722->mbq_regmap; 32 unsigned int addr = (nid << 20) | reg; 33 int ret; 34 35 ret = regmap_write(regmap, addr, value); 36 if (ret < 0) 37 dev_err(&rt722->slave->dev, 38 "%s: Failed to set private value: %06x <= %04x ret=%d\n", 39 __func__, addr, value, ret); 40 41 return ret; 42 } 43 44 int rt722_sdca_index_read(struct rt722_sdca_priv *rt722, 45 unsigned int nid, unsigned int reg, unsigned int *value) 46 { 47 int ret; 48 struct regmap *regmap = rt722->mbq_regmap; 49 unsigned int addr = (nid << 20) | reg; 50 51 ret = regmap_read(regmap, addr, value); 52 if (ret < 0) 53 dev_err(&rt722->slave->dev, 54 "%s: Failed to get private value: %06x => %04x ret=%d\n", 55 __func__, addr, *value, ret); 56 57 return ret; 58 } 59 60 static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722, 61 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val) 62 { 63 unsigned int tmp; 64 int ret; 65 66 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp); 67 if (ret < 0) 68 return ret; 69 70 set_mask_bits(&tmp, mask, val); 71 return rt722_sdca_index_write(rt722, nid, reg, tmp); 72 } 73 74 static int rt722_sdca_btn_type(unsigned char *buffer) 75 { 76 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) || 77 (*(buffer + 1) == 0x10)) 78 return SND_JACK_BTN_2; 79 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) || 80 (*(buffer + 1) == 0x20)) 81 return SND_JACK_BTN_3; 82 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) || 83 (*(buffer + 1) == 0x40)) 84 return SND_JACK_BTN_0; 85 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) || 86 (*(buffer + 1) == 0x80)) 87 return SND_JACK_BTN_1; 88 89 return 0; 90 } 91 92 static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722) 93 { 94 unsigned int btn_type = 0, offset, idx, val, owner; 95 int ret; 96 unsigned char buf[3]; 97 98 /* get current UMP message owner */ 99 ret = regmap_read(rt722->regmap, 100 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 101 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner); 102 if (ret < 0) 103 return 0; 104 105 /* if owner is device then there is no button event from device */ 106 if (owner == 1) 107 return 0; 108 109 /* read UMP message offset */ 110 ret = regmap_read(rt722->regmap, 111 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 112 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 113 if (ret < 0) 114 goto _end_btn_det_; 115 116 for (idx = 0; idx < sizeof(buf); idx++) { 117 ret = regmap_read(rt722->regmap, 118 RT722_BUF_ADDR_HID1 + offset + idx, &val); 119 if (ret < 0) 120 goto _end_btn_det_; 121 buf[idx] = val & 0xff; 122 } 123 124 if (buf[0] == 0x11) 125 btn_type = rt722_sdca_btn_type(&buf[1]); 126 127 _end_btn_det_: 128 /* Host is owner, so set back to device */ 129 if (owner == 0) 130 /* set owner to device */ 131 regmap_write(rt722->regmap, 132 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 133 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01); 134 135 return btn_type; 136 } 137 138 static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722) 139 { 140 unsigned int det_mode; 141 int ret; 142 143 /* get detected_mode */ 144 ret = regmap_read(rt722->regmap, 145 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 146 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 147 if (ret < 0) 148 goto io_error; 149 150 switch (det_mode) { 151 case 0x00: 152 rt722->jack_type = 0; 153 break; 154 case 0x03: 155 rt722->jack_type = SND_JACK_HEADPHONE; 156 break; 157 case 0x05: 158 rt722->jack_type = SND_JACK_HEADSET; 159 break; 160 } 161 162 /* write selected_mode */ 163 if (det_mode) { 164 ret = regmap_write(rt722->regmap, 165 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 166 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode); 167 if (ret < 0) 168 goto io_error; 169 } 170 171 dev_dbg(&rt722->slave->dev, 172 "%s, detected_mode=0x%x\n", __func__, det_mode); 173 174 return 0; 175 176 io_error: 177 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 178 return ret; 179 } 180 181 static void rt722_sdca_jack_detect_handler(struct work_struct *work) 182 { 183 struct rt722_sdca_priv *rt722 = 184 container_of(work, struct rt722_sdca_priv, jack_detect_work.work); 185 int btn_type = 0, ret; 186 187 if (!rt722->hs_jack) 188 return; 189 190 if (!rt722->component->card || !rt722->component->card->instantiated) 191 return; 192 193 /* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */ 194 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) { 195 ret = rt722_sdca_headset_detect(rt722); 196 if (ret < 0) 197 return; 198 } 199 200 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */ 201 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8) 202 btn_type = rt722_sdca_button_detect(rt722); 203 204 if (rt722->jack_type == 0) 205 btn_type = 0; 206 207 dev_dbg(&rt722->slave->dev, 208 "in %s, jack_type=%d\n", __func__, rt722->jack_type); 209 dev_dbg(&rt722->slave->dev, 210 "in %s, btn_type=0x%x\n", __func__, btn_type); 211 dev_dbg(&rt722->slave->dev, 212 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__, 213 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2); 214 215 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 216 SND_JACK_HEADSET | 217 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 218 SND_JACK_BTN_2 | SND_JACK_BTN_3); 219 220 if (btn_type) { 221 /* button released */ 222 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 223 SND_JACK_HEADSET | 224 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 225 SND_JACK_BTN_2 | SND_JACK_BTN_3); 226 227 mod_delayed_work(system_power_efficient_wq, 228 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 229 } 230 } 231 232 static void rt722_sdca_btn_check_handler(struct work_struct *work) 233 { 234 struct rt722_sdca_priv *rt722 = 235 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work); 236 int btn_type = 0, ret, idx; 237 unsigned int det_mode, offset, val; 238 unsigned char buf[3]; 239 240 ret = regmap_read(rt722->regmap, 241 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 242 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 243 if (ret < 0) 244 goto io_error; 245 246 /* pin attached */ 247 if (det_mode) { 248 /* read UMP message offset */ 249 ret = regmap_read(rt722->regmap, 250 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 251 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 252 if (ret < 0) 253 goto io_error; 254 255 for (idx = 0; idx < sizeof(buf); idx++) { 256 ret = regmap_read(rt722->regmap, 257 RT722_BUF_ADDR_HID1 + offset + idx, &val); 258 if (ret < 0) 259 goto io_error; 260 buf[idx] = val & 0xff; 261 } 262 263 if (buf[0] == 0x11) 264 btn_type = rt722_sdca_btn_type(&buf[1]); 265 } else 266 rt722->jack_type = 0; 267 268 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type); 269 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 270 SND_JACK_HEADSET | 271 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 272 SND_JACK_BTN_2 | SND_JACK_BTN_3); 273 274 if (btn_type) { 275 /* button released */ 276 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 277 SND_JACK_HEADSET | 278 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 279 SND_JACK_BTN_2 | SND_JACK_BTN_3); 280 281 mod_delayed_work(system_power_efficient_wq, 282 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 283 } 284 285 return; 286 287 io_error: 288 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 289 } 290 291 static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722) 292 { 293 mutex_lock(&rt722->calibrate_mutex); 294 if (rt722->hs_jack) { 295 /* set SCP_SDCA_IntMask1[0]=1 */ 296 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1, 297 SDW_SCP_SDCA_INTMASK_SDCA_0); 298 /* set SCP_SDCA_IntMask2[0]=1 */ 299 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2, 300 SDW_SCP_SDCA_INTMASK_SDCA_8); 301 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__); 302 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 303 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E); 304 /* set XU(et03h) & XU(et0Dh) to Not bypassed */ 305 regmap_write(rt722->regmap, 306 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03, 307 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 308 regmap_write(rt722->regmap, 309 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D, 310 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 311 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL1, 0x0000); 312 /* trigger GE interrupt */ 313 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 314 RT722_GE_RELATED_CTL2, 0x4000, 0x4000); 315 } 316 mutex_unlock(&rt722->calibrate_mutex); 317 } 318 319 static int rt722_sdca_set_jack_detect(struct snd_soc_component *component, 320 struct snd_soc_jack *hs_jack, void *data) 321 { 322 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 323 int ret; 324 325 rt722->hs_jack = hs_jack; 326 327 ret = pm_runtime_resume_and_get(component->dev); 328 if (ret < 0) { 329 if (ret != -EACCES) { 330 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); 331 return ret; 332 } 333 /* pm_runtime not enabled yet */ 334 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); 335 return 0; 336 } 337 338 rt722_sdca_jack_init(rt722); 339 340 pm_runtime_mark_last_busy(component->dev); 341 pm_runtime_put_autosuspend(component->dev); 342 343 return 0; 344 } 345 346 /* For SDCA control DAC/ADC Gain */ 347 static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol, 348 struct snd_ctl_elem_value *ucontrol) 349 { 350 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 351 struct soc_mixer_control *mc = 352 (struct soc_mixer_control *)kcontrol->private_value; 353 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 354 unsigned int read_l, read_r, gain_l_val, gain_r_val; 355 unsigned int adc_vol_flag = 0, changed = 0; 356 unsigned int lvalue, rvalue; 357 const unsigned int interval_offset = 0xc0; 358 const unsigned int tendB = 0xa00; 359 360 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 361 strstr(ucontrol->id.name, "FU0F Capture Volume")) 362 adc_vol_flag = 1; 363 364 regmap_read(rt722->mbq_regmap, mc->reg, &lvalue); 365 regmap_read(rt722->mbq_regmap, mc->rreg, &rvalue); 366 367 /* L Channel */ 368 gain_l_val = ucontrol->value.integer.value[0]; 369 if (gain_l_val > mc->max) 370 gain_l_val = mc->max; 371 372 if (mc->shift == 8) /* boost gain */ 373 gain_l_val = gain_l_val * tendB; 374 else { 375 /* ADC/DAC gain */ 376 if (adc_vol_flag) 377 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset); 378 else 379 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 380 gain_l_val &= 0xffff; 381 } 382 383 /* R Channel */ 384 gain_r_val = ucontrol->value.integer.value[1]; 385 if (gain_r_val > mc->max) 386 gain_r_val = mc->max; 387 388 if (mc->shift == 8) /* boost gain */ 389 gain_r_val = gain_r_val * tendB; 390 else { 391 /* ADC/DAC gain */ 392 if (adc_vol_flag) 393 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset); 394 else 395 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 396 gain_r_val &= 0xffff; 397 } 398 399 if (lvalue != gain_l_val || rvalue != gain_r_val) 400 changed = 1; 401 else 402 return 0; 403 404 /* Lch*/ 405 regmap_write(rt722->mbq_regmap, mc->reg, gain_l_val); 406 407 /* Rch */ 408 regmap_write(rt722->mbq_regmap, mc->rreg, gain_r_val); 409 410 regmap_read(rt722->mbq_regmap, mc->reg, &read_l); 411 regmap_read(rt722->mbq_regmap, mc->rreg, &read_r); 412 if (read_r == gain_r_val && read_l == gain_l_val) 413 return changed; 414 415 return -EIO; 416 } 417 418 static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol, 419 struct snd_ctl_elem_value *ucontrol) 420 { 421 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 422 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 423 struct soc_mixer_control *mc = 424 (struct soc_mixer_control *)kcontrol->private_value; 425 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 426 unsigned int adc_vol_flag = 0; 427 const unsigned int interval_offset = 0xc0; 428 const unsigned int tendB = 0xa00; 429 430 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 431 strstr(ucontrol->id.name, "FU0F Capture Volume")) 432 adc_vol_flag = 1; 433 434 regmap_read(rt722->mbq_regmap, mc->reg, &read_l); 435 regmap_read(rt722->mbq_regmap, mc->rreg, &read_r); 436 437 if (mc->shift == 8) /* boost gain */ 438 ctl_l = read_l / tendB; 439 else { 440 if (adc_vol_flag) 441 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset); 442 else 443 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 444 } 445 446 if (read_l != read_r) { 447 if (mc->shift == 8) /* boost gain */ 448 ctl_r = read_r / tendB; 449 else { /* ADC/DAC gain */ 450 if (adc_vol_flag) 451 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset); 452 else 453 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 454 } 455 } else { 456 ctl_r = ctl_l; 457 } 458 459 ucontrol->value.integer.value[0] = ctl_l; 460 ucontrol->value.integer.value[1] = ctl_r; 461 462 return 0; 463 } 464 465 static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722) 466 { 467 int err, i; 468 unsigned int ch_mute; 469 470 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) { 471 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i]; 472 err = regmap_write(rt722->regmap, 473 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 474 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 475 if (err < 0) 476 return err; 477 } 478 479 return 0; 480 } 481 482 static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol, 483 struct snd_ctl_elem_value *ucontrol) 484 { 485 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 486 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 487 struct rt722_sdca_dmic_kctrl_priv *p = 488 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 489 unsigned int i; 490 491 for (i = 0; i < p->count; i++) 492 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i]; 493 494 return 0; 495 } 496 497 static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol, 498 struct snd_ctl_elem_value *ucontrol) 499 { 500 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 501 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 502 struct rt722_sdca_dmic_kctrl_priv *p = 503 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 504 int err, changed = 0, i; 505 506 for (i = 0; i < p->count; i++) { 507 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i]) 508 changed = 1; 509 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i]; 510 } 511 512 err = rt722_sdca_set_fu1e_capture_ctl(rt722); 513 if (err < 0) 514 return err; 515 516 return changed; 517 } 518 519 static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722) 520 { 521 int err; 522 unsigned int ch_l, ch_r; 523 524 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00; 525 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00; 526 527 err = regmap_write(rt722->regmap, 528 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 529 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l); 530 if (err < 0) 531 return err; 532 533 err = regmap_write(rt722->regmap, 534 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 535 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r); 536 if (err < 0) 537 return err; 538 539 return 0; 540 } 541 542 static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol, 543 struct snd_ctl_elem_value *ucontrol) 544 { 545 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 546 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 547 548 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute; 549 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute; 550 return 0; 551 } 552 553 static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol, 554 struct snd_ctl_elem_value *ucontrol) 555 { 556 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 557 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 558 int err, changed = 0; 559 560 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] || 561 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1]) 562 changed = 1; 563 564 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0]; 565 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1]; 566 err = rt722_sdca_set_fu0f_capture_ctl(rt722); 567 if (err < 0) 568 return err; 569 570 return changed; 571 } 572 573 static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol, 574 struct snd_ctl_elem_info *uinfo) 575 { 576 struct rt722_sdca_dmic_kctrl_priv *p = 577 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 578 579 if (p->max == 1) 580 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 581 else 582 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 583 uinfo->count = p->count; 584 uinfo->value.integer.min = 0; 585 uinfo->value.integer.max = p->max; 586 return 0; 587 } 588 589 static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol, 590 struct snd_ctl_elem_value *ucontrol) 591 { 592 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 593 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 594 struct rt722_sdca_dmic_kctrl_priv *p = 595 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 596 unsigned int boost_step = 0x0a00; 597 unsigned int vol_max = 0x1e00; 598 unsigned int regvalue, ctl, i; 599 unsigned int adc_vol_flag = 0; 600 const unsigned int interval_offset = 0xc0; 601 602 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 603 adc_vol_flag = 1; 604 605 /* check all channels */ 606 for (i = 0; i < p->count; i++) { 607 regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value); 608 609 if (!adc_vol_flag) /* boost gain */ 610 ctl = regvalue / boost_step; 611 else /* ADC gain */ 612 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset); 613 614 ucontrol->value.integer.value[i] = ctl; 615 } 616 617 return 0; 618 } 619 620 static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol, 621 struct snd_ctl_elem_value *ucontrol) 622 { 623 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 624 struct rt722_sdca_dmic_kctrl_priv *p = 625 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 626 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 627 unsigned int boost_step = 0x0a00; 628 unsigned int vol_max = 0x1e00; 629 unsigned int gain_val[4]; 630 unsigned int i, adc_vol_flag = 0, changed = 0; 631 unsigned int regvalue[4]; 632 const unsigned int interval_offset = 0xc0; 633 int err; 634 635 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 636 adc_vol_flag = 1; 637 638 /* check all channels */ 639 for (i = 0; i < p->count; i++) { 640 regmap_read(rt722->mbq_regmap, p->reg_base + i, ®value[i]); 641 642 gain_val[i] = ucontrol->value.integer.value[i]; 643 if (gain_val[i] > p->max) 644 gain_val[i] = p->max; 645 646 if (!adc_vol_flag) /* boost gain */ 647 gain_val[i] = gain_val[i] * boost_step; 648 else { /* ADC gain */ 649 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset); 650 gain_val[i] &= 0xffff; 651 } 652 653 if (regvalue[i] != gain_val[i]) 654 changed = 1; 655 } 656 657 if (!changed) 658 return 0; 659 660 for (i = 0; i < p->count; i++) { 661 err = regmap_write(rt722->mbq_regmap, p->reg_base + i, gain_val[i]); 662 if (err < 0) 663 dev_err(&rt722->slave->dev, "%s: %#08x can't be set\n", 664 __func__, p->reg_base + i); 665 } 666 667 return changed; 668 } 669 670 #define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \ 671 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \ 672 {.reg_base = xreg_base, .count = xcount, .max = xmax, \ 673 .invert = xinvert}) 674 675 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \ 676 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 677 .info = rt722_sdca_fu_info, \ 678 .get = rt722_sdca_fu1e_capture_get, \ 679 .put = rt722_sdca_fu1e_capture_put, \ 680 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)} 681 682 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\ 683 xhandler_put, xcount, xmax, tlv_array) \ 684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 685 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 686 SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 687 .tlv.p = (tlv_array), \ 688 .info = rt722_sdca_fu_info, \ 689 .get = xhandler_get, .put = xhandler_put, \ 690 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) } 691 692 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 693 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0); 694 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0); 695 696 static const struct snd_kcontrol_new rt722_sdca_controls[] = { 697 /* Headphone playback settings */ 698 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume", 699 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 700 RT722_SDCA_CTL_FU_VOLUME, CH_L), 701 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 702 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 703 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 704 /* Headset mic capture settings */ 705 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0, 706 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put), 707 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume", 708 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 709 RT722_SDCA_CTL_FU_VOLUME, CH_L), 710 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 711 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0, 712 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv), 713 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume", 714 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 715 RT722_SDCA_CTL_FU_CH_GAIN, CH_L), 716 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 717 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0, 718 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv), 719 /* AMP playback settings */ 720 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume", 721 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 722 RT722_SDCA_CTL_FU_VOLUME, CH_L), 723 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 724 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 725 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 726 /* DMIC capture settings */ 727 RT722_SDCA_FU_CTRL("FU1E Capture Switch", 728 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 729 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4), 730 RT722_SDCA_EXT_TLV("FU1E Capture Volume", 731 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 732 RT722_SDCA_CTL_FU_VOLUME, CH_01), 733 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 734 4, 0x3f, mic_vol_tlv), 735 RT722_SDCA_EXT_TLV("FU15 Boost Volume", 736 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, 737 RT722_SDCA_CTL_FU_CH_GAIN, CH_01), 738 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 739 4, 3, boost_vol_tlv), 740 }; 741 742 static int rt722_sdca_adc_mux_get(struct snd_kcontrol *kcontrol, 743 struct snd_ctl_elem_value *ucontrol) 744 { 745 struct snd_soc_component *component = 746 snd_soc_dapm_kcontrol_component(kcontrol); 747 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 748 unsigned int val = 0, mask_sft; 749 750 if (strstr(ucontrol->id.name, "ADC 22 Mux")) 751 mask_sft = 12; 752 else if (strstr(ucontrol->id.name, "ADC 24 Mux")) 753 mask_sft = 4; 754 else if (strstr(ucontrol->id.name, "ADC 25 Mux")) 755 mask_sft = 0; 756 else 757 return -EINVAL; 758 759 rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL, 760 RT722_HDA_LEGACY_MUX_CTL0, &val); 761 762 ucontrol->value.enumerated.item[0] = (val >> mask_sft) & 0x7; 763 764 return 0; 765 } 766 767 static int rt722_sdca_adc_mux_put(struct snd_kcontrol *kcontrol, 768 struct snd_ctl_elem_value *ucontrol) 769 { 770 struct snd_soc_component *component = 771 snd_soc_dapm_kcontrol_component(kcontrol); 772 struct snd_soc_dapm_context *dapm = 773 snd_soc_dapm_kcontrol_dapm(kcontrol); 774 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 775 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 776 unsigned int *item = ucontrol->value.enumerated.item; 777 unsigned int val, val2 = 0, change, mask_sft; 778 779 if (item[0] >= e->items) 780 return -EINVAL; 781 782 if (strstr(ucontrol->id.name, "ADC 22 Mux")) 783 mask_sft = 12; 784 else if (strstr(ucontrol->id.name, "ADC 24 Mux")) 785 mask_sft = 4; 786 else if (strstr(ucontrol->id.name, "ADC 25 Mux")) 787 mask_sft = 0; 788 else 789 return -EINVAL; 790 791 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 792 793 rt722_sdca_index_read(rt722, RT722_VENDOR_HDA_CTL, 794 RT722_HDA_LEGACY_MUX_CTL0, &val2); 795 val2 = (0x7 << mask_sft) & val2; 796 797 if (val == val2) 798 change = 0; 799 else 800 change = 1; 801 802 if (change) 803 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 804 RT722_HDA_LEGACY_MUX_CTL0, 0x7 << mask_sft, 805 val << mask_sft); 806 807 snd_soc_dapm_mux_update_power(dapm, kcontrol, 808 item[0], e, NULL); 809 810 return change; 811 } 812 813 static const char * const adc22_mux_text[] = { 814 "MIC2", 815 "LINE1", 816 "LINE2", 817 }; 818 819 static const char * const adc07_10_mux_text[] = { 820 "DMIC1", 821 "DMIC2", 822 }; 823 824 static SOC_ENUM_SINGLE_DECL( 825 rt722_adc22_enum, SND_SOC_NOPM, 0, adc22_mux_text); 826 827 static SOC_ENUM_SINGLE_DECL( 828 rt722_adc24_enum, SND_SOC_NOPM, 0, adc07_10_mux_text); 829 830 static SOC_ENUM_SINGLE_DECL( 831 rt722_adc25_enum, SND_SOC_NOPM, 0, adc07_10_mux_text); 832 833 static const struct snd_kcontrol_new rt722_sdca_adc22_mux = 834 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt722_adc22_enum, 835 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put); 836 837 static const struct snd_kcontrol_new rt722_sdca_adc24_mux = 838 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt722_adc24_enum, 839 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put); 840 841 static const struct snd_kcontrol_new rt722_sdca_adc25_mux = 842 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt722_adc25_enum, 843 rt722_sdca_adc_mux_get, rt722_sdca_adc_mux_put); 844 845 static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w, 846 struct snd_kcontrol *kcontrol, int event) 847 { 848 struct snd_soc_component *component = 849 snd_soc_dapm_to_component(w->dapm); 850 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 851 unsigned char unmute = 0x0, mute = 0x1; 852 853 switch (event) { 854 case SND_SOC_DAPM_POST_PMU: 855 regmap_write(rt722->regmap, 856 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 857 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 858 regmap_write(rt722->regmap, 859 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 860 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 861 break; 862 case SND_SOC_DAPM_PRE_PMD: 863 regmap_write(rt722->regmap, 864 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 865 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 866 regmap_write(rt722->regmap, 867 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 868 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 869 break; 870 } 871 return 0; 872 } 873 874 static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w, 875 struct snd_kcontrol *kcontrol, int event) 876 { 877 struct snd_soc_component *component = 878 snd_soc_dapm_to_component(w->dapm); 879 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 880 unsigned char unmute = 0x0, mute = 0x1; 881 882 switch (event) { 883 case SND_SOC_DAPM_POST_PMU: 884 regmap_write(rt722->regmap, 885 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 886 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 887 regmap_write(rt722->regmap, 888 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 889 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 890 break; 891 case SND_SOC_DAPM_PRE_PMD: 892 regmap_write(rt722->regmap, 893 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 894 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 895 regmap_write(rt722->regmap, 896 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 897 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 898 break; 899 } 900 return 0; 901 } 902 903 static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w, 904 struct snd_kcontrol *kcontrol, int event) 905 { 906 struct snd_soc_component *component = 907 snd_soc_dapm_to_component(w->dapm); 908 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 909 910 switch (event) { 911 case SND_SOC_DAPM_POST_PMU: 912 rt722->fu1e_dapm_mute = false; 913 rt722_sdca_set_fu1e_capture_ctl(rt722); 914 break; 915 case SND_SOC_DAPM_PRE_PMD: 916 rt722->fu1e_dapm_mute = true; 917 rt722_sdca_set_fu1e_capture_ctl(rt722); 918 break; 919 } 920 return 0; 921 } 922 923 static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w, 924 struct snd_kcontrol *kcontrol, int event) 925 { 926 struct snd_soc_component *component = 927 snd_soc_dapm_to_component(w->dapm); 928 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 929 930 switch (event) { 931 case SND_SOC_DAPM_POST_PMU: 932 rt722->fu0f_dapm_mute = false; 933 rt722_sdca_set_fu0f_capture_ctl(rt722); 934 break; 935 case SND_SOC_DAPM_PRE_PMD: 936 rt722->fu0f_dapm_mute = true; 937 rt722_sdca_set_fu0f_capture_ctl(rt722); 938 break; 939 } 940 return 0; 941 } 942 943 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w, 944 struct snd_kcontrol *kcontrol, int event) 945 { 946 struct snd_soc_component *component = 947 snd_soc_dapm_to_component(w->dapm); 948 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 949 unsigned char ps0 = 0x0, ps3 = 0x3; 950 951 switch (event) { 952 case SND_SOC_DAPM_POST_PMU: 953 regmap_write(rt722->regmap, 954 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 955 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 956 break; 957 case SND_SOC_DAPM_PRE_PMD: 958 regmap_write(rt722->regmap, 959 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 960 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 961 break; 962 } 963 return 0; 964 } 965 966 static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w, 967 struct snd_kcontrol *kcontrol, int event) 968 { 969 struct snd_soc_component *component = 970 snd_soc_dapm_to_component(w->dapm); 971 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 972 unsigned char ps0 = 0x0, ps3 = 0x3; 973 974 switch (event) { 975 case SND_SOC_DAPM_POST_PMU: 976 regmap_write(rt722->regmap, 977 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 978 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 979 break; 980 case SND_SOC_DAPM_PRE_PMD: 981 regmap_write(rt722->regmap, 982 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 983 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 984 break; 985 } 986 return 0; 987 } 988 989 static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w, 990 struct snd_kcontrol *kcontrol, int event) 991 { 992 struct snd_soc_component *component = 993 snd_soc_dapm_to_component(w->dapm); 994 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 995 unsigned char ps0 = 0x0, ps3 = 0x3; 996 997 switch (event) { 998 case SND_SOC_DAPM_POST_PMU: 999 regmap_write(rt722->regmap, 1000 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1001 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1002 break; 1003 case SND_SOC_DAPM_PRE_PMD: 1004 regmap_write(rt722->regmap, 1005 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1006 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1007 break; 1008 } 1009 return 0; 1010 } 1011 1012 static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w, 1013 struct snd_kcontrol *kcontrol, int event) 1014 { 1015 struct snd_soc_component *component = 1016 snd_soc_dapm_to_component(w->dapm); 1017 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1018 unsigned char ps0 = 0x0, ps3 = 0x3; 1019 1020 switch (event) { 1021 case SND_SOC_DAPM_POST_PMU: 1022 regmap_write(rt722->regmap, 1023 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1024 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1025 break; 1026 case SND_SOC_DAPM_PRE_PMD: 1027 regmap_write(rt722->regmap, 1028 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1029 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1030 break; 1031 } 1032 return 0; 1033 } 1034 1035 static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = { 1036 SND_SOC_DAPM_OUTPUT("HP"), 1037 SND_SOC_DAPM_OUTPUT("SPK"), 1038 SND_SOC_DAPM_INPUT("MIC2"), 1039 SND_SOC_DAPM_INPUT("LINE1"), 1040 SND_SOC_DAPM_INPUT("LINE2"), 1041 SND_SOC_DAPM_INPUT("DMIC1_2"), 1042 SND_SOC_DAPM_INPUT("DMIC3_4"), 1043 1044 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1045 rt722_sdca_pde23_event, 1046 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1047 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0, 1048 rt722_sdca_pde47_event, 1049 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1050 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1051 rt722_sdca_pde11_event, 1052 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1053 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0, 1054 rt722_sdca_pde12_event, 1055 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1056 1057 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0, 1058 rt722_sdca_fu21_event, 1059 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1060 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0, 1061 rt722_sdca_fu42_event, 1062 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1063 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0, 1064 rt722_sdca_fu36_event, 1065 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1066 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0, 1067 rt722_sdca_fu113_event, 1068 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1069 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0, 1070 &rt722_sdca_adc22_mux), 1071 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0, 1072 &rt722_sdca_adc24_mux), 1073 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0, 1074 &rt722_sdca_adc25_mux), 1075 1076 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0), 1077 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0), 1078 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0), 1079 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0), 1080 }; 1081 1082 static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = { 1083 {"FU 42", NULL, "DP1RX"}, 1084 {"FU 21", NULL, "DP3RX"}, 1085 1086 {"ADC 22 Mux", "MIC2", "MIC2"}, 1087 {"ADC 22 Mux", "LINE1", "LINE1"}, 1088 {"ADC 22 Mux", "LINE2", "LINE2"}, 1089 {"ADC 24 Mux", "DMIC1", "DMIC1_2"}, 1090 {"ADC 24 Mux", "DMIC2", "DMIC3_4"}, 1091 {"ADC 25 Mux", "DMIC1", "DMIC1_2"}, 1092 {"ADC 25 Mux", "DMIC2", "DMIC3_4"}, 1093 {"FU 36", NULL, "PDE 12"}, 1094 {"FU 36", NULL, "ADC 22 Mux"}, 1095 {"FU 113", NULL, "PDE 11"}, 1096 {"FU 113", NULL, "ADC 24 Mux"}, 1097 {"FU 113", NULL, "ADC 25 Mux"}, 1098 {"DP2TX", NULL, "FU 36"}, 1099 {"DP6TX", NULL, "FU 113"}, 1100 1101 {"HP", NULL, "PDE 47"}, 1102 {"HP", NULL, "FU 42"}, 1103 {"SPK", NULL, "PDE 23"}, 1104 {"SPK", NULL, "FU 21"}, 1105 }; 1106 1107 static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev) 1108 { 1109 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src); 1110 1111 return 0; 1112 } 1113 1114 static int rt722_sdca_probe(struct snd_soc_component *component) 1115 { 1116 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1117 int ret; 1118 1119 rt722_sdca_parse_dt(rt722, &rt722->slave->dev); 1120 rt722->component = component; 1121 1122 ret = pm_runtime_resume(component->dev); 1123 if (ret < 0 && ret != -EACCES) 1124 return ret; 1125 1126 return 0; 1127 } 1128 1129 static const struct snd_soc_component_driver soc_sdca_dev_rt722 = { 1130 .probe = rt722_sdca_probe, 1131 .controls = rt722_sdca_controls, 1132 .num_controls = ARRAY_SIZE(rt722_sdca_controls), 1133 .dapm_widgets = rt722_sdca_dapm_widgets, 1134 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets), 1135 .dapm_routes = rt722_sdca_audio_map, 1136 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map), 1137 .set_jack = rt722_sdca_set_jack_detect, 1138 .endianness = 1, 1139 }; 1140 1141 static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1142 int direction) 1143 { 1144 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1145 1146 return 0; 1147 } 1148 1149 static void rt722_sdca_shutdown(struct snd_pcm_substream *substream, 1150 struct snd_soc_dai *dai) 1151 { 1152 snd_soc_dai_set_dma_data(dai, substream, NULL); 1153 } 1154 1155 static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream, 1156 struct snd_pcm_hw_params *params, 1157 struct snd_soc_dai *dai) 1158 { 1159 struct snd_soc_component *component = dai->component; 1160 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1161 struct sdw_stream_config stream_config; 1162 struct sdw_port_config port_config; 1163 enum sdw_data_direction direction; 1164 struct sdw_stream_runtime *sdw_stream; 1165 int retval, port, num_channels; 1166 unsigned int sampling_rate; 1167 1168 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1169 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1170 1171 if (!sdw_stream) 1172 return -EINVAL; 1173 1174 if (!rt722->slave) 1175 return -EINVAL; 1176 1177 /* 1178 * RT722_AIF1 with port = 1 for headphone playback 1179 * RT722_AIF1 with port = 2 for headset-mic capture 1180 * RT722_AIF2 with port = 3 for speaker playback 1181 * RT722_AIF3 with port = 6 for digital-mic capture 1182 */ 1183 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1184 direction = SDW_DATA_DIR_RX; 1185 if (dai->id == RT722_AIF1) 1186 port = 1; 1187 else if (dai->id == RT722_AIF2) 1188 port = 3; 1189 else 1190 return -EINVAL; 1191 } else { 1192 direction = SDW_DATA_DIR_TX; 1193 if (dai->id == RT722_AIF1) 1194 port = 2; 1195 else if (dai->id == RT722_AIF3) 1196 port = 6; 1197 else 1198 return -EINVAL; 1199 } 1200 stream_config.frame_rate = params_rate(params); 1201 stream_config.ch_count = params_channels(params); 1202 stream_config.bps = snd_pcm_format_width(params_format(params)); 1203 stream_config.direction = direction; 1204 1205 num_channels = params_channels(params); 1206 port_config.ch_mask = GENMASK(num_channels - 1, 0); 1207 port_config.num = port; 1208 1209 retval = sdw_stream_add_slave(rt722->slave, &stream_config, 1210 &port_config, 1, sdw_stream); 1211 if (retval) { 1212 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1213 return retval; 1214 } 1215 1216 if (params_channels(params) > 16) { 1217 dev_err(component->dev, "%s: Unsupported channels %d\n", 1218 __func__, params_channels(params)); 1219 return -EINVAL; 1220 } 1221 1222 /* sampling rate configuration */ 1223 switch (params_rate(params)) { 1224 case 44100: 1225 sampling_rate = RT722_SDCA_RATE_44100HZ; 1226 break; 1227 case 48000: 1228 sampling_rate = RT722_SDCA_RATE_48000HZ; 1229 break; 1230 case 96000: 1231 sampling_rate = RT722_SDCA_RATE_96000HZ; 1232 break; 1233 case 192000: 1234 sampling_rate = RT722_SDCA_RATE_192000HZ; 1235 break; 1236 default: 1237 dev_err(component->dev, "%s: Rate %d is not supported\n", 1238 __func__, params_rate(params)); 1239 return -EINVAL; 1240 } 1241 1242 /* set sampling frequency */ 1243 if (dai->id == RT722_AIF1) { 1244 regmap_write(rt722->regmap, 1245 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, 1246 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1247 regmap_write(rt722->regmap, 1248 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, 1249 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1250 } 1251 1252 if (dai->id == RT722_AIF2) 1253 regmap_write(rt722->regmap, 1254 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 1255 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1256 1257 if (dai->id == RT722_AIF3) 1258 regmap_write(rt722->regmap, 1259 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 1260 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1261 1262 return 0; 1263 } 1264 1265 static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream, 1266 struct snd_soc_dai *dai) 1267 { 1268 struct snd_soc_component *component = dai->component; 1269 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1270 struct sdw_stream_runtime *sdw_stream = 1271 snd_soc_dai_get_dma_data(dai, substream); 1272 1273 if (!rt722->slave) 1274 return -EINVAL; 1275 1276 sdw_stream_remove_slave(rt722->slave, sdw_stream); 1277 return 0; 1278 } 1279 1280 #define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 1281 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1282 #define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1283 SNDRV_PCM_FMTBIT_S24_LE) 1284 1285 static const struct snd_soc_dai_ops rt722_sdca_ops = { 1286 .hw_params = rt722_sdca_pcm_hw_params, 1287 .hw_free = rt722_sdca_pcm_hw_free, 1288 .set_stream = rt722_sdca_set_sdw_stream, 1289 .shutdown = rt722_sdca_shutdown, 1290 }; 1291 1292 static struct snd_soc_dai_driver rt722_sdca_dai[] = { 1293 { 1294 .name = "rt722-sdca-aif1", 1295 .id = RT722_AIF1, 1296 .playback = { 1297 .stream_name = "DP1 Headphone Playback", 1298 .channels_min = 1, 1299 .channels_max = 2, 1300 .rates = RT722_STEREO_RATES, 1301 .formats = RT722_FORMATS, 1302 }, 1303 .capture = { 1304 .stream_name = "DP2 Headset Capture", 1305 .channels_min = 1, 1306 .channels_max = 2, 1307 .rates = RT722_STEREO_RATES, 1308 .formats = RT722_FORMATS, 1309 }, 1310 .ops = &rt722_sdca_ops, 1311 }, 1312 { 1313 .name = "rt722-sdca-aif2", 1314 .id = RT722_AIF2, 1315 .playback = { 1316 .stream_name = "DP3 Speaker Playback", 1317 .channels_min = 1, 1318 .channels_max = 2, 1319 .rates = RT722_STEREO_RATES, 1320 .formats = RT722_FORMATS, 1321 }, 1322 .ops = &rt722_sdca_ops, 1323 }, 1324 { 1325 .name = "rt722-sdca-aif3", 1326 .id = RT722_AIF3, 1327 .capture = { 1328 .stream_name = "DP6 DMic Capture", 1329 .channels_min = 1, 1330 .channels_max = 4, 1331 .rates = RT722_STEREO_RATES, 1332 .formats = RT722_FORMATS, 1333 }, 1334 .ops = &rt722_sdca_ops, 1335 } 1336 }; 1337 1338 int rt722_sdca_init(struct device *dev, struct regmap *regmap, 1339 struct regmap *mbq_regmap, struct sdw_slave *slave) 1340 { 1341 struct rt722_sdca_priv *rt722; 1342 1343 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL); 1344 if (!rt722) 1345 return -ENOMEM; 1346 1347 dev_set_drvdata(dev, rt722); 1348 rt722->slave = slave; 1349 rt722->regmap = regmap; 1350 rt722->mbq_regmap = mbq_regmap; 1351 1352 mutex_init(&rt722->calibrate_mutex); 1353 mutex_init(&rt722->disable_irq_lock); 1354 1355 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler); 1356 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler); 1357 1358 /* 1359 * Mark hw_init to false 1360 * HW init will be performed when device reports present 1361 */ 1362 rt722->hw_init = false; 1363 rt722->first_hw_init = false; 1364 rt722->fu1e_dapm_mute = true; 1365 rt722->fu0f_dapm_mute = true; 1366 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true; 1367 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] = 1368 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true; 1369 1370 return devm_snd_soc_register_component(dev, 1371 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai)); 1372 } 1373 1374 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722) 1375 { 1376 /* Set AD07 power entity floating control */ 1377 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1378 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29); 1379 /* Set AD10 power entity floating control */ 1380 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1381 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00); 1382 /* Set DMIC1/DMIC2 power entity floating control */ 1383 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1384 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a); 1385 /* Set DMIC2 IT entity floating control */ 1386 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1387 RT722_DMIC_ENT_FLOAT_CTL, 0x2626); 1388 /* Set AD10 FU entity floating control */ 1389 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1390 RT722_ADC_ENT_FLOAT_CTL, 0x1e00); 1391 /* Set DMIC2 FU entity floating control */ 1392 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1393 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515); 1394 /* Set AD10 FU channel floating control */ 1395 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1396 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304); 1397 /* Set DMIC2 FU channel floating control */ 1398 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1399 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304); 1400 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */ 1401 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1402 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000); 1403 /* Enable vf707_r12_05/vf707_r13_05 */ 1404 regmap_write(rt722->regmap, 1405 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 1406 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1407 /* Fine tune PDE2A latency */ 1408 regmap_write(rt722->regmap, 0x2f5c, 0x25); 1409 } 1410 1411 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722) 1412 { 1413 /* Set DVQ=01 */ 1414 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1415 0xc215); 1416 /* Reset dc_cal_top */ 1417 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1418 0x702c); 1419 /* W1C Trigger Calibration */ 1420 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1421 0xf02d); 1422 /* Set DAC02/ClassD power entity floating control */ 1423 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL, 1424 0x2323); 1425 /* Set EAPD high */ 1426 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL, 1427 0x0002); 1428 /* Enable vf707_r14 */ 1429 regmap_write(rt722->regmap, 1430 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 1431 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04); 1432 } 1433 1434 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722) 1435 { 1436 int loop_check, chk_cnt = 100, ret; 1437 unsigned int calib_status = 0; 1438 1439 /* Config analog bias */ 1440 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3, 1441 0xa081); 1442 /* GE related settings */ 1443 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2, 1444 0xa009); 1445 /* Button A, B, C, D bypass mode */ 1446 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4, 1447 0xcf00); 1448 /* HID1 slot enable */ 1449 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5, 1450 0x000f); 1451 /* Report ID for HID1 */ 1452 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0, 1453 0x1100); 1454 /* OSC/OOC for slot 2, 3 */ 1455 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7, 1456 0x0c12); 1457 /* Set JD de-bounce clock control */ 1458 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1, 1459 0x7002); 1460 /* Set DVQ=01 */ 1461 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1462 0xc215); 1463 /* FSM switch to calibration manual mode */ 1464 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL, 1465 0x4100); 1466 /* W1C Trigger DC calibration (HP) */ 1467 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3, 1468 0x008d); 1469 /* check HP calibration FSM status */ 1470 for (loop_check = 0; loop_check < chk_cnt; loop_check++) { 1471 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI, 1472 RT722_DAC_DC_CALI_CTL3, &calib_status); 1473 if (ret < 0 || loop_check == chk_cnt) 1474 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret); 1475 if ((calib_status & 0x0040) == 0x0) 1476 break; 1477 } 1478 /* Set ADC09 power entity floating control */ 1479 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL, 1480 0x2a12); 1481 /* Set MIC2 and LINE1 power entity floating control */ 1482 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL, 1483 0x3429); 1484 /* Set ET41h and LINE2 power entity floating control */ 1485 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL, 1486 0x4112); 1487 /* Set DAC03 and HP power entity floating control */ 1488 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL, 1489 0x4040); 1490 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1, 1491 0x4141); 1492 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1, 1493 0x0101); 1494 /* Fine tune PDE40 latency */ 1495 regmap_write(rt722->regmap, 0x2f58, 0x07); 1496 regmap_write(rt722->regmap, 0x2f03, 0x06); 1497 /* MIC VRefo */ 1498 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1499 RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200); 1500 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1501 RT722_VREFO_GAT, 0x4000, 0x4000); 1502 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */ 1503 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4, 1504 0x0010); 1505 } 1506 1507 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave) 1508 { 1509 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev); 1510 1511 rt722->disable_irq = false; 1512 1513 if (rt722->hw_init) 1514 return 0; 1515 1516 if (rt722->first_hw_init) { 1517 regcache_cache_only(rt722->regmap, false); 1518 regcache_cache_bypass(rt722->regmap, true); 1519 regcache_cache_only(rt722->mbq_regmap, false); 1520 regcache_cache_bypass(rt722->mbq_regmap, true); 1521 } else { 1522 /* 1523 * PM runtime is only enabled when a Slave reports as Attached 1524 */ 1525 1526 /* set autosuspend parameters */ 1527 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 1528 pm_runtime_use_autosuspend(&slave->dev); 1529 1530 /* update count of parent 'active' children */ 1531 pm_runtime_set_active(&slave->dev); 1532 1533 /* make sure the device does not suspend immediately */ 1534 pm_runtime_mark_last_busy(&slave->dev); 1535 1536 pm_runtime_enable(&slave->dev); 1537 } 1538 1539 pm_runtime_get_noresume(&slave->dev); 1540 1541 rt722_sdca_dmic_preset(rt722); 1542 rt722_sdca_amp_preset(rt722); 1543 rt722_sdca_jack_preset(rt722); 1544 1545 if (rt722->first_hw_init) { 1546 regcache_cache_bypass(rt722->regmap, false); 1547 regcache_mark_dirty(rt722->regmap); 1548 regcache_cache_bypass(rt722->mbq_regmap, false); 1549 regcache_mark_dirty(rt722->mbq_regmap); 1550 } else 1551 rt722->first_hw_init = true; 1552 1553 /* Mark Slave initialization complete */ 1554 rt722->hw_init = true; 1555 1556 pm_runtime_mark_last_busy(&slave->dev); 1557 pm_runtime_put_autosuspend(&slave->dev); 1558 1559 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1560 return 0; 1561 } 1562 1563 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver"); 1564 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1565 MODULE_LICENSE("GPL"); 1566