1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver 4 // 5 // Copyright(c) 2023 Realtek Semiconductor Corp. 6 // 7 // 8 9 #include <linux/bitops.h> 10 #include <sound/core.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <sound/initval.h> 14 #include <sound/jack.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <sound/pcm.h> 19 #include <linux/pm_runtime.h> 20 #include <sound/pcm_params.h> 21 #include <linux/soundwire/sdw_registers.h> 22 #include <linux/slab.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "rt722-sdca.h" 27 28 #define RT722_NID_ADDR(nid, reg) ((nid) << 20 | (reg)) 29 30 int rt722_sdca_index_write(struct rt722_sdca_priv *rt722, 31 unsigned int nid, unsigned int reg, unsigned int value) 32 { 33 struct regmap *regmap = rt722->regmap; 34 unsigned int addr = RT722_NID_ADDR(nid, reg); 35 int ret; 36 37 ret = regmap_write(regmap, addr, value); 38 if (ret < 0) 39 dev_err(&rt722->slave->dev, 40 "%s: Failed to set private value: %06x <= %04x ret=%d\n", 41 __func__, addr, value, ret); 42 43 return ret; 44 } 45 46 int rt722_sdca_index_read(struct rt722_sdca_priv *rt722, 47 unsigned int nid, unsigned int reg, unsigned int *value) 48 { 49 int ret; 50 struct regmap *regmap = rt722->regmap; 51 unsigned int addr = RT722_NID_ADDR(nid, reg); 52 53 ret = regmap_read(regmap, addr, value); 54 if (ret < 0) 55 dev_err(&rt722->slave->dev, 56 "%s: Failed to get private value: %06x => %04x ret=%d\n", 57 __func__, addr, *value, ret); 58 59 return ret; 60 } 61 62 static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722, 63 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val) 64 { 65 unsigned int tmp; 66 int ret; 67 68 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp); 69 if (ret < 0) 70 return ret; 71 72 set_mask_bits(&tmp, mask, val); 73 return rt722_sdca_index_write(rt722, nid, reg, tmp); 74 } 75 76 static int rt722_sdca_btn_type(unsigned char *buffer) 77 { 78 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) || 79 (*(buffer + 1) == 0x10)) 80 return SND_JACK_BTN_2; 81 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) || 82 (*(buffer + 1) == 0x20)) 83 return SND_JACK_BTN_3; 84 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) || 85 (*(buffer + 1) == 0x40)) 86 return SND_JACK_BTN_0; 87 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) || 88 (*(buffer + 1) == 0x80)) 89 return SND_JACK_BTN_1; 90 91 return 0; 92 } 93 94 static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722) 95 { 96 unsigned int btn_type = 0, offset, idx, val, owner; 97 int ret; 98 unsigned char buf[3]; 99 100 /* get current UMP message owner */ 101 ret = regmap_read(rt722->regmap, 102 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 103 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner); 104 if (ret < 0) 105 return 0; 106 107 /* if owner is device then there is no button event from device */ 108 if (owner == 1) 109 return 0; 110 111 /* read UMP message offset */ 112 ret = regmap_read(rt722->regmap, 113 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 114 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 115 if (ret < 0) 116 goto _end_btn_det_; 117 118 for (idx = 0; idx < sizeof(buf); idx++) { 119 ret = regmap_read(rt722->regmap, 120 RT722_BUF_ADDR_HID1 + offset + idx, &val); 121 if (ret < 0) 122 goto _end_btn_det_; 123 buf[idx] = val & 0xff; 124 } 125 126 if (buf[0] == 0x11) 127 btn_type = rt722_sdca_btn_type(&buf[1]); 128 129 _end_btn_det_: 130 /* Host is owner, so set back to device */ 131 if (owner == 0) 132 /* set owner to device */ 133 regmap_write(rt722->regmap, 134 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 135 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01); 136 137 return btn_type; 138 } 139 140 static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722) 141 { 142 unsigned int det_mode; 143 int ret; 144 145 /* get detected_mode */ 146 ret = regmap_read(rt722->regmap, 147 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 148 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 149 if (ret < 0) 150 goto io_error; 151 152 switch (det_mode) { 153 case 0x00: 154 rt722->jack_type = 0; 155 break; 156 case 0x03: 157 rt722->jack_type = SND_JACK_HEADPHONE; 158 break; 159 case 0x05: 160 rt722->jack_type = SND_JACK_HEADSET; 161 break; 162 } 163 164 /* write selected_mode */ 165 if (det_mode) { 166 ret = regmap_write(rt722->regmap, 167 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 168 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode); 169 if (ret < 0) 170 goto io_error; 171 } 172 173 dev_dbg(&rt722->slave->dev, 174 "%s, detected_mode=0x%x\n", __func__, det_mode); 175 176 return 0; 177 178 io_error: 179 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 180 return ret; 181 } 182 183 static void rt722_sdca_jack_detect_handler(struct work_struct *work) 184 { 185 struct rt722_sdca_priv *rt722 = 186 container_of(work, struct rt722_sdca_priv, jack_detect_work.work); 187 int btn_type = 0, ret; 188 189 if (!rt722->hs_jack) 190 return; 191 192 if (!rt722->component->card || !rt722->component->card->instantiated) 193 return; 194 195 /* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */ 196 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) { 197 ret = rt722_sdca_headset_detect(rt722); 198 if (ret < 0) 199 return; 200 } 201 202 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */ 203 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8) 204 btn_type = rt722_sdca_button_detect(rt722); 205 206 if (rt722->jack_type == 0) 207 btn_type = 0; 208 209 dev_dbg(&rt722->slave->dev, 210 "in %s, jack_type=%d\n", __func__, rt722->jack_type); 211 dev_dbg(&rt722->slave->dev, 212 "in %s, btn_type=0x%x\n", __func__, btn_type); 213 dev_dbg(&rt722->slave->dev, 214 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__, 215 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2); 216 217 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 218 SND_JACK_HEADSET | 219 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 220 SND_JACK_BTN_2 | SND_JACK_BTN_3); 221 222 if (btn_type) { 223 /* button released */ 224 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 225 SND_JACK_HEADSET | 226 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 227 SND_JACK_BTN_2 | SND_JACK_BTN_3); 228 229 mod_delayed_work(system_power_efficient_wq, 230 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 231 } 232 } 233 234 static void rt722_sdca_btn_check_handler(struct work_struct *work) 235 { 236 struct rt722_sdca_priv *rt722 = 237 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work); 238 int btn_type = 0, ret, idx; 239 unsigned int det_mode, offset, val; 240 unsigned char buf[3]; 241 242 ret = regmap_read(rt722->regmap, 243 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 244 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 245 if (ret < 0) 246 goto io_error; 247 248 /* pin attached */ 249 if (det_mode) { 250 /* read UMP message offset */ 251 ret = regmap_read(rt722->regmap, 252 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 253 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 254 if (ret < 0) 255 goto io_error; 256 257 for (idx = 0; idx < sizeof(buf); idx++) { 258 ret = regmap_read(rt722->regmap, 259 RT722_BUF_ADDR_HID1 + offset + idx, &val); 260 if (ret < 0) 261 goto io_error; 262 buf[idx] = val & 0xff; 263 } 264 265 if (buf[0] == 0x11) 266 btn_type = rt722_sdca_btn_type(&buf[1]); 267 } else 268 rt722->jack_type = 0; 269 270 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type); 271 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 272 SND_JACK_HEADSET | 273 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 274 SND_JACK_BTN_2 | SND_JACK_BTN_3); 275 276 if (btn_type) { 277 /* button released */ 278 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 279 SND_JACK_HEADSET | 280 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 281 SND_JACK_BTN_2 | SND_JACK_BTN_3); 282 283 mod_delayed_work(system_power_efficient_wq, 284 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 285 } 286 287 return; 288 289 io_error: 290 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 291 } 292 293 static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722) 294 { 295 mutex_lock(&rt722->calibrate_mutex); 296 if (rt722->hs_jack) { 297 /* set SCP_SDCA_IntMask1[0]=1 */ 298 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1, 299 SDW_SCP_SDCA_INTMASK_SDCA_0); 300 /* set SCP_SDCA_IntMask2[0]=1 */ 301 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2, 302 SDW_SCP_SDCA_INTMASK_SDCA_8); 303 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__); 304 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 305 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E); 306 /* set XU(et03h) & XU(et0Dh) to Not bypassed */ 307 regmap_write(rt722->regmap, 308 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03, 309 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 310 regmap_write(rt722->regmap, 311 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D, 312 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 313 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL1, 0x0000); 314 /* trigger GE interrupt */ 315 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 316 RT722_GE_RELATED_CTL2, 0x4000, 0x4000); 317 } 318 mutex_unlock(&rt722->calibrate_mutex); 319 } 320 321 static int rt722_sdca_set_jack_detect(struct snd_soc_component *component, 322 struct snd_soc_jack *hs_jack, void *data) 323 { 324 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 325 int ret; 326 327 rt722->hs_jack = hs_jack; 328 329 ret = pm_runtime_resume_and_get(component->dev); 330 if (ret < 0) { 331 if (ret != -EACCES) { 332 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); 333 return ret; 334 } 335 /* pm_runtime not enabled yet */ 336 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); 337 return 0; 338 } 339 340 rt722_sdca_jack_init(rt722); 341 342 pm_runtime_mark_last_busy(component->dev); 343 pm_runtime_put_autosuspend(component->dev); 344 345 return 0; 346 } 347 348 /* For SDCA control DAC/ADC Gain */ 349 static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol, 350 struct snd_ctl_elem_value *ucontrol) 351 { 352 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 353 struct soc_mixer_control *mc = 354 (struct soc_mixer_control *)kcontrol->private_value; 355 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 356 unsigned int read_l, read_r, gain_l_val, gain_r_val; 357 unsigned int adc_vol_flag = 0, changed = 0; 358 unsigned int lvalue, rvalue; 359 const unsigned int interval_offset = 0xc0; 360 const unsigned int tendB = 0xa00; 361 362 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 363 strstr(ucontrol->id.name, "FU0F Capture Volume")) 364 adc_vol_flag = 1; 365 366 regmap_read(rt722->regmap, mc->reg, &lvalue); 367 regmap_read(rt722->regmap, mc->rreg, &rvalue); 368 369 /* L Channel */ 370 gain_l_val = ucontrol->value.integer.value[0]; 371 if (gain_l_val > mc->max) 372 gain_l_val = mc->max; 373 374 if (mc->shift == 8) /* boost gain */ 375 gain_l_val = gain_l_val * tendB; 376 else { 377 /* ADC/DAC gain */ 378 if (adc_vol_flag) 379 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset); 380 else 381 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 382 gain_l_val &= 0xffff; 383 } 384 385 /* R Channel */ 386 gain_r_val = ucontrol->value.integer.value[1]; 387 if (gain_r_val > mc->max) 388 gain_r_val = mc->max; 389 390 if (mc->shift == 8) /* boost gain */ 391 gain_r_val = gain_r_val * tendB; 392 else { 393 /* ADC/DAC gain */ 394 if (adc_vol_flag) 395 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset); 396 else 397 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 398 gain_r_val &= 0xffff; 399 } 400 401 if (lvalue != gain_l_val || rvalue != gain_r_val) 402 changed = 1; 403 else 404 return 0; 405 406 /* Lch*/ 407 regmap_write(rt722->regmap, mc->reg, gain_l_val); 408 409 /* Rch */ 410 regmap_write(rt722->regmap, mc->rreg, gain_r_val); 411 412 regmap_read(rt722->regmap, mc->reg, &read_l); 413 regmap_read(rt722->regmap, mc->rreg, &read_r); 414 if (read_r == gain_r_val && read_l == gain_l_val) 415 return changed; 416 417 return -EIO; 418 } 419 420 static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol, 421 struct snd_ctl_elem_value *ucontrol) 422 { 423 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 424 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 425 struct soc_mixer_control *mc = 426 (struct soc_mixer_control *)kcontrol->private_value; 427 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 428 unsigned int adc_vol_flag = 0; 429 const unsigned int interval_offset = 0xc0; 430 const unsigned int tendB = 0xa00; 431 432 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 433 strstr(ucontrol->id.name, "FU0F Capture Volume")) 434 adc_vol_flag = 1; 435 436 regmap_read(rt722->regmap, mc->reg, &read_l); 437 regmap_read(rt722->regmap, mc->rreg, &read_r); 438 439 if (mc->shift == 8) /* boost gain */ 440 ctl_l = read_l / tendB; 441 else { 442 if (adc_vol_flag) 443 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset); 444 else 445 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 446 } 447 448 if (read_l != read_r) { 449 if (mc->shift == 8) /* boost gain */ 450 ctl_r = read_r / tendB; 451 else { /* ADC/DAC gain */ 452 if (adc_vol_flag) 453 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset); 454 else 455 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 456 } 457 } else { 458 ctl_r = ctl_l; 459 } 460 461 ucontrol->value.integer.value[0] = ctl_l; 462 ucontrol->value.integer.value[1] = ctl_r; 463 464 return 0; 465 } 466 467 static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722) 468 { 469 int err, i; 470 unsigned int ch_mute; 471 472 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) { 473 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i]; 474 err = regmap_write(rt722->regmap, 475 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 476 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 477 if (err < 0) 478 return err; 479 } 480 481 return 0; 482 } 483 484 static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol, 485 struct snd_ctl_elem_value *ucontrol) 486 { 487 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 488 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 489 struct rt722_sdca_dmic_kctrl_priv *p = 490 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 491 unsigned int i; 492 493 for (i = 0; i < p->count; i++) 494 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i]; 495 496 return 0; 497 } 498 499 static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol, 500 struct snd_ctl_elem_value *ucontrol) 501 { 502 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 503 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 504 struct rt722_sdca_dmic_kctrl_priv *p = 505 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 506 int err, changed = 0, i; 507 508 for (i = 0; i < p->count; i++) { 509 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i]) 510 changed = 1; 511 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i]; 512 } 513 514 err = rt722_sdca_set_fu1e_capture_ctl(rt722); 515 if (err < 0) 516 return err; 517 518 return changed; 519 } 520 521 static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722) 522 { 523 int err; 524 unsigned int ch_l, ch_r; 525 526 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00; 527 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00; 528 529 err = regmap_write(rt722->regmap, 530 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 531 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l); 532 if (err < 0) 533 return err; 534 535 err = regmap_write(rt722->regmap, 536 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 537 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r); 538 if (err < 0) 539 return err; 540 541 return 0; 542 } 543 544 static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol, 545 struct snd_ctl_elem_value *ucontrol) 546 { 547 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 548 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 549 550 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute; 551 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute; 552 return 0; 553 } 554 555 static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol, 556 struct snd_ctl_elem_value *ucontrol) 557 { 558 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 559 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 560 int err, changed = 0; 561 562 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] || 563 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1]) 564 changed = 1; 565 566 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0]; 567 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1]; 568 err = rt722_sdca_set_fu0f_capture_ctl(rt722); 569 if (err < 0) 570 return err; 571 572 return changed; 573 } 574 575 static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol, 576 struct snd_ctl_elem_info *uinfo) 577 { 578 struct rt722_sdca_dmic_kctrl_priv *p = 579 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 580 581 if (p->max == 1) 582 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 583 else 584 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 585 uinfo->count = p->count; 586 uinfo->value.integer.min = 0; 587 uinfo->value.integer.max = p->max; 588 return 0; 589 } 590 591 static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol, 592 struct snd_ctl_elem_value *ucontrol) 593 { 594 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 595 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 596 struct rt722_sdca_dmic_kctrl_priv *p = 597 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 598 unsigned int boost_step = 0x0a00; 599 unsigned int vol_max = 0x1e00; 600 unsigned int regvalue, ctl, i; 601 unsigned int adc_vol_flag = 0; 602 const unsigned int interval_offset = 0xc0; 603 604 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 605 adc_vol_flag = 1; 606 607 /* check all channels */ 608 for (i = 0; i < p->count; i++) { 609 regmap_read(rt722->regmap, p->reg_base + i, ®value); 610 611 if (!adc_vol_flag) /* boost gain */ 612 ctl = regvalue / boost_step; 613 else /* ADC gain */ 614 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset); 615 616 ucontrol->value.integer.value[i] = ctl; 617 } 618 619 return 0; 620 } 621 622 static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol, 623 struct snd_ctl_elem_value *ucontrol) 624 { 625 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 626 struct rt722_sdca_dmic_kctrl_priv *p = 627 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 628 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 629 unsigned int boost_step = 0x0a00; 630 unsigned int vol_max = 0x1e00; 631 unsigned int gain_val[4]; 632 unsigned int i, adc_vol_flag = 0, changed = 0; 633 unsigned int regvalue[4]; 634 const unsigned int interval_offset = 0xc0; 635 int err; 636 637 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 638 adc_vol_flag = 1; 639 640 /* check all channels */ 641 for (i = 0; i < p->count; i++) { 642 regmap_read(rt722->regmap, p->reg_base + i, ®value[i]); 643 644 gain_val[i] = ucontrol->value.integer.value[i]; 645 if (gain_val[i] > p->max) 646 gain_val[i] = p->max; 647 648 if (!adc_vol_flag) /* boost gain */ 649 gain_val[i] = gain_val[i] * boost_step; 650 else { /* ADC gain */ 651 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset); 652 gain_val[i] &= 0xffff; 653 } 654 655 if (regvalue[i] != gain_val[i]) 656 changed = 1; 657 } 658 659 if (!changed) 660 return 0; 661 662 for (i = 0; i < p->count; i++) { 663 err = regmap_write(rt722->regmap, p->reg_base + i, gain_val[i]); 664 if (err < 0) 665 dev_err(&rt722->slave->dev, "%s: %#08x can't be set\n", 666 __func__, p->reg_base + i); 667 } 668 669 return changed; 670 } 671 672 #define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \ 673 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \ 674 {.reg_base = xreg_base, .count = xcount, .max = xmax, \ 675 .invert = xinvert}) 676 677 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \ 678 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 679 .info = rt722_sdca_fu_info, \ 680 .get = rt722_sdca_fu1e_capture_get, \ 681 .put = rt722_sdca_fu1e_capture_put, \ 682 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)} 683 684 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\ 685 xhandler_put, xcount, xmax, tlv_array) \ 686 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 687 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 688 SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 689 .tlv.p = (tlv_array), \ 690 .info = rt722_sdca_fu_info, \ 691 .get = xhandler_get, .put = xhandler_put, \ 692 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) } 693 694 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 695 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0); 696 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0); 697 698 static const struct snd_kcontrol_new rt722_sdca_controls[] = { 699 /* Headphone playback settings */ 700 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume", 701 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 702 RT722_SDCA_CTL_FU_VOLUME, CH_L), 703 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 704 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 705 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 706 /* Headset mic capture settings */ 707 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0, 708 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put), 709 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume", 710 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 711 RT722_SDCA_CTL_FU_VOLUME, CH_L), 712 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 713 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0, 714 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv), 715 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume", 716 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 717 RT722_SDCA_CTL_FU_CH_GAIN, CH_L), 718 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 719 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0, 720 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv), 721 /* AMP playback settings */ 722 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume", 723 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 724 RT722_SDCA_CTL_FU_VOLUME, CH_L), 725 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 726 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 727 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 728 /* DMIC capture settings */ 729 RT722_SDCA_FU_CTRL("FU1E Capture Switch", 730 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 731 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4), 732 RT722_SDCA_EXT_TLV("FU1E Capture Volume", 733 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 734 RT722_SDCA_CTL_FU_VOLUME, CH_01), 735 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 736 4, 0x3f, mic_vol_tlv), 737 RT722_SDCA_EXT_TLV("FU15 Boost Volume", 738 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, 739 RT722_SDCA_CTL_FU_CH_GAIN, CH_01), 740 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 741 4, 3, boost_vol_tlv), 742 }; 743 744 static const char * const adc22_mux_text[] = { 745 "MIC2", 746 "LINE1", 747 "LINE2", 748 }; 749 750 static const char * const adc07_10_mux_text[] = { 751 "DMIC1", 752 "DMIC2", 753 }; 754 755 static SOC_ENUM_SINGLE_DECL(rt722_adc22_enum, 756 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 757 12, adc22_mux_text); 758 759 static SOC_ENUM_SINGLE_DECL(rt722_adc24_enum, 760 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 761 4, adc07_10_mux_text); 762 763 static SOC_ENUM_SINGLE_DECL(rt722_adc25_enum, 764 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 765 0, adc07_10_mux_text); 766 767 static const struct snd_kcontrol_new rt722_sdca_adc22_mux = 768 SOC_DAPM_ENUM("ADC 22 Mux", rt722_adc22_enum); 769 770 static const struct snd_kcontrol_new rt722_sdca_adc24_mux = 771 SOC_DAPM_ENUM("ADC 24 Mux", rt722_adc24_enum); 772 773 static const struct snd_kcontrol_new rt722_sdca_adc25_mux = 774 SOC_DAPM_ENUM("ADC 25 Mux", rt722_adc25_enum); 775 776 static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w, 777 struct snd_kcontrol *kcontrol, int event) 778 { 779 struct snd_soc_component *component = 780 snd_soc_dapm_to_component(w->dapm); 781 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 782 unsigned char unmute = 0x0, mute = 0x1; 783 784 switch (event) { 785 case SND_SOC_DAPM_POST_PMU: 786 regmap_write(rt722->regmap, 787 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 788 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 789 regmap_write(rt722->regmap, 790 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 791 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 792 break; 793 case SND_SOC_DAPM_PRE_PMD: 794 regmap_write(rt722->regmap, 795 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 796 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 797 regmap_write(rt722->regmap, 798 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 799 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 800 break; 801 } 802 return 0; 803 } 804 805 static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w, 806 struct snd_kcontrol *kcontrol, int event) 807 { 808 struct snd_soc_component *component = 809 snd_soc_dapm_to_component(w->dapm); 810 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 811 unsigned char unmute = 0x0, mute = 0x1; 812 813 switch (event) { 814 case SND_SOC_DAPM_POST_PMU: 815 regmap_write(rt722->regmap, 816 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 817 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 818 regmap_write(rt722->regmap, 819 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 820 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 821 break; 822 case SND_SOC_DAPM_PRE_PMD: 823 regmap_write(rt722->regmap, 824 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 825 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 826 regmap_write(rt722->regmap, 827 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 828 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 829 break; 830 } 831 return 0; 832 } 833 834 static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w, 835 struct snd_kcontrol *kcontrol, int event) 836 { 837 struct snd_soc_component *component = 838 snd_soc_dapm_to_component(w->dapm); 839 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 840 841 switch (event) { 842 case SND_SOC_DAPM_POST_PMU: 843 rt722->fu1e_dapm_mute = false; 844 rt722_sdca_set_fu1e_capture_ctl(rt722); 845 break; 846 case SND_SOC_DAPM_PRE_PMD: 847 rt722->fu1e_dapm_mute = true; 848 rt722_sdca_set_fu1e_capture_ctl(rt722); 849 break; 850 } 851 return 0; 852 } 853 854 static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w, 855 struct snd_kcontrol *kcontrol, int event) 856 { 857 struct snd_soc_component *component = 858 snd_soc_dapm_to_component(w->dapm); 859 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 860 861 switch (event) { 862 case SND_SOC_DAPM_POST_PMU: 863 rt722->fu0f_dapm_mute = false; 864 rt722_sdca_set_fu0f_capture_ctl(rt722); 865 break; 866 case SND_SOC_DAPM_PRE_PMD: 867 rt722->fu0f_dapm_mute = true; 868 rt722_sdca_set_fu0f_capture_ctl(rt722); 869 break; 870 } 871 return 0; 872 } 873 874 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w, 875 struct snd_kcontrol *kcontrol, int event) 876 { 877 struct snd_soc_component *component = 878 snd_soc_dapm_to_component(w->dapm); 879 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 880 unsigned char ps0 = 0x0, ps3 = 0x3; 881 882 switch (event) { 883 case SND_SOC_DAPM_POST_PMU: 884 regmap_write(rt722->regmap, 885 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 886 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 887 break; 888 case SND_SOC_DAPM_PRE_PMD: 889 regmap_write(rt722->regmap, 890 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 891 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 892 break; 893 } 894 return 0; 895 } 896 897 static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w, 898 struct snd_kcontrol *kcontrol, int event) 899 { 900 struct snd_soc_component *component = 901 snd_soc_dapm_to_component(w->dapm); 902 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 903 unsigned char ps0 = 0x0, ps3 = 0x3; 904 905 switch (event) { 906 case SND_SOC_DAPM_POST_PMU: 907 regmap_write(rt722->regmap, 908 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 909 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 910 break; 911 case SND_SOC_DAPM_PRE_PMD: 912 regmap_write(rt722->regmap, 913 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 914 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 915 break; 916 } 917 return 0; 918 } 919 920 static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w, 921 struct snd_kcontrol *kcontrol, int event) 922 { 923 struct snd_soc_component *component = 924 snd_soc_dapm_to_component(w->dapm); 925 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 926 unsigned char ps0 = 0x0, ps3 = 0x3; 927 928 switch (event) { 929 case SND_SOC_DAPM_POST_PMU: 930 regmap_write(rt722->regmap, 931 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 932 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 933 break; 934 case SND_SOC_DAPM_PRE_PMD: 935 regmap_write(rt722->regmap, 936 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 937 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 938 break; 939 } 940 return 0; 941 } 942 943 static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w, 944 struct snd_kcontrol *kcontrol, int event) 945 { 946 struct snd_soc_component *component = 947 snd_soc_dapm_to_component(w->dapm); 948 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 949 unsigned char ps0 = 0x0, ps3 = 0x3; 950 951 switch (event) { 952 case SND_SOC_DAPM_POST_PMU: 953 regmap_write(rt722->regmap, 954 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 955 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 956 break; 957 case SND_SOC_DAPM_PRE_PMD: 958 regmap_write(rt722->regmap, 959 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 960 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 961 break; 962 } 963 return 0; 964 } 965 966 static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = { 967 SND_SOC_DAPM_OUTPUT("HP"), 968 SND_SOC_DAPM_OUTPUT("SPK"), 969 SND_SOC_DAPM_INPUT("MIC2"), 970 SND_SOC_DAPM_INPUT("LINE1"), 971 SND_SOC_DAPM_INPUT("LINE2"), 972 SND_SOC_DAPM_INPUT("DMIC1_2"), 973 SND_SOC_DAPM_INPUT("DMIC3_4"), 974 975 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 976 rt722_sdca_pde23_event, 977 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 978 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0, 979 rt722_sdca_pde47_event, 980 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 981 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 982 rt722_sdca_pde11_event, 983 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 984 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0, 985 rt722_sdca_pde12_event, 986 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 987 988 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0, 989 rt722_sdca_fu21_event, 990 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 991 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0, 992 rt722_sdca_fu42_event, 993 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 994 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0, 995 rt722_sdca_fu36_event, 996 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 997 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0, 998 rt722_sdca_fu113_event, 999 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1000 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0, 1001 &rt722_sdca_adc22_mux), 1002 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0, 1003 &rt722_sdca_adc24_mux), 1004 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0, 1005 &rt722_sdca_adc25_mux), 1006 1007 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0), 1008 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0), 1009 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0), 1010 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0), 1011 }; 1012 1013 static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = { 1014 {"FU 42", NULL, "DP1RX"}, 1015 {"FU 21", NULL, "DP3RX"}, 1016 1017 {"ADC 22 Mux", "MIC2", "MIC2"}, 1018 {"ADC 22 Mux", "LINE1", "LINE1"}, 1019 {"ADC 22 Mux", "LINE2", "LINE2"}, 1020 {"ADC 24 Mux", "DMIC1", "DMIC1_2"}, 1021 {"ADC 24 Mux", "DMIC2", "DMIC3_4"}, 1022 {"ADC 25 Mux", "DMIC1", "DMIC1_2"}, 1023 {"ADC 25 Mux", "DMIC2", "DMIC3_4"}, 1024 {"FU 36", NULL, "PDE 12"}, 1025 {"FU 36", NULL, "ADC 22 Mux"}, 1026 {"FU 113", NULL, "PDE 11"}, 1027 {"FU 113", NULL, "ADC 24 Mux"}, 1028 {"FU 113", NULL, "ADC 25 Mux"}, 1029 {"DP2TX", NULL, "FU 36"}, 1030 {"DP6TX", NULL, "FU 113"}, 1031 1032 {"HP", NULL, "PDE 47"}, 1033 {"HP", NULL, "FU 42"}, 1034 {"SPK", NULL, "PDE 23"}, 1035 {"SPK", NULL, "FU 21"}, 1036 }; 1037 1038 static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev) 1039 { 1040 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src); 1041 1042 return 0; 1043 } 1044 1045 static int rt722_sdca_probe(struct snd_soc_component *component) 1046 { 1047 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1048 int ret; 1049 1050 rt722_sdca_parse_dt(rt722, &rt722->slave->dev); 1051 rt722->component = component; 1052 1053 ret = pm_runtime_resume(component->dev); 1054 if (ret < 0 && ret != -EACCES) 1055 return ret; 1056 1057 return 0; 1058 } 1059 1060 static const struct snd_soc_component_driver soc_sdca_dev_rt722 = { 1061 .probe = rt722_sdca_probe, 1062 .controls = rt722_sdca_controls, 1063 .num_controls = ARRAY_SIZE(rt722_sdca_controls), 1064 .dapm_widgets = rt722_sdca_dapm_widgets, 1065 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets), 1066 .dapm_routes = rt722_sdca_audio_map, 1067 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map), 1068 .set_jack = rt722_sdca_set_jack_detect, 1069 .endianness = 1, 1070 }; 1071 1072 static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1073 int direction) 1074 { 1075 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1076 1077 return 0; 1078 } 1079 1080 static void rt722_sdca_shutdown(struct snd_pcm_substream *substream, 1081 struct snd_soc_dai *dai) 1082 { 1083 snd_soc_dai_set_dma_data(dai, substream, NULL); 1084 } 1085 1086 static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream, 1087 struct snd_pcm_hw_params *params, 1088 struct snd_soc_dai *dai) 1089 { 1090 struct snd_soc_component *component = dai->component; 1091 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1092 struct sdw_stream_config stream_config; 1093 struct sdw_port_config port_config; 1094 enum sdw_data_direction direction; 1095 struct sdw_stream_runtime *sdw_stream; 1096 int retval, port, num_channels; 1097 unsigned int sampling_rate; 1098 1099 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1100 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1101 1102 if (!sdw_stream) 1103 return -EINVAL; 1104 1105 if (!rt722->slave) 1106 return -EINVAL; 1107 1108 /* 1109 * RT722_AIF1 with port = 1 for headphone playback 1110 * RT722_AIF1 with port = 2 for headset-mic capture 1111 * RT722_AIF2 with port = 3 for speaker playback 1112 * RT722_AIF3 with port = 6 for digital-mic capture 1113 */ 1114 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1115 direction = SDW_DATA_DIR_RX; 1116 if (dai->id == RT722_AIF1) 1117 port = 1; 1118 else if (dai->id == RT722_AIF2) 1119 port = 3; 1120 else 1121 return -EINVAL; 1122 } else { 1123 direction = SDW_DATA_DIR_TX; 1124 if (dai->id == RT722_AIF1) 1125 port = 2; 1126 else if (dai->id == RT722_AIF3) 1127 port = 6; 1128 else 1129 return -EINVAL; 1130 } 1131 stream_config.frame_rate = params_rate(params); 1132 stream_config.ch_count = params_channels(params); 1133 stream_config.bps = snd_pcm_format_width(params_format(params)); 1134 stream_config.direction = direction; 1135 1136 num_channels = params_channels(params); 1137 port_config.ch_mask = GENMASK(num_channels - 1, 0); 1138 port_config.num = port; 1139 1140 retval = sdw_stream_add_slave(rt722->slave, &stream_config, 1141 &port_config, 1, sdw_stream); 1142 if (retval) { 1143 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1144 return retval; 1145 } 1146 1147 if (params_channels(params) > 16) { 1148 dev_err(component->dev, "%s: Unsupported channels %d\n", 1149 __func__, params_channels(params)); 1150 return -EINVAL; 1151 } 1152 1153 /* sampling rate configuration */ 1154 switch (params_rate(params)) { 1155 case 44100: 1156 sampling_rate = RT722_SDCA_RATE_44100HZ; 1157 break; 1158 case 48000: 1159 sampling_rate = RT722_SDCA_RATE_48000HZ; 1160 break; 1161 case 96000: 1162 sampling_rate = RT722_SDCA_RATE_96000HZ; 1163 break; 1164 case 192000: 1165 sampling_rate = RT722_SDCA_RATE_192000HZ; 1166 break; 1167 default: 1168 dev_err(component->dev, "%s: Rate %d is not supported\n", 1169 __func__, params_rate(params)); 1170 return -EINVAL; 1171 } 1172 1173 /* set sampling frequency */ 1174 if (dai->id == RT722_AIF1) { 1175 regmap_write(rt722->regmap, 1176 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, 1177 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1178 regmap_write(rt722->regmap, 1179 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, 1180 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1181 } 1182 1183 if (dai->id == RT722_AIF2) 1184 regmap_write(rt722->regmap, 1185 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 1186 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1187 1188 if (dai->id == RT722_AIF3) 1189 regmap_write(rt722->regmap, 1190 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 1191 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1192 1193 return 0; 1194 } 1195 1196 static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream, 1197 struct snd_soc_dai *dai) 1198 { 1199 struct snd_soc_component *component = dai->component; 1200 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1201 struct sdw_stream_runtime *sdw_stream = 1202 snd_soc_dai_get_dma_data(dai, substream); 1203 1204 if (!rt722->slave) 1205 return -EINVAL; 1206 1207 sdw_stream_remove_slave(rt722->slave, sdw_stream); 1208 return 0; 1209 } 1210 1211 #define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 1212 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1213 #define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1214 SNDRV_PCM_FMTBIT_S24_LE) 1215 1216 static const struct snd_soc_dai_ops rt722_sdca_ops = { 1217 .hw_params = rt722_sdca_pcm_hw_params, 1218 .hw_free = rt722_sdca_pcm_hw_free, 1219 .set_stream = rt722_sdca_set_sdw_stream, 1220 .shutdown = rt722_sdca_shutdown, 1221 }; 1222 1223 static struct snd_soc_dai_driver rt722_sdca_dai[] = { 1224 { 1225 .name = "rt722-sdca-aif1", 1226 .id = RT722_AIF1, 1227 .playback = { 1228 .stream_name = "DP1 Headphone Playback", 1229 .channels_min = 1, 1230 .channels_max = 2, 1231 .rates = RT722_STEREO_RATES, 1232 .formats = RT722_FORMATS, 1233 }, 1234 .capture = { 1235 .stream_name = "DP2 Headset Capture", 1236 .channels_min = 1, 1237 .channels_max = 2, 1238 .rates = RT722_STEREO_RATES, 1239 .formats = RT722_FORMATS, 1240 }, 1241 .ops = &rt722_sdca_ops, 1242 }, 1243 { 1244 .name = "rt722-sdca-aif2", 1245 .id = RT722_AIF2, 1246 .playback = { 1247 .stream_name = "DP3 Speaker Playback", 1248 .channels_min = 1, 1249 .channels_max = 2, 1250 .rates = RT722_STEREO_RATES, 1251 .formats = RT722_FORMATS, 1252 }, 1253 .ops = &rt722_sdca_ops, 1254 }, 1255 { 1256 .name = "rt722-sdca-aif3", 1257 .id = RT722_AIF3, 1258 .capture = { 1259 .stream_name = "DP6 DMic Capture", 1260 .channels_min = 1, 1261 .channels_max = 4, 1262 .rates = RT722_STEREO_RATES, 1263 .formats = RT722_FORMATS, 1264 }, 1265 .ops = &rt722_sdca_ops, 1266 } 1267 }; 1268 1269 int rt722_sdca_init(struct device *dev, struct regmap *regmap, struct sdw_slave *slave) 1270 { 1271 struct rt722_sdca_priv *rt722; 1272 1273 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL); 1274 if (!rt722) 1275 return -ENOMEM; 1276 1277 dev_set_drvdata(dev, rt722); 1278 rt722->slave = slave; 1279 rt722->regmap = regmap; 1280 1281 mutex_init(&rt722->calibrate_mutex); 1282 mutex_init(&rt722->disable_irq_lock); 1283 1284 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler); 1285 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler); 1286 1287 /* 1288 * Mark hw_init to false 1289 * HW init will be performed when device reports present 1290 */ 1291 rt722->hw_init = false; 1292 rt722->first_hw_init = false; 1293 rt722->fu1e_dapm_mute = true; 1294 rt722->fu0f_dapm_mute = true; 1295 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true; 1296 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] = 1297 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true; 1298 1299 return devm_snd_soc_register_component(dev, 1300 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai)); 1301 } 1302 1303 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722) 1304 { 1305 /* Set AD07 power entity floating control */ 1306 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1307 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29); 1308 /* Set AD10 power entity floating control */ 1309 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1310 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00); 1311 /* Set DMIC1/DMIC2 power entity floating control */ 1312 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1313 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a); 1314 /* Set DMIC2 IT entity floating control */ 1315 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1316 RT722_DMIC_ENT_FLOAT_CTL, 0x2626); 1317 /* Set AD10 FU entity floating control */ 1318 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1319 RT722_ADC_ENT_FLOAT_CTL, 0x1e00); 1320 /* Set DMIC2 FU entity floating control */ 1321 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1322 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515); 1323 /* Set AD10 FU channel floating control */ 1324 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1325 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304); 1326 /* Set DMIC2 FU channel floating control */ 1327 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1328 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304); 1329 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */ 1330 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1331 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000); 1332 /* Enable vf707_r12_05/vf707_r13_05 */ 1333 regmap_write(rt722->regmap, 1334 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 1335 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1336 /* Fine tune PDE2A latency */ 1337 regmap_write(rt722->regmap, 0x2f5c, 0x25); 1338 } 1339 1340 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722) 1341 { 1342 /* Set DVQ=01 */ 1343 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1344 0xc215); 1345 /* Reset dc_cal_top */ 1346 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1347 0x702c); 1348 /* W1C Trigger Calibration */ 1349 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1350 0xf02d); 1351 /* Set DAC02/ClassD power entity floating control */ 1352 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL, 1353 0x2323); 1354 /* Set EAPD high */ 1355 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL, 1356 0x0002); 1357 /* Enable vf707_r14 */ 1358 regmap_write(rt722->regmap, 1359 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 1360 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04); 1361 } 1362 1363 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722) 1364 { 1365 int loop_check, chk_cnt = 100, ret; 1366 unsigned int calib_status = 0; 1367 1368 /* Config analog bias */ 1369 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3, 1370 0xa081); 1371 /* GE related settings */ 1372 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2, 1373 0xa009); 1374 /* Button A, B, C, D bypass mode */ 1375 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4, 1376 0xcf00); 1377 /* HID1 slot enable */ 1378 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5, 1379 0x000f); 1380 /* Report ID for HID1 */ 1381 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0, 1382 0x1100); 1383 /* OSC/OOC for slot 2, 3 */ 1384 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7, 1385 0x0c12); 1386 /* Set JD de-bounce clock control */ 1387 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1, 1388 0x7002); 1389 /* Set DVQ=01 */ 1390 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1391 0xc215); 1392 /* FSM switch to calibration manual mode */ 1393 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL, 1394 0x4100); 1395 /* W1C Trigger DC calibration (HP) */ 1396 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3, 1397 0x008d); 1398 /* check HP calibration FSM status */ 1399 for (loop_check = 0; loop_check < chk_cnt; loop_check++) { 1400 usleep_range(10000, 11000); 1401 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI, 1402 RT722_DAC_DC_CALI_CTL3, &calib_status); 1403 if (ret < 0) 1404 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret); 1405 if ((calib_status & 0x0040) == 0x0) 1406 break; 1407 } 1408 1409 if (loop_check == chk_cnt) 1410 dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__); 1411 1412 /* Set ADC09 power entity floating control */ 1413 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL, 1414 0x2a12); 1415 /* Set MIC2 and LINE1 power entity floating control */ 1416 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL, 1417 0x3429); 1418 /* Set ET41h and LINE2 power entity floating control */ 1419 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL, 1420 0x4112); 1421 /* Set DAC03 and HP power entity floating control */ 1422 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL, 1423 0x4040); 1424 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1, 1425 0x4141); 1426 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1, 1427 0x0101); 1428 /* Fine tune PDE40 latency */ 1429 regmap_write(rt722->regmap, 0x2f58, 0x07); 1430 regmap_write(rt722->regmap, 0x2f03, 0x06); 1431 /* MIC VRefo */ 1432 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1433 RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200); 1434 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1435 RT722_VREFO_GAT, 0x4000, 0x4000); 1436 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */ 1437 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4, 1438 0x0010); 1439 } 1440 1441 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave) 1442 { 1443 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev); 1444 1445 rt722->disable_irq = false; 1446 1447 if (rt722->hw_init) 1448 return 0; 1449 1450 if (rt722->first_hw_init) { 1451 regcache_cache_only(rt722->regmap, false); 1452 regcache_cache_bypass(rt722->regmap, true); 1453 } else { 1454 /* 1455 * PM runtime is only enabled when a Slave reports as Attached 1456 */ 1457 1458 /* set autosuspend parameters */ 1459 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 1460 pm_runtime_use_autosuspend(&slave->dev); 1461 1462 /* update count of parent 'active' children */ 1463 pm_runtime_set_active(&slave->dev); 1464 1465 /* make sure the device does not suspend immediately */ 1466 pm_runtime_mark_last_busy(&slave->dev); 1467 1468 pm_runtime_enable(&slave->dev); 1469 } 1470 1471 pm_runtime_get_noresume(&slave->dev); 1472 1473 rt722_sdca_dmic_preset(rt722); 1474 rt722_sdca_amp_preset(rt722); 1475 rt722_sdca_jack_preset(rt722); 1476 1477 if (rt722->first_hw_init) { 1478 regcache_cache_bypass(rt722->regmap, false); 1479 regcache_mark_dirty(rt722->regmap); 1480 } else 1481 rt722->first_hw_init = true; 1482 1483 /* Mark Slave initialization complete */ 1484 rt722->hw_init = true; 1485 1486 pm_runtime_mark_last_busy(&slave->dev); 1487 pm_runtime_put_autosuspend(&slave->dev); 1488 1489 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1490 return 0; 1491 } 1492 1493 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver"); 1494 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1495 MODULE_LICENSE("GPL"); 1496