1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver 4 // 5 // Copyright(c) 2023 Realtek Semiconductor Corp. 6 // 7 // 8 9 #include <linux/cleanup.h> 10 #include <linux/bitops.h> 11 #include <linux/delay.h> 12 #include <linux/dmi.h> 13 #include <linux/firmware.h> 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/soundwire/sdw_registers.h> 21 #include <sound/core.h> 22 #include <sound/initval.h> 23 #include <sound/jack.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/tlv.h> 28 29 #include "rt722-sdca.h" 30 31 #define RT722_NID_ADDR(nid, reg) ((nid) << 20 | (reg)) 32 33 int rt722_sdca_index_write(struct rt722_sdca_priv *rt722, 34 unsigned int nid, unsigned int reg, unsigned int value) 35 { 36 struct regmap *regmap = rt722->regmap; 37 unsigned int addr = RT722_NID_ADDR(nid, reg); 38 int ret; 39 40 ret = regmap_write(regmap, addr, value); 41 if (ret < 0) 42 dev_err(&rt722->slave->dev, 43 "%s: Failed to set private value: %06x <= %04x ret=%d\n", 44 __func__, addr, value, ret); 45 46 return ret; 47 } 48 49 int rt722_sdca_index_read(struct rt722_sdca_priv *rt722, 50 unsigned int nid, unsigned int reg, unsigned int *value) 51 { 52 int ret; 53 struct regmap *regmap = rt722->regmap; 54 unsigned int addr = RT722_NID_ADDR(nid, reg); 55 56 ret = regmap_read(regmap, addr, value); 57 if (ret < 0) 58 dev_err(&rt722->slave->dev, 59 "%s: Failed to get private value: %06x => %04x ret=%d\n", 60 __func__, addr, *value, ret); 61 62 return ret; 63 } 64 65 static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722, 66 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val) 67 { 68 unsigned int tmp; 69 int ret; 70 71 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp); 72 if (ret < 0) 73 return ret; 74 75 set_mask_bits(&tmp, mask, val); 76 return rt722_sdca_index_write(rt722, nid, reg, tmp); 77 } 78 79 static int rt722_sdca_btn_type(unsigned char *buffer) 80 { 81 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) || 82 (*(buffer + 1) == 0x10)) 83 return SND_JACK_BTN_2; 84 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) || 85 (*(buffer + 1) == 0x20)) 86 return SND_JACK_BTN_3; 87 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) || 88 (*(buffer + 1) == 0x40)) 89 return SND_JACK_BTN_0; 90 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) || 91 (*(buffer + 1) == 0x80)) 92 return SND_JACK_BTN_1; 93 94 return 0; 95 } 96 97 static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722) 98 { 99 unsigned int btn_type = 0, offset, idx, val, owner; 100 int ret; 101 unsigned char buf[3]; 102 103 /* get current UMP message owner */ 104 ret = regmap_read(rt722->regmap, 105 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 106 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner); 107 if (ret < 0) 108 return 0; 109 110 /* if owner is device then there is no button event from device */ 111 if (owner == 1) 112 return 0; 113 114 /* read UMP message offset */ 115 ret = regmap_read(rt722->regmap, 116 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 117 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 118 if (ret < 0) 119 goto _end_btn_det_; 120 121 for (idx = 0; idx < sizeof(buf); idx++) { 122 ret = regmap_read(rt722->regmap, 123 RT722_BUF_ADDR_HID1 + offset + idx, &val); 124 if (ret < 0) 125 goto _end_btn_det_; 126 buf[idx] = val & 0xff; 127 } 128 129 if (buf[0] == 0x11) 130 btn_type = rt722_sdca_btn_type(&buf[1]); 131 132 _end_btn_det_: 133 /* Host is owner, so set back to device */ 134 if (owner == 0) 135 /* set owner to device */ 136 regmap_write(rt722->regmap, 137 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 138 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01); 139 140 return btn_type; 141 } 142 143 static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722) 144 { 145 unsigned int det_mode; 146 int ret; 147 148 /* get detected_mode */ 149 ret = regmap_read(rt722->regmap, 150 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 151 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 152 if (ret < 0) 153 goto io_error; 154 155 switch (det_mode) { 156 case 0x00: 157 rt722->jack_type = 0; 158 break; 159 case 0x03: 160 rt722->jack_type = SND_JACK_HEADPHONE; 161 break; 162 case 0x05: 163 rt722->jack_type = SND_JACK_HEADSET; 164 break; 165 } 166 167 /* write selected_mode */ 168 if (det_mode) { 169 ret = regmap_write(rt722->regmap, 170 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 171 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode); 172 if (ret < 0) 173 goto io_error; 174 } 175 176 dev_dbg(&rt722->slave->dev, 177 "%s, detected_mode=0x%x\n", __func__, det_mode); 178 179 return 0; 180 181 io_error: 182 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 183 return ret; 184 } 185 186 static void rt722_sdca_jack_detect_handler(struct work_struct *work) 187 { 188 struct rt722_sdca_priv *rt722 = 189 container_of(work, struct rt722_sdca_priv, jack_detect_work.work); 190 int btn_type = 0, ret; 191 192 if (!rt722->hs_jack) 193 return; 194 195 if (!rt722->component->card || !rt722->component->card->instantiated) 196 return; 197 198 /* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */ 199 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) { 200 ret = rt722_sdca_headset_detect(rt722); 201 if (ret < 0) 202 return; 203 } 204 205 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */ 206 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8) 207 btn_type = rt722_sdca_button_detect(rt722); 208 209 if (rt722->jack_type == 0) 210 btn_type = 0; 211 212 dev_dbg(&rt722->slave->dev, 213 "in %s, jack_type=%d\n", __func__, rt722->jack_type); 214 dev_dbg(&rt722->slave->dev, 215 "in %s, btn_type=0x%x\n", __func__, btn_type); 216 dev_dbg(&rt722->slave->dev, 217 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__, 218 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2); 219 220 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 221 SND_JACK_HEADSET | 222 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 223 SND_JACK_BTN_2 | SND_JACK_BTN_3); 224 225 if (btn_type) { 226 /* button released */ 227 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 228 SND_JACK_HEADSET | 229 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 230 SND_JACK_BTN_2 | SND_JACK_BTN_3); 231 232 mod_delayed_work(system_power_efficient_wq, 233 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 234 } 235 } 236 237 static void rt722_sdca_btn_check_handler(struct work_struct *work) 238 { 239 struct rt722_sdca_priv *rt722 = 240 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work); 241 int btn_type = 0, ret, idx; 242 unsigned int det_mode, offset, val; 243 unsigned char buf[3]; 244 245 ret = regmap_read(rt722->regmap, 246 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, 247 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 248 if (ret < 0) 249 goto io_error; 250 251 /* pin attached */ 252 if (det_mode) { 253 /* read UMP message offset */ 254 ret = regmap_read(rt722->regmap, 255 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 256 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 257 if (ret < 0) 258 goto io_error; 259 260 for (idx = 0; idx < sizeof(buf); idx++) { 261 ret = regmap_read(rt722->regmap, 262 RT722_BUF_ADDR_HID1 + offset + idx, &val); 263 if (ret < 0) 264 goto io_error; 265 buf[idx] = val & 0xff; 266 } 267 268 if (buf[0] == 0x11) 269 btn_type = rt722_sdca_btn_type(&buf[1]); 270 } else 271 rt722->jack_type = 0; 272 273 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type); 274 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type, 275 SND_JACK_HEADSET | 276 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 277 SND_JACK_BTN_2 | SND_JACK_BTN_3); 278 279 if (btn_type) { 280 /* button released */ 281 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type, 282 SND_JACK_HEADSET | 283 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 284 SND_JACK_BTN_2 | SND_JACK_BTN_3); 285 286 mod_delayed_work(system_power_efficient_wq, 287 &rt722->jack_btn_check_work, msecs_to_jiffies(200)); 288 } 289 290 return; 291 292 io_error: 293 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 294 } 295 296 static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722) 297 { 298 guard(mutex)(&rt722->calibrate_mutex); 299 if (rt722->hs_jack) { 300 /* set SCP_SDCA_IntMask1[0]=1 */ 301 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1, 302 SDW_SCP_SDCA_INTMASK_SDCA_0); 303 /* set SCP_SDCA_IntMask2[0]=1 */ 304 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2, 305 SDW_SCP_SDCA_INTMASK_SDCA_8); 306 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__); 307 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 308 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E); 309 /* set XU(et03h) & XU(et0Dh) to Not bypassed */ 310 regmap_write(rt722->regmap, 311 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03, 312 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 313 regmap_write(rt722->regmap, 314 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D, 315 RT722_SDCA_CTL_SELECTED_MODE, 0), 0); 316 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL1, 0x0000); 317 /* trigger GE interrupt */ 318 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 319 RT722_GE_RELATED_CTL2, 0x4000, 0x4000); 320 } 321 } 322 323 static int rt722_sdca_set_jack_detect(struct snd_soc_component *component, 324 struct snd_soc_jack *hs_jack, void *data) 325 { 326 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 327 int ret; 328 329 rt722->hs_jack = hs_jack; 330 331 ret = pm_runtime_resume_and_get(component->dev); 332 if (ret < 0) { 333 if (ret != -EACCES) { 334 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); 335 return ret; 336 } 337 /* pm_runtime not enabled yet */ 338 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); 339 return 0; 340 } 341 342 rt722_sdca_jack_init(rt722); 343 344 pm_runtime_put_autosuspend(component->dev); 345 346 return 0; 347 } 348 349 static int rt722_cae_load(struct rt722_sdca_priv *rt722) 350 { 351 struct device *dev = &rt722->slave->dev; 352 static const char func_tag[] = "FUNC"; 353 static const char xu_tag[] = "XU"; 354 const char *dmi_vendor, *dmi_product, *dmi_sku; 355 unsigned int cae_st_spk, cae_st_hp, cae_st_mic; 356 unsigned int func, value; 357 unsigned int combined_val; 358 unsigned int addr, size; 359 unsigned int fw_offset; 360 unsigned char mbq_high_val = 0; 361 unsigned char *param_data; 362 unsigned char *fw_data; 363 char tag[5]; 364 char *space; 365 int v_len, p_len, s_len; 366 int ret = 0, i; 367 int retry = 50; 368 369 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR); 370 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME); 371 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU); 372 373 if (!dmi_vendor || !dmi_product || !dmi_sku) { 374 dev_warn(dev, "%s: Incomplete DMI info\n", __func__); 375 return -EINVAL; 376 } 377 space = strchr(dmi_vendor, ' '); 378 v_len = space ? space - dmi_vendor : strlen(dmi_vendor); 379 380 space = strchr(dmi_product, ' '); 381 p_len = space ? space - dmi_product : strlen(dmi_product); 382 383 space = strchr(dmi_sku, ' '); 384 s_len = space ? space - dmi_sku : strlen(dmi_sku); 385 386 char *cae_filename __free(kfree) = 387 kasprintf(GFP_KERNEL, 388 "realtek/rt722/rt722_RAE_%.*s_%.*s_%.*s.dat", 389 v_len, dmi_vendor, 390 p_len, dmi_product, 391 s_len, dmi_sku); 392 if (!cae_filename) 393 return -ENOMEM; 394 dev_dbg(dev, "%s: try to load CAE file %s\n", __func__, cae_filename); 395 396 regmap_write(rt722->regmap, RT722_SPK_CAE_PARAM1, 0x5f); 397 regmap_write(rt722->regmap, RT722_HP_CAE_PARAM39, 0x5f); 398 regmap_write(rt722->regmap, RT722_MIC_CAE_PARAM39, 0x5f); 399 usleep_range(50000, 60000); 400 401 const struct firmware *cae_fw __free(firmware) = NULL; 402 request_firmware(&cae_fw, cae_filename, dev); 403 if (!cae_fw) { 404 dev_err(dev, "%s: Failed to load CAE firmware\n", __func__); 405 return -ENOENT; 406 } 407 408 regmap_read(rt722->regmap, RT722_SPK_CAE_PARAM38, &cae_st_spk); 409 regmap_read(rt722->regmap, RT722_HP_CAE_PARAM68, &cae_st_hp); 410 regmap_read(rt722->regmap, RT722_MIC_CAE_PARAM99, &cae_st_mic); 411 cae_st_spk &= 0x80; 412 cae_st_hp &= 0x80; 413 cae_st_mic &= 0x80; 414 415 dev_dbg(dev, "%s(%d) spk_crc:%x, hp_crc:%x, mic_crc:%x\n", 416 __func__, __LINE__, cae_st_spk, cae_st_hp, cae_st_mic); 417 418 if (cae_st_spk) 419 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_EQ_CAE, 420 RT722_EQ_CTRL_SPK, 0x0008, 0x0008); 421 else if (cae_st_hp) 422 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_EQ_CAE, 423 RT722_EQ_CTRL_HP, 0x0008, 0x0008); 424 else if (cae_st_mic) 425 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_EQ_CAE, 426 RT722_EQ_CTRL_DMIC, 0x0008, 0x0008); 427 428 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 429 RT722_MISC_CTRL1, 0x8000, 0x8000); 430 431 regmap_update_bits(rt722->regmap, RT722_SPK_CAE_PARAM34, 0x1, 0x0); 432 regmap_update_bits(rt722->regmap, RT722_HP_CAE_PARAM64, 0x1, 0x0); 433 regmap_update_bits(rt722->regmap, RT722_MIC_CAE_PARAM95, 0x1, 0x0); 434 435 while (--retry) { 436 regmap_read(rt722->regmap, RT722_SPK_CAE_PARAM35, &cae_st_spk); 437 regmap_read(rt722->regmap, RT722_HP_CAE_PARAM65, &cae_st_hp); 438 regmap_read(rt722->regmap, RT722_MIC_CAE_PARAM96, &cae_st_mic); 439 dev_dbg(dev, "%s(%d) cae_st_spk:%x, cae_st_hp:%x, cae_st_mic:%x\n", 440 __func__, __LINE__, cae_st_spk, cae_st_hp, cae_st_mic); 441 if ((cae_st_spk & 0x40) && (cae_st_hp & 0x40) && (cae_st_mic & 0x40)) 442 break; 443 usleep_range(1000, 1100); 444 } 445 446 if (!retry && !((cae_st_spk & 0x40) && (cae_st_hp & 0x40) 447 && (cae_st_mic & 0x40))) { 448 dev_err(dev, "%s: CAE is not ready to be loaded.\n", __func__); 449 ret = -ETIMEDOUT; 450 goto out_release; 451 } 452 453 dev_dbg(dev, "%s, cae_fw size=0x%zx, start\n", __func__, cae_fw->size); 454 455 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 456 RT722_EQ_CTRL_AMIC, 0x8000); 457 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 458 RT722_EQ_CTRL_DMIC, 0x8004); 459 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 460 RT722_EQ_CTRL_HP, 0x8074); 461 rt722_sdca_index_write(rt722, RT722_VENDOR_EQ_CAE, 462 RT722_EQ_CTRL_SPK, 0xa074); 463 464 regcache_cache_bypass(rt722->regmap, true); 465 for (fw_offset = 0; fw_offset < cae_fw->size;) { 466 467 if (fw_offset + 12 > cae_fw->size) { 468 dev_err(dev, "%s: Unexpected end of firmware\n", __func__); 469 ret = -EINVAL; 470 goto verify_abort; 471 } 472 473 fw_data = (unsigned char *)&cae_fw->data[fw_offset]; 474 memcpy(tag, fw_data, 4); 475 tag[4] = '\0'; 476 477 if (strcmp(tag, xu_tag) == 0) { 478 dev_dbg(dev, "%s: This is a XU tag", __func__); 479 memcpy(&addr, (fw_data + 4), 4); 480 memcpy(&size, (fw_data + 8), 4); 481 482 if (size == 0 || size > cae_fw->size - fw_offset - 12) { 483 dev_err(dev, "%s: Invalid payload size: %u\n", __func__, size); 484 ret = -EINVAL; 485 goto verify_abort; 486 } 487 488 param_data = (unsigned char *)(fw_data + 12); 489 490 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size); 491 492 if ((addr <= 0x05302300 && addr >= 0x05300000) || 493 (addr <= 0x020020b4 && addr >= 0x020000b1)) { 494 if (addr & BIT(13)) { 495 mbq_high_val = param_data[0]; 496 dev_dbg(dev, "MBQ: High Byte 0x%02x\n", mbq_high_val); 497 fw_offset += (size + 12); 498 499 continue; 500 } else { 501 regcache_cache_bypass(rt722->regmap, false); 502 combined_val = (mbq_high_val << 8) | param_data[0]; 503 if (addr == 0x20000b1 || addr == 0x20000b4) 504 combined_val |= (0x2 << 8); 505 ret = regmap_write(rt722->regmap, addr, combined_val); 506 if (ret) { 507 dev_err(dev, 508 "MBQ fail: addr=0x%x ret=%d\n", addr, ret); 509 regcache_cache_bypass(rt722->regmap, true); 510 goto verify_abort; 511 } 512 513 dev_dbg(dev, "MBQ-reg=0x%x, value=0x%x\n", 514 addr, combined_val); 515 516 fw_offset += (size + 12); 517 regcache_cache_bypass(rt722->regmap, true); 518 continue; 519 } 520 } 521 522 for (i = 0; i < size; i++) { 523 ret = regmap_write(rt722->regmap, addr + i, param_data[i]); 524 if (ret) { 525 dev_err(dev, 526 "CAE write fail: addr=0x%x ret=%d\n", 527 addr + i, ret); 528 goto verify_abort; 529 } 530 } 531 fw_offset += (size + 12); 532 } else if (strcmp(tag, func_tag) == 0) { 533 dev_dbg(dev, "%s: This is a FUNC tag", __func__); 534 535 memcpy(&func, (fw_data + 4), 4); 536 memcpy(&value, (fw_data + 8), 4); 537 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", 538 __func__, func, value); 539 540 if (func == 1) 541 msleep(value); 542 543 fw_offset += 12; 544 } else { 545 dev_err(dev, "%s: No XU/FUNC tag at fw_offset=0x%x\n", 546 __func__, fw_offset); 547 ret = -EINVAL; 548 goto verify_abort; 549 } 550 } 551 552 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 553 RT722_MISC_CTRL1, 0x8000, 0x0000); 554 regcache_cache_bypass(rt722->regmap, false); 555 rt722->cae_update_done = 1; 556 dev_dbg(dev, "%s: CAE FW update done.\n", __func__); 557 return 0; 558 559 verify_abort: 560 regcache_cache_bypass(rt722->regmap, false); 561 if (!ret) 562 ret = -EIO; 563 out_release: 564 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 565 RT722_MISC_CTRL1, 0x8000, 0x0000); 566 dev_err(dev, "%s: CAE FW update aborted (ret=%d).\n", __func__, ret); 567 return ret; 568 } 569 570 static int rt722_cae_update_put(struct snd_kcontrol *kcontrol, 571 struct snd_ctl_elem_value *ucontrol) 572 { 573 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 574 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 575 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 576 int ret, changed = 0; 577 578 if (!rt722->hw_init) 579 return 0; 580 581 ret = pm_runtime_resume_and_get(component->dev); 582 if (ret < 0 && ret != -EACCES) 583 return ret; 584 585 if (ucontrol->value.integer.value[0]) { 586 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 587 ret = rt722_cae_load(rt722); 588 if (ret) { 589 dev_err(component->dev, "CAE load failed: %d\n", ret); 590 goto out; 591 } else 592 changed = 1; 593 } 594 } else { 595 if (rt722->cae_update_done) { 596 rt722->cae_update_done = 0; 597 changed = 1; 598 } 599 } 600 601 out: 602 pm_runtime_mark_last_busy(component->dev); 603 pm_runtime_put_autosuspend(component->dev); 604 605 return ret < 0 ? ret : changed; 606 } 607 608 static int rt722_cae_update_get(struct snd_kcontrol *kcontrol, 609 struct snd_ctl_elem_value *ucontrol) 610 { 611 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 612 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 613 614 ucontrol->value.integer.value[0] = rt722->cae_update_done; 615 616 return 0; 617 } 618 619 620 /* For SDCA control DAC/ADC Gain */ 621 static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol, 622 struct snd_ctl_elem_value *ucontrol) 623 { 624 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 625 struct soc_mixer_control *mc = 626 (struct soc_mixer_control *)kcontrol->private_value; 627 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 628 unsigned int read_l, read_r, gain_l_val, gain_r_val; 629 unsigned int adc_vol_flag = 0, changed = 0; 630 unsigned int lvalue, rvalue; 631 const unsigned int interval_offset = 0xc0; 632 const unsigned int tendB = 0xa00; 633 634 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 635 strstr(ucontrol->id.name, "FU0F Capture Volume")) 636 adc_vol_flag = 1; 637 638 regmap_read(rt722->regmap, mc->reg, &lvalue); 639 regmap_read(rt722->regmap, mc->rreg, &rvalue); 640 641 /* L Channel */ 642 gain_l_val = ucontrol->value.integer.value[0]; 643 if (gain_l_val > mc->max) 644 gain_l_val = mc->max; 645 646 if (mc->shift == 8) /* boost gain */ 647 gain_l_val = gain_l_val * tendB; 648 else { 649 /* ADC/DAC gain */ 650 if (adc_vol_flag) 651 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset); 652 else 653 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 654 gain_l_val &= 0xffff; 655 } 656 657 /* R Channel */ 658 gain_r_val = ucontrol->value.integer.value[1]; 659 if (gain_r_val > mc->max) 660 gain_r_val = mc->max; 661 662 if (mc->shift == 8) /* boost gain */ 663 gain_r_val = gain_r_val * tendB; 664 else { 665 /* ADC/DAC gain */ 666 if (adc_vol_flag) 667 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset); 668 else 669 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 670 gain_r_val &= 0xffff; 671 } 672 673 if (lvalue != gain_l_val || rvalue != gain_r_val) 674 changed = 1; 675 else 676 return 0; 677 678 /* Lch*/ 679 regmap_write(rt722->regmap, mc->reg, gain_l_val); 680 681 /* Rch */ 682 regmap_write(rt722->regmap, mc->rreg, gain_r_val); 683 684 regmap_read(rt722->regmap, mc->reg, &read_l); 685 regmap_read(rt722->regmap, mc->rreg, &read_r); 686 if (read_r == gain_r_val && read_l == gain_l_val) 687 return changed; 688 689 return -EIO; 690 } 691 692 static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol, 693 struct snd_ctl_elem_value *ucontrol) 694 { 695 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 696 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 697 struct soc_mixer_control *mc = 698 (struct soc_mixer_control *)kcontrol->private_value; 699 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 700 unsigned int adc_vol_flag = 0; 701 const unsigned int interval_offset = 0xc0; 702 const unsigned int tendB = 0xa00; 703 704 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 705 strstr(ucontrol->id.name, "FU0F Capture Volume")) 706 adc_vol_flag = 1; 707 708 regmap_read(rt722->regmap, mc->reg, &read_l); 709 regmap_read(rt722->regmap, mc->rreg, &read_r); 710 711 if (mc->shift == 8) /* boost gain */ 712 ctl_l = read_l / tendB; 713 else { 714 if (adc_vol_flag) 715 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset); 716 else 717 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 718 } 719 720 if (read_l != read_r) { 721 if (mc->shift == 8) /* boost gain */ 722 ctl_r = read_r / tendB; 723 else { /* ADC/DAC gain */ 724 if (adc_vol_flag) 725 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset); 726 else 727 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 728 } 729 } else { 730 ctl_r = ctl_l; 731 } 732 733 ucontrol->value.integer.value[0] = ctl_l; 734 ucontrol->value.integer.value[1] = ctl_r; 735 736 return 0; 737 } 738 739 static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722) 740 { 741 int err, i; 742 unsigned int ch_mute; 743 744 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) { 745 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i]; 746 err = regmap_write(rt722->regmap, 747 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 748 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 749 if (err < 0) 750 return err; 751 } 752 753 return 0; 754 } 755 756 static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol, 757 struct snd_ctl_elem_value *ucontrol) 758 { 759 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 760 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 761 struct rt722_sdca_dmic_kctrl_priv *p = 762 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 763 unsigned int i; 764 765 for (i = 0; i < p->count; i++) 766 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i]; 767 768 return 0; 769 } 770 771 static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol, 772 struct snd_ctl_elem_value *ucontrol) 773 { 774 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 775 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 776 struct rt722_sdca_dmic_kctrl_priv *p = 777 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 778 int err, changed = 0, i; 779 780 for (i = 0; i < p->count; i++) { 781 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i]) 782 changed = 1; 783 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i]; 784 } 785 786 err = rt722_sdca_set_fu1e_capture_ctl(rt722); 787 if (err < 0) 788 return err; 789 790 return changed; 791 } 792 793 static int rt722_sdca_set_fu06_playback_ctl(struct rt722_sdca_priv *rt722) 794 { 795 int err; 796 unsigned int ch_l, ch_r; 797 798 ch_l = (rt722->fu06_dapm_mute || rt722->fu06_mixer_l_mute) ? 0x01 : 0x00; 799 ch_r = (rt722->fu06_dapm_mute || rt722->fu06_mixer_r_mute) ? 0x01 : 0x00; 800 801 err = regmap_write(rt722->regmap, 802 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 803 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l); 804 if (err < 0) 805 return err; 806 807 err = regmap_write(rt722->regmap, 808 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 809 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r); 810 if (err < 0) 811 return err; 812 813 return 0; 814 } 815 816 static int rt722_sdca_fu06_playback_get(struct snd_kcontrol *kcontrol, 817 struct snd_ctl_elem_value *ucontrol) 818 { 819 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 820 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 821 822 ucontrol->value.integer.value[0] = !rt722->fu06_mixer_l_mute; 823 ucontrol->value.integer.value[1] = !rt722->fu06_mixer_r_mute; 824 return 0; 825 } 826 827 static int rt722_sdca_fu06_playback_put(struct snd_kcontrol *kcontrol, 828 struct snd_ctl_elem_value *ucontrol) 829 { 830 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 831 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 832 int err, changed = 0; 833 834 if (rt722->fu06_mixer_l_mute != !ucontrol->value.integer.value[0] || 835 rt722->fu06_mixer_r_mute != !ucontrol->value.integer.value[1]) 836 changed = 1; 837 838 rt722->fu06_mixer_l_mute = !ucontrol->value.integer.value[0]; 839 rt722->fu06_mixer_r_mute = !ucontrol->value.integer.value[1]; 840 841 err = rt722_sdca_set_fu06_playback_ctl(rt722); 842 if (err < 0) 843 return err; 844 845 return changed; 846 } 847 848 static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722) 849 { 850 int err; 851 unsigned int ch_l, ch_r; 852 853 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00; 854 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00; 855 856 err = regmap_write(rt722->regmap, 857 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 858 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l); 859 if (err < 0) 860 return err; 861 862 err = regmap_write(rt722->regmap, 863 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 864 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r); 865 if (err < 0) 866 return err; 867 868 return 0; 869 } 870 871 static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol, 872 struct snd_ctl_elem_value *ucontrol) 873 { 874 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 875 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 876 877 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute; 878 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute; 879 return 0; 880 } 881 882 static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol, 883 struct snd_ctl_elem_value *ucontrol) 884 { 885 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 886 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 887 int err, changed = 0; 888 889 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] || 890 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1]) 891 changed = 1; 892 893 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0]; 894 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1]; 895 err = rt722_sdca_set_fu0f_capture_ctl(rt722); 896 if (err < 0) 897 return err; 898 899 return changed; 900 } 901 902 static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol, 903 struct snd_ctl_elem_info *uinfo) 904 { 905 struct rt722_sdca_dmic_kctrl_priv *p = 906 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 907 908 if (p->max == 1) 909 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 910 else 911 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 912 uinfo->count = p->count; 913 uinfo->value.integer.min = 0; 914 uinfo->value.integer.max = p->max; 915 return 0; 916 } 917 918 static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol, 919 struct snd_ctl_elem_value *ucontrol) 920 { 921 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 922 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 923 struct rt722_sdca_dmic_kctrl_priv *p = 924 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 925 unsigned int boost_step = 0x0a00; 926 unsigned int vol_max = 0x1e00; 927 unsigned int regvalue, ctl, i; 928 unsigned int adc_vol_flag = 0; 929 const unsigned int interval_offset = 0xc0; 930 931 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 932 adc_vol_flag = 1; 933 934 /* check all channels */ 935 for (i = 0; i < p->count; i++) { 936 regmap_read(rt722->regmap, p->reg_base + i, ®value); 937 938 if (!adc_vol_flag) /* boost gain */ 939 ctl = regvalue / boost_step; 940 else /* ADC gain */ 941 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset); 942 943 ucontrol->value.integer.value[i] = ctl; 944 } 945 946 return 0; 947 } 948 949 static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol, 950 struct snd_ctl_elem_value *ucontrol) 951 { 952 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 953 struct rt722_sdca_dmic_kctrl_priv *p = 954 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value; 955 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 956 unsigned int boost_step = 0x0a00; 957 unsigned int vol_max = 0x1e00; 958 unsigned int gain_val[4]; 959 unsigned int i, adc_vol_flag = 0, changed = 0; 960 unsigned int regvalue[4]; 961 const unsigned int interval_offset = 0xc0; 962 int err; 963 964 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 965 adc_vol_flag = 1; 966 967 /* check all channels */ 968 for (i = 0; i < p->count; i++) { 969 regmap_read(rt722->regmap, p->reg_base + i, ®value[i]); 970 971 gain_val[i] = ucontrol->value.integer.value[i]; 972 if (gain_val[i] > p->max) 973 gain_val[i] = p->max; 974 975 if (!adc_vol_flag) /* boost gain */ 976 gain_val[i] = gain_val[i] * boost_step; 977 else { /* ADC gain */ 978 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset); 979 gain_val[i] &= 0xffff; 980 } 981 982 if (regvalue[i] != gain_val[i]) 983 changed = 1; 984 } 985 986 if (!changed) 987 return 0; 988 989 for (i = 0; i < p->count; i++) { 990 err = regmap_write(rt722->regmap, p->reg_base + i, gain_val[i]); 991 if (err < 0) 992 dev_err(&rt722->slave->dev, "%s: %#08x can't be set\n", 993 __func__, p->reg_base + i); 994 } 995 996 return changed; 997 } 998 999 #define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \ 1000 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \ 1001 {.reg_base = xreg_base, .count = xcount, .max = xmax, \ 1002 .invert = xinvert}) 1003 1004 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \ 1005 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 1006 .info = rt722_sdca_fu_info, \ 1007 .get = rt722_sdca_fu1e_capture_get, \ 1008 .put = rt722_sdca_fu1e_capture_put, \ 1009 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)} 1010 1011 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\ 1012 xhandler_put, xcount, xmax, tlv_array) \ 1013 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 1014 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 1015 SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 1016 .tlv.p = (tlv_array), \ 1017 .info = rt722_sdca_fu_info, \ 1018 .get = xhandler_get, .put = xhandler_put, \ 1019 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) } 1020 1021 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 1022 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0); 1023 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0); 1024 1025 static const struct snd_kcontrol_new rt722_sdca_controls[] = { 1026 /* Headphone playback settings */ 1027 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume", 1028 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1029 RT722_SDCA_CTL_FU_VOLUME, CH_L), 1030 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1031 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 1032 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 1033 /* Headset mic capture settings */ 1034 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0, 1035 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put), 1036 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume", 1037 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 1038 RT722_SDCA_CTL_FU_VOLUME, CH_L), 1039 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 1040 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0, 1041 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv), 1042 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume", 1043 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 1044 RT722_SDCA_CTL_FU_CH_GAIN, CH_L), 1045 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 1046 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0, 1047 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv), 1048 /* AMP playback settings */ 1049 SOC_DOUBLE_EXT("FU06 Playback Switch", SND_SOC_NOPM, 0, 1, 1, 0, 1050 rt722_sdca_fu06_playback_get, rt722_sdca_fu06_playback_put), 1051 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume", 1052 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 1053 RT722_SDCA_CTL_FU_VOLUME, CH_L), 1054 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 1055 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 1056 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv), 1057 /* DMIC capture settings */ 1058 RT722_SDCA_FU_CTRL("FU1E Capture Switch", 1059 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 1060 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4), 1061 RT722_SDCA_EXT_TLV("FU1E Capture Volume", 1062 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 1063 RT722_SDCA_CTL_FU_VOLUME, CH_01), 1064 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 1065 4, 0x3f, mic_vol_tlv), 1066 RT722_SDCA_EXT_TLV("FU15 Boost Volume", 1067 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, 1068 RT722_SDCA_CTL_FU_CH_GAIN, CH_01), 1069 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put, 1070 4, 3, boost_vol_tlv), 1071 /* CAE firmware update */ 1072 SOC_SINGLE_EXT("CAE Update", SND_SOC_NOPM, 0, 1, 0, 1073 rt722_cae_update_get, rt722_cae_update_put), 1074 }; 1075 1076 static const char * const adc22_mux_text[] = { 1077 "MIC2", 1078 "LINE1", 1079 "LINE2", 1080 }; 1081 1082 static const char * const adc07_10_mux_text[] = { 1083 "DMIC1", 1084 "DMIC2", 1085 }; 1086 1087 static SOC_ENUM_SINGLE_DECL(rt722_adc22_enum, 1088 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 1089 12, adc22_mux_text); 1090 1091 static SOC_ENUM_SINGLE_DECL(rt722_adc24_enum, 1092 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 1093 4, adc07_10_mux_text); 1094 1095 static SOC_ENUM_SINGLE_DECL(rt722_adc25_enum, 1096 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0), 1097 0, adc07_10_mux_text); 1098 1099 static const struct snd_kcontrol_new rt722_sdca_adc22_mux = 1100 SOC_DAPM_ENUM("ADC 22 Mux", rt722_adc22_enum); 1101 1102 static const struct snd_kcontrol_new rt722_sdca_adc24_mux = 1103 SOC_DAPM_ENUM("ADC 24 Mux", rt722_adc24_enum); 1104 1105 static const struct snd_kcontrol_new rt722_sdca_adc25_mux = 1106 SOC_DAPM_ENUM("ADC 25 Mux", rt722_adc25_enum); 1107 1108 static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w, 1109 struct snd_kcontrol *kcontrol, int event) 1110 { 1111 struct snd_soc_component *component = 1112 snd_soc_dapm_to_component(w->dapm); 1113 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1114 unsigned char unmute = 0x0, mute = 0x1; 1115 1116 switch (event) { 1117 case SND_SOC_DAPM_POST_PMU: 1118 regmap_write(rt722->regmap, 1119 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1120 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute); 1121 regmap_write(rt722->regmap, 1122 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1123 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute); 1124 break; 1125 case SND_SOC_DAPM_PRE_PMD: 1126 regmap_write(rt722->regmap, 1127 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1128 RT722_SDCA_CTL_FU_MUTE, CH_L), mute); 1129 regmap_write(rt722->regmap, 1130 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 1131 RT722_SDCA_CTL_FU_MUTE, CH_R), mute); 1132 break; 1133 } 1134 return 0; 1135 } 1136 1137 static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w, 1138 struct snd_kcontrol *kcontrol, int event) 1139 { 1140 struct snd_soc_component *component = 1141 snd_soc_dapm_to_component(w->dapm); 1142 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1143 1144 switch (event) { 1145 case SND_SOC_DAPM_POST_PMU: 1146 rt722->fu06_dapm_mute = false; 1147 break; 1148 case SND_SOC_DAPM_PRE_PMD: 1149 rt722->fu06_dapm_mute = true; 1150 break; 1151 } 1152 1153 return rt722_sdca_set_fu06_playback_ctl(rt722); 1154 } 1155 1156 static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w, 1157 struct snd_kcontrol *kcontrol, int event) 1158 { 1159 struct snd_soc_component *component = 1160 snd_soc_dapm_to_component(w->dapm); 1161 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1162 1163 switch (event) { 1164 case SND_SOC_DAPM_POST_PMU: 1165 rt722->fu1e_dapm_mute = false; 1166 rt722_sdca_set_fu1e_capture_ctl(rt722); 1167 usleep_range(150000, 160000); 1168 break; 1169 case SND_SOC_DAPM_PRE_PMD: 1170 rt722->fu1e_dapm_mute = true; 1171 rt722_sdca_set_fu1e_capture_ctl(rt722); 1172 break; 1173 } 1174 return 0; 1175 } 1176 1177 static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w, 1178 struct snd_kcontrol *kcontrol, int event) 1179 { 1180 struct snd_soc_component *component = 1181 snd_soc_dapm_to_component(w->dapm); 1182 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1183 1184 switch (event) { 1185 case SND_SOC_DAPM_POST_PMU: 1186 rt722->fu0f_dapm_mute = false; 1187 rt722_sdca_set_fu0f_capture_ctl(rt722); 1188 break; 1189 case SND_SOC_DAPM_PRE_PMD: 1190 rt722->fu0f_dapm_mute = true; 1191 rt722_sdca_set_fu0f_capture_ctl(rt722); 1192 break; 1193 } 1194 return 0; 1195 } 1196 1197 static void rt722_pde_transition_delay(struct rt722_sdca_priv *rt722, unsigned char func, 1198 unsigned char entity, unsigned char ps) 1199 { 1200 unsigned int delay = 1000, val; 1201 1202 pm_runtime_mark_last_busy(&rt722->slave->dev); 1203 1204 /* waiting for Actual PDE becomes to PS0/PS3 */ 1205 while (delay) { 1206 regmap_read(rt722->regmap, 1207 SDW_SDCA_CTL(func, entity, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 1208 if (val == ps) 1209 break; 1210 1211 usleep_range(1000, 1500); 1212 delay--; 1213 } 1214 if (!delay) { 1215 dev_warn(&rt722->slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 1216 } 1217 } 1218 1219 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w, 1220 struct snd_kcontrol *kcontrol, int event) 1221 { 1222 struct snd_soc_component *component = 1223 snd_soc_dapm_to_component(w->dapm); 1224 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1225 unsigned char ps0 = 0x0, ps3 = 0x3; 1226 1227 switch (event) { 1228 case SND_SOC_DAPM_POST_PMU: 1229 regmap_write(rt722->regmap, 1230 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 1231 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1232 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps0); 1233 break; 1234 case SND_SOC_DAPM_PRE_PMD: 1235 regmap_write(rt722->regmap, 1236 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 1237 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1238 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps3); 1239 break; 1240 } 1241 return 0; 1242 } 1243 1244 static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w, 1245 struct snd_kcontrol *kcontrol, int event) 1246 { 1247 struct snd_soc_component *component = 1248 snd_soc_dapm_to_component(w->dapm); 1249 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1250 unsigned char ps0 = 0x0, ps3 = 0x3; 1251 1252 switch (event) { 1253 case SND_SOC_DAPM_POST_PMU: 1254 regmap_write(rt722->regmap, 1255 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 1256 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1257 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps0); 1258 break; 1259 case SND_SOC_DAPM_PRE_PMD: 1260 regmap_write(rt722->regmap, 1261 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 1262 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1263 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps3); 1264 break; 1265 } 1266 return 0; 1267 } 1268 1269 static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w, 1270 struct snd_kcontrol *kcontrol, int event) 1271 { 1272 struct snd_soc_component *component = 1273 snd_soc_dapm_to_component(w->dapm); 1274 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1275 unsigned char ps0 = 0x0, ps3 = 0x3; 1276 1277 switch (event) { 1278 case SND_SOC_DAPM_POST_PMU: 1279 regmap_write(rt722->regmap, 1280 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1281 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1282 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps0); 1283 break; 1284 case SND_SOC_DAPM_PRE_PMD: 1285 regmap_write(rt722->regmap, 1286 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 1287 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1288 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps3); 1289 break; 1290 } 1291 return 0; 1292 } 1293 1294 static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w, 1295 struct snd_kcontrol *kcontrol, int event) 1296 { 1297 struct snd_soc_component *component = 1298 snd_soc_dapm_to_component(w->dapm); 1299 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1300 unsigned char ps0 = 0x0, ps3 = 0x3; 1301 1302 switch (event) { 1303 case SND_SOC_DAPM_POST_PMU: 1304 regmap_write(rt722->regmap, 1305 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1306 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1307 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps0); 1308 break; 1309 case SND_SOC_DAPM_PRE_PMD: 1310 regmap_write(rt722->regmap, 1311 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 1312 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1313 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps3); 1314 break; 1315 } 1316 return 0; 1317 } 1318 1319 static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = { 1320 SND_SOC_DAPM_OUTPUT("HP"), 1321 SND_SOC_DAPM_OUTPUT("SPK"), 1322 SND_SOC_DAPM_INPUT("MIC2"), 1323 SND_SOC_DAPM_INPUT("LINE1"), 1324 SND_SOC_DAPM_INPUT("LINE2"), 1325 SND_SOC_DAPM_INPUT("DMIC1_2"), 1326 SND_SOC_DAPM_INPUT("DMIC3_4"), 1327 1328 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, 1329 rt722_sdca_pde23_event, 1330 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1331 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0, 1332 rt722_sdca_pde47_event, 1333 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1334 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1335 rt722_sdca_pde11_event, 1336 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1337 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0, 1338 rt722_sdca_pde12_event, 1339 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1340 1341 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0, 1342 rt722_sdca_fu21_event, 1343 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1344 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0, 1345 rt722_sdca_fu42_event, 1346 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1347 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0, 1348 rt722_sdca_fu36_event, 1349 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1350 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0, 1351 rt722_sdca_fu113_event, 1352 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1353 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0, 1354 &rt722_sdca_adc22_mux), 1355 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0, 1356 &rt722_sdca_adc24_mux), 1357 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0, 1358 &rt722_sdca_adc25_mux), 1359 1360 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0), 1361 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0), 1362 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0), 1363 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0), 1364 }; 1365 1366 static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = { 1367 {"FU 42", NULL, "DP1RX"}, 1368 {"FU 21", NULL, "DP3RX"}, 1369 1370 {"ADC 22 Mux", "MIC2", "MIC2"}, 1371 {"ADC 22 Mux", "LINE1", "LINE1"}, 1372 {"ADC 22 Mux", "LINE2", "LINE2"}, 1373 {"ADC 24 Mux", "DMIC1", "DMIC1_2"}, 1374 {"ADC 24 Mux", "DMIC2", "DMIC3_4"}, 1375 {"ADC 25 Mux", "DMIC1", "DMIC1_2"}, 1376 {"ADC 25 Mux", "DMIC2", "DMIC3_4"}, 1377 {"FU 36", NULL, "PDE 12"}, 1378 {"FU 36", NULL, "ADC 22 Mux"}, 1379 {"FU 113", NULL, "PDE 11"}, 1380 {"FU 113", NULL, "ADC 24 Mux"}, 1381 {"FU 113", NULL, "ADC 25 Mux"}, 1382 {"DP2TX", NULL, "FU 36"}, 1383 {"DP6TX", NULL, "FU 113"}, 1384 1385 {"HP", NULL, "PDE 47"}, 1386 {"HP", NULL, "FU 42"}, 1387 {"SPK", NULL, "PDE 23"}, 1388 {"SPK", NULL, "FU 21"}, 1389 }; 1390 1391 static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev) 1392 { 1393 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src); 1394 1395 return 0; 1396 } 1397 1398 static int rt722_sdca_probe(struct snd_soc_component *component) 1399 { 1400 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1401 int ret; 1402 1403 rt722_sdca_parse_dt(rt722, &rt722->slave->dev); 1404 rt722->component = component; 1405 1406 ret = pm_runtime_resume(component->dev); 1407 if (ret < 0 && ret != -EACCES) 1408 return ret; 1409 1410 return 0; 1411 } 1412 1413 static const struct snd_soc_component_driver soc_sdca_dev_rt722 = { 1414 .probe = rt722_sdca_probe, 1415 .controls = rt722_sdca_controls, 1416 .num_controls = ARRAY_SIZE(rt722_sdca_controls), 1417 .dapm_widgets = rt722_sdca_dapm_widgets, 1418 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets), 1419 .dapm_routes = rt722_sdca_audio_map, 1420 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map), 1421 .set_jack = rt722_sdca_set_jack_detect, 1422 .endianness = 1, 1423 }; 1424 1425 static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1426 int direction) 1427 { 1428 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1429 1430 return 0; 1431 } 1432 1433 static void rt722_sdca_shutdown(struct snd_pcm_substream *substream, 1434 struct snd_soc_dai *dai) 1435 { 1436 snd_soc_dai_set_dma_data(dai, substream, NULL); 1437 } 1438 1439 static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream, 1440 struct snd_pcm_hw_params *params, 1441 struct snd_soc_dai *dai) 1442 { 1443 struct snd_soc_component *component = dai->component; 1444 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1445 struct sdw_stream_config stream_config; 1446 struct sdw_port_config port_config; 1447 enum sdw_data_direction direction; 1448 struct sdw_stream_runtime *sdw_stream; 1449 int retval, port, num_channels; 1450 unsigned int sampling_rate; 1451 1452 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1453 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1454 1455 if (!sdw_stream) 1456 return -EINVAL; 1457 1458 if (!rt722->slave) 1459 return -EINVAL; 1460 1461 /* 1462 * RT722_AIF1 with port = 1 for headphone playback 1463 * RT722_AIF1 with port = 2 for headset-mic capture 1464 * RT722_AIF2 with port = 3 for speaker playback 1465 * RT722_AIF3 with port = 6 for digital-mic capture 1466 */ 1467 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1468 direction = SDW_DATA_DIR_RX; 1469 if (dai->id == RT722_AIF1) 1470 port = 1; 1471 else if (dai->id == RT722_AIF2) 1472 port = 3; 1473 else 1474 return -EINVAL; 1475 } else { 1476 direction = SDW_DATA_DIR_TX; 1477 if (dai->id == RT722_AIF1) 1478 port = 2; 1479 else if (dai->id == RT722_AIF3) 1480 port = 6; 1481 else 1482 return -EINVAL; 1483 } 1484 stream_config.frame_rate = params_rate(params); 1485 stream_config.ch_count = params_channels(params); 1486 stream_config.bps = snd_pcm_format_width(params_format(params)); 1487 stream_config.direction = direction; 1488 1489 num_channels = params_channels(params); 1490 port_config.ch_mask = GENMASK(num_channels - 1, 0); 1491 port_config.num = port; 1492 1493 retval = sdw_stream_add_slave(rt722->slave, &stream_config, 1494 &port_config, 1, sdw_stream); 1495 if (retval) { 1496 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 1497 return retval; 1498 } 1499 1500 if (params_channels(params) > 16) { 1501 dev_err(component->dev, "%s: Unsupported channels %d\n", 1502 __func__, params_channels(params)); 1503 return -EINVAL; 1504 } 1505 1506 /* sampling rate configuration */ 1507 switch (params_rate(params)) { 1508 case 44100: 1509 sampling_rate = RT722_SDCA_RATE_44100HZ; 1510 break; 1511 case 48000: 1512 sampling_rate = RT722_SDCA_RATE_48000HZ; 1513 break; 1514 case 96000: 1515 sampling_rate = RT722_SDCA_RATE_96000HZ; 1516 break; 1517 case 192000: 1518 sampling_rate = RT722_SDCA_RATE_192000HZ; 1519 break; 1520 default: 1521 dev_err(component->dev, "%s: Rate %d is not supported\n", 1522 __func__, params_rate(params)); 1523 return -EINVAL; 1524 } 1525 1526 /* set sampling frequency */ 1527 if (dai->id == RT722_AIF1) { 1528 regmap_write(rt722->regmap, 1529 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, 1530 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1531 regmap_write(rt722->regmap, 1532 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, 1533 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1534 } 1535 1536 if (dai->id == RT722_AIF2) 1537 regmap_write(rt722->regmap, 1538 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 1539 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1540 1541 if (dai->id == RT722_AIF3) 1542 regmap_write(rt722->regmap, 1543 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 1544 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1545 1546 return 0; 1547 } 1548 1549 static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream, 1550 struct snd_soc_dai *dai) 1551 { 1552 struct snd_soc_component *component = dai->component; 1553 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component); 1554 struct sdw_stream_runtime *sdw_stream = 1555 snd_soc_dai_get_dma_data(dai, substream); 1556 1557 if (!rt722->slave) 1558 return -EINVAL; 1559 1560 sdw_stream_remove_slave(rt722->slave, sdw_stream); 1561 return 0; 1562 } 1563 1564 #define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 1565 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1566 #define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1567 SNDRV_PCM_FMTBIT_S24_LE) 1568 1569 static const struct snd_soc_dai_ops rt722_sdca_ops = { 1570 .hw_params = rt722_sdca_pcm_hw_params, 1571 .hw_free = rt722_sdca_pcm_hw_free, 1572 .set_stream = rt722_sdca_set_sdw_stream, 1573 .shutdown = rt722_sdca_shutdown, 1574 }; 1575 1576 static struct snd_soc_dai_driver rt722_sdca_dai[] = { 1577 { 1578 .name = "rt722-sdca-aif1", 1579 .id = RT722_AIF1, 1580 .playback = { 1581 .stream_name = "DP1 Headphone Playback", 1582 .channels_min = 1, 1583 .channels_max = 2, 1584 .rates = RT722_STEREO_RATES, 1585 .formats = RT722_FORMATS, 1586 }, 1587 .capture = { 1588 .stream_name = "DP2 Headset Capture", 1589 .channels_min = 1, 1590 .channels_max = 2, 1591 .rates = RT722_STEREO_RATES, 1592 .formats = RT722_FORMATS, 1593 }, 1594 .ops = &rt722_sdca_ops, 1595 }, 1596 { 1597 .name = "rt722-sdca-aif2", 1598 .id = RT722_AIF2, 1599 .playback = { 1600 .stream_name = "DP3 Speaker Playback", 1601 .channels_min = 1, 1602 .channels_max = 2, 1603 .rates = RT722_STEREO_RATES, 1604 .formats = RT722_FORMATS, 1605 }, 1606 .ops = &rt722_sdca_ops, 1607 }, 1608 { 1609 .name = "rt722-sdca-aif3", 1610 .id = RT722_AIF3, 1611 .capture = { 1612 .stream_name = "DP6 DMic Capture", 1613 .channels_min = 1, 1614 .channels_max = 4, 1615 .rates = RT722_STEREO_RATES, 1616 .formats = RT722_FORMATS, 1617 }, 1618 .ops = &rt722_sdca_ops, 1619 } 1620 }; 1621 1622 int rt722_sdca_init(struct device *dev, struct regmap *regmap, struct sdw_slave *slave) 1623 { 1624 struct rt722_sdca_priv *rt722; 1625 1626 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL); 1627 if (!rt722) 1628 return -ENOMEM; 1629 1630 dev_set_drvdata(dev, rt722); 1631 rt722->slave = slave; 1632 rt722->regmap = regmap; 1633 1634 regcache_cache_only(rt722->regmap, true); 1635 1636 mutex_init(&rt722->calibrate_mutex); 1637 mutex_init(&rt722->disable_irq_lock); 1638 1639 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler); 1640 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler); 1641 1642 /* 1643 * Mark hw_init to false 1644 * HW init will be performed when device reports present 1645 */ 1646 rt722->hw_init = false; 1647 rt722->first_hw_init = false; 1648 rt722->fu1e_dapm_mute = true; 1649 rt722->fu0f_dapm_mute = true; 1650 rt722->fu06_dapm_mute = true; 1651 rt722->fu06_mixer_l_mute = rt722->fu06_mixer_r_mute = false; 1652 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true; 1653 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] = 1654 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true; 1655 rt722->cae_update_done = 0; 1656 1657 return devm_snd_soc_register_component(dev, 1658 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai)); 1659 } 1660 1661 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722) 1662 { 1663 unsigned int mic_func_status; 1664 struct device *dev = &rt722->slave->dev; 1665 1666 regmap_read(rt722->regmap, 1667 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &mic_func_status); 1668 dev_dbg(dev, "%s mic func_status=0x%x\n", __func__, mic_func_status); 1669 1670 if ((mic_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1671 /* Set AD07 power entity floating control */ 1672 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1673 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29); 1674 /* Set AD10 power entity floating control */ 1675 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1676 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00); 1677 /* Set DMIC1/DMIC2 power entity floating control */ 1678 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1679 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a); 1680 /* Set DMIC2 IT entity floating control */ 1681 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1682 RT722_DMIC_ENT_FLOAT_CTL, 0x2626); 1683 /* Set AD10 FU entity floating control */ 1684 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1685 RT722_ADC_ENT_FLOAT_CTL, 0x1e00); 1686 /* Set DMIC2 FU entity floating control */ 1687 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1688 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515); 1689 /* Set AD10 FU channel floating control */ 1690 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1691 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304); 1692 /* Set DMIC2 FU channel floating control */ 1693 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1694 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304); 1695 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */ 1696 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1697 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000); 1698 /* Enable vf707_r12_05/vf707_r13_05 */ 1699 regmap_write(rt722->regmap, 1700 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 1701 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1702 /* Fine tune PDE2A latency */ 1703 regmap_write(rt722->regmap, 0x2f5c, 0x25); 1704 /* PHYtiming TDZ/TZD control */ 1705 regmap_write(rt722->regmap, 0x2f03, 0x06); 1706 1707 if (rt722->hw_vid == RT722_VB) 1708 regmap_write(rt722->regmap, 0x2f52, 0x00); 1709 1710 /* clear flag */ 1711 regmap_write(rt722->regmap, 1712 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1713 FUNCTION_NEEDS_INITIALIZATION); 1714 } 1715 } 1716 1717 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722) 1718 { 1719 unsigned int amp_func_status; 1720 struct device *dev = &rt722->slave->dev; 1721 1722 regmap_read(rt722->regmap, 1723 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &_func_status); 1724 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 1725 1726 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1727 /* Set DVQ=01 */ 1728 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1729 0xc215); 1730 /* Reset dc_cal_top */ 1731 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1732 0x702c); 1733 /* W1C Trigger Calibration */ 1734 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1735 0xf02d); 1736 /* Set DAC02/ClassD power entity floating control */ 1737 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL, 1738 0x2323); 1739 /* Set EAPD high */ 1740 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL, 1741 0x0002); 1742 /* Enable vf707_r14 */ 1743 regmap_write(rt722->regmap, 1744 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 1745 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04); 1746 1747 if (rt722->hw_vid == RT722_VB) 1748 regmap_write(rt722->regmap, 0x2f54, 0x00); 1749 1750 /* clear flag */ 1751 regmap_write(rt722->regmap, 1752 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1753 FUNCTION_NEEDS_INITIALIZATION); 1754 } 1755 } 1756 1757 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722) 1758 { 1759 int loop_check, chk_cnt = 100, ret; 1760 unsigned int calib_status = 0; 1761 unsigned int jack_func_status; 1762 struct device *dev = &rt722->slave->dev; 1763 1764 regmap_read(rt722->regmap, 1765 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &jack_func_status); 1766 dev_dbg(dev, "%s jack func_status=0x%x\n", __func__, jack_func_status); 1767 1768 if ((jack_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1769 /* Config analog bias */ 1770 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3, 1771 0xa081); 1772 /* GE related settings */ 1773 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2, 1774 0xa009); 1775 /* Button A, B, C, D bypass mode */ 1776 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4, 1777 0xcf00); 1778 /* HID1 slot enable */ 1779 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5, 1780 0x000f); 1781 /* Report ID for HID1 */ 1782 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0, 1783 0x1100); 1784 /* OSC/OOC for slot 2, 3 */ 1785 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7, 1786 0x0c12); 1787 /* Set JD de-bounce clock control */ 1788 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1, 1789 0x7002); 1790 /* Set DVQ=01 */ 1791 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1792 0xc215); 1793 /* FSM switch to calibration manual mode */ 1794 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL, 1795 0x4100); 1796 /* W1C Trigger DC calibration (HP) */ 1797 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3, 1798 0x008d); 1799 /* check HP calibration FSM status */ 1800 for (loop_check = 0; loop_check < chk_cnt; loop_check++) { 1801 usleep_range(10000, 11000); 1802 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI, 1803 RT722_DAC_DC_CALI_CTL3, &calib_status); 1804 if (ret < 0) 1805 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret); 1806 if ((calib_status & 0x0040) == 0x0) 1807 break; 1808 } 1809 1810 if (loop_check == chk_cnt) 1811 dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__); 1812 1813 /* Set ADC09 power entity floating control */ 1814 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL, 1815 0x2a12); 1816 /* Set MIC2 and LINE1 power entity floating control */ 1817 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL, 1818 0x3429); 1819 /* Set ET41h and LINE2 power entity floating control */ 1820 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL, 1821 0x4112); 1822 /* Set DAC03 and HP power entity floating control */ 1823 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL, 1824 0x4040); 1825 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1, 1826 0x4141); 1827 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1, 1828 0x0101); 1829 /* Fine tune PDE40 latency */ 1830 regmap_write(rt722->regmap, 0x2f58, 0x07); 1831 regmap_write(rt722->regmap, 0x2f03, 0x06); 1832 /* MIC VRefo */ 1833 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1834 RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200); 1835 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1836 RT722_VREFO_GAT, 0x4000, 0x4000); 1837 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */ 1838 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4, 1839 0x0010); 1840 1841 if (rt722->hw_vid == RT722_VB) 1842 regmap_write(rt722->regmap, 0x2f51, 0x00); 1843 1844 /* clear flag */ 1845 regmap_write(rt722->regmap, 1846 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1847 FUNCTION_NEEDS_INITIALIZATION); 1848 } 1849 } 1850 1851 static void rt722_sdca_reset(struct rt722_sdca_priv *rt722) 1852 { 1853 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1854 RT722_LDO1_CTL, RT722_HIDDEN_REG_SW_RESET, 1855 RT722_HIDDEN_REG_SW_RESET); 1856 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL, 1857 RT722_HDA_LEGACY_RESET_CTL, 0x1, 0x1); 1858 if (rt722->hw_vid == RT722_VA) 1859 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_LDO1_CTL, 0xb091); 1860 } 1861 1862 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave) 1863 { 1864 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev); 1865 unsigned int val; 1866 1867 rt722->disable_irq = false; 1868 1869 if (rt722->hw_init) 1870 return 0; 1871 1872 regcache_cache_only(rt722->regmap, false); 1873 if (rt722->first_hw_init) { 1874 regcache_cache_bypass(rt722->regmap, true); 1875 } else { 1876 /* 1877 * PM runtime is only enabled when a Slave reports as Attached 1878 */ 1879 1880 /* set autosuspend parameters */ 1881 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 1882 pm_runtime_use_autosuspend(&slave->dev); 1883 1884 /* update count of parent 'active' children */ 1885 pm_runtime_set_active(&slave->dev); 1886 1887 /* make sure the device does not suspend immediately */ 1888 pm_runtime_mark_last_busy(&slave->dev); 1889 1890 pm_runtime_enable(&slave->dev); 1891 } 1892 1893 pm_runtime_get_noresume(&slave->dev); 1894 1895 rt722_sdca_index_read(rt722, RT722_VENDOR_REG, RT722_JD_PRODUCT_NUM, &val); 1896 rt722->hw_vid = (val & 0x0f00) >> 8; 1897 dev_dbg(&slave->dev, "%s hw_vid=0x%x\n", __func__, rt722->hw_vid); 1898 1899 if (!rt722->first_hw_init) 1900 rt722_sdca_reset(rt722); 1901 1902 rt722_sdca_dmic_preset(rt722); 1903 rt722_sdca_amp_preset(rt722); 1904 rt722_sdca_jack_preset(rt722); 1905 1906 if (rt722->hs_jack && (!rt722->first_hw_init)) 1907 rt722_sdca_jack_init(rt722); 1908 1909 if (rt722->first_hw_init) { 1910 regcache_cache_bypass(rt722->regmap, false); 1911 regcache_mark_dirty(rt722->regmap); 1912 } else 1913 rt722->first_hw_init = true; 1914 1915 /* Mark Slave initialization complete */ 1916 rt722->hw_init = true; 1917 1918 pm_runtime_put_autosuspend(&slave->dev); 1919 1920 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1921 return 0; 1922 } 1923 1924 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver"); 1925 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1926 MODULE_LICENSE("GPL"); 1927