1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt722-sdca-sdw.c -- rt722 SDCA ALSA SoC audio driver 4 // 5 // Copyright(c) 2023 Realtek Semiconductor Corp. 6 // 7 // 8 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/soundwire/sdw_registers.h> 14 15 #include "rt722-sdca.h" 16 #include "rt722-sdca-sdw.h" 17 18 static int rt722_sdca_mbq_size(struct device *dev, unsigned int reg) 19 { 20 switch (reg) { 21 case 0x22f0 ... 0x22f1: 22 case 0x2f01 ... 0x2f0c: 23 case 0x2f21 ... 0x2f24: 24 case 0x2f35 ... 0x2f36: 25 case 0x2f50 ... 0x2f52: 26 case 0x2f54: 27 case 0x2f58 ... 0x2f5d: 28 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 29 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_SELECTED_MODE, 30 0): 31 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE, 32 0): 33 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03, RT722_SDCA_CTL_SELECTED_MODE, 34 0): 35 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 36 RT722_SDCA_CTL_FU_MUTE, CH_L) ... 37 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, 38 RT722_SDCA_CTL_FU_MUTE, CH_R): 39 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D, 40 RT722_SDCA_CTL_SELECTED_MODE, 0): 41 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 42 RT722_SDCA_CTL_FU_MUTE, CH_L) ... 43 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, 44 RT722_SDCA_CTL_FU_MUTE, CH_R): 45 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 46 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 47 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 48 RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 49 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 50 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 51 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 52 RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 53 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, 54 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 55 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, 56 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 57 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 58 RT722_SDCA_CTL_FU_MUTE, CH_01) ... 59 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, 60 RT722_SDCA_CTL_FU_MUTE, CH_04): 61 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 62 RT722_SDCA_CTL_VENDOR_DEF, 0): 63 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 64 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 65 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 66 RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 67 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 68 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 69 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 70 case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 71 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0) ... 72 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 73 RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0): 74 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 75 RT722_SDCA_CTL_FU_MUTE, CH_L) ... 76 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, 77 RT722_SDCA_CTL_FU_MUTE, CH_R): 78 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 79 RT722_SDCA_CTL_VENDOR_DEF, CH_08): 80 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 81 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 82 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 83 RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 84 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 85 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 86 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 87 case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2: 88 case 0x44011000 ... 0x440115ff: 89 case 0x44012000: 90 case 0x44012021: 91 case 0x44012022: 92 case 0x44012025: 93 case 0x44021000 ... 0x440211ff: 94 case 0x44022000: 95 case 0x44022019: 96 case 0x4402201a: 97 case 0x4402201d: 98 case 0x44041000 ... 0x440415ff: 99 case 0x44042000: 100 case 0x44042019: 101 case 0x4404201a: 102 case 0x4404201d: 103 return 1; 104 case 0x2000000 ... 0x2000024: 105 case 0x2000029 ... 0x200004a: 106 case 0x2000051 ... 0x2000052: 107 case 0x200005a ... 0x200005b: 108 case 0x2000061 ... 0x2000069: 109 case 0x200006b: 110 case 0x2000070: 111 case 0x200007f: 112 case 0x2000082 ... 0x200008e: 113 case 0x2000090 ... 0x2000094: 114 case 0x20000b1: 115 case 0x20000b4: 116 case 0x3010000: 117 case 0x3110000: 118 case 0x5300000 ... 0x5300300: 119 case 0x5400002: 120 case 0x5600000 ... 0x5600007: 121 case 0x5700000 ... 0x5700004: 122 case 0x5800000 ... 0x5800004: 123 case 0x5810000: 124 case 0x5b00003: 125 case 0x5c00011: 126 case 0x5d00006: 127 case 0x5f00000 ... 0x5f0000d: 128 case 0x5f00030: 129 case 0x6100000 ... 0x6100051: 130 case 0x6100055 ... 0x6100057: 131 case 0x6100060: 132 case 0x6100062: 133 case 0x6100064 ... 0x6100065: 134 case 0x6100067: 135 case 0x6100070 ... 0x610007c: 136 case 0x6100080: 137 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, 138 CH_01) ... 139 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, 140 CH_04): 141 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 142 CH_01): 143 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 144 CH_02): 145 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 146 CH_03): 147 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 148 CH_04): 149 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L): 150 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R): 151 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME, 152 CH_L): 153 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME, 154 CH_R): 155 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME, 156 CH_L): 157 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME, 158 CH_R): 159 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 160 RT722_SDCA_CTL_FU_CH_GAIN, CH_L): 161 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, 162 RT722_SDCA_CTL_FU_CH_GAIN, CH_R): 163 return 2; 164 default: 165 return 0; 166 } 167 } 168 169 static const struct regmap_sdw_mbq_cfg rt722_mbq_config = { 170 .mbq_size = rt722_sdca_mbq_size, 171 }; 172 173 static bool rt722_sdca_readable_register(struct device *dev, unsigned int reg) 174 { 175 return rt722_sdca_mbq_size(dev, reg) > 0; 176 } 177 178 static bool rt722_sdca_volatile_register(struct device *dev, unsigned int reg) 179 { 180 switch (reg) { 181 case 0x2f01: 182 case 0x2f54: 183 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 184 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 185 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 186 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE, 187 0): 188 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 189 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 190 case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 191 0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 192 RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0): 193 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 194 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 195 case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2: 196 case 0x2000000: 197 case 0x2000007: 198 case 0x200000d: 199 case 0x2000019: 200 case 0x200001a: 201 case 0x2000020: 202 case 0x2000030: 203 case 0x2000046: 204 case 0x2000067: 205 case 0x2000084: 206 case 0x2000086: 207 case 0x3010000: 208 case 0x3110000: 209 case 0x5800003: 210 case 0x5810000: 211 case 0x6100008: 212 case 0x44011000 ... 0x440115ff: 213 case 0x44012000: 214 case 0x44012021: 215 case 0x44012022: 216 case 0x44012025: 217 case 0x44021000 ... 0x440211ff: 218 case 0x44022000: 219 case 0x44022019: 220 case 0x4402201a: 221 case 0x4402201d: 222 case 0x44041000 ... 0x440415ff: 223 case 0x44042000: 224 case 0x44042019: 225 case 0x4404201a: 226 case 0x4404201d: 227 return true; 228 default: 229 return false; 230 } 231 } 232 233 static const struct regmap_config rt722_sdca_regmap = { 234 .reg_bits = 32, 235 .val_bits = 16, 236 .readable_reg = rt722_sdca_readable_register, 237 .volatile_reg = rt722_sdca_volatile_register, 238 .max_register = 0x44ffffff, 239 .reg_defaults = rt722_sdca_reg_defaults, 240 .num_reg_defaults = ARRAY_SIZE(rt722_sdca_reg_defaults), 241 .cache_type = REGCACHE_MAPLE, 242 .use_single_read = true, 243 .use_single_write = true, 244 }; 245 246 static int rt722_sdca_update_status(struct sdw_slave *slave, 247 enum sdw_slave_status status) 248 { 249 struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev); 250 251 if (status == SDW_SLAVE_UNATTACHED) 252 rt722->hw_init = false; 253 254 if (status == SDW_SLAVE_ATTACHED) { 255 if (rt722->hs_jack) { 256 /* 257 * Due to the SCP_SDCA_INTMASK will be cleared by any reset, and then 258 * if the device attached again, we will need to set the setting back. 259 * It could avoid losing the jack detection interrupt. 260 * This also could sync with the cache value as the rt722_sdca_jack_init set. 261 */ 262 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1, 263 SDW_SCP_SDCA_INTMASK_SDCA_0); 264 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2, 265 SDW_SCP_SDCA_INTMASK_SDCA_8); 266 } 267 } 268 269 /* 270 * Perform initialization only if slave status is present and 271 * hw_init flag is false 272 */ 273 if (rt722->hw_init || status != SDW_SLAVE_ATTACHED) 274 return 0; 275 276 /* perform I/O transfers required for Slave initialization */ 277 return rt722_sdca_io_init(&slave->dev, slave); 278 } 279 280 static int rt722_sdca_read_prop(struct sdw_slave *slave) 281 { 282 struct sdw_slave_prop *prop = &slave->prop; 283 int nval; 284 int i, j; 285 u32 bit; 286 unsigned long addr; 287 struct sdw_dpn_prop *dpn; 288 289 sdw_slave_read_lane_mapping(slave); 290 291 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 292 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 293 294 prop->paging_support = true; 295 296 /* 297 * port = 1 for headphone playback 298 * port = 2 for headset-mic capture 299 * port = 3 for speaker playback 300 * port = 6 for digital-mic capture 301 */ 302 prop->source_ports = BIT(6) | BIT(2); /* BITMAP: 01000100 */ 303 prop->sink_ports = BIT(3) | BIT(1); /* BITMAP: 00001010 */ 304 305 nval = hweight32(prop->source_ports); 306 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 307 sizeof(*prop->src_dpn_prop), GFP_KERNEL); 308 if (!prop->src_dpn_prop) 309 return -ENOMEM; 310 311 i = 0; 312 dpn = prop->src_dpn_prop; 313 addr = prop->source_ports; 314 for_each_set_bit(bit, &addr, 32) { 315 dpn[i].num = bit; 316 dpn[i].type = SDW_DPN_FULL; 317 dpn[i].simple_ch_prep_sm = true; 318 dpn[i].ch_prep_timeout = 10; 319 i++; 320 } 321 322 /* do this again for sink now */ 323 nval = hweight32(prop->sink_ports); 324 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 325 sizeof(*prop->sink_dpn_prop), GFP_KERNEL); 326 if (!prop->sink_dpn_prop) 327 return -ENOMEM; 328 329 j = 0; 330 dpn = prop->sink_dpn_prop; 331 addr = prop->sink_ports; 332 for_each_set_bit(bit, &addr, 32) { 333 dpn[j].num = bit; 334 dpn[j].type = SDW_DPN_FULL; 335 dpn[j].simple_ch_prep_sm = true; 336 dpn[j].ch_prep_timeout = 10; 337 j++; 338 } 339 340 /* set the timeout values */ 341 prop->clk_stop_timeout = 900; 342 343 /* wake-up event */ 344 prop->wake_capable = 1; 345 346 /* Three data lanes are supported by rt722-sdca codec */ 347 prop->lane_control_support = true; 348 349 return 0; 350 } 351 352 static int rt722_sdca_interrupt_callback(struct sdw_slave *slave, 353 struct sdw_slave_intr_status *status) 354 { 355 struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev); 356 int ret, stat; 357 int count = 0, retry = 3; 358 unsigned int sdca_cascade, scp_sdca_stat1, scp_sdca_stat2 = 0; 359 360 if (cancel_delayed_work_sync(&rt722->jack_detect_work)) { 361 dev_warn(&slave->dev, "%s the pending delayed_work was cancelled", __func__); 362 /* avoid the HID owner doesn't change to device */ 363 if (rt722->scp_sdca_stat2) 364 scp_sdca_stat2 = rt722->scp_sdca_stat2; 365 } 366 367 /* 368 * The critical section below intentionally protects a rather large piece of code. 369 * We don't want to allow the system suspend to disable an interrupt while we are 370 * processing it, which could be problematic given the quirky SoundWire interrupt 371 * scheme. We do want however to prevent new workqueues from being scheduled if 372 * the disable_irq flag was set during system suspend. 373 */ 374 mutex_lock(&rt722->disable_irq_lock); 375 376 ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1); 377 if (ret < 0) 378 goto io_error; 379 rt722->scp_sdca_stat1 = ret; 380 ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2); 381 if (ret < 0) 382 goto io_error; 383 rt722->scp_sdca_stat2 = ret; 384 if (scp_sdca_stat2) 385 rt722->scp_sdca_stat2 |= scp_sdca_stat2; 386 do { 387 /* clear flag */ 388 ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1); 389 if (ret < 0) 390 goto io_error; 391 if (ret & SDW_SCP_SDCA_INTMASK_SDCA_0) { 392 ret = sdw_update_no_pm(rt722->slave, SDW_SCP_SDCA_INT1, 393 SDW_SCP_SDCA_INT_SDCA_0, SDW_SCP_SDCA_INT_SDCA_0); 394 if (ret < 0) 395 goto io_error; 396 } 397 398 ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2); 399 if (ret < 0) 400 goto io_error; 401 if (ret & SDW_SCP_SDCA_INTMASK_SDCA_8) { 402 ret = sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INT2, 403 SDW_SCP_SDCA_INTMASK_SDCA_8); 404 if (ret < 0) 405 goto io_error; 406 } 407 408 /* check if flag clear or not */ 409 ret = sdw_read_no_pm(rt722->slave, SDW_DP0_INT); 410 if (ret < 0) 411 goto io_error; 412 sdca_cascade = ret & SDW_DP0_SDCA_CASCADE; 413 414 ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1); 415 if (ret < 0) 416 goto io_error; 417 scp_sdca_stat1 = ret & SDW_SCP_SDCA_INTMASK_SDCA_0; 418 419 ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2); 420 if (ret < 0) 421 goto io_error; 422 scp_sdca_stat2 = ret & SDW_SCP_SDCA_INTMASK_SDCA_8; 423 424 stat = scp_sdca_stat1 || scp_sdca_stat2 || sdca_cascade; 425 426 count++; 427 } while (stat != 0 && count < retry); 428 429 if (stat) 430 dev_warn(&slave->dev, 431 "%s scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__, 432 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2); 433 434 if (status->sdca_cascade && !rt722->disable_irq) 435 mod_delayed_work(system_power_efficient_wq, 436 &rt722->jack_detect_work, msecs_to_jiffies(280)); 437 438 mutex_unlock(&rt722->disable_irq_lock); 439 440 return 0; 441 442 io_error: 443 mutex_unlock(&rt722->disable_irq_lock); 444 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 445 return ret; 446 } 447 448 static const struct sdw_slave_ops rt722_sdca_slave_ops = { 449 .read_prop = rt722_sdca_read_prop, 450 .interrupt_callback = rt722_sdca_interrupt_callback, 451 .update_status = rt722_sdca_update_status, 452 }; 453 454 static int rt722_sdca_sdw_probe(struct sdw_slave *slave, 455 const struct sdw_device_id *id) 456 { 457 struct regmap *regmap; 458 459 /* Regmap Initialization */ 460 regmap = devm_regmap_init_sdw_mbq_cfg(&slave->dev, slave, 461 &rt722_sdca_regmap, 462 &rt722_mbq_config); 463 if (IS_ERR(regmap)) 464 return PTR_ERR(regmap); 465 466 return rt722_sdca_init(&slave->dev, regmap, slave); 467 } 468 469 static void rt722_sdca_sdw_remove(struct sdw_slave *slave) 470 { 471 struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev); 472 473 if (rt722->hw_init) { 474 cancel_delayed_work_sync(&rt722->jack_detect_work); 475 cancel_delayed_work_sync(&rt722->jack_btn_check_work); 476 } 477 478 if (rt722->first_hw_init) 479 pm_runtime_disable(&slave->dev); 480 481 mutex_destroy(&rt722->calibrate_mutex); 482 mutex_destroy(&rt722->disable_irq_lock); 483 } 484 485 static const struct sdw_device_id rt722_sdca_id[] = { 486 SDW_SLAVE_ENTRY_EXT(0x025d, 0x722, 0x3, 0x1, 0), 487 {}, 488 }; 489 MODULE_DEVICE_TABLE(sdw, rt722_sdca_id); 490 491 static int rt722_sdca_dev_suspend(struct device *dev) 492 { 493 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev); 494 495 if (!rt722->hw_init) 496 return 0; 497 498 cancel_delayed_work_sync(&rt722->jack_detect_work); 499 cancel_delayed_work_sync(&rt722->jack_btn_check_work); 500 501 regcache_cache_only(rt722->regmap, true); 502 503 return 0; 504 } 505 506 static int rt722_sdca_dev_system_suspend(struct device *dev) 507 { 508 struct rt722_sdca_priv *rt722_sdca = dev_get_drvdata(dev); 509 struct sdw_slave *slave = dev_to_sdw_dev(dev); 510 int ret1, ret2; 511 512 if (!rt722_sdca->hw_init) 513 return 0; 514 515 /* 516 * prevent new interrupts from being handled after the 517 * deferred work completes and before the parent disables 518 * interrupts on the link 519 */ 520 mutex_lock(&rt722_sdca->disable_irq_lock); 521 rt722_sdca->disable_irq = true; 522 ret1 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK1, 523 SDW_SCP_SDCA_INTMASK_SDCA_0, 0); 524 ret2 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK2, 525 SDW_SCP_SDCA_INTMASK_SDCA_8, 0); 526 mutex_unlock(&rt722_sdca->disable_irq_lock); 527 528 if (ret1 < 0 || ret2 < 0) { 529 /* log but don't prevent suspend from happening */ 530 dev_dbg(&slave->dev, "%s: could not disable SDCA interrupts\n:", __func__); 531 } 532 533 return rt722_sdca_dev_suspend(dev); 534 } 535 536 #define RT722_PROBE_TIMEOUT 5000 537 538 static int rt722_sdca_dev_resume(struct device *dev) 539 { 540 struct sdw_slave *slave = dev_to_sdw_dev(dev); 541 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev); 542 int ret; 543 544 if (!rt722->first_hw_init) 545 return 0; 546 547 if (!slave->unattach_request) { 548 mutex_lock(&rt722->disable_irq_lock); 549 if (rt722->disable_irq == true) { 550 sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK1, SDW_SCP_SDCA_INTMASK_SDCA_0); 551 sdw_write_no_pm(slave, SDW_SCP_SDCA_INTMASK2, SDW_SCP_SDCA_INTMASK_SDCA_8); 552 rt722->disable_irq = false; 553 } 554 mutex_unlock(&rt722->disable_irq_lock); 555 } 556 557 ret = sdw_slave_wait_for_init(slave, RT722_PROBE_TIMEOUT); 558 if (ret) { 559 sdw_show_ping_status(slave->bus, true); 560 return ret; 561 } 562 563 regcache_cache_only(rt722->regmap, false); 564 regcache_sync(rt722->regmap); 565 return 0; 566 } 567 568 static const struct dev_pm_ops rt722_sdca_pm = { 569 SYSTEM_SLEEP_PM_OPS(rt722_sdca_dev_system_suspend, rt722_sdca_dev_resume) 570 RUNTIME_PM_OPS(rt722_sdca_dev_suspend, rt722_sdca_dev_resume, NULL) 571 }; 572 573 static struct sdw_driver rt722_sdca_sdw_driver = { 574 .driver = { 575 .name = "rt722-sdca", 576 .pm = pm_ptr(&rt722_sdca_pm), 577 }, 578 .probe = rt722_sdca_sdw_probe, 579 .remove = rt722_sdca_sdw_remove, 580 .ops = &rt722_sdca_slave_ops, 581 .id_table = rt722_sdca_id, 582 }; 583 module_sdw_driver(rt722_sdca_sdw_driver); 584 585 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver"); 586 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 587 MODULE_LICENSE("GPL"); 588