1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt721-sdca.c -- rt721 SDCA ALSA SoC audio driver 4 // 5 // Copyright(c) 2024 Realtek Semiconductor Corp. 6 // 7 // 8 9 #include <linux/bitops.h> 10 #include <sound/core.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <sound/initval.h> 14 #include <sound/jack.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <sound/pcm.h> 19 #include <linux/pm_runtime.h> 20 #include <sound/pcm_params.h> 21 #include <linux/soundwire/sdw_registers.h> 22 #include <linux/slab.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/tlv.h> 25 26 #include "rt721-sdca.h" 27 #include "rt-sdw-common.h" 28 29 static void rt721_sdca_jack_detect_handler(struct work_struct *work) 30 { 31 struct rt721_sdca_priv *rt721 = 32 container_of(work, struct rt721_sdca_priv, jack_detect_work.work); 33 int btn_type = 0; 34 35 if (!rt721->hs_jack) 36 return; 37 38 if (!rt721->component->card || !rt721->component->card->instantiated) 39 return; 40 41 /* SDW_SCP_SDCA_INT_SDCA_6 is used for jack detection */ 42 if (rt721->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_6) { 43 rt721->jack_type = rt_sdca_headset_detect(rt721->regmap, 44 RT721_SDCA_ENT_GE49); 45 if (rt721->jack_type < 0) 46 return; 47 } 48 49 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */ 50 if (rt721->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8) 51 btn_type = rt_sdca_button_detect(rt721->regmap, 52 RT721_SDCA_ENT_HID01, RT721_BUF_ADDR_HID1, 53 RT721_SDCA_HID_ID); 54 55 if (rt721->jack_type == 0) 56 btn_type = 0; 57 58 dev_dbg(&rt721->slave->dev, 59 "in %s, jack_type=%d\n", __func__, rt721->jack_type); 60 dev_dbg(&rt721->slave->dev, 61 "in %s, btn_type=0x%x\n", __func__, btn_type); 62 dev_dbg(&rt721->slave->dev, 63 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__, 64 rt721->scp_sdca_stat1, rt721->scp_sdca_stat2); 65 66 snd_soc_jack_report(rt721->hs_jack, rt721->jack_type | btn_type, 67 SND_JACK_HEADSET | 68 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 69 SND_JACK_BTN_2 | SND_JACK_BTN_3); 70 71 if (btn_type) { 72 /* button released */ 73 snd_soc_jack_report(rt721->hs_jack, rt721->jack_type, 74 SND_JACK_HEADSET | 75 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 76 SND_JACK_BTN_2 | SND_JACK_BTN_3); 77 78 mod_delayed_work(system_power_efficient_wq, 79 &rt721->jack_btn_check_work, msecs_to_jiffies(200)); 80 } 81 } 82 83 static void rt721_sdca_btn_check_handler(struct work_struct *work) 84 { 85 struct rt721_sdca_priv *rt721 = 86 container_of(work, struct rt721_sdca_priv, jack_btn_check_work.work); 87 int btn_type = 0, ret, idx; 88 unsigned int det_mode, offset, val; 89 unsigned char buf[3]; 90 91 ret = regmap_read(rt721->regmap, 92 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_GE49, 93 RT721_SDCA_CTL_DETECTED_MODE, 0), &det_mode); 94 if (ret < 0) 95 goto io_error; 96 97 /* pin attached */ 98 if (det_mode) { 99 /* read UMP message offset */ 100 ret = regmap_read(rt721->regmap, 101 SDW_SDCA_CTL(FUNC_NUM_HID, RT721_SDCA_ENT_HID01, 102 RT721_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset); 103 if (ret < 0) 104 goto io_error; 105 106 for (idx = 0; idx < sizeof(buf); idx++) { 107 ret = regmap_read(rt721->regmap, 108 RT721_BUF_ADDR_HID1 + offset + idx, &val); 109 if (ret < 0) 110 goto io_error; 111 buf[idx] = val & 0xff; 112 } 113 /* Report ID for HID1 */ 114 if (buf[0] == 0x11) 115 btn_type = rt_sdca_btn_type(&buf[1]); 116 } else 117 rt721->jack_type = 0; 118 119 dev_dbg(&rt721->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type); 120 snd_soc_jack_report(rt721->hs_jack, rt721->jack_type | btn_type, 121 SND_JACK_HEADSET | 122 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 123 SND_JACK_BTN_2 | SND_JACK_BTN_3); 124 125 if (btn_type) { 126 /* button released */ 127 snd_soc_jack_report(rt721->hs_jack, rt721->jack_type, 128 SND_JACK_HEADSET | 129 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 130 SND_JACK_BTN_2 | SND_JACK_BTN_3); 131 132 mod_delayed_work(system_power_efficient_wq, 133 &rt721->jack_btn_check_work, msecs_to_jiffies(200)); 134 } 135 136 return; 137 138 io_error: 139 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret); 140 } 141 142 static void rt721_sdca_dmic_preset(struct rt721_sdca_priv *rt721) 143 { 144 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 145 RT721_MISC_POWER_CTL31, 0x8000); 146 rt_sdca_index_write(rt721->mbq_regmap, RT721_ANA_POW_PART, 147 RT721_VREF1_HV_CTRL1, 0xe000); 148 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 149 RT721_MISC_POWER_CTL31, 0x8007); 150 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 151 RT721_ENT_FLOAT_CTL9, 0x2a2a); 152 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 153 RT721_ENT_FLOAT_CTL10, 0x2a00); 154 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 155 RT721_ENT_FLOAT_CTL6, 0x2a2a); 156 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 157 RT721_ENT_FLOAT_CTL5, 0x2626); 158 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 159 RT721_ENT_FLOAT_CTL8, 0x1e00); 160 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 161 RT721_ENT_FLOAT_CTL7, 0x1515); 162 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 163 RT721_CH_FLOAT_CTL3, 0x0304); 164 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 165 RT721_CH_FLOAT_CTL4, 0x0304); 166 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 167 RT721_HDA_LEGACY_CTL1, 0x0000); 168 regmap_write(rt721->regmap, 169 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_IT26, 170 RT721_SDCA_CTL_VENDOR_DEF, 0), 0x01); 171 regmap_write(rt721->mbq_regmap, 0x5910009, 0x2e01); 172 rt_sdca_index_write(rt721->mbq_regmap, RT721_RC_CALIB_CTRL, 173 RT721_RC_CALIB_CTRL0, 0x0b00); 174 rt_sdca_index_write(rt721->mbq_regmap, RT721_RC_CALIB_CTRL, 175 RT721_RC_CALIB_CTRL0, 0x0b40); 176 regmap_write(rt721->regmap, 0x2f5c, 0x25); 177 } 178 179 static void rt721_sdca_amp_preset(struct rt721_sdca_priv *rt721) 180 { 181 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 182 RT721_MISC_POWER_CTL31, 0x8000); 183 rt_sdca_index_write(rt721->mbq_regmap, RT721_ANA_POW_PART, 184 RT721_VREF1_HV_CTRL1, 0xe000); 185 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 186 RT721_MISC_POWER_CTL31, 0x8007); 187 regmap_write(rt721->mbq_regmap, 0x5810000, 0x6420); 188 regmap_write(rt721->mbq_regmap, 0x5810000, 0x6421); 189 regmap_write(rt721->mbq_regmap, 0x5810000, 0xe421); 190 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 191 RT721_CH_FLOAT_CTL6, 0x5561); 192 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_REG, 193 RT721_GPIO_PAD_CTRL5, 0x8003); 194 regmap_write(rt721->regmap, 195 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_OT23, 196 RT721_SDCA_CTL_VENDOR_DEF, 0), 0x04); 197 regmap_write(rt721->regmap, 198 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 199 RT721_SDCA_CTL_FU_MUTE, CH_01), 0x00); 200 regmap_write(rt721->regmap, 201 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 202 RT721_SDCA_CTL_FU_MUTE, CH_02), 0x00); 203 regmap_write(rt721->regmap, 204 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_FU55, 205 RT721_SDCA_CTL_FU_MUTE, CH_01), 0x00); 206 regmap_write(rt721->regmap, 207 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_FU55, 208 RT721_SDCA_CTL_FU_MUTE, CH_02), 0x00); 209 } 210 211 static void rt721_sdca_jack_preset(struct rt721_sdca_priv *rt721) 212 { 213 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 214 RT721_MISC_POWER_CTL31, 0x8000); 215 rt_sdca_index_write(rt721->mbq_regmap, RT721_ANA_POW_PART, 216 RT721_VREF1_HV_CTRL1, 0xe000); 217 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 218 RT721_MISC_POWER_CTL31, 0x8007); 219 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 220 RT721_GE_REL_CTRL1, 0x8011); 221 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 222 RT721_UMP_HID_CTRL3, 0xcf00); 223 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 224 RT721_UMP_HID_CTRL4, 0x000f); 225 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 226 RT721_UMP_HID_CTRL1, 0x1100); 227 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 228 RT721_UMP_HID_CTRL5, 0x0c12); 229 rt_sdca_index_write(rt721->mbq_regmap, RT721_JD_CTRL, 230 RT721_JD_1PIN_GAT_CTRL2, 0xc002); 231 rt_sdca_index_write(rt721->mbq_regmap, RT721_RC_CALIB_CTRL, 232 RT721_RC_CALIB_CTRL0, 0x0b00); 233 rt_sdca_index_write(rt721->mbq_regmap, RT721_RC_CALIB_CTRL, 234 RT721_RC_CALIB_CTRL0, 0x0b40); 235 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 236 RT721_UAJ_TOP_TCON14, 0x3333); 237 regmap_write(rt721->mbq_regmap, 0x5810035, 0x0036); 238 regmap_write(rt721->mbq_regmap, 0x5810030, 0xee00); 239 rt_sdca_index_write(rt721->mbq_regmap, RT721_CAP_PORT_CTRL, 240 RT721_HP_AMP_2CH_CAL1, 0x0140); 241 regmap_write(rt721->mbq_regmap, 0x5810000, 0x0021); 242 regmap_write(rt721->mbq_regmap, 0x5810000, 0x8021); 243 rt_sdca_index_write(rt721->mbq_regmap, RT721_CAP_PORT_CTRL, 244 RT721_HP_AMP_2CH_CAL18, 0x5522); 245 regmap_write(rt721->mbq_regmap, 0x5b10007, 0x2000); 246 regmap_write(rt721->mbq_regmap, 0x5B10017, 0x1b0f); 247 rt_sdca_index_write(rt721->mbq_regmap, RT721_CBJ_CTRL, 248 RT721_CBJ_A0_GAT_CTRL1, 0x2a02); 249 rt_sdca_index_write(rt721->mbq_regmap, RT721_CAP_PORT_CTRL, 250 RT721_HP_AMP_2CH_CAL4, 0xa105); 251 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 252 RT721_UAJ_TOP_TCON14, 0x3b33); 253 regmap_write(rt721->mbq_regmap, 0x310400, 0x3023); 254 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 255 RT721_UAJ_TOP_TCON14, 0x3f33); 256 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 257 RT721_UAJ_TOP_TCON13, 0x6048); 258 regmap_write(rt721->mbq_regmap, 0x310401, 0x3000); 259 regmap_write(rt721->mbq_regmap, 0x310402, 0x1b00); 260 regmap_write(rt721->mbq_regmap, 0x310300, 0x000f); 261 regmap_write(rt721->mbq_regmap, 0x310301, 0x3000); 262 regmap_write(rt721->mbq_regmap, 0x310302, 0x1b00); 263 rt_sdca_index_write(rt721->mbq_regmap, RT721_VENDOR_ANA_CTL, 264 RT721_UAJ_TOP_TCON17, 0x0008); 265 rt_sdca_index_write(rt721->mbq_regmap, RT721_DAC_CTRL, 266 RT721_DAC_2CH_CTRL3, 0x55ff); 267 rt_sdca_index_write(rt721->mbq_regmap, RT721_DAC_CTRL, 268 RT721_DAC_2CH_CTRL4, 0xcc00); 269 rt_sdca_index_write(rt721->mbq_regmap, RT721_ANA_POW_PART, 270 RT721_MBIAS_LV_CTRL2, 0x6677); 271 rt_sdca_index_write(rt721->mbq_regmap, RT721_ANA_POW_PART, 272 RT721_VREF2_LV_CTRL1, 0x7600); 273 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 274 RT721_ENT_FLOAT_CTL2, 0x1234); 275 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 276 RT721_ENT_FLOAT_CTL3, 0x3512); 277 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 278 RT721_ENT_FLOAT_CTL1, 0x4040); 279 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 280 RT721_ENT_FLOAT_CTL4, 0x1201); 281 regmap_write(rt721->regmap, 0x2f58, 0x07); 282 } 283 284 static void rt721_sdca_jack_init(struct rt721_sdca_priv *rt721) 285 { 286 mutex_lock(&rt721->calibrate_mutex); 287 if (rt721->hs_jack) { 288 sdw_write_no_pm(rt721->slave, SDW_SCP_SDCA_INTMASK1, 289 SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6); 290 sdw_write_no_pm(rt721->slave, SDW_SCP_SDCA_INTMASK2, 291 SDW_SCP_SDCA_INTMASK_SDCA_8); 292 dev_dbg(&rt721->slave->dev, "in %s enable\n", __func__); 293 rt_sdca_index_write(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 294 RT721_HDA_LEGACY_UAJ_CTL, 0x036E); 295 regmap_write(rt721->regmap, 296 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_XU03, 297 RT721_SDCA_CTL_SELECTED_MODE, 0), 0); 298 regmap_write(rt721->regmap, 299 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_XU0D, 300 RT721_SDCA_CTL_SELECTED_MODE, 0), 0); 301 rt_sdca_index_update_bits(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 302 RT721_GE_REL_CTRL1, 0x4000, 0x4000); 303 } 304 mutex_unlock(&rt721->calibrate_mutex); 305 } 306 307 static int rt721_sdca_set_jack_detect(struct snd_soc_component *component, 308 struct snd_soc_jack *hs_jack, void *data) 309 { 310 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 311 int ret; 312 313 rt721->hs_jack = hs_jack; 314 315 ret = pm_runtime_resume_and_get(component->dev); 316 if (ret < 0) { 317 if (ret != -EACCES) { 318 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret); 319 return ret; 320 } 321 /* pm_runtime not enabled yet */ 322 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__); 323 return 0; 324 } 325 326 rt721_sdca_jack_init(rt721); 327 328 pm_runtime_mark_last_busy(component->dev); 329 pm_runtime_put_autosuspend(component->dev); 330 331 return 0; 332 } 333 334 /* For SDCA control DAC/ADC Gain */ 335 static int rt721_sdca_set_gain_put(struct snd_kcontrol *kcontrol, 336 struct snd_ctl_elem_value *ucontrol) 337 { 338 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 339 struct soc_mixer_control *mc = 340 (struct soc_mixer_control *)kcontrol->private_value; 341 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 342 unsigned int read_l, read_r, gain_l_val, gain_r_val; 343 unsigned int adc_vol_flag = 0, changed = 0; 344 unsigned int lvalue, rvalue; 345 const unsigned int interval_offset = 0xc0; 346 const unsigned int tendA = 0x200; 347 const unsigned int tendB = 0xa00; 348 349 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 350 strstr(ucontrol->id.name, "FU0F Capture Volume")) 351 adc_vol_flag = 1; 352 353 regmap_read(rt721->mbq_regmap, mc->reg, &lvalue); 354 regmap_read(rt721->mbq_regmap, mc->rreg, &rvalue); 355 356 /* L Channel */ 357 gain_l_val = ucontrol->value.integer.value[0]; 358 if (gain_l_val > mc->max) 359 gain_l_val = mc->max; 360 361 if (mc->shift == 8) { 362 /* boost gain */ 363 gain_l_val = gain_l_val * tendB; 364 } else if (mc->shift == 1) { 365 /* FU33 boost gain */ 366 if (gain_l_val == 0) 367 gain_l_val = 0x8000; 368 else 369 gain_l_val = (gain_l_val - 1) * tendA; 370 } else { 371 /* ADC/DAC gain */ 372 if (adc_vol_flag) 373 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset); 374 else 375 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); 376 gain_l_val &= 0xffff; 377 } 378 379 /* R Channel */ 380 gain_r_val = ucontrol->value.integer.value[1]; 381 if (gain_r_val > mc->max) 382 gain_r_val = mc->max; 383 384 if (mc->shift == 8) { 385 /* boost gain */ 386 gain_r_val = gain_r_val * tendB; 387 } else if (mc->shift == 1) { 388 /* FU33 boost gain */ 389 if (gain_r_val == 0) 390 gain_r_val = 0x8000; 391 else 392 gain_r_val = (gain_r_val - 1) * tendA; 393 } else { 394 /* ADC/DAC gain */ 395 if (adc_vol_flag) 396 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset); 397 else 398 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); 399 gain_r_val &= 0xffff; 400 } 401 402 if (lvalue != gain_l_val || rvalue != gain_r_val) 403 changed = 1; 404 else 405 return 0; 406 407 /* Lch*/ 408 regmap_write(rt721->mbq_regmap, mc->reg, gain_l_val); 409 410 /* Rch */ 411 regmap_write(rt721->mbq_regmap, mc->rreg, gain_r_val); 412 413 regmap_read(rt721->mbq_regmap, mc->reg, &read_l); 414 regmap_read(rt721->mbq_regmap, mc->rreg, &read_r); 415 if (read_r == gain_r_val && read_l == gain_l_val) 416 return changed; 417 418 return -EIO; 419 } 420 421 static int rt721_sdca_set_gain_get(struct snd_kcontrol *kcontrol, 422 struct snd_ctl_elem_value *ucontrol) 423 { 424 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 425 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 426 struct soc_mixer_control *mc = 427 (struct soc_mixer_control *)kcontrol->private_value; 428 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; 429 unsigned int adc_vol_flag = 0; 430 const unsigned int interval_offset = 0xc0; 431 const unsigned int tendB = 0xa00; 432 433 if (strstr(ucontrol->id.name, "FU1E Capture Volume") || 434 strstr(ucontrol->id.name, "FU0F Capture Volume")) 435 adc_vol_flag = 1; 436 437 regmap_read(rt721->mbq_regmap, mc->reg, &read_l); 438 regmap_read(rt721->mbq_regmap, mc->rreg, &read_r); 439 440 if (mc->shift == 8) /* boost gain */ 441 ctl_l = read_l / tendB; 442 else { 443 if (adc_vol_flag) 444 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset); 445 else 446 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); 447 } 448 449 if (read_l != read_r) { 450 if (mc->shift == 8) /* boost gain */ 451 ctl_r = read_r / tendB; 452 else { /* ADC/DAC gain */ 453 if (adc_vol_flag) 454 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset); 455 else 456 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); 457 } 458 } else { 459 ctl_r = ctl_l; 460 } 461 462 ucontrol->value.integer.value[0] = ctl_l; 463 ucontrol->value.integer.value[1] = ctl_r; 464 465 return 0; 466 } 467 468 static int rt721_sdca_set_fu1e_capture_ctl(struct rt721_sdca_priv *rt721) 469 { 470 int err, i; 471 unsigned int ch_mute; 472 473 for (i = 0; i < ARRAY_SIZE(rt721->fu1e_mixer_mute); i++) { 474 ch_mute = rt721->fu1e_dapm_mute || rt721->fu1e_mixer_mute[i]; 475 err = regmap_write(rt721->regmap, 476 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, 477 RT721_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute); 478 if (err < 0) 479 return err; 480 } 481 482 return 0; 483 } 484 485 static int rt721_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol, 486 struct snd_ctl_elem_value *ucontrol) 487 { 488 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 489 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 490 struct rt721_sdca_dmic_kctrl_priv *p = 491 (struct rt721_sdca_dmic_kctrl_priv *)kcontrol->private_value; 492 unsigned int i; 493 494 for (i = 0; i < p->count; i++) 495 ucontrol->value.integer.value[i] = !rt721->fu1e_mixer_mute[i]; 496 497 return 0; 498 } 499 500 static int rt721_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol, 501 struct snd_ctl_elem_value *ucontrol) 502 { 503 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 504 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 505 struct rt721_sdca_dmic_kctrl_priv *p = 506 (struct rt721_sdca_dmic_kctrl_priv *)kcontrol->private_value; 507 int err, changed = 0, i; 508 509 for (i = 0; i < p->count; i++) { 510 if (rt721->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i]) 511 changed = 1; 512 rt721->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i]; 513 } 514 515 err = rt721_sdca_set_fu1e_capture_ctl(rt721); 516 if (err < 0) 517 return err; 518 519 return changed; 520 } 521 522 static int rt721_sdca_set_fu0f_capture_ctl(struct rt721_sdca_priv *rt721) 523 { 524 int err; 525 unsigned int ch_l, ch_r; 526 527 ch_l = (rt721->fu0f_dapm_mute || rt721->fu0f_mixer_l_mute) ? 0x01 : 0x00; 528 ch_r = (rt721->fu0f_dapm_mute || rt721->fu0f_mixer_r_mute) ? 0x01 : 0x00; 529 530 err = regmap_write(rt721->regmap, 531 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, 532 RT721_SDCA_CTL_FU_MUTE, CH_L), ch_l); 533 if (err < 0) 534 return err; 535 536 err = regmap_write(rt721->regmap, 537 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, 538 RT721_SDCA_CTL_FU_MUTE, CH_R), ch_r); 539 if (err < 0) 540 return err; 541 542 return 0; 543 } 544 545 static int rt721_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol, 546 struct snd_ctl_elem_value *ucontrol) 547 { 548 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 549 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 550 551 ucontrol->value.integer.value[0] = !rt721->fu0f_mixer_l_mute; 552 ucontrol->value.integer.value[1] = !rt721->fu0f_mixer_r_mute; 553 return 0; 554 } 555 556 static int rt721_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol, 557 struct snd_ctl_elem_value *ucontrol) 558 { 559 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 560 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 561 int err, changed = 0; 562 563 if (rt721->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] || 564 rt721->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1]) 565 changed = 1; 566 567 rt721->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0]; 568 rt721->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1]; 569 err = rt721_sdca_set_fu0f_capture_ctl(rt721); 570 if (err < 0) 571 return err; 572 573 return changed; 574 } 575 576 static int rt721_sdca_fu_info(struct snd_kcontrol *kcontrol, 577 struct snd_ctl_elem_info *uinfo) 578 { 579 struct rt721_sdca_dmic_kctrl_priv *p = 580 (struct rt721_sdca_dmic_kctrl_priv *)kcontrol->private_value; 581 582 if (p->max == 1) 583 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 584 else 585 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 586 uinfo->count = p->count; 587 uinfo->value.integer.min = 0; 588 uinfo->value.integer.max = p->max; 589 return 0; 590 } 591 592 static int rt721_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol, 593 struct snd_ctl_elem_value *ucontrol) 594 { 595 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 596 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 597 struct rt721_sdca_dmic_kctrl_priv *p = 598 (struct rt721_sdca_dmic_kctrl_priv *)kcontrol->private_value; 599 unsigned int boost_step = 0x0a00; 600 unsigned int vol_max = 0x1e00; 601 unsigned int regvalue, ctl, i; 602 unsigned int adc_vol_flag = 0; 603 const unsigned int interval_offset = 0xc0; 604 605 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 606 adc_vol_flag = 1; 607 608 /* check all channels */ 609 for (i = 0; i < p->count; i++) { 610 regmap_read(rt721->mbq_regmap, p->reg_base + i, ®value); 611 612 if (!adc_vol_flag) /* boost gain */ 613 ctl = regvalue / boost_step; 614 else /* ADC gain */ 615 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset); 616 617 ucontrol->value.integer.value[i] = ctl; 618 } 619 620 return 0; 621 } 622 623 static int rt721_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol, 624 struct snd_ctl_elem_value *ucontrol) 625 { 626 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 627 struct rt721_sdca_dmic_kctrl_priv *p = 628 (struct rt721_sdca_dmic_kctrl_priv *)kcontrol->private_value; 629 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 630 unsigned int boost_step = 0x0a00; 631 unsigned int vol_max = 0x1e00; 632 unsigned int gain_val[4]; 633 unsigned int i, adc_vol_flag = 0, changed = 0; 634 unsigned int regvalue[4]; 635 const unsigned int interval_offset = 0xc0; 636 int err; 637 638 if (strstr(ucontrol->id.name, "FU1E Capture Volume")) 639 adc_vol_flag = 1; 640 641 /* check all channels */ 642 for (i = 0; i < p->count; i++) { 643 regmap_read(rt721->mbq_regmap, p->reg_base + i, ®value[i]); 644 645 gain_val[i] = ucontrol->value.integer.value[i]; 646 if (gain_val[i] > p->max) 647 gain_val[i] = p->max; 648 649 if (!adc_vol_flag) /* boost gain */ 650 gain_val[i] = gain_val[i] * boost_step; 651 else { /* ADC gain */ 652 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset); 653 gain_val[i] &= 0xffff; 654 } 655 656 if (regvalue[i] != gain_val[i]) 657 changed = 1; 658 } 659 660 if (!changed) 661 return 0; 662 663 for (i = 0; i < p->count; i++) { 664 err = regmap_write(rt721->mbq_regmap, p->reg_base + i, gain_val[i]); 665 if (err < 0) 666 dev_err(&rt721->slave->dev, "%#08x can't be set\n", p->reg_base + i); 667 } 668 669 return changed; 670 } 671 672 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); 673 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0); 674 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0); 675 static const DECLARE_TLV_DB_SCALE(mic2_boost_vol_tlv, -200, 200, 0); 676 677 static const struct snd_kcontrol_new rt721_sdca_controls[] = { 678 /* Headphone playback settings */ 679 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume", 680 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 681 RT721_SDCA_CTL_FU_VOLUME, CH_L), 682 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 683 RT721_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 684 rt721_sdca_set_gain_get, rt721_sdca_set_gain_put, out_vol_tlv), 685 /* Headset mic capture settings */ 686 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0, 687 rt721_sdca_fu0f_capture_get, rt721_sdca_fu0f_capture_put), 688 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume", 689 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, 690 RT721_SDCA_CTL_FU_VOLUME, CH_L), 691 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, 692 RT721_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0, 693 rt721_sdca_set_gain_get, rt721_sdca_set_gain_put, mic_vol_tlv), 694 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume", 695 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PLATFORM_FU44, 696 RT721_SDCA_CTL_FU_CH_GAIN, CH_L), 697 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PLATFORM_FU44, 698 RT721_SDCA_CTL_FU_CH_GAIN, CH_R), 1, 0x15, 0, 699 rt721_sdca_set_gain_get, rt721_sdca_set_gain_put, mic2_boost_vol_tlv), 700 /* AMP playback settings */ 701 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume", 702 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 703 RT721_SDCA_CTL_FU_VOLUME, CH_L), 704 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 705 RT721_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0, 706 rt721_sdca_set_gain_get, rt721_sdca_set_gain_put, out_vol_tlv), 707 /* DMIC capture settings */ 708 RT_SDCA_FU_CTRL("FU1E Capture Switch", 709 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, 710 RT721_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4, rt721_sdca_fu_info, 711 rt721_sdca_fu1e_capture_get, rt721_sdca_fu1e_capture_put), 712 RT_SDCA_EXT_TLV("FU1E Capture Volume", 713 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, 714 RT721_SDCA_CTL_FU_VOLUME, CH_01), 715 rt721_sdca_dmic_set_gain_get, rt721_sdca_dmic_set_gain_put, 716 4, 0x3f, mic_vol_tlv, rt721_sdca_fu_info), 717 RT_SDCA_EXT_TLV("FU15 Boost Volume", 718 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_FU15, 719 RT721_SDCA_CTL_FU_CH_GAIN, CH_01), 720 rt721_sdca_dmic_set_gain_get, rt721_sdca_dmic_set_gain_put, 721 4, 3, boost_vol_tlv, rt721_sdca_fu_info), 722 }; 723 724 static int rt721_sdca_adc_mux_get(struct snd_kcontrol *kcontrol, 725 struct snd_ctl_elem_value *ucontrol) 726 { 727 struct snd_soc_component *component = 728 snd_soc_dapm_kcontrol_component(kcontrol); 729 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 730 unsigned int val = 0, mask_sft, mask; 731 732 if (strstr(ucontrol->id.name, "ADC 09 Mux")) { 733 mask_sft = 12; 734 mask = 0x7; 735 } else if (strstr(ucontrol->id.name, "ADC 08 R Mux")) { 736 mask_sft = 10; 737 mask = 0x3; 738 } else if (strstr(ucontrol->id.name, "ADC 08 L Mux")) { 739 mask_sft = 8; 740 mask = 0x3; 741 } else if (strstr(ucontrol->id.name, "ADC 10 R Mux")) { 742 mask_sft = 6; 743 mask = 0x3; 744 } else if (strstr(ucontrol->id.name, "ADC 10 L Mux")) { 745 mask_sft = 4; 746 mask = 0x3; 747 } else if (strstr(ucontrol->id.name, "ADC 07 R Mux")) { 748 mask_sft = 2; 749 mask = 0x3; 750 } else if (strstr(ucontrol->id.name, "ADC 07 L Mux")) { 751 mask_sft = 0; 752 mask = 0x3; 753 } else 754 return -EINVAL; 755 756 rt_sdca_index_read(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 757 RT721_HDA_LEGACY_MUX_CTL0, &val); 758 759 ucontrol->value.enumerated.item[0] = (val >> mask_sft) & mask; 760 761 return 0; 762 } 763 764 static int rt721_sdca_adc_mux_put(struct snd_kcontrol *kcontrol, 765 struct snd_ctl_elem_value *ucontrol) 766 { 767 struct snd_soc_component *component = 768 snd_soc_dapm_kcontrol_component(kcontrol); 769 struct snd_soc_dapm_context *dapm = 770 snd_soc_dapm_kcontrol_dapm(kcontrol); 771 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 772 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 773 unsigned int *item = ucontrol->value.enumerated.item; 774 unsigned int val, val2 = 0, change, mask_sft, mask; 775 unsigned int check; 776 777 if (item[0] >= e->items) 778 return -EINVAL; 779 780 if (strstr(ucontrol->id.name, "ADC 09 Mux")) { 781 mask_sft = 12; 782 mask = 0x7; 783 } else if (strstr(ucontrol->id.name, "ADC 08 R Mux")) { 784 mask_sft = 10; 785 mask = 0x3; 786 } else if (strstr(ucontrol->id.name, "ADC 08 L Mux")) { 787 mask_sft = 8; 788 mask = 0x3; 789 } else if (strstr(ucontrol->id.name, "ADC 10 R Mux")) { 790 mask_sft = 6; 791 mask = 0x3; 792 } else if (strstr(ucontrol->id.name, "ADC 10 L Mux")) { 793 mask_sft = 4; 794 mask = 0x3; 795 } else if (strstr(ucontrol->id.name, "ADC 07 R Mux")) { 796 mask_sft = 2; 797 mask = 0x3; 798 } else if (strstr(ucontrol->id.name, "ADC 07 L Mux")) { 799 mask_sft = 0; 800 mask = 0x3; 801 } else 802 return -EINVAL; 803 804 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 805 rt_sdca_index_read(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 806 RT721_HDA_LEGACY_MUX_CTL0, &val2); 807 808 if (strstr(ucontrol->id.name, "ADC 09 Mux")) 809 val2 = (val2 >> mask_sft) & 0x7; 810 else 811 val2 = (val2 >> mask_sft) & 0x3; 812 813 if (val == val2) 814 change = 0; 815 else 816 change = 1; 817 818 if (change) { 819 rt_sdca_index_read(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 820 RT721_HDA_LEGACY_MUX_CTL0, &check); 821 rt_sdca_index_update_bits(rt721->mbq_regmap, RT721_HDA_SDCA_FLOAT, 822 RT721_HDA_LEGACY_MUX_CTL0, mask << mask_sft, 823 val << mask_sft); 824 } 825 826 snd_soc_dapm_mux_update_power(dapm, kcontrol, 827 item[0], e, NULL); 828 829 return change; 830 } 831 832 static const char * const adc09_mux_text[] = { 833 "MIC2", 834 "LINE1", 835 "LINE2", 836 }; 837 static const char * const adc07_10_mux_text[] = { 838 "DMIC1 RE", 839 "DMIC1 FE", 840 "DMIC2 RE", 841 "DMIC2 FE", 842 }; 843 844 static SOC_ENUM_SINGLE_DECL( 845 rt721_adc09_enum, SND_SOC_NOPM, 0, adc09_mux_text); 846 static SOC_ENUM_SINGLE_DECL( 847 rt721_dmic_enum, SND_SOC_NOPM, 0, adc07_10_mux_text); 848 849 static const struct snd_kcontrol_new rt721_sdca_adc09_mux = 850 SOC_DAPM_ENUM_EXT("ADC 09 Mux", rt721_adc09_enum, 851 rt721_sdca_adc_mux_get, rt721_sdca_adc_mux_put); 852 static const struct snd_kcontrol_new rt721_sdca_adc08_r_mux = 853 SOC_DAPM_ENUM_EXT("ADC 08 R Mux", rt721_dmic_enum, 854 rt721_sdca_adc_mux_get, rt721_sdca_adc_mux_put); 855 static const struct snd_kcontrol_new rt721_sdca_adc08_l_mux = 856 SOC_DAPM_ENUM_EXT("ADC 08 L Mux", rt721_dmic_enum, 857 rt721_sdca_adc_mux_get, rt721_sdca_adc_mux_put); 858 static const struct snd_kcontrol_new rt721_sdca_adc10_r_mux = 859 SOC_DAPM_ENUM_EXT("ADC 10 R Mux", rt721_dmic_enum, 860 rt721_sdca_adc_mux_get, rt721_sdca_adc_mux_put); 861 static const struct snd_kcontrol_new rt721_sdca_adc10_l_mux = 862 SOC_DAPM_ENUM_EXT("ADC 10 L Mux", rt721_dmic_enum, 863 rt721_sdca_adc_mux_get, rt721_sdca_adc_mux_put); 864 static const struct snd_kcontrol_new rt721_sdca_adc07_r_mux = 865 SOC_DAPM_ENUM_EXT("ADC 07 R Mux", rt721_dmic_enum, 866 rt721_sdca_adc_mux_get, rt721_sdca_adc_mux_put); 867 static const struct snd_kcontrol_new rt721_sdca_adc07_l_mux = 868 SOC_DAPM_ENUM_EXT("ADC 07 L Mux", rt721_dmic_enum, 869 rt721_sdca_adc_mux_get, rt721_sdca_adc_mux_put); 870 871 872 static int rt721_sdca_fu42_event(struct snd_soc_dapm_widget *w, 873 struct snd_kcontrol *kcontrol, int event) 874 { 875 struct snd_soc_component *component = 876 snd_soc_dapm_to_component(w->dapm); 877 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 878 unsigned char unmute = 0x0, mute = 0x1; 879 880 switch (event) { 881 case SND_SOC_DAPM_POST_PMU: 882 msleep(100); 883 regmap_write(rt721->regmap, 884 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 885 RT721_SDCA_CTL_FU_MUTE, CH_L), unmute); 886 regmap_write(rt721->regmap, 887 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 888 RT721_SDCA_CTL_FU_MUTE, CH_R), unmute); 889 break; 890 case SND_SOC_DAPM_PRE_PMD: 891 regmap_write(rt721->regmap, 892 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 893 RT721_SDCA_CTL_FU_MUTE, CH_L), mute); 894 regmap_write(rt721->regmap, 895 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 896 RT721_SDCA_CTL_FU_MUTE, CH_R), mute); 897 break; 898 } 899 return 0; 900 } 901 902 static int rt721_sdca_fu21_event(struct snd_soc_dapm_widget *w, 903 struct snd_kcontrol *kcontrol, int event) 904 { 905 struct snd_soc_component *component = 906 snd_soc_dapm_to_component(w->dapm); 907 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 908 unsigned char unmute = 0x0, mute = 0x1; 909 910 switch (event) { 911 case SND_SOC_DAPM_POST_PMU: 912 regmap_write(rt721->regmap, 913 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 914 RT721_SDCA_CTL_FU_MUTE, CH_L), unmute); 915 regmap_write(rt721->regmap, 916 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 917 RT721_SDCA_CTL_FU_MUTE, CH_R), unmute); 918 break; 919 case SND_SOC_DAPM_PRE_PMD: 920 regmap_write(rt721->regmap, 921 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 922 RT721_SDCA_CTL_FU_MUTE, CH_L), mute); 923 regmap_write(rt721->regmap, 924 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 925 RT721_SDCA_CTL_FU_MUTE, CH_R), mute); 926 break; 927 } 928 return 0; 929 } 930 931 static int rt721_sdca_fu23_event(struct snd_soc_dapm_widget *w, 932 struct snd_kcontrol *kcontrol, int event) 933 { 934 struct snd_soc_component *component = 935 snd_soc_dapm_to_component(w->dapm); 936 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 937 unsigned char unmute = 0x0, mute = 0x1; 938 939 switch (event) { 940 case SND_SOC_DAPM_POST_PMU: 941 regmap_write(rt721->regmap, 942 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 943 RT721_SDCA_CTL_FU_MUTE, CH_L), unmute); 944 regmap_write(rt721->regmap, 945 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 946 RT721_SDCA_CTL_FU_MUTE, CH_R), unmute); 947 break; 948 case SND_SOC_DAPM_PRE_PMD: 949 regmap_write(rt721->regmap, 950 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 951 RT721_SDCA_CTL_FU_MUTE, CH_L), mute); 952 regmap_write(rt721->regmap, 953 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 954 RT721_SDCA_CTL_FU_MUTE, CH_R), mute); 955 break; 956 } 957 return 0; 958 } 959 960 static int rt721_sdca_fu113_event(struct snd_soc_dapm_widget *w, 961 struct snd_kcontrol *kcontrol, int event) 962 { 963 struct snd_soc_component *component = 964 snd_soc_dapm_to_component(w->dapm); 965 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 966 967 switch (event) { 968 case SND_SOC_DAPM_POST_PMU: 969 rt721->fu1e_dapm_mute = false; 970 rt721_sdca_set_fu1e_capture_ctl(rt721); 971 break; 972 case SND_SOC_DAPM_PRE_PMD: 973 rt721->fu1e_dapm_mute = true; 974 rt721_sdca_set_fu1e_capture_ctl(rt721); 975 break; 976 } 977 return 0; 978 } 979 980 static int rt721_sdca_fu36_event(struct snd_soc_dapm_widget *w, 981 struct snd_kcontrol *kcontrol, int event) 982 { 983 struct snd_soc_component *component = 984 snd_soc_dapm_to_component(w->dapm); 985 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 986 987 switch (event) { 988 case SND_SOC_DAPM_POST_PMU: 989 rt721->fu0f_dapm_mute = false; 990 rt721_sdca_set_fu0f_capture_ctl(rt721); 991 break; 992 case SND_SOC_DAPM_PRE_PMD: 993 rt721->fu0f_dapm_mute = true; 994 rt721_sdca_set_fu0f_capture_ctl(rt721); 995 break; 996 } 997 return 0; 998 } 999 1000 static int rt721_sdca_pde47_event(struct snd_soc_dapm_widget *w, 1001 struct snd_kcontrol *kcontrol, int event) 1002 { 1003 struct snd_soc_component *component = 1004 snd_soc_dapm_to_component(w->dapm); 1005 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 1006 unsigned char ps0 = 0x0, ps3 = 0x3; 1007 1008 switch (event) { 1009 case SND_SOC_DAPM_POST_PMU: 1010 regmap_write(rt721->regmap, 1011 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PDE40, 1012 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1013 break; 1014 case SND_SOC_DAPM_PRE_PMD: 1015 regmap_write(rt721->regmap, 1016 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PDE40, 1017 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1018 break; 1019 } 1020 return 0; 1021 } 1022 1023 static int rt721_sdca_pde41_event(struct snd_soc_dapm_widget *w, 1024 struct snd_kcontrol *kcontrol, int event) 1025 { 1026 struct snd_soc_component *component = 1027 snd_soc_dapm_to_component(w->dapm); 1028 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 1029 unsigned char ps0 = 0x0, ps3 = 0x3; 1030 1031 switch (event) { 1032 case SND_SOC_DAPM_POST_PMU: 1033 regmap_write(rt721->regmap, 1034 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE41, 1035 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1036 break; 1037 case SND_SOC_DAPM_PRE_PMD: 1038 regmap_write(rt721->regmap, 1039 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE41, 1040 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1041 break; 1042 } 1043 return 0; 1044 } 1045 1046 static int rt721_sdca_pde11_event(struct snd_soc_dapm_widget *w, 1047 struct snd_kcontrol *kcontrol, int event) 1048 { 1049 struct snd_soc_component *component = 1050 snd_soc_dapm_to_component(w->dapm); 1051 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 1052 unsigned char ps0 = 0x0, ps3 = 0x3; 1053 1054 switch (event) { 1055 case SND_SOC_DAPM_POST_PMU: 1056 regmap_write(rt721->regmap, 1057 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_PDE2A, 1058 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1059 break; 1060 case SND_SOC_DAPM_PRE_PMD: 1061 regmap_write(rt721->regmap, 1062 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_PDE2A, 1063 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1064 break; 1065 } 1066 return 0; 1067 } 1068 1069 static int rt721_sdca_pde34_event(struct snd_soc_dapm_widget *w, 1070 struct snd_kcontrol *kcontrol, int event) 1071 { 1072 struct snd_soc_component *component = 1073 snd_soc_dapm_to_component(w->dapm); 1074 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 1075 unsigned char ps0 = 0x0, ps3 = 0x3; 1076 1077 switch (event) { 1078 case SND_SOC_DAPM_POST_PMU: 1079 regmap_write(rt721->regmap, 1080 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PDE12, 1081 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 1082 break; 1083 case SND_SOC_DAPM_PRE_PMD: 1084 regmap_write(rt721->regmap, 1085 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PDE12, 1086 RT721_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 1087 break; 1088 } 1089 return 0; 1090 } 1091 1092 static const struct snd_soc_dapm_widget rt721_sdca_dapm_widgets[] = { 1093 SND_SOC_DAPM_OUTPUT("HP"), 1094 SND_SOC_DAPM_OUTPUT("SPK"), 1095 SND_SOC_DAPM_INPUT("MIC2"), 1096 SND_SOC_DAPM_INPUT("LINE1"), 1097 SND_SOC_DAPM_INPUT("LINE2"), 1098 SND_SOC_DAPM_INPUT("DMIC1_2"), 1099 SND_SOC_DAPM_INPUT("DMIC3_4"), 1100 1101 SND_SOC_DAPM_SUPPLY("PDE 41", SND_SOC_NOPM, 0, 0, 1102 rt721_sdca_pde41_event, 1103 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1104 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0, 1105 rt721_sdca_pde47_event, 1106 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1107 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0, 1108 rt721_sdca_pde11_event, 1109 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1110 SND_SOC_DAPM_SUPPLY("PDE 34", SND_SOC_NOPM, 0, 0, 1111 rt721_sdca_pde34_event, 1112 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1113 1114 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0, 1115 rt721_sdca_fu21_event, 1116 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1117 SND_SOC_DAPM_DAC_E("FU 23", NULL, SND_SOC_NOPM, 0, 0, 1118 rt721_sdca_fu23_event, 1119 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1120 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0, 1121 rt721_sdca_fu42_event, 1122 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1123 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0, 1124 rt721_sdca_fu36_event, 1125 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1126 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0, 1127 rt721_sdca_fu113_event, 1128 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1129 SND_SOC_DAPM_MUX("ADC 09 Mux", SND_SOC_NOPM, 0, 0, 1130 &rt721_sdca_adc09_mux), 1131 SND_SOC_DAPM_MUX("ADC 08 R Mux", SND_SOC_NOPM, 0, 0, 1132 &rt721_sdca_adc08_r_mux), 1133 SND_SOC_DAPM_MUX("ADC 08 L Mux", SND_SOC_NOPM, 0, 0, 1134 &rt721_sdca_adc08_l_mux), 1135 SND_SOC_DAPM_MUX("ADC 10 R Mux", SND_SOC_NOPM, 0, 0, 1136 &rt721_sdca_adc10_r_mux), 1137 SND_SOC_DAPM_MUX("ADC 10 L Mux", SND_SOC_NOPM, 0, 0, 1138 &rt721_sdca_adc10_l_mux), 1139 SND_SOC_DAPM_MUX("ADC 07 R Mux", SND_SOC_NOPM, 0, 0, 1140 &rt721_sdca_adc07_r_mux), 1141 SND_SOC_DAPM_MUX("ADC 07 L Mux", SND_SOC_NOPM, 0, 0, 1142 &rt721_sdca_adc07_l_mux), 1143 1144 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0), 1145 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0), 1146 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0), 1147 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0), 1148 }; 1149 1150 static const struct snd_soc_dapm_route rt721_sdca_audio_map[] = { 1151 {"FU 42", NULL, "DP1RX"}, 1152 {"FU 21", NULL, "DP3RX"}, 1153 {"FU 23", NULL, "DP3RX"}, 1154 1155 {"ADC 09 Mux", "MIC2", "MIC2"}, 1156 {"ADC 09 Mux", "LINE1", "LINE1"}, 1157 {"ADC 09 Mux", "LINE2", "LINE2"}, 1158 {"ADC 07 R Mux", "DMIC1 RE", "DMIC1_2"}, 1159 {"ADC 07 R Mux", "DMIC1 FE", "DMIC1_2"}, 1160 {"ADC 07 R Mux", "DMIC2 RE", "DMIC3_4"}, 1161 {"ADC 07 R Mux", "DMIC2 FE", "DMIC3_4"}, 1162 {"ADC 07 L Mux", "DMIC1 RE", "DMIC1_2"}, 1163 {"ADC 07 L Mux", "DMIC1 FE", "DMIC1_2"}, 1164 {"ADC 07 L Mux", "DMIC2 RE", "DMIC3_4"}, 1165 {"ADC 07 L Mux", "DMIC2 FE", "DMIC3_4"}, 1166 {"ADC 08 R Mux", "DMIC1 RE", "DMIC1_2"}, 1167 {"ADC 08 R Mux", "DMIC1 FE", "DMIC1_2"}, 1168 {"ADC 08 R Mux", "DMIC2 RE", "DMIC3_4"}, 1169 {"ADC 08 R Mux", "DMIC2 FE", "DMIC3_4"}, 1170 {"ADC 08 L Mux", "DMIC1 RE", "DMIC1_2"}, 1171 {"ADC 08 L Mux", "DMIC1 FE", "DMIC1_2"}, 1172 {"ADC 08 L Mux", "DMIC2 RE", "DMIC3_4"}, 1173 {"ADC 08 L Mux", "DMIC2 FE", "DMIC3_4"}, 1174 {"ADC 10 R Mux", "DMIC1 RE", "DMIC1_2"}, 1175 {"ADC 10 R Mux", "DMIC1 FE", "DMIC1_2"}, 1176 {"ADC 10 R Mux", "DMIC2 RE", "DMIC3_4"}, 1177 {"ADC 10 R Mux", "DMIC2 FE", "DMIC3_4"}, 1178 {"ADC 10 L Mux", "DMIC1 RE", "DMIC1_2"}, 1179 {"ADC 10 L Mux", "DMIC1 FE", "DMIC1_2"}, 1180 {"ADC 10 L Mux", "DMIC2 RE", "DMIC3_4"}, 1181 {"ADC 10 L Mux", "DMIC2 FE", "DMIC3_4"}, 1182 {"FU 36", NULL, "PDE 34"}, 1183 {"FU 36", NULL, "ADC 09 Mux"}, 1184 {"FU 113", NULL, "PDE 11"}, 1185 {"FU 113", NULL, "ADC 07 R Mux"}, 1186 {"FU 113", NULL, "ADC 07 L Mux"}, 1187 {"FU 113", NULL, "ADC 10 R Mux"}, 1188 {"FU 113", NULL, "ADC 10 L Mux"}, 1189 {"DP2TX", NULL, "FU 36"}, 1190 {"DP6TX", NULL, "FU 113"}, 1191 1192 {"HP", NULL, "PDE 47"}, 1193 {"HP", NULL, "FU 42"}, 1194 {"SPK", NULL, "PDE 41"}, 1195 {"SPK", NULL, "FU 21"}, 1196 {"SPK", NULL, "FU 23"}, 1197 }; 1198 1199 static int rt721_sdca_parse_dt(struct rt721_sdca_priv *rt721, struct device *dev) 1200 { 1201 device_property_read_u32(dev, "realtek,jd-src", &rt721->jd_src); 1202 1203 return 0; 1204 } 1205 1206 static int rt721_sdca_probe(struct snd_soc_component *component) 1207 { 1208 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 1209 int ret; 1210 1211 rt721_sdca_parse_dt(rt721, &rt721->slave->dev); 1212 rt721->component = component; 1213 1214 ret = pm_runtime_resume(component->dev); 1215 if (ret < 0 && ret != -EACCES) 1216 return ret; 1217 1218 return 0; 1219 } 1220 1221 static const struct snd_soc_component_driver soc_sdca_dev_rt721 = { 1222 .probe = rt721_sdca_probe, 1223 .controls = rt721_sdca_controls, 1224 .num_controls = ARRAY_SIZE(rt721_sdca_controls), 1225 .dapm_widgets = rt721_sdca_dapm_widgets, 1226 .num_dapm_widgets = ARRAY_SIZE(rt721_sdca_dapm_widgets), 1227 .dapm_routes = rt721_sdca_audio_map, 1228 .num_dapm_routes = ARRAY_SIZE(rt721_sdca_audio_map), 1229 .set_jack = rt721_sdca_set_jack_detect, 1230 .endianness = 1, 1231 }; 1232 1233 static int rt721_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 1234 int direction) 1235 { 1236 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 1237 1238 return 0; 1239 } 1240 1241 static void rt721_sdca_shutdown(struct snd_pcm_substream *substream, 1242 struct snd_soc_dai *dai) 1243 { 1244 snd_soc_dai_set_dma_data(dai, substream, NULL); 1245 } 1246 1247 static int rt721_sdca_pcm_hw_params(struct snd_pcm_substream *substream, 1248 struct snd_pcm_hw_params *params, 1249 struct snd_soc_dai *dai) 1250 { 1251 struct snd_soc_component *component = dai->component; 1252 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 1253 struct sdw_stream_config stream_config; 1254 struct sdw_port_config port_config; 1255 enum sdw_data_direction direction; 1256 struct sdw_stream_runtime *sdw_stream; 1257 int retval, port, num_channels; 1258 unsigned int sampling_rate; 1259 1260 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 1261 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 1262 1263 if (!sdw_stream) 1264 return -EINVAL; 1265 1266 if (!rt721->slave) 1267 return -EINVAL; 1268 1269 /* 1270 * RT721_AIF1 with port = 1 for headphone playback 1271 * RT721_AIF1 with port = 2 for headset-mic capture 1272 * RT721_AIF2 with port = 3 for speaker playback 1273 * RT721_AIF3 with port = 6 for digital-mic capture 1274 */ 1275 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1276 direction = SDW_DATA_DIR_RX; 1277 if (dai->id == RT721_AIF1) 1278 port = 1; 1279 else if (dai->id == RT721_AIF2) 1280 port = 3; 1281 else 1282 return -EINVAL; 1283 } else { 1284 direction = SDW_DATA_DIR_TX; 1285 if (dai->id == RT721_AIF1) 1286 port = 2; 1287 else if (dai->id == RT721_AIF3) 1288 port = 6; 1289 else 1290 return -EINVAL; 1291 } 1292 stream_config.frame_rate = params_rate(params); 1293 stream_config.ch_count = params_channels(params); 1294 stream_config.bps = snd_pcm_format_width(params_format(params)); 1295 stream_config.direction = direction; 1296 1297 num_channels = params_channels(params); 1298 port_config.ch_mask = GENMASK(num_channels - 1, 0); 1299 port_config.num = port; 1300 1301 retval = sdw_stream_add_slave(rt721->slave, &stream_config, 1302 &port_config, 1, sdw_stream); 1303 if (retval) { 1304 dev_err(dai->dev, "Unable to configure port\n"); 1305 return retval; 1306 } 1307 1308 if (params_channels(params) > 16) { 1309 dev_err(component->dev, "Unsupported channels %d\n", 1310 params_channels(params)); 1311 return -EINVAL; 1312 } 1313 1314 /* sampling rate configuration */ 1315 switch (params_rate(params)) { 1316 case 8000: 1317 sampling_rate = RT721_SDCA_RATE_8000HZ; 1318 break; 1319 case 16000: 1320 sampling_rate = RT721_SDCA_RATE_16000HZ; 1321 break; 1322 case 24000: 1323 sampling_rate = RT721_SDCA_RATE_24000HZ; 1324 break; 1325 case 32000: 1326 sampling_rate = RT721_SDCA_RATE_32000HZ; 1327 break; 1328 case 44100: 1329 sampling_rate = RT721_SDCA_RATE_44100HZ; 1330 break; 1331 case 48000: 1332 sampling_rate = RT721_SDCA_RATE_48000HZ; 1333 break; 1334 case 96000: 1335 sampling_rate = RT721_SDCA_RATE_96000HZ; 1336 break; 1337 case 192000: 1338 sampling_rate = RT721_SDCA_RATE_192000HZ; 1339 break; 1340 case 384000: 1341 sampling_rate = RT721_SDCA_RATE_384000HZ; 1342 break; 1343 case 768000: 1344 sampling_rate = RT721_SDCA_RATE_768000HZ; 1345 break; 1346 default: 1347 dev_err(component->dev, "Rate %d is not supported\n", 1348 params_rate(params)); 1349 return -EINVAL; 1350 } 1351 1352 /* set sampling frequency */ 1353 if (dai->id == RT721_AIF1) { 1354 regmap_write(rt721->regmap, 1355 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_CS01, 1356 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1357 regmap_write(rt721->regmap, 1358 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_CS11, 1359 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1360 } 1361 1362 if (dai->id == RT721_AIF2) 1363 regmap_write(rt721->regmap, 1364 SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_CS31, 1365 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1366 1367 if (dai->id == RT721_AIF3) 1368 regmap_write(rt721->regmap, 1369 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_CS1F, 1370 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate); 1371 1372 return 0; 1373 } 1374 1375 static int rt721_sdca_pcm_hw_free(struct snd_pcm_substream *substream, 1376 struct snd_soc_dai *dai) 1377 { 1378 struct snd_soc_component *component = dai->component; 1379 struct rt721_sdca_priv *rt721 = snd_soc_component_get_drvdata(component); 1380 struct sdw_stream_runtime *sdw_stream = 1381 snd_soc_dai_get_dma_data(dai, substream); 1382 1383 if (!rt721->slave) 1384 return -EINVAL; 1385 1386 sdw_stream_remove_slave(rt721->slave, sdw_stream); 1387 return 0; 1388 } 1389 1390 #define RT721_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 1391 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 1392 #define RT721_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1393 SNDRV_PCM_FMTBIT_S24_LE) 1394 1395 static const struct snd_soc_dai_ops rt721_sdca_ops = { 1396 .hw_params = rt721_sdca_pcm_hw_params, 1397 .hw_free = rt721_sdca_pcm_hw_free, 1398 .set_stream = rt721_sdca_set_sdw_stream, 1399 .shutdown = rt721_sdca_shutdown, 1400 }; 1401 1402 static struct snd_soc_dai_driver rt721_sdca_dai[] = { 1403 { 1404 .name = "rt721-sdca-aif1", 1405 .id = RT721_AIF1, 1406 .playback = { 1407 .stream_name = "DP1 Headphone Playback", 1408 .channels_min = 1, 1409 .channels_max = 2, 1410 .rates = RT721_STEREO_RATES, 1411 .formats = RT721_FORMATS, 1412 }, 1413 .capture = { 1414 .stream_name = "DP2 Headset Capture", 1415 .channels_min = 1, 1416 .channels_max = 2, 1417 .rates = RT721_STEREO_RATES, 1418 .formats = RT721_FORMATS, 1419 }, 1420 .ops = &rt721_sdca_ops, 1421 }, 1422 { 1423 .name = "rt721-sdca-aif2", 1424 .id = RT721_AIF2, 1425 .playback = { 1426 .stream_name = "DP3 Speaker Playback", 1427 .channels_min = 1, 1428 .channels_max = 2, 1429 .rates = RT721_STEREO_RATES, 1430 .formats = RT721_FORMATS, 1431 }, 1432 .ops = &rt721_sdca_ops, 1433 }, 1434 { 1435 .name = "rt721-sdca-aif3", 1436 .id = RT721_AIF3, 1437 .capture = { 1438 .stream_name = "DP6 DMic Capture", 1439 .channels_min = 1, 1440 .channels_max = 4, 1441 .rates = RT721_STEREO_RATES, 1442 .formats = RT721_FORMATS, 1443 }, 1444 .ops = &rt721_sdca_ops, 1445 } 1446 }; 1447 1448 int rt721_sdca_init(struct device *dev, struct regmap *regmap, 1449 struct regmap *mbq_regmap, struct sdw_slave *slave) 1450 { 1451 struct rt721_sdca_priv *rt721; 1452 1453 rt721 = devm_kzalloc(dev, sizeof(*rt721), GFP_KERNEL); 1454 if (!rt721) 1455 return -ENOMEM; 1456 1457 dev_set_drvdata(dev, rt721); 1458 rt721->slave = slave; 1459 rt721->regmap = regmap; 1460 rt721->mbq_regmap = mbq_regmap; 1461 1462 regcache_cache_only(rt721->regmap, true); 1463 regcache_cache_only(rt721->mbq_regmap, true); 1464 1465 mutex_init(&rt721->calibrate_mutex); 1466 mutex_init(&rt721->disable_irq_lock); 1467 1468 INIT_DELAYED_WORK(&rt721->jack_detect_work, rt721_sdca_jack_detect_handler); 1469 INIT_DELAYED_WORK(&rt721->jack_btn_check_work, rt721_sdca_btn_check_handler); 1470 1471 /* 1472 * Mark hw_init to false 1473 * HW init will be performed when device reports present 1474 */ 1475 rt721->hw_init = false; 1476 rt721->first_hw_init = false; 1477 rt721->fu1e_dapm_mute = true; 1478 rt721->fu0f_dapm_mute = true; 1479 rt721->fu0f_mixer_l_mute = rt721->fu0f_mixer_r_mute = true; 1480 rt721->fu1e_mixer_mute[0] = rt721->fu1e_mixer_mute[1] = 1481 rt721->fu1e_mixer_mute[2] = rt721->fu1e_mixer_mute[3] = true; 1482 1483 return devm_snd_soc_register_component(dev, 1484 &soc_sdca_dev_rt721, rt721_sdca_dai, ARRAY_SIZE(rt721_sdca_dai)); 1485 } 1486 1487 int rt721_sdca_io_init(struct device *dev, struct sdw_slave *slave) 1488 { 1489 struct rt721_sdca_priv *rt721 = dev_get_drvdata(dev); 1490 1491 rt721->disable_irq = false; 1492 1493 if (rt721->hw_init) 1494 return 0; 1495 1496 regcache_cache_only(rt721->regmap, false); 1497 regcache_cache_only(rt721->mbq_regmap, false); 1498 if (rt721->first_hw_init) { 1499 regcache_cache_bypass(rt721->regmap, true); 1500 regcache_cache_bypass(rt721->mbq_regmap, true); 1501 } else { 1502 /* 1503 * PM runtime is only enabled when a Slave reports as Attached 1504 */ 1505 1506 /* set autosuspend parameters */ 1507 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 1508 pm_runtime_use_autosuspend(&slave->dev); 1509 1510 /* update count of parent 'active' children */ 1511 pm_runtime_set_active(&slave->dev); 1512 1513 /* make sure the device does not suspend immediately */ 1514 pm_runtime_mark_last_busy(&slave->dev); 1515 1516 pm_runtime_enable(&slave->dev); 1517 } 1518 1519 pm_runtime_get_noresume(&slave->dev); 1520 rt721_sdca_dmic_preset(rt721); 1521 rt721_sdca_amp_preset(rt721); 1522 rt721_sdca_jack_preset(rt721); 1523 if (rt721->first_hw_init) { 1524 regcache_cache_bypass(rt721->regmap, false); 1525 regcache_mark_dirty(rt721->regmap); 1526 regcache_cache_bypass(rt721->mbq_regmap, false); 1527 regcache_mark_dirty(rt721->mbq_regmap); 1528 } else 1529 rt721->first_hw_init = true; 1530 1531 /* Mark Slave initialization complete */ 1532 rt721->hw_init = true; 1533 1534 pm_runtime_mark_last_busy(&slave->dev); 1535 pm_runtime_put_autosuspend(&slave->dev); 1536 1537 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 1538 return 0; 1539 } 1540 1541 MODULE_DESCRIPTION("ASoC RT721 SDCA SDW driver"); 1542 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1543 MODULE_LICENSE("GPL"); 1544