1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt721-sdca-sdw.h -- RT721 SDCA ALSA SoC audio driver header 4 * 5 * Copyright(c) 2024 Realtek Semiconductor Corp. 6 */ 7 8 #ifndef __RT721_SDW_H__ 9 #define __RT721_SDW_H__ 10 11 #include <linux/regmap.h> 12 #include <linux/soundwire/sdw_registers.h> 13 14 static const struct reg_default rt721_sdca_reg_defaults[] = { 15 { 0x202d, 0x00 }, 16 { 0x2f01, 0x00 }, 17 { 0x2f02, 0x09 }, 18 { 0x2f03, 0x08 }, 19 { 0x2f04, 0x00 }, 20 { 0x2f05, 0x0e }, 21 { 0x2f06, 0x01 }, 22 { 0x2f09, 0x00 }, 23 { 0x2f0a, 0x00 }, 24 { 0x2f35, 0x00 }, 25 { 0x2f50, 0xf0 }, 26 { 0x2f58, 0x07 }, 27 { 0x2f59, 0x07 }, 28 { 0x2f5a, 0x00 }, 29 { 0x2f5b, 0x07 }, 30 { 0x2f5c, 0x27 }, 31 { 0x2f5d, 0x07 }, 32 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_CS01, 33 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 34 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_CS11, 35 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 36 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PDE12, 37 RT721_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 38 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PDE40, 39 RT721_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 40 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 41 RT721_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 42 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, 43 RT721_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 44 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, 45 RT721_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 46 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, 47 RT721_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 48 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, 49 RT721_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 50 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, 51 RT721_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 52 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, 53 RT721_SDCA_CTL_FU_MUTE, CH_03), 0x01 }, 54 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, 55 RT721_SDCA_CTL_FU_MUTE, CH_04), 0x01 }, 56 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_CS1F, 57 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 58 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_IT26, 59 RT721_SDCA_CTL_VENDOR_DEF, 0), 0x00 }, 60 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_PDE2A, 61 RT721_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 62 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_CS31, 63 RT721_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, 64 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 65 RT721_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, 66 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, 67 RT721_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, 68 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 69 RT721_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, 70 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_OT23, 71 RT721_SDCA_CTL_VENDOR_DEF, 0), 0x00 }, 72 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 73 RT721_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 74 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_PDE23, 75 RT721_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 76 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_FU55, 77 RT721_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, 78 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_FU55, 79 RT721_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, 80 }; 81 82 static const struct reg_default rt721_sdca_mbq_defaults[] = { 83 { 0x0900007, 0xc004 }, 84 { 0x2000001, 0x0000 }, 85 { 0x2000002, 0x0000 }, 86 { 0x2000003, 0x0000 }, 87 { 0x2000013, 0x8001 }, 88 { 0x200003c, 0x0000 }, 89 { 0x2000046, 0x3400 }, 90 { 0x5f00044, 0x6040 }, 91 { 0x5f00045, 0x3333 }, 92 { 0x5f00048, 0x0000 }, 93 { 0x6100005, 0x0005 }, 94 { 0x6100006, 0x0000 }, 95 { 0x610000d, 0x0051 }, 96 { 0x6100010, 0x0180 }, 97 { 0x6100011, 0x0000 }, 98 { 0x6100013, 0x0000 }, 99 { 0x6100015, 0x0000 }, 100 { 0x6100017, 0x8049 }, 101 { 0x6100025, 0x1000 }, 102 { 0x6100029, 0x0809 }, 103 { 0x610002c, 0x2828 }, 104 { 0x610002d, 0x2929 }, 105 { 0x610002e, 0x3529 }, 106 { 0x610002f, 0x2901 }, 107 { 0x6100053, 0x2630 }, 108 { 0x6100054, 0x2a2a }, 109 { 0x6100055, 0x152f }, 110 { 0x6100057, 0x2200 }, 111 { 0x610005a, 0x2a4b }, 112 { 0x610005b, 0x2a00 }, 113 { 0x610006a, 0x0102 }, 114 { 0x610006d, 0x0102 }, 115 { 0x6100092, 0x4f61 }, 116 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, RT721_SDCA_CTL_FU_VOLUME, 117 CH_L), 0x0000 }, 118 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU05, RT721_SDCA_CTL_FU_VOLUME, 119 CH_R), 0x0000 }, 120 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, RT721_SDCA_CTL_FU_VOLUME, 121 CH_L), 0x0000 }, 122 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_USER_FU0F, RT721_SDCA_CTL_FU_VOLUME, 123 CH_R), 0x0000 }, 124 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PLATFORM_FU44, RT721_SDCA_CTL_FU_CH_GAIN, 125 CH_L), 0xfe00 }, 126 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT721_SDCA_ENT_PLATFORM_FU44, RT721_SDCA_CTL_FU_CH_GAIN, 127 CH_R), 0xfe00 }, 128 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_FU15, RT721_SDCA_CTL_FU_CH_GAIN, CH_01), 129 0x0000 }, 130 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_FU15, RT721_SDCA_CTL_FU_CH_GAIN, CH_02), 131 0x0000 }, 132 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_FU15, RT721_SDCA_CTL_FU_CH_GAIN, CH_03), 133 0x0000 }, 134 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_FU15, RT721_SDCA_CTL_FU_CH_GAIN, CH_04), 135 0x0000 }, 136 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, RT721_SDCA_CTL_FU_VOLUME, 137 CH_01), 0x0000 }, 138 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, RT721_SDCA_CTL_FU_VOLUME, 139 CH_02), 0x0000 }, 140 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, RT721_SDCA_CTL_FU_VOLUME, 141 CH_03), 0x0000 }, 142 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT721_SDCA_ENT_USER_FU1E, RT721_SDCA_CTL_FU_VOLUME, 143 CH_04), 0x0000 }, 144 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, RT721_SDCA_CTL_FU_VOLUME, CH_L), 145 0x0000 }, 146 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT721_SDCA_ENT_USER_FU06, RT721_SDCA_CTL_FU_VOLUME, CH_R), 147 0x0000 }, 148 }; 149 150 #endif /* __RT721_SDW_H__ */ 151